From 069c68ad04bd6210fc50dbc2aeb2c62448c1731d Mon Sep 17 00:00:00 2001 From: IngHK Date: Fri, 23 Feb 2024 23:27:38 +0100 Subject: sorted driver functions into Control Request, Driver API, Enumeration and Helper. no functional changes --- src/class/cdc/cdc_host.c | 359 +++++++++++++++++++++++++---------------------- 1 file changed, 189 insertions(+), 170 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 2fb37d835..26eb70c9b 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -782,92 +782,7 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { // ACM //--------------------------------------------------------------------+ -enum { - CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, - CONFIG_ACM_SET_LINE_CODING, - CONFIG_ACM_COMPLETE, -}; - -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { - uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len; - - cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY(p_cdc); - p_cdc->serial_drid = SERIAL_DRIVER_ACM; - - //------------- Control Interface -------------// - uint8_t const* p_desc = tu_desc_next(itf_desc); - - // Communication Functional Descriptors - while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { - if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) { - // save ACM bmCapabilities - p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities; - } - - p_desc = tu_desc_next(p_desc); - } - - // Open notification endpoint of control interface if any - if (itf_desc->bNumEndpoints == 1) { - TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); - tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc; - - TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); - p_cdc->ep_notif = desc_ep->bEndpointAddress; - - p_desc = tu_desc_next(p_desc); - } - - //------------- Data Interface (if any) -------------// - if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) { - // next to endpoint descriptor - p_desc = tu_desc_next(p_desc); - - // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc)); - } - - return true; -} - -static void acm_process_config(tuh_xfer_t* xfer) { - uintptr_t const state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); - - switch (state) { - case CONFIG_ACM_SET_CONTROL_LINE_STATE: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); - break; - } - #endif - TU_ATTR_FALLTHROUGH; - - case CONFIG_ACM_SET_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),); - break; - } - #endif - TU_ATTR_FALLTHROUGH; - - case CONFIG_ACM_COMPLETE: - // itf_num+1 to account for data interface as well - set_config_complete(p_cdc, idx, itf_num + 1); - break; - - default: - break; - } -} +//------------- Driver API -------------// static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); @@ -953,37 +868,104 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfe return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); } -//--------------------------------------------------------------------+ -// FTDI -//--------------------------------------------------------------------+ -#if CFG_TUH_CDC_FTDI +//------------- Enumeration -------------// enum { - CONFIG_FTDI_RESET = 0, - CONFIG_FTDI_MODEM_CTRL, - CONFIG_FTDI_SET_BAUDRATE, - CONFIG_FTDI_SET_DATA, - CONFIG_FTDI_COMPLETE + CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, + CONFIG_ACM_SET_LINE_CODING, + CONFIG_ACM_COMPLETE, }; -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { - // FTDI Interface includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { + uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len; - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); + p_cdc->serial_drid = SERIAL_DRIVER_ACM; - TU_LOG_DRV("FTDI opened\r\n"); - p_cdc->serial_drid = SERIAL_DRIVER_FTDI; + //------------- Control Interface -------------// + uint8_t const* p_desc = tu_desc_next(itf_desc); - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + // Communication Functional Descriptors + while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { + if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) { + // save ACM bmCapabilities + p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities; + } - // data endpoints expected to be in pairs - return open_ep_stream_pair(p_cdc, desc_ep); + p_desc = tu_desc_next(p_desc); + } + + // Open notification endpoint of control interface if any + if (itf_desc->bNumEndpoints == 1) { + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); + tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc; + + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + + p_desc = tu_desc_next(p_desc); + } + + //------------- Data Interface (if any) -------------// + if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && + (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) { + // next to endpoint descriptor + p_desc = tu_desc_next(p_desc); + + // data endpoints expected to be in pairs + TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc)); + } + + return true; } +static void acm_process_config(tuh_xfer_t* xfer) { + uintptr_t const state = xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + + switch (state) { + case CONFIG_ACM_SET_CONTROL_LINE_STATE: + #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + if (p_cdc->acm_capability.support_line_request) { + TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); + break; + } + #endif + TU_ATTR_FALLTHROUGH; + + case CONFIG_ACM_SET_LINE_CODING: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + if (p_cdc->acm_capability.support_line_request) { + cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),); + break; + } + #endif + TU_ATTR_FALLTHROUGH; + + case CONFIG_ACM_COMPLETE: + // itf_num+1 to account for data interface as well + set_config_complete(p_cdc, idx, itf_num + 1); + break; + + default: + break; + } +} + +//--------------------------------------------------------------------+ +// FTDI +//--------------------------------------------------------------------+ +#if CFG_TUH_CDC_FTDI + +static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud); + +//------------- Control Request -------------// + // set request without data static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { @@ -1014,6 +996,20 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); } +//------------- Driver API -------------// + +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); + TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); + + p_cdc->user_control_cb = complete_cb; + p_cdc->requested_line_coding.bit_rate = baudrate; + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, + complete_cb ? cdch_internal_control_complete : NULL, user_data)); + + return true; +} + static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) p_cdc; @@ -1043,40 +1039,32 @@ static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state return true; } -static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { - const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; - uint32_t divisor; - - /* divisor shifted 3 bits to the left */ - uint32_t divisor3 = base / (2 * baud); - divisor = (divisor3 >> 3); - divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; +//------------- Enumeration -------------// - /* Deal with special cases for highest baud rates. */ - if (divisor == 1) { /* 1.0 */ - divisor = 0; - } - else if (divisor == 0x4001) { /* 1.5 */ - divisor = 1; - } +enum { + CONFIG_FTDI_RESET = 0, + CONFIG_FTDI_MODEM_CTRL, + CONFIG_FTDI_SET_BAUDRATE, + CONFIG_FTDI_SET_DATA, + CONFIG_FTDI_COMPLETE +}; - return divisor; -} +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { + // FTDI Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); -static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { - return ftdi_232bm_baud_base_to_divisor(baud, 48000000u); -} + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); - TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); + TU_LOG_DRV("FTDI opened\r\n"); + p_cdc->serial_drid = SERIAL_DRIVER_FTDI; - p_cdc->user_control_cb = complete_cb; - p_cdc->requested_line_coding.bit_rate = baudrate; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, - complete_cb ? cdch_internal_control_complete : NULL, user_data)); + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); - return true; + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); } static void ftdi_process_config(tuh_xfer_t* xfer) { @@ -1131,39 +1119,40 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { } } -#endif +//------------- Helper -------------// -//--------------------------------------------------------------------+ -// CP210x -//--------------------------------------------------------------------+ +static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { + const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint32_t divisor; -#if CFG_TUH_CDC_CP210X + /* divisor shifted 3 bits to the left */ + uint32_t divisor3 = base / (2 * baud); + divisor = (divisor3 >> 3); + divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; -enum { - CONFIG_CP210X_IFC_ENABLE = 0, - CONFIG_CP210X_SET_BAUDRATE, - CONFIG_CP210X_SET_LINE_CTL, - CONFIG_CP210X_SET_DTR_RTS, - CONFIG_CP210X_COMPLETE -}; + /* Deal with special cases for highest baud rates. */ + if (divisor == 1) { /* 1.0 */ + divisor = 0; + } + else if (divisor == 0x4001) { /* 1.5 */ + divisor = 1; + } -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { - // CP210x Interface includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + return divisor; +} - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY(p_cdc); +static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { + return ftdi_232bm_baud_base_to_divisor(baud, 48000000u); +} - TU_LOG_DRV("CP210x opened\r\n"); - p_cdc->serial_drid = SERIAL_DRIVER_CP210X; +#endif - // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); +//--------------------------------------------------------------------+ +// CP210x +//--------------------------------------------------------------------+ +#if CFG_TUH_CDC_CP210X - // data endpoints expected to be in pairs - return open_ep_stream_pair(p_cdc, desc_ep); -} +//------------- Control Request -------------// static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { @@ -1202,14 +1191,7 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); } -static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // TODO implement later - (void) p_cdc; - (void) line_coding; - (void) complete_cb; - (void) user_data; - return false; -} +//------------- Driver API -------------// static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate); @@ -1231,6 +1213,15 @@ static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, u return false; } +static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // TODO implement later + (void) p_cdc; + (void) line_coding; + (void) complete_cb; + (void) user_data; + return false; +} + static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_DRV("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; @@ -1238,6 +1229,34 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, complete_cb ? cdch_internal_control_complete : NULL, user_data); } +//------------- Enumeration -------------// + +enum { + CONFIG_CP210X_IFC_ENABLE = 0, + CONFIG_CP210X_SET_BAUDRATE, + CONFIG_CP210X_SET_LINE_CTL, + CONFIG_CP210X_SET_DTR_RTS, + CONFIG_CP210X_COMPLETE +}; + +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + // CP210x Interface includes 1 vendor interface + 2 bulk endpoints + TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + TU_LOG_DRV("CP210x opened\r\n"); + p_cdc->serial_drid = SERIAL_DRIVER_CP210X; + + // endpoint pair + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + + // data endpoints expected to be in pairs + return open_ep_stream_pair(p_cdc, desc_ep); +} + static void cp210x_process_config(tuh_xfer_t* xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); @@ -1296,7 +1315,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits); static uint16_t ch34x_get_divisor_prescaler(uint32_t baval); -//------------- control request -------------// +//------------- Control Request -------------// static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -1471,6 +1490,7 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, } //------------- Enumeration -------------// + enum { CONFIG_CH34X_READ_VERSION = 0, CONFIG_CH34X_SERIAL_INIT, @@ -1565,7 +1585,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { } } -//------------- CH34x helper -------------// +//------------- Helper -------------// // calculate divisor and prescaler for baudrate, return it as 16-bit combined value static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { @@ -1654,7 +1674,6 @@ static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bit return lcr; } - #endif // CFG_TUH_CDC_CH34X #endif -- cgit v1.3.1 From 47777a63050f9438d79364436c25d0f6a80dfd55 Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 20 Feb 2024 22:08:51 +0100 Subject: improved TU_LOGs --- src/class/cdc/cdc_host.c | 86 +++++++++++++++++++++++++++++++----------------- 1 file changed, 55 insertions(+), 31 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 26eb70c9b..856db32ff 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -41,7 +41,11 @@ #define CFG_TUH_CDC_LOG_LEVEL CFG_TUH_LOG_LEVEL #endif -#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_CDC(TXT,DADDR,ITF_NUM,NAME,...) TU_LOG_DRV("[:%u:%u] CDCh %s " TXT "\r\n", \ + DADDR, ITF_NUM, NAME, ##__VA_ARGS__) +#define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ + serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) //--------------------------------------------------------------------+ // Host CDC Interface @@ -169,6 +173,9 @@ typedef struct { bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + uint8_t const * name; + #endif } cdch_serial_driver_t; // Note driver list must be in the same order as SERIAL_DRIVER enum @@ -181,7 +188,10 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_control_line_state = acm_set_control_line_state, .set_baudrate = acm_set_baudrate, .set_data_format = acm_set_data_format, - .set_line_coding = acm_set_line_coding + .set_line_coding = acm_set_line_coding, + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + .name = (uint8_t const *) "ACM" + #endif }, #if CFG_TUH_CDC_FTDI @@ -193,7 +203,10 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_control_line_state = ftdi_sio_set_modem_ctrl, .set_baudrate = ftdi_sio_set_baudrate, .set_data_format = ftdi_set_data_format, - .set_line_coding = ftdi_set_line_coding + .set_line_coding = ftdi_set_line_coding, + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + .name = (uint8_t const *) "FTDI" + #endif }, #endif @@ -206,7 +219,10 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, .set_data_format = cp210x_set_data_format, - .set_line_coding = cp210x_set_line_coding + .set_line_coding = cp210x_set_line_coding, + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + .name = (uint8_t const *) "CP210x" + #endif }, #endif @@ -219,7 +235,10 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, .set_data_format = ch34x_set_data_format, - .set_line_coding = ch34x_set_line_coding + .set_line_coding = ch34x_set_line_coding, + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + .name = (uint8_t const *) "CH34x" + #endif }, #endif }; @@ -408,8 +427,10 @@ static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) cdch_interface_t* p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); uint16_t const value = tu_le16toh(xfer->setup->wValue); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); - if (xfer->result == XFER_RESULT_SUCCESS) { + if (success) { switch (p_cdc->serial_drid) { case SERIAL_DRIVER_ACM: switch (xfer->setup->bRequest) { @@ -525,6 +546,7 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer) { bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set control line state line_state = %u", line_state); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if (complete_cb) { @@ -548,6 +570,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set baudrate = %lu", baudrate); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if (complete_cb) { @@ -572,6 +595,8 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set data format data_bits = %u parity = %u stop_bits = %u (indexes!)", + data_bits, parity, stop_bits); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if (complete_cb) { @@ -597,6 +622,8 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set line coding baudrate = %lu data_bits = %u parity = %u stop_bits = %u (indexes!)", + line_coding->bit_rate, line_coding->data_bits, line_coding->parity, line_coding->stop_bits); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; if ( complete_cb ) { @@ -641,7 +668,7 @@ void cdch_close(uint8_t daddr) { for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { cdch_interface_t* p_cdc = &cdch_data[idx]; if (p_cdc->daddr == daddr) { - TU_LOG_DRV(" CDCh close addr = %u index = %u\r\n", daddr, idx); + TU_LOG_P_CDC("close"); // Invoke application callback if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx); @@ -722,33 +749,42 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; + cdch_serial_driver_t const * driver_detected = NULL; // For CDC: only support ACM subclass // Note: Protocol 0xFF can be RNDIS device if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { - return acm_open(daddr, itf_desc, max_len); - } - else if (SERIAL_DRIVER_COUNT > 1 && - TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { + driver_detected = &serial_drivers[0]; + } else if (SERIAL_DRIVER_COUNT > 1 && TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { - cdch_serial_driver_t const* driver = &serial_drivers[dr]; + cdch_serial_driver_t const * driver = &serial_drivers[dr]; for (size_t i = 0; i < driver->vid_pid_count; i++) { if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { - return driver->open(daddr, itf_desc, max_len); + driver_detected = driver; + break; } } + if (driver_detected) { + break; + } } } + if (driver_detected) { + TU_LOG_CDC("open", daddr, itf_desc->bInterfaceNumber, driver_detected->name); + bool ret = driver_detected->open(daddr, itf_desc, max_len); + return ret; + } + return false; } static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { - TU_LOG_DRV("CDCh Set Configure complete\r\n"); + TU_LOG_P_CDC("set config complete"); p_cdc->mounted = true; if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); @@ -762,6 +798,10 @@ static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t i bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set config"); // fake transfer to kick-off process tuh_xfer_t xfer; @@ -770,10 +810,6 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { xfer.setup = &request; xfer.user_data = 0; // initial state - uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - serial_drivers[p_cdc->serial_drid].process_set_config(&xfer); return true; } @@ -786,7 +822,6 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); - TU_LOG_DRV("CDC ACM Set Control Line State\r\n"); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -816,8 +851,6 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st } static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC ACM Set Line Conding\r\n"); - tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -850,7 +883,6 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC ACM Set Data Format\r\n"); cdc_line_coding_t line_coding; line_coding.bit_rate = p_cdc->line_coding.bit_rate; @@ -1000,7 +1032,6 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); - TU_LOG_DRV("CDC FTDI Set BaudRate = %lu, divisor = 0x%04x\r\n", baudrate, divisor); p_cdc->user_control_cb = complete_cb; p_cdc->requested_line_coding.bit_rate = baudrate; @@ -1032,7 +1063,6 @@ static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t cons } static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC FTDI Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, complete_cb ? cdch_internal_control_complete : NULL, user_data)); @@ -1057,7 +1087,6 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - TU_LOG_DRV("FTDI opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_FTDI; // endpoint pair @@ -1194,7 +1223,6 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe //------------- Driver API -------------// static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC CP210x Set BaudRate = %lu\r\n", baudrate); uint32_t baud_le = tu_htole32(baudrate); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, @@ -1223,7 +1251,6 @@ static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t co } static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_LOG_DRV("CDC CP210x Set Control Line State\r\n"); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, complete_cb ? cdch_internal_control_complete : NULL, user_data); @@ -1247,7 +1274,6 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); - TU_LOG_DRV("CP210x opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_CP210X; // endpoint pair @@ -1508,7 +1534,6 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uin cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY (p_cdc); - TU_LOG_DRV ("CH34x opened\r\n"); p_cdc->serial_drid = SERIAL_DRIVER_CH34X; tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc); @@ -1538,14 +1563,13 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CH34X_READ_VERSION: - TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr); TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); break; case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t const version = xfer->buffer[0]; - TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version); + TU_LOG_P_CDC("Chip Version = %02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); // init CH34x with line coding -- cgit v1.3.1 From 829ea52873387f6fe269c44089c339cfd6d7c64e Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 08:56:15 +0100 Subject: splitted cdch_internal_control_complete() into driver's _internal_control_complete() and moved them into driver's sections. no functional change --- src/class/cdc/cdc_host.c | 289 +++++++++++++++++++++++++---------------------- 1 file changed, 154 insertions(+), 135 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 856db32ff..e39122e8f 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -286,7 +286,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep); static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); -static void cdch_internal_control_complete(tuh_xfer_t* xfer); //--------------------------------------------------------------------+ // APPLICATION API @@ -422,127 +421,6 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ -static void process_internal_control_complete(tuh_xfer_t* xfer, uint8_t itf_num) { - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - uint16_t const value = tu_le16toh(xfer->setup->wValue); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); - - if (success) { - switch (p_cdc->serial_drid) { - case SERIAL_DRIVER_ACM: - switch (xfer->setup->bRequest) { - case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = (uint8_t) value; - break; - - case CDC_REQUEST_SET_LINE_CODING: { - uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); - memcpy(&p_cdc->line_coding, xfer->buffer, len); - break; - } - - default: break; - } - break; - - #if CFG_TUH_CDC_FTDI - case SERIAL_DRIVER_FTDI: - switch (xfer->setup->bRequest) { - case FTDI_SIO_MODEM_CTRL: - p_cdc->line_state = (uint8_t) value; - break; - - case FTDI_SIO_SET_BAUD_RATE: - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - break; - - default: break; - } - break; - #endif - - #if CFG_TUH_CDC_CP210X - case SERIAL_DRIVER_CP210X: - switch(xfer->setup->bRequest) { - case CP210X_SET_MHS: - p_cdc->line_state = (uint8_t) value; - break; - - case CP210X_SET_BAUDRATE: { - uint32_t baudrate; - memcpy(&baudrate, xfer->buffer, sizeof(uint32_t)); - p_cdc->line_coding.bit_rate = tu_le32toh(baudrate); - break; - } - - default: break; - } - break; - #endif - - #if CFG_TUH_CDC_CH34X - case SERIAL_DRIVER_CH34X: - switch (xfer->setup->bRequest) { - case CH34X_REQ_WRITE_REG: - // register write request - switch (value) { - case CH34X_REG16_DIVISOR_PRESCALER: - // baudrate - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - break; - - case CH32X_REG16_LCR2_LCR: - // data format - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; - break; - - default: break; - } - break; - - case CH34X_REQ_MODEM_CTRL: { - // set modem controls RTS/DTR request. Note: signals are inverted - uint16_t const modem_signal = ~value; - if (modem_signal & CH34X_BIT_RTS) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; - } - - if (modem_signal & CH34X_BIT_DTR) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; - } - break; - } - - default: break; - } - break; - #endif - - default: break; - } - } - - xfer->complete_cb = p_cdc->user_control_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); - } -} - -// internal control complete to update state such as line state, encoding -static void cdch_internal_control_complete(tuh_xfer_t* xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - process_internal_control_complete(xfer, itf_num); -} - bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t* p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); @@ -820,6 +698,36 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { //------------- Driver API -------------// +// internal control complete to update state such as line state, encoding +static void acm_internal_control_complete(tuh_xfer_t * xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); + + if (success) { + switch (xfer->setup->bRequest) { + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + case CDC_REQUEST_SET_LINE_CODING: + uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); + memcpy(&p_cdc->line_coding, xfer->buffer, len); + break; + + default: break; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); @@ -842,7 +750,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call + .complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call .user_data = user_data }; @@ -873,7 +781,7 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const .ep_addr = 0, .setup = &request, .buffer = enum_buf, - .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, // complete_cb is NULL for sync call + .complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call .user_data = user_data }; @@ -1030,13 +938,42 @@ static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, u //------------- Driver API -------------// +// internal control complete to update state such as line state, line_coding +static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); + + if (success) { + switch (xfer->setup->bRequest) { + case FTDI_SIO_MODEM_CTRL: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + case FTDI_SIO_SET_BAUD_RATE: + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + break; + + default: break; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); p_cdc->user_control_cb = complete_cb; p_cdc->requested_line_coding.bit_rate = baudrate; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, - complete_cb ? cdch_internal_control_complete : NULL, user_data)); + complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } @@ -1065,7 +1002,7 @@ static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t cons static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, - complete_cb ? cdch_internal_control_complete : NULL, user_data)); + complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } @@ -1222,11 +1159,42 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe //------------- Driver API -------------// +// internal control complete to update state such as line state, encoding +static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); + + if (success) { + switch(xfer->setup->bRequest) { + case CP210X_SET_MHS: + p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + break; + + case CP210X_SET_BAUDRATE: + uint32_t baudrate; + memcpy(&baudrate, xfer->buffer, sizeof(uint32_t)); + p_cdc->line_coding.bit_rate = tu_le32toh(baudrate); + break; + + default: break; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint32_t baud_le = tu_htole32(baudrate); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, - complete_cb ? cdch_internal_control_complete : NULL, user_data); + complete_cb ? cp210x_internal_control_complete : NULL, user_data); } static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, @@ -1253,7 +1221,7 @@ static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t co static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, - complete_cb ? cdch_internal_control_complete : NULL, user_data); + complete_cb ? cp210x_internal_control_complete : NULL, user_data); } //------------- Enumeration -------------// @@ -1412,9 +1380,60 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void ch34x_control_complete(tuh_xfer_t* xfer) { - // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber - process_internal_control_complete(xfer, 0); +static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { + // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); + + if (success) { + switch (xfer->setup->bRequest) { + case CH34X_REQ_WRITE_REG: + // register write request + switch (tu_le16toh(xfer->setup->wValue)) { + case CH34X_REG16_DIVISOR_PRESCALER: + // baudrate + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + break; + + case CH32X_REG16_LCR2_LCR: + // data format + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + break; + + default: break; + } + break; + + case CH34X_REQ_MODEM_CTRL: + // set modem controls RTS/DTR request. Note: signals are inverted + uint16_t const modem_signal = ~tu_le16toh(xfer->setup->wValue); + if (modem_signal & CH34X_BIT_RTS) { + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; + } else { + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; + } + + if (modem_signal & CH34X_BIT_DTR) { + p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; + } else { + p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; + } + break; + + default: break; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } } static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, @@ -1426,7 +1445,7 @@ static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, ui uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); TU_VERIFY(lcr); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, - complete_cb ? ch34x_control_complete : NULL, user_data)); + complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } @@ -1435,7 +1454,7 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, p_cdc->requested_line_coding.bit_rate = baudrate; p_cdc->user_control_cb = complete_cb; TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate, - complete_cb ? ch34x_control_complete : NULL, user_data)); + complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } @@ -1450,7 +1469,7 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { // stage 1 success, continue to stage 2 p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity, - p_cdc->requested_line_coding.data_bits, ch34x_control_complete, xfer->user_data), ); + p_cdc->requested_line_coding.data_bits, ch34x_internal_control_complete, xfer->user_data), ); } else { // stage 1 failed, notify user xfer->complete_cb = p_cdc->user_control_cb; @@ -1511,7 +1530,7 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, p_cdc->user_control_cb = complete_cb; TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, - complete_cb ? ch34x_control_complete : NULL, user_data)); + complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } -- cgit v1.3.1 From 2f50f5a4263dc3d65f3bf96b593edac5ac271a5a Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 14:59:16 +0100 Subject: changed to use of p_cdc->requested_line_coding --- src/class/cdc/cdc_host.c | 215 +++++++++++++++++++++-------------------------- 1 file changed, 96 insertions(+), 119 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index e39122e8f..b2ba7c9ea 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -63,12 +63,10 @@ typedef struct { cdc_acm_capability_t acm_capability; TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width - uint8_t line_state; // DTR (bit0), RTS (bit1) - - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X - cdc_line_coding_t requested_line_coding; + TU_ATTR_ALIGNED(4) cdc_line_coding_t requested_line_coding; // 1 byte padding - #endif + + uint8_t line_state; // DTR (bit0), RTS (bit1) tuh_xfer_cb_t user_control_cb; @@ -95,9 +93,9 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC]; static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void acm_process_config(tuh_xfer_t* xfer); -static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); //------------- FTDI prototypes -------------// @@ -109,9 +107,9 @@ static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); static void ftdi_process_config(tuh_xfer_t* xfer); -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -124,9 +122,9 @@ static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIS static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); static void cp210x_process_config(tuh_xfer_t* xfer); -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -139,9 +137,9 @@ static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST} static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len); static void ch34x_process_config(tuh_xfer_t* xfer); -static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -170,9 +168,9 @@ typedef struct { bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); void (*const process_set_config)(tuh_xfer_t* xfer); bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_baudrate)(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_data_format)(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_line_coding)(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_baudrate)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_data_format)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_line_coding)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL uint8_t const * name; #endif @@ -276,6 +274,7 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; + p_cdc->line_coding = (cdc_line_coding_t) { 0, 0, 0, 0 }; p_cdc->line_state = 0; return p_cdc; } @@ -451,12 +450,14 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete TU_LOG_P_CDC("set baudrate = %lu", baudrate); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line_coding.bit_rate = baudrate; + if (complete_cb) { - return driver->set_baudrate(p_cdc, baudrate, complete_cb, user_data); + return driver->set_baudrate(p_cdc, complete_cb, user_data); } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_baudrate(p_cdc, baudrate, complete_cb, (uintptr_t) &result); + bool ret = driver->set_baudrate(p_cdc, complete_cb, (uintptr_t) &result); if (user_data) { // user_data is not NULL, return result via user_data @@ -477,12 +478,16 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin data_bits, parity, stop_bits); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line_coding.stop_bits = stop_bits; + p_cdc->requested_line_coding.parity = parity; + p_cdc->requested_line_coding.data_bits = data_bits; + if (complete_cb) { - return driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, user_data); + return driver->set_data_format(p_cdc, complete_cb, user_data); } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_data_format(p_cdc, stop_bits, parity, data_bits, complete_cb, (uintptr_t) &result); + bool ret = driver->set_data_format(p_cdc, complete_cb, (uintptr_t) &result); if (user_data) { // user_data is not NULL, return result via user_data @@ -491,7 +496,7 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); p_cdc->line_coding.stop_bits = stop_bits; - p_cdc->line_coding.parity = parity; + p_cdc->line_coding.parity = parity; p_cdc->line_coding.data_bits = data_bits; return true; } @@ -504,12 +509,14 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, line_coding->bit_rate, line_coding->data_bits, line_coding->parity, line_coding->stop_bits); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line_coding = *line_coding; + if ( complete_cb ) { - return driver->set_line_coding(p_cdc, line_coding, complete_cb, user_data); + return driver->set_line_coding(p_cdc, complete_cb, user_data); } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_line_coding(p_cdc, line_coding, complete_cb, (uintptr_t) &result); + bool ret = driver->set_line_coding(p_cdc, complete_cb, (uintptr_t) &result); if (user_data) { // user_data is not NULL, return result via user_data @@ -714,8 +721,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { break; case CDC_REQUEST_SET_LINE_CODING: - uint16_t const len = tu_min16(sizeof(cdc_line_coding_t), tu_le16toh(xfer->setup->wLength)); - memcpy(&p_cdc->line_coding, xfer->buffer, len); + p_cdc->line_coding = p_cdc->requested_line_coding; break; default: break; @@ -758,7 +764,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st return true; } -static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -773,7 +779,7 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const // use usbh enum buf to hold line coding since user line_coding variable does not live long enough uint8_t* enum_buf = usbh_get_enum_buf(); - memcpy(enum_buf, line_coding, sizeof(cdc_line_coding_t)); + memcpy(enum_buf, &p_cdc->requested_line_coding, sizeof(cdc_line_coding_t)); p_cdc->user_control_cb = complete_cb; tuh_xfer_t xfer = { @@ -789,23 +795,19 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const return true; } -static bool acm_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - - cdc_line_coding_t line_coding; - line_coding.bit_rate = p_cdc->line_coding.bit_rate; - line_coding.stop_bits = stop_bits; - line_coding.parity = parity; - line_coding.data_bits = data_bits; +static bool acm_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; - return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); + return acm_set_line_coding(p_cdc, complete_cb, user_data); } -static bool acm_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; + p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; + p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; TU_VERIFY(p_cdc->acm_capability.support_line_request); - cdc_line_coding_t line_coding = p_cdc->line_coding; - line_coding.bit_rate = baudrate; - return acm_set_line_coding(p_cdc, &line_coding, complete_cb, user_data); + + return acm_set_line_coding(p_cdc, complete_cb, user_data); } //------------- Enumeration -------------// @@ -879,11 +881,11 @@ static void acm_process_config(tuh_xfer_t* xfer) { case CONFIG_ACM_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, &line_coding, acm_process_config, CONFIG_ACM_COMPLETE),); - break; - } + if (p_cdc->acm_capability.support_line_request) { + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(acm_set_line_coding(p_cdc, acm_process_config, CONFIG_ACM_COMPLETE),); + break; + } #endif TU_ATTR_FALLTHROUGH; @@ -902,7 +904,7 @@ static void acm_process_config(tuh_xfer_t* xfer) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_FTDI -static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud); +static uint32_t ftdi_232bm_baud_to_divisor(cdch_interface_t* p_cdc); //------------- Control Request -------------// @@ -967,32 +969,26 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(baudrate); +static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(p_cdc); p_cdc->user_control_cb = complete_cb; - p_cdc->requested_line_coding.bit_rate = baudrate; TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } -static bool ftdi_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) p_cdc; - (void) stop_bits; - (void) parity; - (void) data_bits; (void) complete_cb; (void) user_data; // TODO not implemented yet return false; } -static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) p_cdc; - (void) line_coding; (void) complete_cb; (void) user_data; // TODO not implemented yet @@ -1056,11 +1052,11 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, line_coding.bit_rate, ftdi_process_config, CONFIG_FTDI_SET_DATA),); - break; + p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; + TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA),); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif } @@ -1107,8 +1103,8 @@ static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { return divisor; } -static uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { - return ftdi_232bm_baud_base_to_divisor(baud, 48000000u); +static uint32_t ftdi_232bm_baud_to_divisor(cdch_interface_t* p_cdc) { + return ftdi_232bm_baud_base_to_divisor(p_cdc->requested_line_coding.bit_rate, 48000000u); } #endif @@ -1175,9 +1171,7 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { break; case CP210X_SET_BAUDRATE: - uint32_t baudrate; - memcpy(&baudrate, xfer->buffer, sizeof(uint32_t)); - p_cdc->line_coding.bit_rate = tu_le32toh(baudrate); + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; break; default: break; @@ -1190,29 +1184,24 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint32_t baud_le = tu_htole32(baudrate); +static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); p_cdc->user_control_cb = complete_cb; return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb ? cp210x_internal_control_complete : NULL, user_data); } -static bool cp210x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { (void) p_cdc; - (void) stop_bits; - (void) parity; - (void) data_bits; (void) complete_cb; (void) user_data; // TODO not implemented yet return false; } -static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // TODO implement later (void) p_cdc; - (void) line_coding; (void) complete_cb; (void) user_data; return false; @@ -1265,11 +1254,11 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(cp210x_set_baudrate(p_cdc, line_coding.bit_rate, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),); - break; + p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; + TU_ASSERT(cp210x_set_baudrate(p_cdc, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif } @@ -1306,8 +1295,8 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { #if CFG_TUH_CDC_CH34X -static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits); -static uint16_t ch34x_get_divisor_prescaler(uint32_t baval); +static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc); +static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc); //------------- Control Request -------------// @@ -1368,9 +1357,8 @@ static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16 // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} -static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const div_ps = ch34x_get_divisor_prescaler(baudrate); +static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); TU_VERIFY(div_ps); TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data)); @@ -1436,25 +1424,17 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ch34x_set_data_format(cdch_interface_t* p_cdc, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.stop_bits = stop_bits; - p_cdc->requested_line_coding.parity = parity; - p_cdc->requested_line_coding.data_bits = data_bits; - - uint8_t const lcr = ch34x_get_lcr(stop_bits, parity, data_bits); +static bool ch34x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t const lcr = ch34x_get_lcr(p_cdc); TU_VERIFY(lcr); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } -static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.bit_rate = baudrate; +static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, baudrate, - complete_cb ? ch34x_internal_control_complete : NULL, user_data)); + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } @@ -1468,8 +1448,7 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { if (xfer->result == XFER_RESULT_SUCCESS) { // stage 1 success, continue to stage 2 p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - TU_ASSERT(ch34x_set_data_format(p_cdc, p_cdc->requested_line_coding.stop_bits, p_cdc->requested_line_coding.parity, - p_cdc->requested_line_coding.data_bits, ch34x_internal_control_complete, xfer->user_data), ); + TU_ASSERT(ch34x_set_data_format(p_cdc, ch34x_internal_control_complete, xfer->user_data), ); } else { // stage 1 failed, notify user xfer->complete_cb = p_cdc->user_control_cb; @@ -1480,31 +1459,24 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { } // 2 stages: set baudrate (stage1) + set data format (stage2) -static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding = *line_coding; +static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; if (complete_cb) { // stage 1 set baudrate - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, - ch34x_set_line_coding_stage1_complete, user_data)); + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, ch34x_set_line_coding_stage1_complete, user_data)); } else { // sync call xfer_result_t result; // stage 1 set baudrate - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, line_coding->bit_rate, NULL, (uintptr_t) &result)); + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, NULL, (uintptr_t) &result)); TU_VERIFY(result == XFER_RESULT_SUCCESS); - p_cdc->line_coding.bit_rate = line_coding->bit_rate; + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; // stage 2 set data format - TU_ASSERT(ch34x_set_data_format(p_cdc, line_coding->stop_bits, line_coding->parity, line_coding->data_bits, - NULL, (uintptr_t) &result)); + TU_ASSERT(ch34x_set_data_format(p_cdc, NULL, (uintptr_t) &result)); TU_VERIFY(result == XFER_RESULT_SUCCESS); - p_cdc->line_coding.stop_bits = line_coding->stop_bits; - p_cdc->line_coding.parity = line_coding->parity; - p_cdc->line_coding.data_bits = line_coding->data_bits; // update transfer result, user_data is expected to point to xfer_result_t if (user_data) { @@ -1592,10 +1564,10 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT (version >= 0x30,); // init CH34x with line coding - cdc_line_coding_t const line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; - uint16_t const div_ps = ch34x_get_divisor_prescaler(line_coding.bit_rate); + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; + uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); TU_ASSERT(div_ps, ); - uint8_t const lcr = ch34x_get_lcr(line_coding.stop_bits, line_coding.parity, line_coding.data_bits); + uint8_t const lcr = ch34x_get_lcr(p_cdc); TU_ASSERT(lcr, ); TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); @@ -1604,7 +1576,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SPECIAL_REG_WRITE: // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver - p_cdc->line_coding = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X); + p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); break; @@ -1631,7 +1603,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { //------------- Helper -------------// // calculate divisor and prescaler for baudrate, return it as 16-bit combined value -static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { +static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc) { + uint32_t const baval = p_cdc->requested_line_coding.bit_rate; uint8_t a; uint8_t b; uint32_t c; @@ -1680,7 +1653,11 @@ static uint16_t ch34x_get_divisor_prescaler(uint32_t baval) { } // calculate lcr value from data coding -static uint8_t ch34x_get_lcr(uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { +static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { + uint8_t const stop_bits = p_cdc->requested_line_coding.stop_bits; + uint8_t const parity = p_cdc->requested_line_coding.parity; + uint8_t const data_bits = p_cdc->requested_line_coding.data_bits; + uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0); lcr |= (uint8_t) (data_bits - 5); -- cgit v1.3.1 From 7dd435cb877f5d3e0b9576dfcdb8c40e9a03c399 Mon Sep 17 00:00:00 2001 From: IngHK Date: Tue, 20 Feb 2024 20:45:50 +0100 Subject: changed to use of p_cdc->requested_line_state --- src/class/cdc/cdc_host.c | 82 ++++++++++++++++++++++-------------------------- 1 file changed, 38 insertions(+), 44 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b2ba7c9ea..0af429e4b 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -67,6 +67,7 @@ typedef struct { // 1 byte padding uint8_t line_state; // DTR (bit0), RTS (bit1) + uint8_t requested_line_state; tuh_xfer_cb_t user_control_cb; @@ -96,7 +97,7 @@ static void acm_process_config(tuh_xfer_t* xfer); static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI @@ -110,7 +111,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer); static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CP210X prototypes -------------// @@ -125,7 +126,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer); static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CH34x prototypes -------------// @@ -140,7 +141,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer); static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- Common -------------// @@ -167,7 +168,7 @@ typedef struct { uint16_t const vid_pid_count; bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); void (*const process_set_config)(tuh_xfer_t* xfer); - bool (*const set_control_line_state)(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_control_line_state)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_baudrate)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_data_format)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_line_coding)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -426,12 +427,14 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_LOG_P_CDC("set control line state line_state = %u", line_state); cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line_state = (uint8_t) line_state; + if (complete_cb) { - return driver->set_control_line_state(p_cdc, line_state, complete_cb, user_data); + return driver->set_control_line_state(p_cdc, complete_cb, user_data); } else { // blocking xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_control_line_state(p_cdc, line_state, complete_cb, (uintptr_t) &result); + bool ret = driver->set_control_line_state(p_cdc, complete_cb, (uintptr_t) &result); if (user_data) { // user_data is not NULL, return result via user_data @@ -717,7 +720,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { if (success) { switch (xfer->setup->bRequest) { case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + p_cdc->line_state = p_cdc->requested_line_state; break; case CDC_REQUEST_SET_LINE_CODING: @@ -734,7 +737,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = { @@ -744,7 +747,7 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, uint16_t line_st .direction = TUSB_DIR_OUT }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16(line_state), + .wValue = tu_htole16(p_cdc->requested_line_state), .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = 0 }; @@ -872,10 +875,11 @@ static void acm_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - TU_ASSERT(acm_set_control_line_state(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); - break; - } + if (p_cdc->acm_capability.support_line_request) { + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); + break; + } #endif TU_ATTR_FALLTHROUGH; @@ -952,7 +956,7 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { if (success) { switch (xfer->setup->bRequest) { case FTDI_SIO_MODEM_CTRL: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + p_cdc->line_state = p_cdc->requested_line_state; break; case FTDI_SIO_SET_BAUD_RATE: @@ -995,9 +999,9 @@ static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete return false; } -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | line_state, + TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | p_cdc->requested_line_state, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } @@ -1044,10 +1048,11 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_MODEM_CTRL: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); - break; + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_FTDI_SET_BAUDRATE: { @@ -1167,7 +1172,7 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { if (success) { switch(xfer->setup->bRequest) { case CP210X_SET_MHS: - p_cdc->line_state = (uint8_t) tu_le16toh(xfer->setup->wValue); + p_cdc->line_state = p_cdc->requested_line_state; break; case CP210X_SET_BAUDRATE: @@ -1207,9 +1212,9 @@ static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t comple return false; } -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | line_state, NULL, 0, + return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | p_cdc->requested_line_state, NULL, 0, complete_cb ? cp210x_internal_control_complete : NULL, user_data); } @@ -1273,10 +1278,11 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_SET_DTR_RTS: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, cp210x_process_config, CONFIG_CP210X_COMPLETE),); - break; + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, cp210x_process_config, CONFIG_CP210X_COMPLETE),); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_CP210X_COMPLETE: @@ -1399,19 +1405,7 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { break; case CH34X_REQ_MODEM_CTRL: - // set modem controls RTS/DTR request. Note: signals are inverted - uint16_t const modem_signal = ~tu_le16toh(xfer->setup->wValue); - if (modem_signal & CH34X_BIT_RTS) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_RTS; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_RTS; - } - - if (modem_signal & CH34X_BIT_DTR) { - p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR; - } else { - p_cdc->line_state &= (uint8_t) ~CDC_CONTROL_LINE_STATE_DTR; - } + p_cdc->line_state = p_cdc->requested_line_state; break; default: break; @@ -1487,13 +1481,12 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complet return true; } -static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint8_t control = 0; - if (line_state & CDC_CONTROL_LINE_STATE_RTS) { + if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_RTS) { control |= CH34X_BIT_RTS; } - if (line_state & CDC_CONTROL_LINE_STATE_DTR) { + if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_DTR) { control |= CH34X_BIT_DTR; } @@ -1587,7 +1580,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) - TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),); + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, ch34x_process_config, CONFIG_CH34X_COMPLETE),); break; case CONFIG_CH34X_COMPLETE: -- cgit v1.3.1 From dcadf8c2a2a79b838cfccf32612fadcb15216c77 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 15:04:24 +0100 Subject: created set_function_call() --- src/class/cdc/cdc_host.c | 108 +++++++++++++++++++++-------------------------- 1 file changed, 47 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 0af429e4b..6a650071d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -421,115 +421,101 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t* p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set control line state line_state = %u", line_state); - cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; - - p_cdc->requested_line_state = (uint8_t) line_state; - +// call of (non-)blocking set-functions (to set line state, baudrate, ...) +static bool set_function_call ( + cdch_interface_t * p_cdc, + bool (*set_function)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { if (complete_cb) { - return driver->set_control_line_state(p_cdc, complete_cb, user_data); + // non-blocking with call back + return set_function(p_cdc, complete_cb, user_data); } else { // blocking - xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_control_line_state(p_cdc, complete_cb, (uintptr_t) &result); + xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL + bool ret = set_function(p_cdc, NULL, (uintptr_t) &result); if (user_data) { - // user_data is not NULL, return result via user_data - *((xfer_result_t*) user_data) = result; + *((xfer_result_t *) user_data) = result; } - TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); + return (ret && result == XFER_RESULT_SUCCESS); + } +} + +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t * p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_P_CDC("set control line state line_state = %u", line_state); + cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; + + p_cdc->requested_line_state = (uint8_t) line_state; + + bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); + + if (ret && !complete_cb) { p_cdc->line_state = (uint8_t) line_state; - return true; } + + return ret; } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set baudrate = %lu", baudrate); - cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.bit_rate = baudrate; - if (complete_cb) { - return driver->set_baudrate(p_cdc, complete_cb, user_data); - } else { - // blocking - xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_baudrate(p_cdc, complete_cb, (uintptr_t) &result); - - if (user_data) { - // user_data is not NULL, return result via user_data - *((xfer_result_t*) user_data) = result; - } + bool ret = set_function_call(p_cdc, driver->set_baudrate, complete_cb, user_data); - TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); + if (ret && !complete_cb) { p_cdc->line_coding.bit_rate = baudrate; - return true; } + + return ret; } bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set data format data_bits = %u parity = %u stop_bits = %u (indexes!)", data_bits, parity, stop_bits); - cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.stop_bits = stop_bits; p_cdc->requested_line_coding.parity = parity; p_cdc->requested_line_coding.data_bits = data_bits; - if (complete_cb) { - return driver->set_data_format(p_cdc, complete_cb, user_data); - } else { - // blocking - xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_data_format(p_cdc, complete_cb, (uintptr_t) &result); - - if (user_data) { - // user_data is not NULL, return result via user_data - *((xfer_result_t*) user_data) = result; - } + bool ret = set_function_call(p_cdc, driver->set_data_format, complete_cb, user_data); - TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); + if (ret && !complete_cb) { p_cdc->line_coding.stop_bits = stop_bits; p_cdc->line_coding.parity = parity; p_cdc->line_coding.data_bits = data_bits; - return true; } + + return ret; } -bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t* p_cdc = get_itf(idx); +bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const * line_coding, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set line coding baudrate = %lu data_bits = %u parity = %u stop_bits = %u (indexes!)", line_coding->bit_rate, line_coding->data_bits, line_coding->parity, line_coding->stop_bits); - cdch_serial_driver_t const* driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding = *line_coding; - if ( complete_cb ) { - return driver->set_line_coding(p_cdc, complete_cb, user_data); - } else { - // blocking - xfer_result_t result = XFER_RESULT_INVALID; - bool ret = driver->set_line_coding(p_cdc, complete_cb, (uintptr_t) &result); + bool ret = set_function_call(p_cdc, driver->set_line_coding, complete_cb, user_data); - if (user_data) { - // user_data is not NULL, return result via user_data - *((xfer_result_t*) user_data) = result; - } - - TU_VERIFY(ret && result == XFER_RESULT_SUCCESS); + if (ret && !complete_cb) { p_cdc->line_coding = *line_coding; - return true; } + + return ret; } //--------------------------------------------------------------------+ -- cgit v1.3.1 From ea86bbe5f742344b307e52945c0977143522810b Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 21 Feb 2024 16:30:02 +0100 Subject: added continue enum after config fail --- src/class/cdc/cdc_host.c | 109 +++++++++++++++++++++++++++++------------------ 1 file changed, 67 insertions(+), 42 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 6a650071d..226f389e3 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -47,6 +47,16 @@ #define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) +#define TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) \ + do { \ + if (!(_cond)) { _MESS_FAILED(); TU_BREAKPOINT(); set_config_complete(idx, _itf_offset, false); } \ + } while(0) + +#define TU_ASSERT_COMPLETE_1ARGS(_cond) TU_ASSERT_COMPLETE_DEFINE(_cond, 0) +#define TU_ASSERT_COMPLETE_2ARGS(_cond, _itf_offset) TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) + +#define TU_ASSERT_COMPLETE(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_COMPLETE_2ARGS, TU_ASSERT_COMPLETE_1ARGS, _dummy)(__VA_ARGS__) + //--------------------------------------------------------------------+ // Host CDC Interface //--------------------------------------------------------------------+ @@ -285,7 +295,6 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const } static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep); -static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num); //--------------------------------------------------------------------+ // APPLICATION API @@ -657,16 +666,26 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d return false; } -static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { - TU_LOG_P_CDC("set config complete"); - p_cdc->mounted = true; - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); +static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + TU_LOG_P_CDC("set config complete success = %u", success); - // Prepare for incoming data - tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + if (success) { + p_cdc->mounted = true; + if (tuh_cdc_mount_cb) { + tuh_cdc_mount_cb(idx); + } + // Prepare for incoming data + tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + } else { + // clear the interface entry + p_cdc->daddr = 0; + p_cdc->bInterfaceNumber = 0; + } // notify usbh that driver enumeration is complete - usbh_driver_set_config_complete(p_cdc->daddr, itf_num); + usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset); } bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { @@ -856,14 +875,14 @@ static void acm_process_config(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS, 1); switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING),); + TU_ASSERT_COMPLETE(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING), 1); break; } #endif @@ -873,7 +892,7 @@ static void acm_process_config(tuh_xfer_t* xfer) { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM if (p_cdc->acm_capability.support_line_request) { p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, acm_process_config, CONFIG_ACM_COMPLETE),); + TU_ASSERT_COMPLETE(acm_set_line_coding(p_cdc, acm_process_config, CONFIG_ACM_COMPLETE), 1); break; } #endif @@ -881,10 +900,11 @@ static void acm_process_config(tuh_xfer_t* xfer) { case CONFIG_ACM_COMPLETE: // itf_num+1 to account for data interface as well - set_config_complete(p_cdc, idx, itf_num + 1); + set_config_complete(idx, 1, true); break; default: + set_config_complete(idx, 1, false); break; } } @@ -1024,18 +1044,18 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); + TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch(state) { // Note may need to read FTDI eeprom case CONFIG_FTDI_RESET: - TU_ASSERT(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL),); + TU_ASSERT_COMPLETE(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); break; case CONFIG_FTDI_MODEM_CTRL: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(ftdi_sio_set_modem_ctrl(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE),); + TU_ASSERT_COMPLETE(ftdi_sio_set_modem_ctrl(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE)); break; #else TU_ATTR_FALLTHROUGH; @@ -1044,7 +1064,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { case CONFIG_FTDI_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; - TU_ASSERT(ftdi_sio_set_baudrate(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA),); + TU_ASSERT_COMPLETE(ftdi_sio_set_baudrate(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA)); break; #else TU_ATTR_FALLTHROUGH; @@ -1055,7 +1075,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { #if 0 // TODO set data format #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE),); + TU_ASSERT_COMPLETE(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE)); break; #endif #endif @@ -1064,10 +1084,11 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { } case CONFIG_FTDI_COMPLETE: - set_config_complete(p_cdc, idx, itf_num); + set_config_complete(idx, 0, true); break; default: + set_config_complete(idx, 0, false); break; } } @@ -1150,8 +1171,8 @@ static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfe static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC("control complete success = %u", success); @@ -1236,17 +1257,17 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE),); + TU_ASSERT_COMPLETE(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE)); break; case CONFIG_CP210X_SET_BAUDRATE: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; - TU_ASSERT(cp210x_set_baudrate(p_cdc, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL),); + TU_ASSERT_COMPLETE(cp210x_set_baudrate(p_cdc, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL)); break; #else TU_ATTR_FALLTHROUGH; @@ -1265,17 +1286,19 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { case CONFIG_CP210X_SET_DTR_RTS: #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(cp210x_set_modem_ctrl(p_cdc, cp210x_process_config, CONFIG_CP210X_COMPLETE),); + TU_ASSERT_COMPLETE(cp210x_set_modem_ctrl(p_cdc, cp210x_process_config, CONFIG_CP210X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; #endif case CONFIG_CP210X_COMPLETE: - set_config_complete(p_cdc, idx, itf_num); + set_config_complete(idx, 0, true); break; - default: break; + default: + set_config_complete(idx, 0, false); + break; } } @@ -1361,11 +1384,11 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t comp // internal control complete to update state such as line state, encoding static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { - // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC("control complete success = %u", success); @@ -1526,14 +1549,14 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); + TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); uintptr_t const state = xfer->user_data; uint8_t buffer[2]; // TODO remove - TU_ASSERT (p_cdc,); - TU_ASSERT (xfer->result == XFER_RESULT_SUCCESS,); switch (state) { case CONFIG_CH34X_READ_VERSION: - TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),); + TU_ASSERT_COMPLETE(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, + ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); break; case CONFIG_CH34X_SERIAL_INIT: { @@ -1541,41 +1564,43 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { uint8_t const version = xfer->buffer[0]; TU_LOG_P_CDC("Chip Version = %02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD - TU_ASSERT (version >= 0x30,); + TU_ASSERT_COMPLETE(version >= 0x30); // init CH34x with line coding p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); - TU_ASSERT(div_ps, ); + TU_ASSERT_COMPLETE(div_ps); uint8_t const lcr = ch34x_get_lcr(p_cdc); - TU_ASSERT(lcr, ); - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, - ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),); + TU_ASSERT_COMPLETE(lcr); + TU_ASSERT_COMPLETE(ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, + ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE)); break; } case CONFIG_CH34X_SPECIAL_REG_WRITE: // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; - TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),); + TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, + ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control - TU_ASSERT (ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),); + TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, + ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); break; case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, ch34x_process_config, CONFIG_CH34X_COMPLETE),); + TU_ASSERT_COMPLETE(ch34x_set_modem_ctrl(p_cdc, ch34x_process_config, CONFIG_CH34X_COMPLETE)); break; case CONFIG_CH34X_COMPLETE: - set_config_complete(p_cdc, idx, itf_num); + set_config_complete(idx, 0, true); break; default: - TU_ASSERT (false,); + set_config_complete(idx, 0, false); break; } } -- cgit v1.3.1 From 22a12c76689399bd1a67e52531171876e5d88a28 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 09:28:06 +0100 Subject: improved ACM checks --- src/class/cdc/cdc_host.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 226f389e3..ae8245b0e 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -773,6 +773,11 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t co } static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_VERIFY(p_cdc->acm_capability.support_line_request); + TU_VERIFY(p_cdc->requested_line_coding.data_bits && p_cdc->requested_line_coding.bit_rate); + TU_VERIFY((p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8) || + p_cdc->requested_line_coding.data_bits == 16); + tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -813,7 +818,6 @@ static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; - TU_VERIFY(p_cdc->acm_capability.support_line_request); return acm_set_line_coding(p_cdc, complete_cb, user_data); } -- cgit v1.3.1 From 138567af3e39e08742b3d1edf5b83d27d8526a4a Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 18 Feb 2024 20:33:54 +0100 Subject: fixed #2448 CH34x ch34x_set_line_coding() callback bug --- src/class/cdc/cdc_host.c | 127 ++++++++++++++++++++++++++++------------------- 1 file changed, 75 insertions(+), 52 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ae8245b0e..f6804ca2b 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -80,6 +80,9 @@ typedef struct { uint8_t requested_line_state; tuh_xfer_cb_t user_control_cb; + #if CFG_TUH_CDC_CH34X + tuh_xfer_cb_t requested_complete_cb; + #endif struct { tu_edpt_stream_t tx; @@ -1376,12 +1379,33 @@ static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16 // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} -static bool ch34x_write_reg_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_write_reg_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t const lcr = ch34x_get_lcr(p_cdc); + TU_VERIFY(lcr); + + return ch34x_write_reg(p_cdc, CH32X_REG16_LCR2_LCR, lcr, complete_cb, user_data); +} + +static bool ch34x_write_reg_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); TU_VERIFY(div_ps); - TU_ASSERT(ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, - complete_cb, user_data)); - return true; + + return ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data); +} + +static bool ch34x_modem_ctrl_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t control = 0; + if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_RTS) { + control |= CH34X_BIT_RTS; + } + if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_DTR) { + control |= CH34X_BIT_DTR; + } + + // CH34x signals are inverted + control = ~control; + + return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } //------------- Driver API -------------// @@ -1431,34 +1455,34 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ch34x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t const lcr = ch34x_get_lcr(p_cdc); - TU_VERIFY(lcr); - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, CH32X_REG16_LCR2_LCR, lcr, - complete_cb ? ch34x_internal_control_complete : NULL, user_data)); +static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); + return true; } -static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); + return true; } -static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { - // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber +static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { + // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); if (xfer->result == XFER_RESULT_SUCCESS) { - // stage 1 success, continue to stage 2 - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - TU_ASSERT(ch34x_set_data_format(p_cdc, ch34x_internal_control_complete, xfer->user_data), ); + // stage 1 success, continue with stage 2 + p_cdc->user_control_cb = p_cdc->requested_complete_cb; + ch34x_write_reg_data_format(p_cdc, ch34x_internal_control_complete, xfer->user_data); } else { // stage 1 failed, notify user - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->requested_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } @@ -1466,49 +1490,46 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t* xfer) { } // 2 stages: set baudrate (stage1) + set data format (stage2) -static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; - +static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { if (complete_cb) { // stage 1 set baudrate - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, ch34x_set_line_coding_stage1_complete, user_data)); + p_cdc->requested_complete_cb = complete_cb; + p_cdc->user_control_cb = ch34x_set_line_coding_stage1_complete; + return ch34x_write_reg_baudrate(p_cdc, ch34x_internal_control_complete, user_data); } else { - // sync call - xfer_result_t result; - + // blocking sequence // stage 1 set baudrate - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, NULL, (uintptr_t) &result)); + xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL + bool ret = ch34x_write_reg_baudrate(p_cdc, NULL, (uintptr_t) &result); + + // store/check results + if (user_data) { + *((xfer_result_t*) user_data) = result; + } + TU_ASSERT(ret); TU_VERIFY(result == XFER_RESULT_SUCCESS); + + // overtake baudrate p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; // stage 2 set data format - TU_ASSERT(ch34x_set_data_format(p_cdc, NULL, (uintptr_t) &result)); - TU_VERIFY(result == XFER_RESULT_SUCCESS); + result = XFER_RESULT_INVALID; + ret = ch34x_write_reg_data_format(p_cdc, NULL, (uintptr_t) &result); - // update transfer result, user_data is expected to point to xfer_result_t + // store/check results if (user_data) { *((xfer_result_t*) user_data) = result; } + TU_ASSERT(ret); + return (result == XFER_RESULT_SUCCESS); + // the overtaking of remaining requested_line_coding will be done in tuh_cdc_set_line_coding() } - - return true; } -static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t control = 0; - if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_RTS) { - control |= CH34X_BIT_RTS; - } - if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_DTR) { - control |= CH34X_BIT_DTR; - } - - // CH34x signals are inverted - control = ~control; - +static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, - complete_cb ? ch34x_internal_control_complete : NULL, user_data)); + TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); + return true; } @@ -1549,25 +1570,27 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uin } static void ch34x_process_config(tuh_xfer_t* xfer) { - // CH34x only has 1 interface and use wIndex as payload and not for bInterfaceNumber + // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber + uintptr_t const state = xfer->user_data; uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - uintptr_t const state = xfer->user_data; uint8_t buffer[2]; // TODO remove switch (state) { case CONFIG_CH34X_READ_VERSION: + p_cdc->user_control_cb = ch34x_process_config; // set once for whole process config TU_ASSERT_COMPLETE(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, - ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); + ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); break; case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t const version = xfer->buffer[0]; TU_LOG_P_CDC("Chip Version = %02x", version); - // only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD + // only versions >= 0x30 are tested, below 0x30 seems having other programming + // see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT_COMPLETE(version >= 0x30); // init CH34x with line coding p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; @@ -1584,19 +1607,19 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, - ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); + ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, - ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); + ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); break; case CONFIG_CH34X_MODEM_CONTROL: // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ch34x_set_modem_ctrl(p_cdc, ch34x_process_config, CONFIG_CH34X_COMPLETE)); + TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; case CONFIG_CH34X_COMPLETE: @@ -1668,7 +1691,7 @@ static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { uint8_t const data_bits = p_cdc->requested_line_coding.data_bits; uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; - TU_VERIFY(data_bits >= 5 && data_bits <= 8, 0); + TU_VERIFY(data_bits >= 5 && data_bits <= 8); lcr |= (uint8_t) (data_bits - 5); switch(parity) { @@ -1695,7 +1718,7 @@ static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { } // 1.5 stop bits not supported - TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5, 0); + TU_VERIFY(stop_bits != CDC_LINE_CODING_STOP_BITS_1_5); if (stop_bits == CDC_LINE_CODING_STOP_BITS_2) { lcr |= CH34X_LCR_STOP_BITS_2; } -- cgit v1.3.1 From db511fb2f3df190f538d84d08b6be83746adae0e Mon Sep 17 00:00:00 2001 From: IngHK Date: Mon, 19 Feb 2024 08:05:16 +0100 Subject: fixed CFG_TUH_CDC_LINE_CONTROL_ON_ENUM handling. only set if defined. value 0 is also valid --- src/class/cdc/cdc_host.c | 17 ++++++++++------- src/class/cdc/cdc_host.h | 10 ---------- 2 files changed, 10 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f6804ca2b..850c1fceb 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -886,7 +886,7 @@ static void acm_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING), 1); @@ -1060,7 +1060,7 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { break; case CONFIG_FTDI_MODEM_CTRL: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(ftdi_sio_set_modem_ctrl(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE)); break; @@ -1291,7 +1291,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { } case CONFIG_CP210X_SET_DTR_RTS: - #if CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(cp210x_set_modem_ctrl(p_cdc, cp210x_process_config, CONFIG_CP210X_COMPLETE)); break; @@ -1617,10 +1617,13 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { break; case CONFIG_CH34X_MODEM_CONTROL: - // !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT) - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); - break; + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif case CONFIG_CH34X_COMPLETE: set_config_complete(idx, 0, true); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index d512a23a5..ca6567453 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -37,16 +37,6 @@ // Class Driver Configuration //--------------------------------------------------------------------+ -// Set Line Control state on enumeration/mounted: DTR ( bit 0), RTS (bit 1) -#ifndef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM -#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0 -#endif - -// Set Line Coding on enumeration/mounted, value for cdc_line_coding_t -//#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM -//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } -//#endif - // RX FIFO size #ifndef CFG_TUH_CDC_RX_BUFSIZE #define CFG_TUH_CDC_RX_BUFSIZE USBH_EPSIZE_BULK_MAX -- cgit v1.3.1 From 0b5f85eee0f34a80dd8debe2f764607070293119 Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 21 Feb 2024 17:25:13 +0100 Subject: created set_line_coding_sequence() and void set_line_coding_stage1_complete() to be reused by FTDI & CP210x --- src/class/cdc/cdc_host.c | 131 +++++++++++++++++++++++++++++------------------ 1 file changed, 81 insertions(+), 50 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 850c1fceb..8deeffc37 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -433,6 +433,77 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ +// set line coding using sequence with 2 stages: set baudrate (stage1) + set data format (stage2) +static bool set_line_coding_sequence( + cdch_interface_t * p_cdc, + // control request function to set baudrate + bool (*set_baudrate_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), + // control request function to set data format + bool (*set_data_format_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), + // function to be called after stage 1 completed + void (*set_line_coding_stage1_complete)(tuh_xfer_t * xfer), + // control complete function to be called after request + void (*internal_control_complete)(tuh_xfer_t * xfer), + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + if (complete_cb) { + // non-blocking + // stage 1 set baudrate + p_cdc->requested_complete_cb = complete_cb; // store complete_cb to be used in set_line_coding_stage1_complete() + p_cdc->user_control_cb = set_line_coding_stage1_complete; + return set_baudrate_request(p_cdc, internal_control_complete, user_data); + } else { + // blocking sequence + // stage 1 set baudrate + xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL + bool ret = set_baudrate_request(p_cdc, NULL, (uintptr_t) &result); + + if (user_data) { + *((xfer_result_t *) user_data) = result; + } + + TU_ASSERT(ret); + TU_VERIFY(result == XFER_RESULT_SUCCESS); + + // overtake baudrate after successful request + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + + // stage 2 set data format + result = XFER_RESULT_INVALID; + ret = set_data_format_request(p_cdc, NULL, (uintptr_t) &result); + + if (user_data) { + *((xfer_result_t *) user_data) = result; + } + + TU_ASSERT(ret); + return (result == XFER_RESULT_SUCCESS); + // the overtaking of remaining requested_line_coding will be done in tuh_cdc_set_line_coding() + } +} + +static void set_line_coding_stage1_complete( + tuh_xfer_t * xfer, uint8_t const itf_num, + // control request function to set data format + bool (*set_data_format_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), + // control complete function to be called after request + void (*internal_control_complete)(tuh_xfer_t * xfer)) { + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + + if (xfer->result == XFER_RESULT_SUCCESS) { + // stage 1 success, continue with stage 2 + p_cdc->user_control_cb = p_cdc->requested_complete_cb; + set_data_format_request(p_cdc, internal_control_complete, xfer->user_data); + } else { + // stage 1 failed, notify user + xfer->complete_cb = p_cdc->requested_complete_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } + } +} + // call of (non-)blocking set-functions (to set line state, baudrate, ...) static bool set_function_call ( cdch_interface_t * p_cdc, @@ -1470,60 +1541,20 @@ static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_ } static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { - // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - - if (xfer->result == XFER_RESULT_SUCCESS) { - // stage 1 success, continue with stage 2 - p_cdc->user_control_cb = p_cdc->requested_complete_cb; - ch34x_write_reg_data_format(p_cdc, ch34x_internal_control_complete, xfer->user_data); - } else { - // stage 1 failed, notify user - xfer->complete_cb = p_cdc->requested_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); - } - } + uint8_t const itf_num = 0; // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + set_line_coding_stage1_complete(xfer, itf_num, + ch34x_write_reg_data_format, // control request function to set data format + ch34x_internal_control_complete); // control complete function to be called after request } // 2 stages: set baudrate (stage1) + set data format (stage2) static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - if (complete_cb) { - // stage 1 set baudrate - p_cdc->requested_complete_cb = complete_cb; - p_cdc->user_control_cb = ch34x_set_line_coding_stage1_complete; - return ch34x_write_reg_baudrate(p_cdc, ch34x_internal_control_complete, user_data); - } else { - // blocking sequence - // stage 1 set baudrate - xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL - bool ret = ch34x_write_reg_baudrate(p_cdc, NULL, (uintptr_t) &result); - - // store/check results - if (user_data) { - *((xfer_result_t*) user_data) = result; - } - TU_ASSERT(ret); - TU_VERIFY(result == XFER_RESULT_SUCCESS); - - // overtake baudrate - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - - // stage 2 set data format - result = XFER_RESULT_INVALID; - ret = ch34x_write_reg_data_format(p_cdc, NULL, (uintptr_t) &result); - - // store/check results - if (user_data) { - *((xfer_result_t*) user_data) = result; - } - TU_ASSERT(ret); - return (result == XFER_RESULT_SUCCESS); - // the overtaking of remaining requested_line_coding will be done in tuh_cdc_set_line_coding() - } + return set_line_coding_sequence(p_cdc, + ch34x_write_reg_baudrate, // control request function to set baudrate + ch34x_write_reg_data_format, // control request function to set data format + ch34x_set_line_coding_stage1_complete, // function to be called after stage 1 completed + ch34x_internal_control_complete, // control complete function to be called after request + complete_cb, user_data); } static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { -- cgit v1.3.1 From 7fef5943eff0d7f1b7122e878cf2caa78bea06aa Mon Sep 17 00:00:00 2001 From: IngHK Date: Sat, 24 Feb 2024 12:58:45 +0100 Subject: improved FTDI support --- src/class/cdc/cdc_host.c | 503 +++++++++++++++++++++++++++++++++------- src/class/cdc/serial/ftdi_sio.h | 385 +++++++++++++++--------------- src/tusb_option.h | 19 +- 3 files changed, 616 insertions(+), 291 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 8deeffc37..f9540efbe 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -35,6 +35,9 @@ #include "host/usbh_pvt.h" #include "cdc_host.h" +#include "serial/ftdi_sio.h" +#include "serial/cp210x.h" +#include "serial/ch34x.h" // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUH_CDC_LOG_LEVEL @@ -80,10 +83,14 @@ typedef struct { uint8_t requested_line_state; tuh_xfer_cb_t user_control_cb; - #if CFG_TUH_CDC_CH34X + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X tuh_xfer_cb_t requested_complete_cb; #endif + #if CFG_TUH_CDC_FTDI + ftdi_private_t ftdi; + #endif + struct { tu_edpt_stream_t tx; tu_edpt_stream_t rx; @@ -98,6 +105,9 @@ typedef struct { CFG_TUH_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; +#if CFG_TUH_CDC_FTDI + static tusb_desc_device_t desc_dev[CFG_TUH_CDC][CFG_TUH_ENUMERATION_BUFSIZE]; +#endif //--------------------------------------------------------------------+ // Serial Driver @@ -114,23 +124,22 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t co //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI -#include "serial/ftdi_sio.h" - static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; +#if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL +static uint8_t const * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; +#endif static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); static void ftdi_process_config(tuh_xfer_t* xfer); -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CP210X prototypes -------------// #if CFG_TUH_CDC_CP210X -#include "serial/cp210x.h" - static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST}; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); @@ -144,8 +153,6 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complet //------------- CH34x prototypes -------------// #if CFG_TUH_CDC_CH34X -#include "serial/ch34x.h" - static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len); @@ -212,8 +219,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_count = TU_ARRAY_SIZE(ftdi_vid_pid_list), .open = ftdi_open, .process_set_config = ftdi_process_config, - .set_control_line_state = ftdi_sio_set_modem_ctrl, - .set_baudrate = ftdi_sio_set_baudrate, + .set_control_line_state = ftdi_set_modem_ctrl, + .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, .set_line_coding = ftdi_set_line_coding, #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL @@ -992,28 +999,27 @@ static void acm_process_config(tuh_xfer_t* xfer) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_FTDI -static uint32_t ftdi_232bm_baud_to_divisor(cdch_interface_t* p_cdc); +static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx); +static uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc); +static uint8_t ftdi_get_idx(tuh_xfer_t * xfer); //------------- Control Request -------------// // set request without data -static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_VENDOR, - .direction = TUSB_DIR_OUT - }, - .bRequest = command, - .wValue = tu_htole16(value), - .wIndex = 0, - .wLength = 0 +static bool ftdi_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request_setup = { + .bmRequestType = requesttype, + .bRequest = request, + .wValue = tu_htole16(value), + .wIndex = tu_htole16(index), + .wLength = 0 }; tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, - .setup = &request, + .setup = &request_setup, .buffer = NULL, .complete_cb = complete_cb, .user_data = user_data @@ -1022,16 +1028,57 @@ static bool ftdi_sio_set_request(cdch_interface_t* p_cdc, uint8_t command, uint1 return tuh_control_xfer(&xfer); } -static bool ftdi_sio_reset(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return ftdi_sio_set_request(p_cdc, FTDI_SIO_RESET, FTDI_SIO_RESET_SIO, complete_cb, user_data); +#ifdef CFG_TUH_CDC_FTDI_LATENCY +static int8_t ftdi_write_latency_timer(cdch_interface_t * p_cdc, uint16_t latency, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + if (p_cdc->ftdi.chip_type == SIO /* || p_cdc->ftdi.chip_type == FT232A */ ) + return FTDI_NOT_POSSIBLE; + return ftdi_set_request(p_cdc, FTDI_SIO_SET_LATENCY_TIMER_REQUEST, FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE, + latency, p_cdc->ftdi.channel, complete_cb, user_data) ? FTDI_REQUESTED : FTDI_FAIL; +} +#endif + +static inline bool ftdi_sio_reset(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return ftdi_set_request(p_cdc, FTDI_SIO_RESET_REQUEST, FTDI_SIO_RESET_REQUEST_TYPE, FTDI_SIO_RESET_SIO, + p_cdc->ftdi.channel, complete_cb, user_data); +} + +static bool ftdi_change_speed(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint32_t index_value = ftdi_get_divisor(p_cdc); + TU_VERIFY(index_value); + uint16_t value = (uint16_t) index_value; + uint16_t index = (uint16_t) (index_value >> 16); + if (p_cdc->ftdi.channel) { + index = (uint16_t)((index << 8) | p_cdc->ftdi.channel); + } + + return ftdi_set_request(p_cdc, FTDI_SIO_SET_BAUDRATE_REQUEST, FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE, + value, index, complete_cb, user_data); +} + +static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); + uint16_t value = (uint16_t) ( + ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xf) | // data bit quantity is stored in bits 0-3 + ((uint32_t) p_cdc->requested_line_coding.parity & 0x7) << 8 | // parity is stored in bits 8-10, same coding + ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0x3) << 11 ); // stop bits quantity is stored in bits 11-12, same coding + // not each FTDI supports 1.5 stop bits + + return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, + value, p_cdc->ftdi.channel, complete_cb, user_data); +} + +static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // FTDI has the same bit coding + return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, + p_cdc->requested_line_state, p_cdc->ftdi.channel, complete_cb, user_data); } //------------- Driver API -------------// // internal control complete to update state such as line state, line_coding static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + uint8_t const idx = ftdi_get_idx(xfer); cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); @@ -1039,11 +1086,17 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { if (success) { switch (xfer->setup->bRequest) { - case FTDI_SIO_MODEM_CTRL: + case FTDI_SIO_SET_MODEM_CTRL_REQUEST: p_cdc->line_state = p_cdc->requested_line_state; break; - case FTDI_SIO_SET_BAUD_RATE: + case FTDI_SIO_SET_DATA_REQUEST: + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + break; + + case FTDI_SIO_SET_BAUDRATE_REQUEST: p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; break; @@ -1057,52 +1110,62 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ftdi_sio_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const divisor = (uint16_t) ftdi_232bm_baud_to_divisor(p_cdc); +static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + + return true; +} +static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_SET_BAUD_RATE, divisor, - complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } -static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - (void) p_cdc; - (void) complete_cb; - (void) user_data; - // TODO not implemented yet - return false; +static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + set_line_coding_stage1_complete(xfer, itf_num, + ftdi_set_data_request, // control request function to set data format + ftdi_internal_control_complete); // control complete function to be called after request } -static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - (void) p_cdc; - (void) complete_cb; - (void) user_data; - // TODO not implemented yet - return false; +// 2 stages: set baudrate (stage1) + set data format (stage2) +static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return set_line_coding_sequence(p_cdc, + ftdi_change_speed, // control request function to set baudrate + ftdi_set_data_request, // control request function to set data format + ftdi_set_line_coding_stage1_complete, // function to be called after stage 1 completed + ftdi_internal_control_complete, // control complete function to be called after request + complete_cb, user_data); } -static bool ftdi_sio_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - TU_ASSERT(ftdi_sio_set_request(p_cdc, FTDI_SIO_MODEM_CTRL, 0x0300 | p_cdc->requested_line_state, - complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + TU_ASSERT(ftdi_update_mctrl(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + return true; } //------------- Enumeration -------------// enum { - CONFIG_FTDI_RESET = 0, - CONFIG_FTDI_MODEM_CTRL, - CONFIG_FTDI_SET_BAUDRATE, + CONFIG_FTDI_GET_DESC = 0, + CONFIG_FTDI_DETERMINE_TYPE, + CONFIG_FTDI_WRITE_LATENCY, + CONFIG_FTDI_SIO_RESET, CONFIG_FTDI_SET_DATA, + CONFIG_FTDI_SET_BAUDRATE, + CONFIG_FTDI_FLOW_CONTROL, + CONFIG_FTDI_MODEM_CTRL, CONFIG_FTDI_COMPLETE }; -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len) { // FTDI Interface includes 1 vendor interface + 2 bulk endpoints - TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); + TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && + itf_desc->bNumEndpoints == 2); TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); @@ -1113,53 +1176,96 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint // endpoint pair tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + /* + * NOTE: Some customers have programmed FT232R/FT245R devices + * with an endpoint size of 0 - not good. + */ + TU_ASSERT(desc_ep->wMaxPacketSize != 0); + // data endpoints expected to be in pairs return open_ep_stream_pair(p_cdc, desc_ep); } -static void ftdi_process_config(tuh_xfer_t* xfer) { +static void ftdi_process_config(tuh_xfer_t * xfer) { uintptr_t const state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + uint8_t const idx = ftdi_get_idx(xfer); cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); + uint8_t const itf_num = p_cdc->bInterfaceNumber; switch(state) { - // Note may need to read FTDI eeprom - case CONFIG_FTDI_RESET: - TU_ASSERT_COMPLETE(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); + + // from here sequence overtaken from Linux Kernel function ftdi_port_probe() + case CONFIG_FTDI_GET_DESC: + // get device descriptor + p_cdc->user_control_cb = ftdi_process_config; // set once for whole process config + if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 + TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, desc_dev[idx], sizeof(tusb_desc_device_t), + ftdi_process_config, CONFIG_FTDI_DETERMINE_TYPE)); + break; + } + TU_ATTR_FALLTHROUGH; + + case CONFIG_FTDI_DETERMINE_TYPE: + // determine type + if (itf_num == 0) { + TU_ASSERT_COMPLETE(ftdi_determine_type(p_cdc, idx)); + } else { + // other interfaces have same type as interface 0 + uint8_t const idx_itf0 = tuh_cdc_itf_get_index(xfer->daddr, 0); + cdch_interface_t const * p_cdc_itf0 = get_itf(idx_itf0); + p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type; + } + TU_ATTR_FALLTHROUGH; + + case CONFIG_FTDI_WRITE_LATENCY: + #ifdef CFG_TUH_CDC_FTDI_LATENCY + int8_t result = ftdi_write_latency_timer(p_cdc, CFG_TUH_CDC_FTDI_LATENCY, ftdi_process_config, + CONFIG_FTDI_SIO_RESET); + TU_ASSERT_COMPLETE(result != FTDI_FAIL); + if(result == FTDI_REQUESTED) { + break; + } // else FTDI_NOT_POSSIBLE => continue directly with next state + #endif + TU_ATTR_FALLTHROUGH; + + // from here sequence overtaken from Linux Kernel function ftdi_open() + case CONFIG_FTDI_SIO_RESET: + TU_ASSERT_COMPLETE(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA)); break; - case CONFIG_FTDI_MODEM_CTRL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ftdi_sio_set_modem_ctrl(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_BAUDRATE)); + // from here sequence overtaken from Linux Kernel function ftdi_set_termios() + case CONFIG_FTDI_SET_DATA: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT_COMPLETE(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); break; #else TU_ATTR_FALLTHROUGH; #endif - case CONFIG_FTDI_SET_BAUDRATE: { + case CONFIG_FTDI_SET_BAUDRATE: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; - TU_ASSERT_COMPLETE(ftdi_sio_set_baudrate(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA)); + TU_ASSERT_COMPLETE(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); break; #else TU_ATTR_FALLTHROUGH; #endif - } - case CONFIG_FTDI_SET_DATA: { - #if 0 // TODO set data format - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT_COMPLETE(ftdi_sio_set_data(p_cdc, process_ftdi_config, CONFIG_FTDI_COMPLETE)); + case CONFIG_FTDI_FLOW_CONTROL: + // disable flow control + TU_ASSERT_COMPLETE(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, + 0, FTDI_SIO_DISABLE_FLOW_CTRL, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); break; - #endif - #endif - TU_ATTR_FALLTHROUGH; - } + case CONFIG_FTDI_MODEM_CTRL: + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT_COMPLETE(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif case CONFIG_FTDI_COMPLETE: set_config_complete(idx, 0, true); @@ -1173,28 +1279,249 @@ static void ftdi_process_config(tuh_xfer_t* xfer) { //------------- Helper -------------// +static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx) +{ + uint16_t const version = desc_dev[idx]->bcdDevice; + uint8_t const itf_num = p_cdc->bInterfaceNumber; + + p_cdc->ftdi.chip_type = UNKNOWN; + + /* Assume Hi-Speed type */ + p_cdc->ftdi.channel = CHANNEL_A + itf_num; + + switch (version) { + case 0x200: + // FT232A not supported to keep it simple (no extra _read_latency_timer()) + // not testable + // p_cdc->ftdi.chip_type = FT232A; + // p_cdc->ftdi.baud_base = 48000000 / 2; + // p_cdc->ftdi.channel = 0; + // /* + // * FT232B devices have a bug where bcdDevice gets set to 0x200 + // * when iSerialNumber is 0. Assume it is an FT232B in case the + // * latency timer is readable. + // */ + // if (desc->iSerialNumber == 0 && + // _read_latency_timer(port) >= 0) { + // p_cdc->ftdi.chip_type = FT232B; + // } + break; + case 0x400: + p_cdc->ftdi.chip_type = FT232B; + p_cdc->ftdi.channel = 0; + break; + case 0x500: + p_cdc->ftdi.chip_type = FT2232C; + break; + case 0x600: + p_cdc->ftdi.chip_type = FT232R; + p_cdc->ftdi.channel = 0; + break; + case 0x700: + p_cdc->ftdi.chip_type = FT2232H; + break; + case 0x800: + p_cdc->ftdi.chip_type = FT4232H; + break; + case 0x900: + p_cdc->ftdi.chip_type = FT232H; + break; + case 0x1000: + p_cdc->ftdi.chip_type = FTX; + break; + case 0x2800: + p_cdc->ftdi.chip_type = FT2233HP; + break; + case 0x2900: + p_cdc->ftdi.chip_type = FT4233HP; + break; + case 0x3000: + p_cdc->ftdi.chip_type = FT2232HP; + break; + case 0x3100: + p_cdc->ftdi.chip_type = FT4232HP; + break; + case 0x3200: + p_cdc->ftdi.chip_type = FT233HP; + break; + case 0x3300: + p_cdc->ftdi.chip_type = FT232HP; + break; + case 0x3600: + p_cdc->ftdi.chip_type = FT4232HA; + break; + default: + if (version < 0x200) { + p_cdc->ftdi.chip_type = SIO; + p_cdc->ftdi.channel = 0; + } + break; + } + + TU_LOG_P_CDC("%s detected", ftdi_chip_name[p_cdc->ftdi.chip_type]); + + return (p_cdc->ftdi.chip_type != UNKNOWN); +} + +// FT232A not supported +//static uint32_t ftdi_232am_baud_base_to_divisor(uint32_t baud, uint32_t base) +//{ +// uint32_t divisor; +// /* divisor shifted 3 bits to the left */ +// uint32_t divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); +// if ((divisor3 & 0x7) == 7) +// divisor3++; /* round x.7/8 up to x+1 */ +// divisor = divisor3 >> 3; +// divisor3 &= 0x7; +// if (divisor3 == 1) +// divisor |= 0xc000; /* +0.125 */ +// else if (divisor3 >= 4) +// divisor |= 0x4000; /* +0.5 */ +// else if (divisor3 != 0) +// divisor |= 0x8000; /* +0.25 */ +// else if (divisor == 1) +// divisor = 0; /* special case for maximum baud rate */ +// return divisor; +//} + +// FT232A not supported +//static inline uint32_t ftdi_232am_baud_to_divisor(uint32_t baud) +//{ +// return ftdi_232am_baud_base_to_divisor(baud, (uint32_t) 48000000); +//} + static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { - const uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; uint32_t divisor; - /* divisor shifted 3 bits to the left */ - uint32_t divisor3 = base / (2 * baud); - divisor = (divisor3 >> 3); - divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; + uint32_t divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); + divisor = divisor3 >> 3; + divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; + /* Deal with special cases for highest baud rates. */ + if (divisor == 1) /* 1.0 */ + divisor = 0; + else if (divisor == 0x4001) /* 1.5 */ + divisor = 1; + return divisor; +} + +static inline uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) +{ + return ftdi_232bm_baud_base_to_divisor(baud, 48000000); +} + +static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, uint32_t base) +{ + static const unsigned char divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint32_t divisor; + uint32_t divisor3; + + /* hi-speed baud rate is 10-bit sampling instead of 16-bit */ + divisor3 = DIV_ROUND_CLOSEST(8 * base, 10 * baud); + divisor = divisor3 >> 3; + divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; /* Deal with special cases for highest baud rates. */ - if (divisor == 1) { /* 1.0 */ + if (divisor == 1) /* 1.0 */ divisor = 0; - } - else if (divisor == 0x4001) { /* 1.5 */ + else if (divisor == 0x4001) /* 1.5 */ divisor = 1; + /* + * Set this bit to turn off a divide by 2.5 on baud rate generator + * This enables baud rates up to 12Mbaud but cannot reach below 1200 + * baud with this bit set + */ + divisor |= 0x00020000; + return divisor; +} + +static inline uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) +{ + return ftdi_2232h_baud_base_to_divisor(baud, (uint32_t) 120000000); +} + +static inline uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc) +{ + uint32_t baud = p_cdc->requested_line_coding.bit_rate; + uint32_t div_value = 0; + TU_VERIFY(baud); + + switch (p_cdc->ftdi.chip_type) { + case UNKNOWN: + return 0; + case SIO: + switch (baud) { + case 300: div_value = ftdi_sio_b300; break; + case 600: div_value = ftdi_sio_b600; break; + case 1200: div_value = ftdi_sio_b1200; break; + case 2400: div_value = ftdi_sio_b2400; break; + case 4800: div_value = ftdi_sio_b4800; break; + case 9600: div_value = ftdi_sio_b9600; break; + case 19200: div_value = ftdi_sio_b19200; break; + case 38400: div_value = ftdi_sio_b38400; break; + case 57600: div_value = ftdi_sio_b57600; break; + case 115200: div_value = ftdi_sio_b115200; break; + default: + // Baudrate not supported + return 0; + break; + } + break; + // FT232A not supported + // case FT232A: + // if (baud <= 3000000) { + // div_value = ftdi_232am_baud_to_divisor(baud); + // } else { + // // Baud rate too high! + // baud = 9600; + // div_value = ftdi_232am_baud_to_divisor(9600); + // div_okay = false; + // } + // break; + case FT232B: + case FT2232C: + case FT232R: + case FTX: + TU_VERIFY(baud <= 3000000); // else Baud rate too high! + div_value = ftdi_232bm_baud_to_divisor(baud); + break; + case FT232H: + case FT2232H: + case FT4232H: + case FT4232HA: + case FT232HP: + case FT233HP: + case FT2232HP: + case FT2233HP: + case FT4232HP: + case FT4233HP: + default: + TU_VERIFY(baud <= 12000000); // else Baud rate too high! + if (baud >= 1200) { + div_value = ftdi_2232h_baud_to_divisor(baud); + } else { + div_value = ftdi_232bm_baud_to_divisor(baud); + } + break; } - return divisor; + TU_LOG_P_CDC("Baudrate divisor 0x%lu", div_value); + + return div_value; } -static uint32_t ftdi_232bm_baud_to_divisor(cdch_interface_t* p_cdc) { - return ftdi_232bm_baud_base_to_divisor(p_cdc->requested_line_coding.bit_rate, 48000000u); +static uint8_t ftdi_get_idx(tuh_xfer_t * xfer) { + uint8_t const channel = (uint8_t) tu_le16toh(xfer->setup->wIndex); // channel index, or 0 for legacy types + for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { + const cdch_interface_t * p_cdc = &cdch_data[i]; + if (p_cdc->daddr == xfer->daddr && + (!p_cdc->ftdi.channel || // 0 for legacy types (only interface 0) + channel == p_cdc->ftdi.channel)) { // or multi-channel types (interfaces 0..n) + return i; + } + } + + return TUSB_INDEX_INVALID_8; } #endif diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index 0825f0719..42716f73e 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -25,222 +25,207 @@ #ifndef TUSB_FTDI_SIO_H #define TUSB_FTDI_SIO_H -// VID for matching FTDI devices -#define TU_FTDI_VID 0x0403 +#include // Commands -#define FTDI_SIO_RESET 0 /* Reset the port */ -#define FTDI_SIO_MODEM_CTRL 1 /* Set the modem control register */ -#define FTDI_SIO_SET_FLOW_CTRL 2 /* Set flow control register */ -#define FTDI_SIO_SET_BAUD_RATE 3 /* Set baud rate */ -#define FTDI_SIO_SET_DATA 4 /* Set the data characteristics of the port */ -#define FTDI_SIO_GET_MODEM_STATUS 5 /* Retrieve current value of modem status register */ -#define FTDI_SIO_SET_EVENT_CHAR 6 /* Set the event character */ -#define FTDI_SIO_SET_ERROR_CHAR 7 /* Set the error character */ -#define FTDI_SIO_SET_LATENCY_TIMER 9 /* Set the latency timer */ -#define FTDI_SIO_GET_LATENCY_TIMER 0x0a /* Get the latency timer */ -#define FTDI_SIO_SET_BITMODE 0x0b /* Set bitbang mode */ -#define FTDI_SIO_READ_PINS 0x0c /* Read immediate value of pins */ -#define FTDI_SIO_READ_EEPROM 0x90 /* Read EEPROM */ - -/* FTDI_SIO_RESET */ +#define FTDI_SIO_RESET 0 // Reset the port +#define FTDI_SIO_MODEM_CTRL 1 // Set the modem control register +#define FTDI_SIO_SET_FLOW_CTRL 2 // Set flow control register +#define FTDI_SIO_SET_BAUD_RATE 3 // Set baud rate +#define FTDI_SIO_SET_DATA 4 // Set the data characteristics of the port +#define FTDI_SIO_GET_MODEM_STATUS 5 // Retrieve current value of modem status register +#define FTDI_SIO_SET_EVENT_CHAR 6 // Set the event character +#define FTDI_SIO_SET_ERROR_CHAR 7 // Set the error character +#define FTDI_SIO_SET_LATENCY_TIMER 9 // Set the latency timer +#define FTDI_SIO_GET_LATENCY_TIMER 10 // Get the latency timer +#define FTDI_SIO_SET_BITMODE 11 // Set bitbang mode +#define FTDI_SIO_READ_PINS 12 // Read immediate value of pins +#define FTDI_SIO_READ_EEPROM 0x90 // Read EEPROM + +// Channel indices for FT2232, FT2232H and FT4232H devices +#define CHANNEL_A 1 +#define CHANNEL_B 2 +#define CHANNEL_C 3 +#define CHANNEL_D 4 + +// Port Identifier Table +#define PIT_DEFAULT 0 // SIOA +#define PIT_SIOA 1 // SIOA +// The device this driver is tested with one has only one port +#define PIT_SIOB 2 // SIOB +#define PIT_PARALLEL 3 // Parallel + +// FTDI_SIO_RESET +#define FTDI_SIO_RESET_REQUEST FTDI_SIO_RESET +#define FTDI_SIO_RESET_REQUEST_TYPE 0x40 #define FTDI_SIO_RESET_SIO 0 #define FTDI_SIO_RESET_PURGE_RX 1 #define FTDI_SIO_RESET_PURGE_TX 2 -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_RESET - * wValue: Control Value - * 0 = Reset SIO - * 1 = Purge RX buffer - * 2 = Purge TX buffer - * wIndex: Port - * wLength: 0 - * Data: None - * - * The Reset SIO command has this effect: - * - * Sets flow control set to 'none' - * Event char = $0D - * Event trigger = disabled - * Purge RX buffer - * Purge TX buffer - * Clear DTR - * Clear RTS - * baud and data format not reset - * - * The Purge RX and TX buffer commands affect nothing except the buffers - * - */ - -/* FTDI_SIO_MODEM_CTRL */ -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_MODEM_CTRL - * wValue: ControlValue (see below) - * wIndex: Port - * wLength: 0 - * Data: None - * - * NOTE: If the device is in RTS/CTS flow control, the RTS set by this - * command will be IGNORED without an error being returned - * Also - you can not set DTR and RTS with one control message - */ +// FTDI_SIO_SET_BAUDRATE +#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_BAUDRATE_REQUEST 3 + +enum ftdi_sio_baudrate { + ftdi_sio_b300 = 0, + ftdi_sio_b600 = 1, + ftdi_sio_b1200 = 2, + ftdi_sio_b2400 = 3, + ftdi_sio_b4800 = 4, + ftdi_sio_b9600 = 5, + ftdi_sio_b19200 = 6, + ftdi_sio_b38400 = 7, + ftdi_sio_b57600 = 8, + ftdi_sio_b115200 = 9 +}; + +// FTDI_SIO_SET_DATA +#define FTDI_SIO_SET_DATA_REQUEST FTDI_SIO_SET_DATA +#define FTDI_SIO_SET_DATA_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) + +// FTDI_SIO_MODEM_CTRL +#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL #define FTDI_SIO_SET_DTR_MASK 0x1 -#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) -#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) #define FTDI_SIO_SET_RTS_MASK 0x2 #define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) #define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) -/* - * ControlValue - * B0 DTR state - * 0 = reset - * 1 = set - * B1 RTS state - * 0 = reset - * 1 = set - * B2..7 Reserved - * B8 DTR state enable - * 0 = ignore - * 1 = use DTR state - * B9 RTS state enable - * 0 = ignore - * 1 = use RTS state - * B10..15 Reserved - */ - -/* FTDI_SIO_SET_FLOW_CTRL */ +// FTDI_SIO_SET_FLOW_CTRL +#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL #define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 #define FTDI_SIO_RTS_CTS_HS (0x1 << 8) #define FTDI_SIO_DTR_DSR_HS (0x2 << 8) #define FTDI_SIO_XON_XOFF_HS (0x4 << 8) -/* - * BmRequestType: 0100 0000b - * bRequest: FTDI_SIO_SET_FLOW_CTRL - * wValue: Xoff/Xon - * wIndex: Protocol/Port - hIndex is protocol / lIndex is port - * wLength: 0 - * Data: None - * - * hIndex protocol is: - * B0 Output handshaking using RTS/CTS - * 0 = disabled - * 1 = enabled - * B1 Output handshaking using DTR/DSR - * 0 = disabled - * 1 = enabled - * B2 Xon/Xoff handshaking - * 0 = disabled - * 1 = enabled - * - * A value of zero in the hIndex field disables handshaking - * - * If Xon/Xoff handshaking is specified, the hValue field should contain the - * XOFF character and the lValue field contains the XON character. - */ - -/* FTDI_SIO_SET_BAUD_RATE */ -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_SET_BAUDRATE - * wValue: BaudDivisor value - see below - * wIndex: Port - * wLength: 0 - * Data: None - * The BaudDivisor values are calculated as follows (too complicated): - */ - -/* FTDI_SIO_SET_DATA */ -#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) -#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) -#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) -#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) -#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) -#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) -#define FTDI_SIO_SET_BREAK (0x1 << 14) - -/* - * BmRequestType: 0100 0000B - * bRequest: FTDI_SIO_SET_DATA - * wValue: Data characteristics (see below) - * wIndex: Port - * wLength: 0 - * Data: No - * - * Data characteristics - * - * B0..7 Number of data bits - * B8..10 Parity - * 0 = None - * 1 = Odd - * 2 = Even - * 3 = Mark - * 4 = Space - * B11..13 Stop Bits - * 0 = 1 - * 1 = 1.5 - * 2 = 2 - * B14 - * 1 = TX ON (break) - * 0 = TX OFF (normal state) - * B15 Reserved - * - */ - -/* -* DATA FORMAT -* -* IN Endpoint -* -* The device reserves the first two bytes of data on this endpoint to contain -* the current values of the modem and line status registers. In the absence of -* data, the device generates a message consisting of these two status bytes - * every 40 ms - * - * Byte 0: Modem Status -* -* Offset Description -* B0 Reserved - must be 1 -* B1 Reserved - must be 0 -* B2 Reserved - must be 0 -* B3 Reserved - must be 0 -* B4 Clear to Send (CTS) -* B5 Data Set Ready (DSR) -* B6 Ring Indicator (RI) -* B7 Receive Line Signal Detect (RLSD) -* -* Byte 1: Line Status -* -* Offset Description -* B0 Data Ready (DR) -* B1 Overrun Error (OE) -* B2 Parity Error (PE) -* B3 Framing Error (FE) -* B4 Break Interrupt (BI) -* B5 Transmitter Holding Register (THRE) -* B6 Transmitter Empty (TEMT) -* B7 Error in RCVR FIFO -* -*/ -#define FTDI_RS0_CTS (1 << 4) -#define FTDI_RS0_DSR (1 << 5) -#define FTDI_RS0_RI (1 << 6) -#define FTDI_RS0_RLSD (1 << 7) - -#define FTDI_RS_DR 1 -#define FTDI_RS_OE (1<<1) -#define FTDI_RS_PE (1<<2) -#define FTDI_RS_FE (1<<3) -#define FTDI_RS_BI (1<<4) -#define FTDI_RS_THRE (1<<5) -#define FTDI_RS_TEMT (1<<6) -#define FTDI_RS_FIFO (1<<7) +// FTDI_SIO_GET_LATENCY_TIMER +#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST FTDI_SIO_GET_LATENCY_TIMER +#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE 0xC0 + +// FTDI_SIO_SET_LATENCY_TIMER +#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST FTDI_SIO_SET_LATENCY_TIMER +#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE 0x40 + +// FTDI_SIO_SET_EVENT_CHAR +#define FTDI_SIO_SET_EVENT_CHAR_REQUEST FTDI_SIO_SET_EVENT_CHAR +#define FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE 0x40 + +// FTDI_SIO_GET_MODEM_STATUS +#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE 0xc0 +#define FTDI_SIO_GET_MODEM_STATUS_REQUEST FTDI_SIO_GET_MODEM_STATUS +#define FTDI_SIO_CTS_MASK 0x10 +#define FTDI_SIO_DSR_MASK 0x20 +#define FTDI_SIO_RI_MASK 0x40 +#define FTDI_SIO_RLSD_MASK 0x80 + +// FTDI_SIO_SET_BITMODE +#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_BITMODE_REQUEST FTDI_SIO_SET_BITMODE + +// Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST +#define FTDI_SIO_BITMODE_RESET 0x00 +#define FTDI_SIO_BITMODE_CBUS 0x20 + +// FTDI_SIO_READ_PINS +#define FTDI_SIO_READ_PINS_REQUEST_TYPE 0xc0 +#define FTDI_SIO_READ_PINS_REQUEST FTDI_SIO_READ_PINS + +// FTDI_SIO_READ_EEPROM +#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE 0xc0 +#define FTDI_SIO_READ_EEPROM_REQUEST FTDI_SIO_READ_EEPROM + +#define FTDI_FTX_CBUS_MUX_GPIO 0x8 +#define FTDI_FT232R_CBUS_MUX_GPIO 0xa + +#define FTDI_RS0_CTS (1 << 4) +#define FTDI_RS0_DSR (1 << 5) +#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RLSD (1 << 7) + +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1<<1) +#define FTDI_RS_PE (1<<2) +#define FTDI_RS_FE (1<<3) +#define FTDI_RS_BI (1<<4) +#define FTDI_RS_THRE (1<<5) +#define FTDI_RS_TEMT (1<<6) +#define FTDI_RS_FIFO (1<<7) + +// chip types and names +enum ftdi_chip_type { + SIO = 0, +// FT232A, + FT232B, + FT2232C, + FT232R, + FT232H, + FT2232H, + FT4232H, + FT4232HA, + FT232HP, + FT233HP, + FT2232HP, + FT2233HP, + FT4232HP, + FT4233HP, + FTX, + UNKNOWN +}; + +#define FTDI_CHIP_NAMES \ + [SIO] = (uint8_t const*) "SIO", /* the serial part of FT8U100AX */ \ +/* [FT232A] = (uint8_t const*) "FT232A", */ \ + [FT232B] = (uint8_t const*) "FT232B", \ + [FT2232C] = (uint8_t const*) "FT2232C/D", \ + [FT232R] = (uint8_t const*) "FT232R", \ + [FT232H] = (uint8_t const*) "FT232H", \ + [FT2232H] = (uint8_t const*) "FT2232H", \ + [FT4232H] = (uint8_t const*) "FT4232H", \ + [FT4232HA] = (uint8_t const*) "FT4232HA", \ + [FT232HP] = (uint8_t const*) "FT232HP", \ + [FT233HP] = (uint8_t const*) "FT233HP", \ + [FT2232HP] = (uint8_t const*) "FT2232HP", \ + [FT2233HP] = (uint8_t const*) "FT2233HP", \ + [FT4232HP] = (uint8_t const*) "FT4232HP", \ + [FT4233HP] = (uint8_t const*) "FT4233HP", \ + [FTX] = (uint8_t const*) "FT-X", \ + [UNKNOWN] = (uint8_t const*) "UNKNOWN" + +// private interface data +typedef struct ftdi_private { + enum ftdi_chip_type chip_type; + uint8_t channel; // channel index, or 0 for legacy types +} ftdi_private_t; + +#define FTDI_OK true +#define FTDI_FAIL false +#define FTDI_NOT_POSSIBLE -1 +#define FTDI_REQUESTED -2 + +// division and round function overtaken from math.h +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || \ + (((__x) > 0) == ((__d) > 0))) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) #endif //TUSB_FTDI_SIO_H diff --git a/src/tusb_option.h b/src/tusb_option.h index 767323bdd..ebf9a4d4d 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -456,9 +456,22 @@ #ifndef CFG_TUH_CDC_FTDI_VID_PID_LIST // List of product IDs that can use the FTDI CDC driver. 0x0403 is FTDI's VID #define CFG_TUH_CDC_FTDI_VID_PID_LIST \ - {0x0403, 0x6001}, {0x0403, 0x6006}, {0x0403, 0x6010}, {0x0403, 0x6011}, \ - {0x0403, 0x6014}, {0x0403, 0x6015}, {0x0403, 0x8372}, {0x0403, 0xFBFA}, \ - {0x0403, 0xCD18} + {0x0403, 0x6001}, /* Similar device to SIO above */ \ + {0x0403, 0x6006}, /* FTDI's alternate PID for above */ \ + {0x0403, 0x6010}, /* Dual channel device */ \ + {0x0403, 0x6011}, /* Quad channel hi-speed device */ \ + {0x0403, 0x6014}, /* Single channel hi-speed device */ \ + {0x0403, 0x6015}, /* FT-X series (FT201X, FT230X, FT231X, etc) */ \ + {0x0403, 0x6040}, /* Dual channel hi-speed device with PD */ \ + {0x0403, 0x6041}, /* Quad channel hi-speed device with PD */ \ + {0x0403, 0x6042}, /* Dual channel hi-speed device with PD */ \ + {0x0403, 0x6043}, /* Quad channel hi-speed device with PD */ \ + {0x0403, 0x6044}, /* Dual channel hi-speed device with PD */ \ + {0x0403, 0x6045}, /* Dual channel hi-speed device with PD */ \ + {0x0403, 0x6048}, /* Quad channel automotive grade hi-speed device */ \ + {0x0403, 0x8372}, /* Product Id SIO application of 8U100AX */ \ + {0x0403, 0xFBFA}, /* Product ID for FT232RL */ \ + {0x0403, 0xCD18}, /* ??? */ #endif #ifndef CFG_TUH_CDC_CP210X -- cgit v1.3.1 From 4547737833de0368354cb4823d908c6b250f92df Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 15:42:33 +0100 Subject: improved CP210x support --- src/class/cdc/cdc_host.c | 135 +++++++++++++++++++++++++++++------------- src/class/cdc/serial/cp210x.h | 63 +++++++++++++++++++- src/tusb_option.h | 4 +- 3 files changed, 159 insertions(+), 43 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f9540efbe..86c010fa7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -83,7 +83,7 @@ typedef struct { uint8_t requested_line_state; tuh_xfer_cb_t user_control_cb; - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CH34X + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X tuh_xfer_cb_t requested_complete_cb; #endif @@ -1533,7 +1533,8 @@ static uint8_t ftdi_get_idx(tuh_xfer_t * xfer) { //------------- Control Request -------------// -static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_t value, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_request(cdch_interface_t * p_cdc, uint8_t command, uint16_t value, + uint8_t * buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, @@ -1542,12 +1543,12 @@ static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_ }, .bRequest = command, .wValue = tu_htole16(value), - .wIndex = p_cdc->bInterfaceNumber, + .wIndex = tu_htole16(p_cdc->bInterfaceNumber), .wLength = tu_htole16(length) }; // use usbh enum buf since application variable does not live long enough - uint8_t* enum_buf = NULL; + uint8_t * enum_buf = NULL; if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); @@ -1566,18 +1567,52 @@ static bool cp210x_set_request(cdch_interface_t* p_cdc, uint8_t command, uint16_ return tuh_control_xfer(&xfer); } -static bool cp210x_ifc_enable(cdch_interface_t* p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool cp210x_ifc_enable(cdch_interface_t * p_cdc, uint16_t enabled, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); } +static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // Check baudrate is supported. It's only a specific list. reference: datasheets and AN205 "CP210x Baud Rate Support" + uint32_t const supported_baudrates_list[] = CP210X_SUPPORTED_BAUDRATES_LIST; + uint8_t i; + for ( i=0; supported_baudrates_list[i]; i++ ){ + if (p_cdc->requested_line_coding.bit_rate == supported_baudrates_list[i]) { + break; + } + } + TU_VERIFY(supported_baudrates_list[i]); + uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); + + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); +} + +static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 9, 0); + uint16_t lcr = (uint16_t) ( + ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xf) << 8 | // data bit quantity is stored in bits 8-11 + ((uint32_t) p_cdc->requested_line_coding.parity & 0xf) << 4 | // parity is stored in bits 4-7, same coding + ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0xf)); // parity is stored in bits 0-3, same coding + + return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); +} + +static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // CP210x has the same bit coding + return cp210x_set_request(p_cdc, CP210X_SET_MHS, + (uint16_t) ((uint32_t) CP210X_CONTROL_WRITE_DTR | + (uint32_t) CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line_state), + NULL, 0, complete_cb, user_data); +} + //------------- Driver API -------------// // internal control complete to update state such as line state, encoding static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC("control complete success = %u", success); @@ -1587,6 +1622,12 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { p_cdc->line_state = p_cdc->requested_line_state; break; + case CP210X_SET_LINE_CTL: + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + break; + case CP210X_SET_BAUDRATE: p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; break; @@ -1601,46 +1642,55 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); +static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, - complete_cb ? cp210x_internal_control_complete : NULL, user_data); + TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); + + return true; } -static bool cp210x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - (void) p_cdc; - (void) complete_cb; - (void) user_data; - // TODO not implemented yet - return false; +static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); + + return true; } -static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // TODO implement later - (void) p_cdc; - (void) complete_cb; - (void) user_data; - return false; +static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + set_line_coding_stage1_complete(xfer, itf_num, + cp210x_set_line_ctl, // control request function to set data format + cp210x_internal_control_complete); // control complete function to be called after request +} + +// 2 stages: set baudrate (stage1) + set data format (stage2) +static bool cp210x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + return set_line_coding_sequence(p_cdc, + cp210x_set_baudrate_request, // control request function to set baudrate + cp210x_set_line_ctl, // control request function to set data format + cp210x_set_line_coding_stage1_complete, // function to be called after stage 1 completed + cp210x_internal_control_complete, // control complete function to be called after request + complete_cb, user_data); } -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; - return cp210x_set_request(p_cdc, CP210X_SET_MHS, 0x0300 | p_cdc->requested_line_state, NULL, 0, - complete_cb ? cp210x_internal_control_complete : NULL, user_data); + TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); + + return true; } //------------- Enumeration -------------// enum { CONFIG_CP210X_IFC_ENABLE = 0, - CONFIG_CP210X_SET_BAUDRATE, + CONFIG_CP210X_SET_BAUDRATE_REQUEST, CONFIG_CP210X_SET_LINE_CTL, CONFIG_CP210X_SET_DTR_RTS, CONFIG_CP210X_COMPLETE }; -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { // CP210x Interface includes 1 vendor interface + 2 bulk endpoints TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); @@ -1657,7 +1707,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui return open_ep_stream_pair(p_cdc, desc_ep); } -static void cp210x_process_config(tuh_xfer_t* xfer) { +static void cp210x_process_config(tuh_xfer_t * xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -1666,32 +1716,35 @@ static void cp210x_process_config(tuh_xfer_t* xfer) { switch (state) { case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT_COMPLETE(cp210x_ifc_enable(p_cdc, 1, cp210x_process_config, CONFIG_CP210X_SET_BAUDRATE)); + p_cdc->user_control_cb = cp210x_process_config; // set once for whole process config + TU_ASSERT_COMPLETE(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cp210x_process_config, + CONFIG_CP210X_SET_BAUDRATE_REQUEST)); break; - case CONFIG_CP210X_SET_BAUDRATE: { + case CONFIG_CP210X_SET_BAUDRATE_REQUEST: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding.bit_rate = ((cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM).bit_rate; - TU_ASSERT_COMPLETE(cp210x_set_baudrate(p_cdc, cp210x_process_config, CONFIG_CP210X_SET_LINE_CTL)); + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT_COMPLETE(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, + CONFIG_CP210X_SET_LINE_CTL)); break; #else TU_ATTR_FALLTHROUGH; #endif - } - case CONFIG_CP210X_SET_LINE_CTL: { - #if defined(CFG_TUH_CDC_LINE_CODING_ON_ENUM) && 0 // skip for now - cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM; - break; + case CONFIG_CP210X_SET_LINE_CTL: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + TU_ASSERT_COMPLETE(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, + CONFIG_CP210X_SET_DTR_RTS)); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif - } case CONFIG_CP210X_SET_DTR_RTS: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(cp210x_set_modem_ctrl(p_cdc, cp210x_process_config, CONFIG_CP210X_COMPLETE)); + TU_ASSERT_COMPLETE(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, + CONFIG_CP210X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index 2c749f522..e18da7d51 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -28,7 +28,8 @@ // Protocol details can be found at AN571: CP210x Virtual COM Port Interface // https://www.silabs.com/documents/public/application-notes/AN571.pdf -#define TU_CP210X_VID 0x10C4 +// parts are overtaken from vendors driver +// https://www.silabs.com/documents/public/software/cp210x-3.1.0.tar.gz /* Config request codes */ #define CP210X_IFC_ENABLE 0x00 @@ -59,4 +60,64 @@ #define CP210X_SET_BAUDRATE 0x1E #define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device +/* SILABSER_IFC_ENABLE_REQUEST_CODE */ +#define CP210X_UART_ENABLE 0x0001 +#define CP210X_UART_DISABLE 0x0000 + +/* SILABSER_SET_BAUDDIV_REQUEST_CODE */ +#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 + +/*SILABSER_SET_LINE_CTL_REQUEST_CODE */ +#define CP210X_BITS_DATA_MASK 0x0f00 +#define CP210X_BITS_DATA_5 0x0500 +#define CP210X_BITS_DATA_6 0x0600 +#define CP210X_BITS_DATA_7 0x0700 +#define CP210X_BITS_DATA_8 0x0800 +#define CP210X_BITS_DATA_9 0x0900 + +#define CP210X_BITS_PARITY_MASK 0x00f0 +#define CP210X_BITS_PARITY_NONE 0x0000 +#define CP210X_BITS_PARITY_ODD 0x0010 +#define CP210X_BITS_PARITY_EVEN 0x0020 +#define CP210X_BITS_PARITY_MARK 0x0030 +#define CP210X_BITS_PARITY_SPACE 0x0040 + +#define CP210X_BITS_STOP_MASK 0x000f +#define CP210X_BITS_STOP_1 0x0000 +#define CP210X_BITS_STOP_1_5 0x0001 +#define CP210X_BITS_STOP_2 0x0002 + +/* SILABSER_SET_BREAK_REQUEST_CODE */ +#define CP210X_BREAK_ON 0x0001 +#define CP210X_BREAK_OFF 0x0000 + +/* SILABSER_SET_MHS_REQUEST_CODE */ +#define CP210X_MCR_DTR 0x0001 +#define CP210X_MCR_RTS 0x0002 +#define CP210X_MCR_ALL 0x0003 +#define CP210X_MSR_CTS 0x0010 +#define CP210X_MSR_DSR 0x0020 +#define CP210X_MSR_RING 0x0040 +#define CP210X_MSR_DCD 0x0080 +#define CP210X_MSR_ALL 0x00F0 + +#define CP210X_CONTROL_WRITE_DTR 0x0100 +#define CP210X_CONTROL_WRITE_RTS 0x0200 + +#define CP210X_LSR_BREAK 0x0001 +#define CP210X_LSR_FRAMING_ERROR 0x0002 +#define CP210X_LSR_HW_OVERRUN 0x0004 +#define CP210X_LSR_QUEUE_OVERRUN 0x0008 +#define CP210X_LSR_PARITY_ERROR 0x0010 +#define CP210X_LSR_ALL 0x001F + +// supported baudrates +// reference: datasheets and AN205 "CP210x Baud Rate Support" +#define CP210X_SUPPORTED_BAUDRATES_LIST { \ + 300, 600, \ + 1200, 1800, 2400, 4000, 4800, 7200, 9600, \ + 14400, 16000, 19200, 28800, 38400, 51200, 56000, 57600, 64000, 76800, \ + 115200, 128000, 153600, 230400, 250000, 256000, 460800, 500000, 576000, 921600, \ + 0 } + #endif //TUSB_CP210X_H diff --git a/src/tusb_option.h b/src/tusb_option.h index ebf9a4d4d..281341685 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -482,7 +482,9 @@ #ifndef CFG_TUH_CDC_CP210X_VID_PID_LIST // List of product IDs that can use the CP210X CDC driver. 0x10C4 is Silicon Labs' VID #define CFG_TUH_CDC_CP210X_VID_PID_LIST \ - {0x10C4, 0xEA60}, {0x10C4, 0xEA70} + { 0x10C4, 0xEA60 }, /* Silicon Labs factory default */ \ + { 0x10C4, 0xEA61 }, /* Silicon Labs factory default */ \ + { 0x10C4, 0xEA70 } /* Silicon Labs Dual Port factory default */ #endif #ifndef CFG_TUH_CDC_CH34X -- cgit v1.3.1 From aabee25e189d2a05cb52e5c54329ab1ec875f084 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 11:45:38 +0100 Subject: added PL2303 support --- examples/host/cdc_msc_hid/src/tusb_config.h | 1 + .../host/cdc_msc_hid_freertos/src/tusb_config.h | 1 + src/class/cdc/cdc_host.c | 754 ++++++++++++++++++++- src/class/cdc/serial/pl2303.h | 172 +++++ src/tusb_option.h | 18 + 5 files changed, 942 insertions(+), 4 deletions(-) create mode 100644 src/class/cdc/serial/pl2303.h (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index e4d74077f..fc956c6d3 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -106,6 +106,7 @@ #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_PL2303 1 // PL2303 Serial. PL2303 is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 9dc89dc55..dd732c700 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -111,6 +111,7 @@ #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API +#define CFG_TUH_CDC_PL2303 1 // PL2303 Serial. PL2303 is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_HID (3*CFG_TUH_DEVICE_MAX) // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MSC 1 #define CFG_TUH_VENDOR 0 diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 86c010fa7..429d0a113 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -38,6 +38,7 @@ #include "serial/ftdi_sio.h" #include "serial/cp210x.h" #include "serial/ch34x.h" +#include "serial/pl2303.h" // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUH_CDC_LOG_LEVEL @@ -91,6 +92,10 @@ typedef struct { ftdi_private_t ftdi; #endif + #if CFG_TUH_CDC_PL2303 + pl2303_private_t pl2303; + #endif + struct { tu_edpt_stream_t tx; tu_edpt_stream_t rx; @@ -105,7 +110,7 @@ typedef struct { CFG_TUH_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; -#if CFG_TUH_CDC_FTDI +#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_PL2303 static tusb_desc_device_t desc_dev[CFG_TUH_CDC][CFG_TUH_ENUMERATION_BUFSIZE]; #endif @@ -164,6 +169,22 @@ static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complet static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif +//------------- PL2303 prototypes -------------// +#if CFG_TUH_CDC_PL2303 +static uint16_t const pl2303_vid_pid_list[][2] = {CFG_TUH_CDC_PL2303_VID_PID_LIST}; +static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = {PL2303_TYPE_DATA}; + +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN + +static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +static void pl2303_process_config(tuh_xfer_t * xfer); + +static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool pl2303_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool pl2303_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +#endif + //------------- Common -------------// enum { SERIAL_DRIVER_ACM = 0, @@ -180,6 +201,10 @@ enum { SERIAL_DRIVER_CH34X, #endif +#if CFG_TUH_CDC_PL2303 + SERIAL_DRIVER_PL2303, +#endif + SERIAL_DRIVER_COUNT }; @@ -260,6 +285,22 @@ static const cdch_serial_driver_t serial_drivers[] = { #endif }, #endif + + #if CFG_TUH_CDC_PL2303 + { + .vid_pid_list = pl2303_vid_pid_list, + .vid_pid_count = TU_ARRAY_SIZE(pl2303_vid_pid_list), + .open = pl2303_open, + .process_set_config = pl2303_process_config, + .set_control_line_state = pl2303_set_modem_ctrl, + .set_baudrate = pl2303_set_baudrate, + .set_data_format = pl2303_set_data_format, + .set_line_coding = pl2303_set_line_coding, + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + .name = (uint8_t const *) "PL2303" + #endif + } + #endif }; TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial driver count mismatch"); @@ -1863,7 +1904,7 @@ static bool ch34x_modem_ctrl_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t com // internal control complete to update state such as line state, encoding static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { - // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber + // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t* p_cdc = get_itf(idx); @@ -1921,7 +1962,8 @@ static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_ } static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { - uint8_t const itf_num = 0; // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; set_line_coding_stage1_complete(xfer, itf_num, ch34x_write_reg_data_format, // control request function to set data format ch34x_internal_control_complete); // control complete function to be called after request @@ -1981,7 +2023,7 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uin } static void ch34x_process_config(tuh_xfer_t* xfer) { - // CH34x only has 1 interface and wIndex used as payload and not for bInterfaceNumber + // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uintptr_t const state = xfer->user_data; uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -2142,4 +2184,708 @@ static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { #endif // CFG_TUH_CDC_CH34X +//--------------------------------------------------------------------+ +// PL2303 +//--------------------------------------------------------------------+ +#if CFG_TUH_CDC_PL2303 + +static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, uint8_t step, + tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); + +//------------- Control Request -------------// + +static bool pl2303_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, uint8_t * buffer, uint16_t length, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + tusb_control_request_t const request_setup = { + .bmRequestType = requesttype, + .bRequest = request, + .wValue = tu_htole16 (value), + .wIndex = tu_htole16 (index), + .wLength = tu_htole16 (length) + }; + + // use usbh enum buf since application variable does not live long enough + uint8_t * enum_buf = NULL; + + if (buffer && length > 0) { + enum_buf = usbh_get_enum_buf(); + if (request_setup.bmRequestType_bit.direction == TUSB_DIR_OUT) { + tu_memcpy_s(enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length); + } + } + + tuh_xfer_t xfer = { + .daddr = p_cdc->daddr, + .ep_addr = 0, + .setup = &request_setup, + .buffer = enum_buf, + .complete_cb = complete_cb, + .user_data = user_data + }; + + return tuh_control_xfer(&xfer); +} + +static bool pl2303_vendor_read(cdch_interface_t * p_cdc, uint16_t value, uint8_t * buf, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? + PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; + + return pl2303_set_request(p_cdc, request, PL2303_VENDOR_READ_REQUEST_TYPE, value, 0, buf, 1, complete_cb, user_data); +} + +static bool pl2303_vendor_write(cdch_interface_t * p_cdc, uint16_t value, uint16_t index, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? + PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; + + return pl2303_set_request(p_cdc, request, PL2303_VENDOR_WRITE_REQUEST_TYPE, value, index, NULL, 0, complete_cb, user_data); +} + +static inline bool pl2303_supports_hx_status(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + uint8_t buf; + + return pl2303_set_request(p_cdc, PL2303_VENDOR_READ_REQUEST, PL2303_VENDOR_READ_REQUEST_TYPE, PL2303_READ_TYPE_HX_STATUS, 0, + &buf, 1, complete_cb, user_data); +} + +static inline bool pl2303_set_control_lines(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, + p_cdc->requested_line_state, 0, NULL, 0, complete_cb, user_data); +} + +//static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) +//{ +// return pl2303_set_request(p_cdc, PL2303_GET_LINE_REQUEST, PL2303_GET_LINE_REQUEST_TYPE, 0, 0, buf, PL2303_LINE_CODING_BUFSIZE); +//} + +static bool pl2303_set_line_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // the caller has to precheck, that the new line coding different than the current, else false returned + uint8_t buf[PL2303_LINE_CODING_BUFSIZE]; + /* + * Some PL2303 are known to lose bytes if you change serial settings + * even to the same values as before. Thus we actually need to filter + * in this specific case. + */ + // TODO really necessary to check? what to do in this case when no transfer will happen? + // callback is not called... + TU_VERIFY(memcmp(&p_cdc->requested_line_coding, &p_cdc->line_coding, sizeof(cdc_line_coding_t) ) != 0); + + /* For reference buf[6] data bits value */ + TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); + buf[6] = p_cdc->requested_line_coding.data_bits; + + /* For reference buf[0]:buf[3] baud rate value */ + TU_VERIFY(pl2303_encode_baud_rate(p_cdc, &buf[0])); + + /* For reference buf[4]=0 is 1 stop bits */ + /* For reference buf[4]=1 is 1.5 stop bits */ + /* For reference buf[4]=2 is 2 stop bits */ + buf[4] = p_cdc->requested_line_coding.stop_bits; // PL2303 has the same coding + + /* For reference buf[5]=0 is none parity */ + /* For reference buf[5]=1 is odd parity */ + /* For reference buf[5]=2 is even parity */ + /* For reference buf[5]=3 is mark parity */ + /* For reference buf[5]=4 is space parity */ + buf[5] = p_cdc->requested_line_coding.parity; // PL2303 has the same coding + + return pl2303_set_request(p_cdc, PL2303_SET_LINE_REQUEST, PL2303_SET_LINE_REQUEST_TYPE, 0, 0, + buf, PL2303_LINE_CODING_BUFSIZE, complete_cb, user_data); +} + +//static bool pl2303_set_break(cdch_interface_t * p_cdc, bool enable) +//{ +// uint16_t state = enable ? PL2303_BREAK_ON : PL2303_BREAK_OFF; +// return pl2303_set_request(p_cdc, PL2303_BREAK_REQUEST, PL2303_BREAK_REQUEST_TYPE, state, 0, NULL, 0); +//} + +static inline int pl2303_clear_halt(cdch_interface_t * p_cdc, uint8_t endp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) +{ + /* we don't care if it wasn't halted first. in fact some devices + * (like some ibmcam model 1 units) seem to expect hosts to make + * this request for iso endpoints, which can't halt! + */ + return pl2303_set_request(p_cdc, TUSB_REQ_CLEAR_FEATURE, PL2303_CLEAR_HALT_REQUEST_TYPE, TUSB_REQ_FEATURE_EDPT_HALT, endp, + NULL, 0, complete_cb, user_data); +} + +//------------- Driver API -------------// + +// internal control complete to update state such as line state, encoding +static void pl2303_internal_control_complete(tuh_xfer_t * xfer) { + // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; + uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + bool const success = (xfer->result == XFER_RESULT_SUCCESS); + TU_LOG_P_CDC("control complete success = %u", success); + + if (success) { + if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { + p_cdc->line_coding = p_cdc->requested_line_coding; + } + if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { + p_cdc->line_state = p_cdc->requested_line_state; + } + } + + xfer->complete_cb = p_cdc->user_control_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + +static bool pl2303_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + + return true; +} + +static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + + return true; +} + +static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; + p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; + p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + + return true; +} + +static bool pl2303_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // PL2303 has the same bit coding + p_cdc->user_control_cb = complete_cb; + TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + + return true; +} + +//------------- Enumeration -------------// + +enum { + CONFIG_PL2303_GET_DESC = 0, + CONFIG_PL2303_DETECT_TYPE, + CONFIG_PL2303_READ1, + CONFIG_PL2303_WRITE1, + CONFIG_PL2303_READ2, + CONFIG_PL2303_READ3, + CONFIG_PL2303_READ4, + CONFIG_PL2303_WRITE2, + CONFIG_PL2303_READ5, + CONFIG_PL2303_READ6, + CONFIG_PL2303_WRITE3, + CONFIG_PL2303_WRITE4, + CONFIG_PL2303_WRITE5, + CONFIG_PL2303_RESET_ENDP1, + CONFIG_PL2303_RESET_ENDP2, + CONFIG_PL2303_LINE_CODING, + CONFIG_PL2303_MODEM_CONTROL, + CONFIG_PL2303_FLOW_CTRL_READ, + CONFIG_PL2303_FLOW_CTRL_WRITE, + CONFIG_PL2303_COMPLETE +}; + +static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { + // PL2303 Interface includes 1 vendor interface + 1 interrupt endpoints + 2 bulk + TU_VERIFY(itf_desc->bNumEndpoints == 3); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); + + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); + + p_cdc->serial_drid = SERIAL_DRIVER_PL2303; + p_cdc->pl2303.serial_private.quirks = 0; + p_cdc->pl2303.supports_hx_status = false; + + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const * ) tu_desc_next(itf_desc); + + // Interrupt endpoint: not used for now + TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) && + TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer); + TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); + p_cdc->ep_notif = desc_ep->bEndpointAddress; + desc_ep += 1; + + // data endpoints expected to be in pairs + TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); + + return true; +} + +static void pl2303_process_config(tuh_xfer_t * xfer) { + // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber + uint8_t const itf_num = 0; + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); + cdch_interface_t * p_cdc = get_itf(idx); + // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() + TU_ASSERT_COMPLETE(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); + uint8_t buf; + int8_t type; + + switch (xfer->user_data) { + + // from here sequence overtaken from Linux Kernel function pl2303_startup() + case CONFIG_PL2303_GET_DESC: + p_cdc->user_control_cb = pl2303_process_config; // set once for whole process config + // get device descriptor + TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, desc_dev[idx], sizeof(tusb_desc_device_t), + pl2303_process_config, CONFIG_PL2303_DETECT_TYPE)); + break; + + case CONFIG_PL2303_DETECT_TYPE: + // get type and quirks (step 1) + type = pl2303_detect_type (p_cdc, idx, 1, pl2303_process_config, CONFIG_PL2303_READ1); // step 1 + TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); + if (type == PL2303_SUPPORTS_HX_STATUS_TRIGGERED) { + break; + } // else: no transfer triggered and continue with CONFIG_PL2303_READ1 + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ1: + // get supports_hx_status, type and quirks (step 2), do special read + p_cdc->pl2303.supports_hx_status = ( // will not be true, if coming directly from previous case + xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS ); + type = pl2303_detect_type (p_cdc, idx, 2, NULL, 0); // step 2 now with supports_hx_status + TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); + p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; + p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; + #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0 // can be activated if necessary + TU_LOG(CFG_TUH_CDC_LOG_LEVEL, "PL2303 bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", + desc_dev[idx]->bDeviceClass, desc_dev[idx]->bMaxPacketSize0, desc_dev[idx]->bcdUSB, desc_dev[idx]->bcdDevice ); + uint16_t vid, pid; + TU_ASSERT_COMPLETE(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); + TU_LOG(CFG_TUH_CDC_LOG_LEVEL, " vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", + vid, pid, p_cdc->pl2303.supports_hx_status, + p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); + #endif + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_WRITE1)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_WRITE1: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0x0404, 0, pl2303_process_config, CONFIG_PL2303_READ2)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ2: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_READ3)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ3: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8383, &buf, pl2303_process_config, CONFIG_PL2303_READ4)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ4: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_WRITE2)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_WRITE2: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0x0404, 1, pl2303_process_config, CONFIG_PL2303_READ5)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ5: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_READ6)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_READ6: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8383, &buf, pl2303_process_config, CONFIG_PL2303_WRITE3)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_WRITE3: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, 1, pl2303_process_config, CONFIG_PL2303_WRITE4)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_WRITE4: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 1, 0, pl2303_process_config, CONFIG_PL2303_WRITE5)); + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + case CONFIG_PL2303_WRITE5: + // purpose unknown, overtaken from Linux Kernel driver + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 2, 0x24, pl2303_process_config, CONFIG_PL2303_RESET_ENDP1)); + } else { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 2, 0x44, pl2303_process_config, CONFIG_PL2303_RESET_ENDP1)); + } + break; + } // else: continue with next step + TU_ATTR_FALLTHROUGH; + + // from here sequence overtaken from Linux Kernel function pl2303_open() + case CONFIG_PL2303_RESET_ENDP1: + // step 1 + if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { + TU_ASSERT_COMPLETE(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, pl2303_process_config, CONFIG_PL2303_RESET_ENDP2)); + } else { + /* reset upstream data pipes */ + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG, // skip CONFIG_PL2303_RESET_ENDP2, no 2nd step + PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, + pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + } else { + pl2303_vendor_write(p_cdc, 8, 0, pl2303_process_config, CONFIG_PL2303_RESET_ENDP2); + } + } + break; + + case CONFIG_PL2303_RESET_ENDP2: + // step 2 + if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { + TU_ASSERT_COMPLETE(pl2303_clear_halt(p_cdc, PL2303_IN_EP, pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + } else { + /* reset upstream data pipes */ + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + // here nothing to do, only structure of previous step overtaken for better reading and comparison + } else { + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 9, 0, pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + } + } + break; + + // from here sequence overtaken from Linux Kernel function pl2303_set_termios() + // unnecessary pl2303_get_line_request() is skipped due to a stall + case CONFIG_PL2303_LINE_CODING: + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT_COMPLETE( pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_PL2303_MODEM_CONTROL: + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_FLOW_CTRL_READ)); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case CONFIG_PL2303_FLOW_CTRL_READ: + // read flow control register for modify & write back in next step + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, pl2303_process_config, + CONFIG_PL2303_FLOW_CTRL_WRITE)); + } else { + TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0, &buf, pl2303_process_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); + } + break; + + case CONFIG_PL2303_FLOW_CTRL_WRITE: + // no flow control + buf = xfer->buffer[0]; + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; + buf |= PL2303_HXN_FLOWCTRL_NONE; + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, pl2303_process_config, + CONFIG_PL2303_COMPLETE)); + } else { + buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; + TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, buf, pl2303_process_config, CONFIG_PL2303_COMPLETE)); + } + break; + + case CONFIG_PL2303_COMPLETE: + set_config_complete(idx, 0, true); + break; + + default: + set_config_complete(idx, 0, false); + break; + } +} + +//------------- Helper -------------// + +static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, uint8_t step, + tuh_xfer_cb_t complete_cb, uintptr_t user_data ) +{ + /* + * Legacy PL2303H, variants 0 and 1 (difference unknown). + */ + if (desc_dev[idx]->bDeviceClass == 0x02) { + return TYPE_H; /* variant 0 */ + } + + if (desc_dev[idx]->bMaxPacketSize0 != 0x40) { + if (desc_dev[idx]->bDeviceClass == 0x00 || desc_dev[idx]->bDeviceClass == 0xff) { + return TYPE_H; /* variant 1 */ + } + return TYPE_H; /* variant 0 */ + } + + switch (desc_dev[idx]->bcdUSB) { + case 0x101: + /* USB 1.0.1? Let's assume they meant 1.1... */ + TU_ATTR_FALLTHROUGH; + case 0x110: + switch (desc_dev[idx]->bcdDevice) { + case 0x300: + return TYPE_HX; + case 0x400: + return TYPE_HXD; + default: + return TYPE_HX; + } + break; + case 0x200: + switch (desc_dev[idx]->bcdDevice) { + case 0x100: /* GC */ + case 0x105: + return TYPE_HXN; + case 0x300: /* GT / TA */ + if (step == 1) { + // step 1 trigger pl2303_supports_hx_status() request + TU_ASSERT(pl2303_supports_hx_status (p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); + return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; + } else { + // step 2 use supports_hx_status + if (p_cdc->pl2303.supports_hx_status) { + return TYPE_TA; + } + } + TU_ATTR_FALLTHROUGH; + case 0x305: + case 0x400: /* GL */ + case 0x405: + return TYPE_HXN; + case 0x500: /* GE / TB */ + if (step == 1) { + // step 1 trigger pl2303_supports_hx_status() request + TU_ASSERT(pl2303_supports_hx_status (p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); + return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; + } else { + // step 2 use supports_hx_status + if (p_cdc->pl2303.supports_hx_status) { + return TYPE_TB; + } + } + TU_ATTR_FALLTHROUGH; + case 0x505: + case 0x600: /* GS */ + case 0x605: + case 0x700: /* GR */ + case 0x705: + return TYPE_HXN; + default: + break; + } + break; + default: break; + } + + TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev[idx]->bcdUSB); + + return PL2303_DETECT_TYPE_FAILED; +} + +/* + * Returns the nearest supported baud rate that can be set directly without + * using divisors. + */ +static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) +{ + static const uint32_t baud_sup[] = { + 75, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, + 14400, 19200, 28800, 38400, 57600, 115200, 230400, 460800, + 614400, 921600, 1228800, 2457600, 3000000, 6000000 + }; + + uint8_t i; + for (i = 0; i < TU_ARRAY_SIZE(baud_sup); ++i) { + if (baud_sup[i] > baud) { + break; + } + } + + if (i == TU_ARRAY_SIZE(baud_sup)) { + baud = baud_sup[i - 1]; + } else if (i > 0 && (baud_sup[i] - baud) > (baud - baud_sup[i - 1])) { + baud = baud_sup[i - 1]; + } else { + baud = baud_sup[i]; + } + + return baud; +} + +/* + * NOTE: If unsupported baud rates are set directly, the PL2303 seems to + * use 9600 baud. + */ +static uint32_t pl2303_encode_baud_rate_direct(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) +{ + uint32_t baud_le = tu_htole32(baud); + buf[0] = (uint8_t) ( baud_le & 0xff); + buf[1] = (uint8_t) ((baud_le >> 8) & 0xff); + buf[2] = (uint8_t) ((baud_le >> 16) & 0xff); + buf[3] = (uint8_t) ((baud_le >> 24) & 0xff); + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) +{ + uint32_t baseline, mantissa, exponent; + + /* + * Apparently the formula is: + * baudrate = 12M * 32 / (mantissa * 4^exponent) + * where + * mantissa = buf[8:0] + * exponent = buf[11:9] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) + mantissa = 1; /* Avoid dividing by zero if baud > 32 * 12M. */ + exponent = 0; + while (mantissa >= 512) { + if (exponent < 7) { + mantissa >>= 2; /* divide by 4 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 511; + break; + } + } + + buf[3] = 0x80; + buf[2] = 0; + buf[1] = (uint8_t) ((exponent << 1 | mantissa >> 8) & 0xff); + buf[0] = (uint8_t) (mantissa & 0xff); + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> (exponent << 1); + + return baud; +} + +static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) +{ + uint32_t baseline, mantissa, exponent; + + /* + * Apparently, for the TA version the formula is: + * baudrate = 12M * 32 / (mantissa * 2^exponent) + * where + * mantissa = buf[10:0] + * exponent = buf[15:13 16] + */ + baseline = 12000000 * 32; + mantissa = baseline / baud; + if (mantissa == 0) { + mantissa = 1; /* Avoid dividing by zero if baud > 32 * 12M. */ + } + exponent = 0; + while (mantissa >= 2048) { + if (exponent < 15) { + mantissa >>= 1; /* divide by 2 */ + exponent++; + } else { + /* Exponent is maxed. Trim mantissa and leave. */ + mantissa = 2047; + break; + } + } + + buf[3] = 0x80; + buf[2] = (uint8_t) (exponent & 0x01); + buf[1] = (uint8_t) (((exponent & (uint32_t) ~0x01) << 4 | mantissa >> 8 ) & 0xff); + buf[0] = (uint8_t) (mantissa & 0xff); + + /* Calculate and return the exact baud rate. */ + baud = (baseline / mantissa) >> exponent; + + return baud; +} + +static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]) +{ + uint32_t baud = p_cdc->requested_line_coding.bit_rate; + uint32_t baud_sup; + + TU_VERIFY(baud && baud <= p_cdc->pl2303.serial_private.type->max_baud_rate); + /* + * Use direct method for supported baud rates, otherwise use divisors. + * Newer chip types do not support divisor encoding. + */ + if (p_cdc->pl2303.serial_private.type->no_divisors) { + baud_sup = baud; + } else { + baud_sup = pl2303_get_supported_baud_rate(baud); + } + + if (baud == baud_sup) { + baud = pl2303_encode_baud_rate_direct(buf, baud); + } else if (p_cdc->pl2303.serial_private.type->alt_divisors) { + baud = pl2303_encode_baud_rate_divisor_alt(buf, baud); + } else { + baud = pl2303_encode_baud_rate_divisor(buf, baud); + } + TU_LOG_P_CDC("real baudrate = %lu", baud); + + return true; +} + +#endif // CFG_TUH_CDC_PL2303 + #endif diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h new file mode 100644 index 000000000..bf264191b --- /dev/null +++ b/src/class/cdc/serial/pl2303.h @@ -0,0 +1,172 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Heiko Kuester + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _PL2303_H_ +#define _PL2303_H_ + +#include +#include + +// There is no official documentation for the PL2303 chips. +// Reference can be found +// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.h and +// https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.c +// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uplcom.c + +/* quirks */ +#define PL2303_QUIRK_UART_STATE_IDX0 1 +#define PL2303_QUIRK_LEGACY 2 +#define PL2303_QUIRK_ENDPOINT_HACK 4 + +/* requests and bits */ +#define PL2303_SET_LINE_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_SET_LINE_REQUEST 0x20 // dec 32 + +#define PL2303_SET_CONTROL_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_SET_CONTROL_REQUEST 0x22 // dec 34 +#define PL2303_CONTROL_DTR 0x01 // dec 1 +#define PL2303_CONTROL_RTS 0x02 // dec 2 + +#define PL2303_BREAK_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_BREAK_REQUEST 0x23 // dec 35 +#define PL2303_BREAK_ON 0xffff +#define PL2303_BREAK_OFF 0x0000 + +#define PL2303_GET_LINE_REQUEST_TYPE 0xa1 // class request device to host interface +#define PL2303_GET_LINE_REQUEST 0x21 // dec 33 + +#define PL2303_VENDOR_WRITE_REQUEST_TYPE 0x40 // vendor request host to device interface +#define PL2303_VENDOR_WRITE_REQUEST 0x01 // dec 1 +#define PL2303_VENDOR_WRITE_NREQUEST 0x80 // dec 128 + +#define PL2303_VENDOR_READ_REQUEST_TYPE 0xc0 // vendor request device to host interface +#define PL2303_VENDOR_READ_REQUEST 0x01 // dec 1 +#define PL2303_VENDOR_READ_NREQUEST 0x81 // dec 129 + +#define PL2303_UART_STATE_INDEX 8 +#define PL2303_UART_STATE_MSR_MASK 0x8b +#define PL2303_UART_STATE_TRANSIENT_MASK 0x74 +#define PL2303_UART_DCD 0x01 +#define PL2303_UART_DSR 0x02 +#define PL2303_UART_BREAK_ERROR 0x04 +#define PL2303_UART_RING 0x08 +#define PL2303_UART_FRAME_ERROR 0x10 +#define PL2303_UART_PARITY_ERROR 0x20 +#define PL2303_UART_OVERRUN_ERROR 0x40 +#define PL2303_UART_CTS 0x80 + +#define PL2303_FLOWCTRL_MASK 0xf0 + +#define PL2303_CLEAR_HALT_REQUEST_TYPE 0x02 // standard request host to device endpoint + +/* registers via vendor read/write requests */ +#define PL2303_READ_TYPE_HX_STATUS 0x8080 + +#define PL2303_HXN_RESET_REG 0x07 +#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 +#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 + +#define PL2303_HXN_FLOWCTRL_REG 0x0a +#define PL2303_HXN_FLOWCTRL_MASK 0x1c +#define PL2303_HXN_FLOWCTRL_NONE 0x1c +#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 +#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c + +/* type data */ +enum pl2303_type { + TYPE_H, + TYPE_HX, + TYPE_TA, + TYPE_TB, + TYPE_HXD, + TYPE_HXN, + TYPE_COUNT +}; + +struct pl2303_type_data { + uint8_t const *name; + uint32_t const max_baud_rate; + uint8_t const quirks; + uint16_t const no_autoxonxoff:1; + uint16_t const no_divisors:1; + uint16_t const alt_divisors:1; +}; + +#define PL2303_TYPE_DATA \ + [TYPE_H] = { \ + .name = (uint8_t const*)"H", \ + .max_baud_rate = 1228800, \ + .quirks = PL2303_QUIRK_LEGACY, \ + .no_autoxonxoff = true, \ + }, \ + [TYPE_HX] = { \ + .name = (uint8_t const*)"HX", \ + .max_baud_rate = 6000000, \ + }, \ + [TYPE_TA] = { \ + .name = (uint8_t const*)"TA", \ + .max_baud_rate = 6000000, \ + .alt_divisors = true, \ + }, \ + [TYPE_TB] = { \ + .name = (uint8_t const*)"TB", \ + .max_baud_rate = 12000000, \ + .alt_divisors = true, \ + }, \ + [TYPE_HXD] = { \ + .name = (uint8_t const*)"HXD", \ + .max_baud_rate = 12000000, \ + }, \ + [TYPE_HXN] = { \ + .name = (uint8_t const*)"G (HXN)", \ + .max_baud_rate = 12000000, \ + .no_divisors = true, \ + } + +/* private data types */ +struct pl2303_serial_private { + const struct pl2303_type_data* type; + uint8_t quirks; +}; + +typedef struct TU_ATTR_PACKED { + struct pl2303_serial_private serial_private; + bool supports_hx_status; +} pl2303_private_t; + +/* buffer sizes for line coding data */ +#define PL2303_LINE_CODING_BUFSIZE 7 +#define PL2303_LINE_CODING_BAUDRATE_BUFSIZE 4 + +/* bulk endpoints */ +#define PL2303_OUT_EP 0x02 +#define PL2303_IN_EP 0x83 + +/* return values of pl2303_detect_type() */ +#define PL2303_SUPPORTS_HX_STATUS_TRIGGERED -1 +#define PL2303_DETECT_TYPE_FAILED -2 + +#endif /* _PL2303_H_ */ diff --git a/src/tusb_option.h b/src/tusb_option.h index 281341685..f023b490a 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -504,6 +504,24 @@ { 0x9986, 0x7523 } /* overtaken from Linux Kernel driver /drivers/usb/serial/ch341.c */ #endif +#ifndef CFG_TUH_CDC_PL2303 + // PL2303 is not part of CDC class, only to re-use CDC driver API + #define CFG_TUH_CDC_PL2303 0 +#endif + +#ifndef CFG_TUH_CDC_PL2303_VID_PID_QUIRKS_LIST + // List of product IDs that can use the PL2303 CDC driver + #define CFG_TUH_CDC_PL2303_VID_PID_LIST \ + { 0x067b, 0x2303 }, /* initial 2303 */ \ + { 0x067b, 0x2304 }, /* TB */ \ + { 0x067b, 0x23a3 }, /* GC */ \ + { 0x067b, 0x23b3 }, /* GB */ \ + { 0x067b, 0x23c3 }, /* GT */ \ + { 0x067b, 0x23d3 }, /* GL */ \ + { 0x067b, 0x23e3 }, /* GE */ \ + { 0x067b, 0x23f3 } /* GS */ +#endif + #ifndef CFG_TUH_HID #define CFG_TUH_HID 0 #endif -- cgit v1.3.1 From ea175a78aad5bd258954aa61550aae0162bc884b Mon Sep 17 00:00:00 2001 From: IngHK Date: Sat, 24 Feb 2024 13:00:46 +0100 Subject: updated contribution, readme and some comments --- CONTRIBUTORS.rst | 7 +++++++ README.rst | 2 +- src/class/cdc/cdc_host.c | 6 +++--- 3 files changed, 11 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/CONTRIBUTORS.rst b/CONTRIBUTORS.rst index 085f8082a..451ac0783 100644 --- a/CONTRIBUTORS.rst +++ b/CONTRIBUTORS.rst @@ -31,6 +31,13 @@ Notable contributors - Most features development +`Heiko Kuester `__ +-------------------------------------------- + +- Add CH34x and PL2303 support (CDC host) +- Improve FTDI and CP210x support (CDC host) + + `Hristo Gochkov `__ ------------------------------------------------- diff --git a/README.rst b/README.rst index fe2417451..6922c231e 100644 --- a/README.rst +++ b/README.rst @@ -77,7 +77,7 @@ Host Stack - Human Interface Device (HID): Keyboard, Mouse, Generic - Mass Storage Class (MSC) - Communication Device Class: CDC-ACM -- Vendor serial over USB: FTDI, CP210x +- Vendor serial over USB: FTDI, CP210x, CH34x, PL2303 - Hub with multiple-level support Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 429d0a113..b35a8fd93 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -24,7 +24,7 @@ * This file is part of the TinyUSB stack. * * Contribution - * - Heiko Kuester: CH34x support + * - Heiko Kuester: add support of CH34x & PL2303, improve support of FTDI & CP210x */ #include "tusb_option.h" @@ -818,12 +818,12 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set config"); - // fake transfer to kick-off process + // fake transfer to kick-off process_set_config() tuh_xfer_t xfer; xfer.daddr = daddr; xfer.result = XFER_RESULT_SUCCESS; xfer.setup = &request; - xfer.user_data = 0; // initial state + xfer.user_data = 0; // initial state 0 serial_drivers[p_cdc->serial_drid].process_set_config(&xfer); return true; -- cgit v1.3.1 From 2b507dba4d9901d1208c4166bbc6026bb6062c9b Mon Sep 17 00:00:00 2001 From: IngHK Date: Sat, 24 Feb 2024 13:01:38 +0100 Subject: small changes & code style --- src/class/cdc/cdc_host.c | 236 +++++++++++++++++++++++++---------------------- 1 file changed, 124 insertions(+), 112 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b35a8fd93..50aa4b6f0 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -85,7 +85,7 @@ typedef struct { tuh_xfer_cb_t user_control_cb; #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X - tuh_xfer_cb_t requested_complete_cb; + tuh_xfer_cb_t requested_complete_cb; #endif #if CFG_TUH_CDC_FTDI @@ -119,54 +119,54 @@ static cdch_interface_t cdch_data[CFG_TUH_CDC]; //--------------------------------------------------------------------+ //------------- ACM prototypes -------------// -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); -static void acm_process_config(tuh_xfer_t* xfer); +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +static void acm_process_config(tuh_xfer_t * xfer); -static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL -static uint8_t const * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; + static uint8_t const * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; #endif -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); -static void ftdi_process_config(tuh_xfer_t* xfer); +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); +static void ftdi_process_config(tuh_xfer_t * xfer); -static bool ftdi_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CP210X prototypes -------------// #if CFG_TUH_CDC_CP210X static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST}; -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); -static void cp210x_process_config(tuh_xfer_t* xfer); +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +static void cp210x_process_config(tuh_xfer_t * xfer); -static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- CH34x prototypes -------------// #if CFG_TUH_CDC_CH34X static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; -static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len); -static void ch34x_process_config(tuh_xfer_t* xfer); +static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); +static void ch34x_process_config(tuh_xfer_t * xfer); -static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_modem_ctrl(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif //------------- PL2303 prototypes -------------// @@ -211,14 +211,14 @@ enum { typedef struct { uint16_t const (*vid_pid_list)[2]; uint16_t const vid_pid_count; - bool (*const open)(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len); - void (*const process_set_config)(tuh_xfer_t* xfer); - bool (*const set_control_line_state)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_baudrate)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_data_format)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_line_coding)(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const open)(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); + void (*const process_set_config)(tuh_xfer_t * xfer); + bool (*const set_control_line_state)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_baudrate)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_data_format)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + bool (*const set_line_coding)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - uint8_t const * name; + uint8_t const * name; #endif } cdch_serial_driver_t; @@ -309,17 +309,17 @@ TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial d // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static inline cdch_interface_t* get_itf(uint8_t idx) { +static inline cdch_interface_t * get_itf(uint8_t idx) { TU_ASSERT(idx < CFG_TUH_CDC, NULL); - cdch_interface_t* p_cdc = &cdch_data[idx]; + cdch_interface_t * p_cdc = &cdch_data[idx]; return (p_cdc->daddr != 0) ? p_cdc : NULL; } static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { for(uint8_t i=0; idaddr == daddr) && + cdch_interface_t * p_cdc = &cdch_data[i]; + if ((p_cdc->daddr == daddr) && (ep_addr == p_cdc->ep_notif || ep_addr == p_cdc->stream.rx.ep_addr || ep_addr == p_cdc->stream.tx.ep_addr)) { return i; } @@ -328,10 +328,10 @@ static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { return TUSB_INDEX_INVALID_8; } -static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const *itf_desc) { +static cdch_interface_t * make_new_itf(uint8_t daddr, tusb_desc_interface_t const * itf_desc) { for(uint8_t i=0; idaddr = daddr; p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; @@ -345,7 +345,7 @@ static cdch_interface_t* make_new_itf(uint8_t daddr, tusb_desc_interface_t const return NULL; } -static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t const *desc_ep); +static bool open_ep_stream_pair(cdch_interface_t * p_cdc , tusb_desc_endpoint_t const *desc_ep); //--------------------------------------------------------------------+ // APPLICATION API @@ -353,21 +353,21 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc , tusb_desc_endpoint_t c uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) { for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { - const cdch_interface_t* p_cdc = &cdch_data[i]; + const cdch_interface_t * p_cdc = &cdch_data[i]; if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; } return TUSB_INDEX_INVALID_8; } -bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { - cdch_interface_t* p_cdc = get_itf(idx); +bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t * info) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && info); info->daddr = p_cdc->daddr; // re-construct descriptor - tusb_desc_interface_t* desc = &info->desc; + tusb_desc_interface_t * desc = &info->desc; desc->bLength = sizeof(tusb_desc_interface_t); desc->bDescriptorType = TUSB_DESC_INTERFACE; @@ -383,27 +383,27 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { } bool tuh_cdc_mounted(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return p_cdc->mounted; } bool tuh_cdc_get_dtr(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; } bool tuh_cdc_get_rts(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; } -bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) { - cdch_interface_t* p_cdc = get_itf(idx); +bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t * line_coding) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); *line_coding = p_cdc->line_coding; @@ -415,29 +415,29 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding) // Write //--------------------------------------------------------------------+ -uint32_t tuh_cdc_write(uint8_t idx, void const* buffer, uint32_t bufsize) { - cdch_interface_t* p_cdc = get_itf(idx); +uint32_t tuh_cdc_write(uint8_t idx, void const * buffer, uint32_t bufsize) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_write(&p_cdc->stream.tx, buffer, bufsize); } uint32_t tuh_cdc_write_flush(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_write_xfer(&p_cdc->stream.tx); } bool tuh_cdc_write_clear(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_clear(&p_cdc->stream.tx); } uint32_t tuh_cdc_write_available(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_write_available(&p_cdc->stream.tx); @@ -447,33 +447,34 @@ uint32_t tuh_cdc_write_available(uint8_t idx) { // Read //--------------------------------------------------------------------+ -uint32_t tuh_cdc_read (uint8_t idx, void* buffer, uint32_t bufsize) { - cdch_interface_t* p_cdc = get_itf(idx); +uint32_t tuh_cdc_read (uint8_t idx, void * buffer, uint32_t bufsize) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_read(&p_cdc->stream.rx, buffer, bufsize); } uint32_t tuh_cdc_read_available(uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_read_available(&p_cdc->stream.rx); } -bool tuh_cdc_peek(uint8_t idx, uint8_t* ch) { - cdch_interface_t* p_cdc = get_itf(idx); +bool tuh_cdc_peek(uint8_t idx, uint8_t * ch) { + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); } bool tuh_cdc_read_clear (uint8_t idx) { - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); bool ret = tu_edpt_stream_clear(&p_cdc->stream.rx); tu_edpt_stream_read_xfer(&p_cdc->stream.rx); + return ret; } @@ -657,7 +658,7 @@ void cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); for (size_t i = 0; i < CFG_TUH_CDC; i++) { - cdch_interface_t* p_cdc = &cdch_data[i]; + cdch_interface_t * p_cdc = &cdch_data[i]; tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, @@ -671,7 +672,7 @@ void cdch_init(void) { void cdch_close(uint8_t daddr) { for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { - cdch_interface_t* p_cdc = &cdch_data[idx]; + cdch_interface_t * p_cdc = &cdch_data[idx]; if (p_cdc->daddr == daddr) { TU_LOG_P_CDC("close"); @@ -695,35 +696,37 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc); - if ( ep_addr == p_cdc->stream.tx.ep_addr ) { + if (ep_addr == p_cdc->stream.tx.ep_addr) { // invoke tx complete callback to possibly refill tx fifo if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx); - if ( 0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx) ) { + if (0 == tu_edpt_stream_write_xfer(&p_cdc->stream.tx)) { // If there is no data left, a ZLP should be sent if: // - xferred_bytes is multiple of EP Packet size and not zero tu_edpt_stream_write_zlp_if_needed(&p_cdc->stream.tx, xferred_bytes); } - } else if ( ep_addr == p_cdc->stream.rx.ep_addr ) { + } else if (ep_addr == p_cdc->stream.rx.ep_addr) { #if CFG_TUH_CDC_FTDI if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) { // FTDI reserve 2 bytes for status // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]}; tu_edpt_stream_read_xfer_complete_offset(&p_cdc->stream.rx, xferred_bytes, 2); - }else + } else #endif { tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); } // invoke receive callback - if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); + if (tuh_cdc_rx_cb) { + tuh_cdc_rx_cb(idx); + } // prepare for next transfer if needed tu_edpt_stream_read_xfer(&p_cdc->stream.rx); - }else if ( ep_addr == p_cdc->ep_notif ) { + } else if (ep_addr == p_cdc->ep_notif) { // TODO handle notification endpoint - }else { + } else { TU_ASSERT(false); } @@ -734,7 +737,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // Enumeration //--------------------------------------------------------------------+ -static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t const* desc_ep) { +static bool open_ep_stream_pair(cdch_interface_t * p_cdc, tusb_desc_endpoint_t const * desc_ep) { for (size_t i = 0; i < 2; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); @@ -746,13 +749,13 @@ static bool open_ep_stream_pair(cdch_interface_t* p_cdc, tusb_desc_endpoint_t co tu_edpt_stream_open(&p_cdc->stream.tx, p_cdc->daddr, desc_ep); } - desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(desc_ep); + desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(desc_ep); } return true; } -bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { +bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { (void) rhport; cdch_serial_driver_t const * driver_detected = NULL; @@ -826,6 +829,7 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { xfer.user_data = 0; // initial state 0 serial_drivers[p_cdc->serial_drid].process_set_config(&xfer); + return true; } @@ -864,7 +868,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = { @@ -886,15 +890,16 @@ static bool acm_set_control_line_state(cdch_interface_t* p_cdc, tuh_xfer_cb_t co .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call + .complete_cb = complete_cb ? acm_internal_control_complete : NULL, .user_data = user_data }; TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } -static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); TU_VERIFY(p_cdc->requested_line_coding.data_bits && p_cdc->requested_line_coding.bit_rate); TU_VERIFY((p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8) || @@ -913,30 +918,32 @@ static bool acm_set_line_coding(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_ }; // use usbh enum buf to hold line coding since user line_coding variable does not live long enough - uint8_t* enum_buf = usbh_get_enum_buf(); + uint8_t * enum_buf = usbh_get_enum_buf(); memcpy(enum_buf, &p_cdc->requested_line_coding, sizeof(cdc_line_coding_t)); p_cdc->user_control_cb = complete_cb; + tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, .setup = &request, .buffer = enum_buf, - .complete_cb = complete_cb ? acm_internal_control_complete : NULL, // complete_cb is NULL for sync call + .complete_cb = complete_cb ? acm_internal_control_complete : NULL, .user_data = user_data }; TU_ASSERT(tuh_control_xfer(&xfer)); + return true; } -static bool acm_set_data_format(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; return acm_set_line_coding(p_cdc, complete_cb, user_data); } -static bool acm_set_baudrate(cdch_interface_t* p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; @@ -952,21 +959,22 @@ enum { CONFIG_ACM_COMPLETE, }; -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { - uint8_t const* p_desc_end = ((uint8_t const*) itf_desc) + max_len; +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { + uint8_t const * p_desc_end = ((uint8_t const *) itf_desc) + max_len; - cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); + p_cdc->serial_drid = SERIAL_DRIVER_ACM; //------------- Control Interface -------------// - uint8_t const* p_desc = tu_desc_next(itf_desc); + uint8_t const * p_desc = tu_desc_next(itf_desc); // Communication Functional Descriptors while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) { // save ACM bmCapabilities - p_cdc->acm_capability = ((cdc_desc_func_acm_t const*) p_desc)->bmCapabilities; + p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; } p_desc = tu_desc_next(p_desc); @@ -975,7 +983,7 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint1 // Open notification endpoint of control interface if any if (itf_desc->bNumEndpoints == 1) { TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); - tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) p_desc; + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); p_cdc->ep_notif = desc_ep->bEndpointAddress; @@ -985,22 +993,22 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint1 //------------- Data Interface (if any) -------------// if ((TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) && - (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const*) p_desc)->bInterfaceClass)) { + (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass)) { // next to endpoint descriptor p_desc = tu_desc_next(p_desc); // data endpoints expected to be in pairs - TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const*) p_desc)); + TU_ASSERT(open_ep_stream_pair(p_cdc, (tusb_desc_endpoint_t const *) p_desc)); } return true; } -static void acm_process_config(tuh_xfer_t* xfer) { +static void acm_process_config(tuh_xfer_t * xfer) { uintptr_t const state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS, 1); switch (state) { @@ -1814,8 +1822,9 @@ static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc); //------------- Control Request -------------// -static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, - uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_set_request(cdch_interface_t * p_cdc, uint8_t direction, uint8_t request, + uint16_t value, uint16_t index, uint8_t * buffer, uint16_t length, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, @@ -1829,7 +1838,7 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_ }; // use usbh enum buf since application variable does not live long enough - uint8_t* enum_buf = NULL; + uint8_t * enum_buf = NULL; if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); @@ -1850,22 +1859,23 @@ static bool ch34x_set_request(cdch_interface_t* p_cdc, uint8_t direction, uint8_ return tuh_control_xfer(&xfer); } -static inline bool ch34x_control_out(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, +static inline bool ch34x_control_out(cdch_interface_t * p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data); } -static inline bool ch34x_control_in(cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, - uint8_t* buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ch34x_control_in(cdch_interface_t * p_cdc, uint8_t request, uint16_t value, uint16_t index, + uint8_t * buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data); } -static inline bool ch34x_write_reg(cdch_interface_t* p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ch34x_write_reg(cdch_interface_t * p_cdc, uint16_t reg, uint16_t reg_value, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data); } -//static bool ch34x_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, +//static bool ch34x_read_reg_request ( cdch_interface_t * p_cdc, uint16_t reg, // uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) //{ // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); @@ -1907,8 +1917,8 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC("control complete success = %u", success); @@ -1997,17 +2007,17 @@ enum { CONFIG_CH34X_COMPLETE }; -static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uint16_t max_len) { +static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { // CH34x Interface includes 1 vendor interface + 2 bulk + 1 interrupt endpoints - TU_VERIFY (itf_desc->bNumEndpoints == 3); - TU_VERIFY (sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); + TU_VERIFY(itf_desc->bNumEndpoints == 3); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); - cdch_interface_t* p_cdc = make_new_itf(daddr, itf_desc); - TU_VERIFY (p_cdc); + cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_CH34X; - tusb_desc_endpoint_t const* desc_ep = (tusb_desc_endpoint_t const*) tu_desc_next(itf_desc); + tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); // data endpoints expected to be in pairs TU_ASSERT(open_ep_stream_pair(p_cdc, desc_ep)); @@ -2023,11 +2033,11 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const* itf_desc, uin } static void ch34x_process_config(tuh_xfer_t* xfer) { - // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uintptr_t const state = xfer->user_data; + // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t* p_cdc = get_itf(idx); + cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); uint8_t buffer[2]; // TODO remove @@ -2035,7 +2045,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_READ_VERSION: p_cdc->user_control_cb = ch34x_process_config; // set once for whole process config TU_ASSERT_COMPLETE(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, - ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); + ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); break; case CONFIG_CH34X_SERIAL_INIT: { @@ -2060,19 +2070,20 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, - ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); + ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, - ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); + ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); break; case CONFIG_CH34X_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); + TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, + CONFIG_CH34X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -2431,6 +2442,7 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, u } static void pl2303_process_config(tuh_xfer_t * xfer) { + uintptr_t const state = xfer->user_data; // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -2440,7 +2452,7 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { uint8_t buf; int8_t type; - switch (xfer->user_data) { + switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_GET_DESC: -- cgit v1.3.1 From da93fcfc6dbe51ceb73e990aefea9c8d55d3fc94 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 22 Feb 2024 15:09:25 +0100 Subject: improved TU_LOGs --- src/class/cdc/cdc_host.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 50aa4b6f0..f3fbe88ea 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -50,6 +50,7 @@ DADDR, ITF_NUM, NAME, ##__VA_ARGS__) #define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) +#define TU_LOG_RESULT(TXT,RESULT) TU_LOG_P_CDC(TXT " " #RESULT " = %s", RESULT ? "true" : "FALSE" ) #define TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) \ do { \ @@ -587,6 +588,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c if (ret && !complete_cb) { p_cdc->line_state = (uint8_t) line_state; } + TU_LOG_RESULT("set control line state", ret); return ret; } @@ -604,6 +606,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete if (ret && !complete_cb) { p_cdc->line_coding.bit_rate = baudrate; } + TU_LOG_RESULT("set baudrate", ret); return ret; } @@ -627,6 +630,7 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin p_cdc->line_coding.parity = parity; p_cdc->line_coding.data_bits = data_bits; } + TU_LOG_RESULT("set data format", ret); return ret; } @@ -646,6 +650,7 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const * line_coding, if (ret && !complete_cb) { p_cdc->line_coding = *line_coding; } + TU_LOG_RESULT("set line coding", ret); return ret; } @@ -785,6 +790,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ if (driver_detected) { TU_LOG_CDC("open", daddr, itf_desc->bInterfaceNumber, driver_detected->name); bool ret = driver_detected->open(daddr, itf_desc, max_len); + TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); return ret; } @@ -794,7 +800,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); - TU_LOG_P_CDC("set config complete success = %u", success); + TU_LOG_RESULT("set config complete", success); if (success) { p_cdc->mounted = true; @@ -846,7 +852,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); + TU_LOG_RESULT(" control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -1131,7 +1137,7 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); + TU_LOG_RESULT(" control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -1407,7 +1413,7 @@ static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx) break; } - TU_LOG_P_CDC("%s detected", ftdi_chip_name[p_cdc->ftdi.chip_type]); + TU_LOG_P_CDC(" %s detected", ftdi_chip_name[p_cdc->ftdi.chip_type]); return (p_cdc->ftdi.chip_type != UNKNOWN); } @@ -1554,7 +1560,7 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc) break; } - TU_LOG_P_CDC("Baudrate divisor 0x%lu", div_value); + TU_LOG_P_CDC(" Baudrate divisor 0x%lu", div_value); return div_value; } @@ -1663,7 +1669,7 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); + TU_LOG_RESULT(" control complete", success); if (success) { switch(xfer->setup->bRequest) { @@ -1920,7 +1926,7 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); + TU_LOG_RESULT(" control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -2051,7 +2057,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t const version = xfer->buffer[0]; - TU_LOG_P_CDC("Chip Version = %02x", version); + TU_LOG_P_CDC(" Chip Version = %02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming // see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT_COMPLETE(version >= 0x30); @@ -2337,7 +2343,7 @@ static void pl2303_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC("control complete success = %u", success); + TU_LOG_RESULT(" control complete", success); if (success) { if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && @@ -2743,7 +2749,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, ui default: break; } - TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev[idx]->bcdUSB); + TU_LOG_P_CDC(" unknown device type bcdUSB = 0x%04x", desc_dev[idx]->bcdUSB); return PL2303_DETECT_TYPE_FAILED; } @@ -2893,7 +2899,7 @@ static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303 } else { baud = pl2303_encode_baud_rate_divisor(buf, baud); } - TU_LOG_P_CDC("real baudrate = %lu", baud); + TU_LOG_P_CDC(" real baudrate = %lu", baud); return true; } -- cgit v1.3.1 From 46a861b0e31a7382d620986079abd0c373dfe6da Mon Sep 17 00:00:00 2001 From: IngHK Date: Fri, 23 Feb 2024 08:30:50 +0100 Subject: improved PL2303 TU_LOGs --- src/class/cdc/cdc_host.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f3fbe88ea..9d27b1e79 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2486,13 +2486,14 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0 // can be activated if necessary - TU_LOG(CFG_TUH_CDC_LOG_LEVEL, "PL2303 bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", - desc_dev[idx]->bDeviceClass, desc_dev[idx]->bMaxPacketSize0, desc_dev[idx]->bcdUSB, desc_dev[idx]->bcdDevice ); + TU_LOG_P_CDC(" bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", + desc_dev[idx]->bDeviceClass, desc_dev[idx]->bMaxPacketSize0, + desc_dev[idx]->bcdUSB, desc_dev[idx]->bcdDevice ); uint16_t vid, pid; TU_ASSERT_COMPLETE(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); - TU_LOG(CFG_TUH_CDC_LOG_LEVEL, " vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", - vid, pid, p_cdc->pl2303.supports_hx_status, - p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); + TU_LOG_P_CDC(" vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", + vid, pid, p_cdc->pl2303.supports_hx_status, + p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); #endif // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { -- cgit v1.3.1 From f97e31226a959944785122d4c0c10d4b3304704c Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 28 Feb 2024 13:07:40 +0100 Subject: FTDI fixed itf_num and some improvement --- src/class/cdc/cdc_host.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 9d27b1e79..33d201c07 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1140,22 +1140,19 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { TU_LOG_RESULT(" control complete", success); if (success) { - switch (xfer->setup->bRequest) { - case FTDI_SIO_SET_MODEM_CTRL_REQUEST: - p_cdc->line_state = p_cdc->requested_line_state; - break; - - case FTDI_SIO_SET_DATA_REQUEST: - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; - break; - - case FTDI_SIO_SET_BAUDRATE_REQUEST: - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; - break; - - default: break; + if (xfer->setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && + xfer->setup->bmRequestType == FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE ) { + p_cdc->line_state = p_cdc->requested_line_state; + } + if (xfer->setup->bRequest == FTDI_SIO_SET_DATA_REQUEST && + xfer->setup->bmRequestType == FTDI_SIO_SET_DATA_REQUEST_TYPE ) { + p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; + p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; + p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + } + if (xfer->setup->bRequest == FTDI_SIO_SET_BAUDRATE_REQUEST && + xfer->setup->bmRequestType == FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE ) { + p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; } } @@ -1180,7 +1177,10 @@ static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_c } static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = ftdi_get_idx(xfer); + cdch_interface_t * p_cdc = get_itf(idx); + TU_ASSERT(p_cdc,); + uint8_t const itf_num = p_cdc->bInterfaceNumber; set_line_coding_stage1_complete(xfer, itf_num, ftdi_set_data_request, // control request function to set data format ftdi_internal_control_complete); // control complete function to be called after request @@ -1413,7 +1413,8 @@ static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx) break; } - TU_LOG_P_CDC(" %s detected", ftdi_chip_name[p_cdc->ftdi.chip_type]); + TU_LOG_P_CDC(" %s detected (bcdDevice = 0x%04x)", + ftdi_chip_name[p_cdc->ftdi.chip_type], desc_dev[idx]->bcdDevice); return (p_cdc->ftdi.chip_type != UNKNOWN); } -- cgit v1.3.1 From d3d61da0384d066b9930e8e5b658717983f02efb Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 25 Feb 2024 17:20:02 +0100 Subject: improved & fixed compiler warnings device descriptor handling --- src/class/cdc/cdc_host.c | 44 +++++++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 33d201c07..c222e11db 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -111,8 +111,10 @@ typedef struct { CFG_TUH_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; + #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_PL2303 - static tusb_desc_device_t desc_dev[CFG_TUH_CDC][CFG_TUH_ENUMERATION_BUFSIZE]; + CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN + static tusb_desc_device_t desc_dev[CFG_TUH_ENUMERATION_BUFSIZE]; #endif //--------------------------------------------------------------------+ @@ -1054,7 +1056,7 @@ static void acm_process_config(tuh_xfer_t * xfer) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_FTDI -static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx); +static bool ftdi_determine_type(cdch_interface_t * p_cdc); static uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc); static uint8_t ftdi_get_idx(tuh_xfer_t * xfer); @@ -1255,7 +1257,7 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { // get device descriptor p_cdc->user_control_cb = ftdi_process_config; // set once for whole process config if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 - TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, desc_dev[idx], sizeof(tusb_desc_device_t), + TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), ftdi_process_config, CONFIG_FTDI_DETERMINE_TYPE)); break; } @@ -1264,7 +1266,7 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { case CONFIG_FTDI_DETERMINE_TYPE: // determine type if (itf_num == 0) { - TU_ASSERT_COMPLETE(ftdi_determine_type(p_cdc, idx)); + TU_ASSERT_COMPLETE(ftdi_determine_type(p_cdc)); } else { // other interfaces have same type as interface 0 uint8_t const idx_itf0 = tuh_cdc_itf_get_index(xfer->daddr, 0); @@ -1334,9 +1336,9 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { //------------- Helper -------------// -static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx) +static bool ftdi_determine_type(cdch_interface_t * p_cdc) { - uint16_t const version = desc_dev[idx]->bcdDevice; + uint16_t const version = desc_dev->bcdDevice; uint8_t const itf_num = p_cdc->bInterfaceNumber; p_cdc->ftdi.chip_type = UNKNOWN; @@ -1414,7 +1416,7 @@ static bool ftdi_determine_type(cdch_interface_t * p_cdc, uint8_t const idx) } TU_LOG_P_CDC(" %s detected (bcdDevice = 0x%04x)", - ftdi_chip_name[p_cdc->ftdi.chip_type], desc_dev[idx]->bcdDevice); + ftdi_chip_name[p_cdc->ftdi.chip_type], desc_dev->bcdDevice); return (p_cdc->ftdi.chip_type != UNKNOWN); } @@ -2207,7 +2209,7 @@ static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_PL2303 -static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, uint8_t step, +static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); @@ -2465,13 +2467,13 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { case CONFIG_PL2303_GET_DESC: p_cdc->user_control_cb = pl2303_process_config; // set once for whole process config // get device descriptor - TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, desc_dev[idx], sizeof(tusb_desc_device_t), + TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), pl2303_process_config, CONFIG_PL2303_DETECT_TYPE)); break; case CONFIG_PL2303_DETECT_TYPE: // get type and quirks (step 1) - type = pl2303_detect_type (p_cdc, idx, 1, pl2303_process_config, CONFIG_PL2303_READ1); // step 1 + type = pl2303_detect_type (p_cdc, 1, pl2303_process_config, CONFIG_PL2303_READ1); // step 1 TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); if (type == PL2303_SUPPORTS_HX_STATUS_TRIGGERED) { break; @@ -2482,14 +2484,14 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { // get supports_hx_status, type and quirks (step 2), do special read p_cdc->pl2303.supports_hx_status = ( // will not be true, if coming directly from previous case xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS ); - type = pl2303_detect_type (p_cdc, idx, 2, NULL, 0); // step 2 now with supports_hx_status + type = pl2303_detect_type (p_cdc, 2, NULL, 0); // step 2 now with supports_hx_status TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0 // can be activated if necessary TU_LOG_P_CDC(" bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", - desc_dev[idx]->bDeviceClass, desc_dev[idx]->bMaxPacketSize0, - desc_dev[idx]->bcdUSB, desc_dev[idx]->bcdDevice ); + desc_dev->bDeviceClass, desc_dev->bMaxPacketSize0, + desc_dev->bcdUSB, desc_dev->bcdDevice ); uint16_t vid, pid; TU_ASSERT_COMPLETE(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); TU_LOG_P_CDC(" vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", @@ -2674,29 +2676,29 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { //------------- Helper -------------// -static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, uint8_t step, +static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) { /* * Legacy PL2303H, variants 0 and 1 (difference unknown). */ - if (desc_dev[idx]->bDeviceClass == 0x02) { + if (desc_dev->bDeviceClass == 0x02) { return TYPE_H; /* variant 0 */ } - if (desc_dev[idx]->bMaxPacketSize0 != 0x40) { - if (desc_dev[idx]->bDeviceClass == 0x00 || desc_dev[idx]->bDeviceClass == 0xff) { + if (desc_dev->bMaxPacketSize0 != 0x40) { + if (desc_dev->bDeviceClass == 0x00 || desc_dev->bDeviceClass == 0xff) { return TYPE_H; /* variant 1 */ } return TYPE_H; /* variant 0 */ } - switch (desc_dev[idx]->bcdUSB) { + switch (desc_dev->bcdUSB) { case 0x101: /* USB 1.0.1? Let's assume they meant 1.1... */ TU_ATTR_FALLTHROUGH; case 0x110: - switch (desc_dev[idx]->bcdDevice) { + switch (desc_dev->bcdDevice) { case 0x300: return TYPE_HX; case 0x400: @@ -2706,7 +2708,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, ui } break; case 0x200: - switch (desc_dev[idx]->bcdDevice) { + switch (desc_dev->bcdDevice) { case 0x100: /* GC */ case 0x105: return TYPE_HXN; @@ -2751,7 +2753,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t const idx, ui default: break; } - TU_LOG_P_CDC(" unknown device type bcdUSB = 0x%04x", desc_dev[idx]->bcdUSB); + TU_LOG_P_CDC(" unknown device type bcdUSB = 0x%04x", desc_dev->bcdUSB); return PL2303_DETECT_TYPE_FAILED; } -- cgit v1.3.1 From edf13203916931962a53af50abc548dd3eded278 Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 28 Feb 2024 13:13:18 +0100 Subject: removed expendable ACM check --- src/class/cdc/cdc_host.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index c222e11db..4d2134f9d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -909,7 +909,6 @@ static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t c static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); - TU_VERIFY(p_cdc->requested_line_coding.data_bits && p_cdc->requested_line_coding.bit_rate); TU_VERIFY((p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8) || p_cdc->requested_line_coding.data_bits == 16); -- cgit v1.3.1 From 3cf9cb98e630a0cb26bc28a2e4c67fb6df19a884 Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 28 Feb 2024 13:15:37 +0100 Subject: small PL2303 improvements --- src/class/cdc/cdc_host.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4d2134f9d..130993547 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2292,9 +2292,10 @@ static bool pl2303_set_line_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t comp * even to the same values as before. Thus we actually need to filter * in this specific case. */ - // TODO really necessary to check? what to do in this case when no transfer will happen? - // callback is not called... - TU_VERIFY(memcmp(&p_cdc->requested_line_coding, &p_cdc->line_coding, sizeof(cdc_line_coding_t) ) != 0); + TU_VERIFY(p_cdc->requested_line_coding.data_bits != p_cdc->line_coding.data_bits || + p_cdc->requested_line_coding.stop_bits != p_cdc->line_coding.stop_bits || + p_cdc->requested_line_coding.parity != p_cdc->line_coding.parity || + p_cdc->requested_line_coding.bit_rate != p_cdc->line_coding.bit_rate ); /* For reference buf[6] data bits value */ TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); -- cgit v1.3.1 From e7308e313a1fb5482dbbb34cdfc6b7b11a54fd6b Mon Sep 17 00:00:00 2001 From: IngHK Date: Wed, 28 Feb 2024 13:28:38 +0100 Subject: improved TU_LOGs --- src/class/cdc/cdc.h | 12 +++++++++ src/class/cdc/cdc_host.c | 65 +++++++++++++++++++++++++++++------------------- 2 files changed, 51 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 5cbd658fe..b1dca1ad8 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -192,6 +192,11 @@ typedef enum { CDC_LINE_CODING_STOP_BITS_2 = 2, // 2 bits } cdc_line_coding_stopbits_t; +#define CDC_LINE_CODING_STOP_BITS_TEXT(STOP_BITS) ( \ + STOP_BITS == CDC_LINE_CODING_STOP_BITS_1 ? "1" : \ + STOP_BITS == CDC_LINE_CODING_STOP_BITS_1_5 ? "1.5" : \ + STOP_BITS == CDC_LINE_CODING_STOP_BITS_2 ? "2" : "?" ) + // TODO Backward compatible for typos. Maybe removed in the future release #define CDC_LINE_CONDING_STOP_BITS_1 CDC_LINE_CODING_STOP_BITS_1 #define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5 @@ -205,6 +210,13 @@ typedef enum { CDC_LINE_CODING_PARITY_SPACE = 4, } cdc_line_coding_parity_t; +#define CDC_LINE_CODING_PARITY_CHAR(PARITY) ( \ + PARITY == CDC_LINE_CODING_PARITY_NONE ? 'N' : \ + PARITY == CDC_LINE_CODING_PARITY_ODD ? 'O' : \ + PARITY == CDC_LINE_CODING_PARITY_EVEN ? 'E' : \ + PARITY == CDC_LINE_CODING_PARITY_MARK ? 'M' : \ + PARITY == CDC_LINE_CODING_PARITY_SPACE ? 'S' : '?' ) + //--------------------------------------------------------------------+ // Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 130993547..d2bc63d64 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -50,7 +50,7 @@ DADDR, ITF_NUM, NAME, ##__VA_ARGS__) #define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) -#define TU_LOG_RESULT(TXT,RESULT) TU_LOG_P_CDC(TXT " " #RESULT " = %s", RESULT ? "true" : "FALSE" ) +#define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %s", VAL ? "true" : "false" ) #define TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) \ do { \ @@ -395,14 +395,20 @@ bool tuh_cdc_get_dtr(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR) ? true : false; + bool ret = (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR); +// TU_LOG_P_CDC_BOOL("get DTR", ret); + + return ret; } bool tuh_cdc_get_rts(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS) ? true : false; + bool ret = (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS); +// TU_LOG_P_CDC_BOOL("get RTS", ret); + + return ret; } bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t * line_coding) { @@ -410,6 +416,10 @@ bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t * line_coding) TU_VERIFY(p_cdc); *line_coding = p_cdc->line_coding; + TU_LOG_P_CDC("get line coding %lu %u%c%s", + p_cdc->line_coding.bit_rate, p_cdc->line_coding.data_bits, + CDC_LINE_CODING_PARITY_CHAR(p_cdc->line_coding.parity), + CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); return true; } @@ -590,7 +600,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c if (ret && !complete_cb) { p_cdc->line_state = (uint8_t) line_state; } - TU_LOG_RESULT("set control line state", ret); +// TU_LOG_P_CDC_BOOL("set control line state", ret); return ret; } @@ -598,7 +608,7 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set baudrate = %lu", baudrate); + TU_LOG_P_CDC("set baudrate %lu", baudrate); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.bit_rate = baudrate; @@ -608,7 +618,7 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete if (ret && !complete_cb) { p_cdc->line_coding.bit_rate = baudrate; } - TU_LOG_RESULT("set baudrate", ret); +// TU_LOG_P_CDC_BOOL("set baudrate", ret); return ret; } @@ -617,8 +627,9 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set data format data_bits = %u parity = %u stop_bits = %u (indexes!)", - data_bits, parity, stop_bits); + TU_LOG_P_CDC("set data format %u%c%s", + data_bits, CDC_LINE_CODING_PARITY_CHAR(parity), + CDC_LINE_CODING_STOP_BITS_TEXT(stop_bits)); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.stop_bits = stop_bits; @@ -632,7 +643,7 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin p_cdc->line_coding.parity = parity; p_cdc->line_coding.data_bits = data_bits; } - TU_LOG_RESULT("set data format", ret); +// TU_LOG_P_CDC_BOOL("set data format", ret); return ret; } @@ -641,8 +652,10 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const * line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set line coding baudrate = %lu data_bits = %u parity = %u stop_bits = %u (indexes!)", - line_coding->bit_rate, line_coding->data_bits, line_coding->parity, line_coding->stop_bits); + TU_LOG_P_CDC("set line coding %lu %u%c%s", + line_coding->bit_rate, line_coding->data_bits, + CDC_LINE_CODING_PARITY_CHAR(line_coding->parity), + CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding = *line_coding; @@ -652,7 +665,7 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const * line_coding, if (ret && !complete_cb) { p_cdc->line_coding = *line_coding; } - TU_LOG_RESULT("set line coding", ret); +// TU_LOG_P_CDC_BOOL("set line coding", ret); return ret; } @@ -792,7 +805,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ if (driver_detected) { TU_LOG_CDC("open", daddr, itf_desc->bInterfaceNumber, driver_detected->name); bool ret = driver_detected->open(daddr, itf_desc, max_len); - TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); +// TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); return ret; } @@ -802,7 +815,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); - TU_LOG_RESULT("set config complete", success); + TU_LOG_P_CDC_BOOL("set config complete", success); if (success) { p_cdc->mounted = true; @@ -854,7 +867,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_RESULT(" control complete", success); + TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -1138,7 +1151,7 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_RESULT(" control complete", success); + TU_LOG_P_CDC_BOOL("control complete", success); if (success) { if (xfer->setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && @@ -1414,7 +1427,7 @@ static bool ftdi_determine_type(cdch_interface_t * p_cdc) break; } - TU_LOG_P_CDC(" %s detected (bcdDevice = 0x%04x)", + TU_LOG_P_CDC("%s detected (bcdDevice = 0x%04x)", ftdi_chip_name[p_cdc->ftdi.chip_type], desc_dev->bcdDevice); return (p_cdc->ftdi.chip_type != UNKNOWN); @@ -1562,7 +1575,7 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc) break; } - TU_LOG_P_CDC(" Baudrate divisor 0x%lu", div_value); + TU_LOG_P_CDC("Baudrate divisor = 0x%lu", div_value); return div_value; } @@ -1671,7 +1684,7 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_RESULT(" control complete", success); + TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch(xfer->setup->bRequest) { @@ -1928,7 +1941,7 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_RESULT(" control complete", success); + TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -2059,7 +2072,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t const version = xfer->buffer[0]; - TU_LOG_P_CDC(" Chip Version = %02x", version); + TU_LOG_P_CDC("Chip Version = 0x%02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming // see drivers from WCH vendor, Linux kernel and FreeBSD TU_ASSERT_COMPLETE(version >= 0x30); @@ -2346,7 +2359,7 @@ static void pl2303_internal_control_complete(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); TU_ASSERT(p_cdc,); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_RESULT(" control complete", success); + TU_LOG_P_CDC_BOOL("control complete", success); if (success) { if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && @@ -2489,12 +2502,12 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0 // can be activated if necessary - TU_LOG_P_CDC(" bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", + TU_LOG_P_CDC("bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", desc_dev->bDeviceClass, desc_dev->bMaxPacketSize0, desc_dev->bcdUSB, desc_dev->bcdDevice ); uint16_t vid, pid; TU_ASSERT_COMPLETE(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); - TU_LOG_P_CDC(" vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", + TU_LOG_P_CDC("vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", vid, pid, p_cdc->pl2303.supports_hx_status, p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); #endif @@ -2753,7 +2766,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, default: break; } - TU_LOG_P_CDC(" unknown device type bcdUSB = 0x%04x", desc_dev->bcdUSB); + TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev->bcdUSB); return PL2303_DETECT_TYPE_FAILED; } @@ -2903,7 +2916,7 @@ static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303 } else { baud = pl2303_encode_baud_rate_divisor(buf, baud); } - TU_LOG_P_CDC(" real baudrate = %lu", baud); + TU_LOG_P_CDC("real baudrate %lu", baud); return true; } -- cgit v1.3.1 From e6d27b6d3e8fc928cc00ab08898243c7e037ba35 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 29 Feb 2024 20:19:35 +0100 Subject: fixed IAR compile error --- src/class/cdc/cdc_host.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index d2bc63d64..dfe078de4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -113,7 +113,6 @@ CFG_TUH_MEM_SECTION static cdch_interface_t cdch_data[CFG_TUH_CDC]; #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_PL2303 - CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static tusb_desc_device_t desc_dev[CFG_TUH_ENUMERATION_BUFSIZE]; #endif -- cgit v1.3.1 From dea27d28bceeaaa23d3daa6468373cb536390108 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 29 Feb 2024 20:24:13 +0100 Subject: added explicite (uint16_t) casts inside tu_htole16() --- src/class/cdc/cdc_host.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index dfe078de4..d71cda124 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -932,8 +932,8 @@ static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete }, .bRequest = CDC_REQUEST_SET_LINE_CODING, .wValue = 0, - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), - .wLength = tu_htole16(sizeof(cdc_line_coding_t)) + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), + .wLength = tu_htole16((uint16_t) sizeof(cdc_line_coding_t)) }; // use usbh enum buf to hold line coding since user line_coding variable does not live long enough @@ -1612,7 +1612,7 @@ static bool cp210x_set_request(cdch_interface_t * p_cdc, uint8_t command, uint16 }, .bRequest = command, .wValue = tu_htole16(value), - .wIndex = tu_htole16(p_cdc->bInterfaceNumber), + .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = tu_htole16(length) }; @@ -1852,9 +1852,9 @@ static bool ch34x_set_request(cdch_interface_t * p_cdc, uint8_t direction, uint8 .direction = direction & 0x01u }, .bRequest = request, - .wValue = tu_htole16 (value), - .wIndex = tu_htole16 (index), - .wLength = tu_htole16 (length) + .wValue = tu_htole16(value), + .wIndex = tu_htole16(index), + .wLength = tu_htole16(length) }; // use usbh enum buf since application variable does not live long enough @@ -2232,9 +2232,9 @@ static bool pl2303_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_ tusb_control_request_t const request_setup = { .bmRequestType = requesttype, .bRequest = request, - .wValue = tu_htole16 (value), - .wIndex = tu_htole16 (index), - .wLength = tu_htole16 (length) + .wValue = tu_htole16(value), + .wIndex = tu_htole16(index), + .wLength = tu_htole16(length) }; // use usbh enum buf since application variable does not live long enough -- cgit v1.3.1 From e0551043ca8a6b3be92fed57f5e34d6d8014406b Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 3 Mar 2024 13:02:58 +0100 Subject: added use of cdc_line_control_state_t type in CDCh --- src/class/cdc/cdc.h | 14 ++++++++------ src/class/cdc/cdc_device.c | 2 ++ src/class/cdc/cdc_host.c | 45 +++++++++++++++++++-------------------------- 3 files changed, 29 insertions(+), 32 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index b1dca1ad8..10aed79ab 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -414,15 +414,17 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); -typedef struct TU_ATTR_PACKED +typedef union TU_ATTR_PACKED { - uint16_t dtr : 1; - uint16_t rts : 1; - uint16_t : 6; - uint16_t : 8; + struct { + uint8_t dtr : 1; + uint8_t rts : 1; + uint8_t : 6; + }; + uint8_t all; } cdc_line_control_state_t; -TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct"); +TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 1, "size is not correct"); TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index c26264e60..9f51a6d4b 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -56,6 +56,7 @@ typedef struct uint8_t ep_out; // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) + // TODO use cdc_line_control_state_t instead of uint8_t uint8_t line_state; /*------------- From this point, data is not cleared by bus reset -------------*/ @@ -124,6 +125,7 @@ bool tud_cdc_n_connected(uint8_t itf) } uint8_t tud_cdc_n_get_line_state (uint8_t itf) +// TODO use cdc_line_control_state_t instead of uint8_t { return _cdcd_itf[itf].line_state; } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index d71cda124..a3407a5f9 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -81,8 +81,8 @@ typedef struct { TU_ATTR_ALIGNED(4) cdc_line_coding_t requested_line_coding; // 1 byte padding - uint8_t line_state; // DTR (bit0), RTS (bit1) - uint8_t requested_line_state; + cdc_line_control_state_t line_state; + cdc_line_control_state_t requested_line_state; tuh_xfer_cb_t user_control_cb; #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X @@ -339,7 +339,7 @@ static cdch_interface_t * make_new_itf(uint8_t daddr, tusb_desc_interface_t cons p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; p_cdc->line_coding = (cdc_line_coding_t) { 0, 0, 0, 0 }; - p_cdc->line_state = 0; + p_cdc->line_state.all = 0; return p_cdc; } } @@ -394,7 +394,7 @@ bool tuh_cdc_get_dtr(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - bool ret = (p_cdc->line_state & CDC_CONTROL_LINE_STATE_DTR); + bool ret = p_cdc->line_state.dtr; // TU_LOG_P_CDC_BOOL("get DTR", ret); return ret; @@ -404,7 +404,7 @@ bool tuh_cdc_get_rts(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - bool ret = (p_cdc->line_state & CDC_CONTROL_LINE_STATE_RTS); + bool ret = p_cdc->line_state.rts; // TU_LOG_P_CDC_BOOL("get RTS", ret); return ret; @@ -592,12 +592,12 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_LOG_P_CDC("set control line state line_state = %u", line_state); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_state = (uint8_t) line_state; + p_cdc->requested_line_state.all = (uint8_t) line_state; bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_state = (uint8_t) line_state; + p_cdc->line_state.all = (uint8_t) line_state; } // TU_LOG_P_CDC_BOOL("set control line state", ret); @@ -898,7 +898,7 @@ static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t c .direction = TUSB_DIR_OUT }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16(p_cdc->requested_line_state), + .wValue = tu_htole16((uint16_t) p_cdc->requested_line_state.all), .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = 0 }; @@ -1034,7 +1034,7 @@ static void acm_process_config(tuh_xfer_t * xfer) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING), 1); break; } @@ -1139,7 +1139,7 @@ static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // FTDI has the same bit coding return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, - p_cdc->requested_line_state, p_cdc->ftdi.channel, complete_cb, user_data); + p_cdc->requested_line_state.all, p_cdc->ftdi.channel, complete_cb, user_data); } //------------- Driver API -------------// @@ -1328,7 +1328,7 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { case CONFIG_FTDI_MODEM_CTRL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); break; #else @@ -1670,7 +1670,7 @@ static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, (uint16_t) ((uint32_t) CP210X_CONTROL_WRITE_DTR | - (uint32_t) CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line_state), + (uint32_t) CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line_state.all), NULL, 0, complete_cb, user_data); } @@ -1811,7 +1811,7 @@ static void cp210x_process_config(tuh_xfer_t * xfer) { case CONFIG_CP210X_SET_DTR_RTS: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; @@ -1916,16 +1916,8 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t com } static bool ch34x_modem_ctrl_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t control = 0; - if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_RTS) { - control |= CH34X_BIT_RTS; - } - if (p_cdc->requested_line_state & CDC_CONTROL_LINE_STATE_DTR) { - control |= CH34X_BIT_DTR; - } - - // CH34x signals are inverted - control = ~control; + uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) | // CH34x signals are inverted + (p_cdc->requested_line_state.dtr ? CH34X_BIT_DTR : 0)); return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } @@ -2101,7 +2093,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { case CONFIG_CH34X_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; @@ -2287,8 +2279,9 @@ static inline bool pl2303_supports_hx_status(cdch_interface_t * p_cdc, tuh_xfer_ static inline bool pl2303_set_control_lines(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // PL2303 has the same bit coding return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, - p_cdc->requested_line_state, 0, NULL, 0, complete_cb, user_data); + p_cdc->requested_line_state.all, 0, NULL, 0, complete_cb, user_data); } //static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) @@ -2645,7 +2638,7 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { case CONFIG_PL2303_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_FLOW_CTRL_READ)); break; #else -- cgit v1.3.1 From a9cc07fc83599fab4d9576e6f5b793bc1bf2bf35 Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 10 Mar 2024 08:20:12 +0100 Subject: added line control function using cdc_line_control_state_t --- src/class/cdc/cdc_host.c | 35 ++++++++++++++++++++++++++++++----- src/class/cdc/cdc_host.h | 10 ++++++++-- 2 files changed, 38 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index a3407a5f9..86b874b1e 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -50,8 +50,9 @@ DADDR, ITF_NUM, NAME, ##__VA_ARGS__) #define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) -#define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %s", VAL ? "true" : "false" ) +#define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %d", VAL) +// assert and set config complete #define TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) \ do { \ if (!(_cond)) { _MESS_FAILED(); TU_BREAKPOINT(); set_config_complete(idx, _itf_offset, false); } \ @@ -586,24 +587,48 @@ static bool set_function_call ( } } -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // uses cdc_line_control_state_t union for line_state cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set control line state line_state = %u", line_state); + TU_LOG_P_CDC("set control line state dtr = %u rts = %u", line_state.dtr, line_state.rts ); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_state.all = (uint8_t) line_state; + p_cdc->requested_line_state = line_state; bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_state.all = (uint8_t) line_state; + p_cdc->line_state = line_state; } // TU_LOG_P_CDC_BOOL("set control line state", ret); return ret; } +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + // uses uint16_t for line_state => DTR (bit 0), RTS (bit 1) + + return tuh_cdc_set_control_line_state_u(idx, (cdc_line_control_state_t) { .all = (uint8_t) line_state }, + complete_cb, user_data); +} + +bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t * p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + cdc_line_control_state_t const line_state = { .dtr = dtr_state, .rts = p_cdc->line_state.rts }; + + return tuh_cdc_set_control_line_state_u(idx, line_state, complete_cb, user_data); +} + +bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdch_interface_t * p_cdc = get_itf(idx); + TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + cdc_line_control_state_t const line_state = { .rts = rts_state, .dtr = p_cdc->line_state.dtr }; + + return tuh_cdc_set_control_line_state_u(idx, line_state, complete_cb, user_data); +} + bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index ca6567453..77081d3b0 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -132,8 +132,14 @@ bool tuh_cdc_read_clear (uint8_t idx); // - The function will return true if transfer is successful, false otherwise. //--------------------------------------------------------------------+ -// Request to Set Control Line State: DTR (bit 0), RTS (bit 1) -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +// Request to Set Control Line State +bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line_state, // uses cdc_line_control_state_t union for line_state + tuh_xfer_cb_t complete_cb, uintptr_t user_data); +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, // uses uint16_t for line_state (legacy function) + tuh_xfer_cb_t complete_cb, uintptr_t user_data); // DTR (bit 0), RTS (bit 1) + +bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Set DTR +bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Set RTS // Request to set baudrate bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -- cgit v1.3.1 From ee92e582b38e36df53381f8c98a0be54c2caef3e Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 3 Mar 2024 13:12:10 +0100 Subject: added defines CFG_TUH_CDC_DTR_CONTROL_ON_ENUM & CFG_TUH_CDC_RTS_CONTROL_ON_ENUM --- examples/host/cdc_msc_hid/src/tusb_config.h | 4 +-- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 4 +-- src/class/cdc/cdc_host.c | 40 ++++++++++++++++------ 3 files changed, 34 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index fc956c6d3..32a29bd4f 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -121,8 +121,8 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -// DTR ( bit 0), RTS (bit 1) -#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 +#define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM true +#define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM true // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index dd732c700..88b341e95 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -126,8 +126,8 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -// DTR ( bit 0), RTS (bit 1) -#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM 0x03 +#define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM true +#define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM true // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 86b874b1e..5b74d031d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -63,6 +63,26 @@ #define TU_ASSERT_COMPLETE(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_COMPLETE_2ARGS, TU_ASSERT_COMPLETE_1ARGS, _dummy)(__VA_ARGS__) +// handle line control defines +#if defined(CFG_TUH_CDC_LINE_CONTROL_ON_ENUM) && \ + (defined(CFG_TUH_CDC_DTR_CONTROL_ON_ENUM) || defined(CFG_TUH_CDC_RTS_CONTROL_ON_ENUM)) + TU_VERIFY_STATIC(false, "Contradictory line control defines"); +#endif + +#ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + #define LINE_CONTROL_ON_ENUM CFG_TUH_CDC_LINE_CONTROL_ON_ENUM +#elif defined(CFG_TUH_CDC_DTR_CONTROL_ON_ENUM) || defined(CFG_TUH_CDC_RTS_CONTROL_ON_ENUM) + #ifndef CFG_TUH_CDC_DTR_CONTROL_ON_ENUM + #define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM 0 + #endif + #ifndef CFG_TUH_CDC_RTS_CONTROL_ON_ENUM + #define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM 0 + #endif + #define LINE_CONTROL_ON_ENUM ( ( CFG_TUH_CDC_DTR_CONTROL_ON_ENUM ? CDC_CONTROL_LINE_STATE_DTR : 0 ) | \ + ( CFG_TUH_CDC_RTS_CONTROL_ON_ENUM ? CDC_CONTROL_LINE_STATE_RTS : 0 ) ) +#endif + + //--------------------------------------------------------------------+ // Host CDC Interface //--------------------------------------------------------------------+ @@ -1057,9 +1077,9 @@ static void acm_process_config(tuh_xfer_t * xfer) { switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + #ifdef LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING), 1); break; } @@ -1352,8 +1372,8 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { break; case CONFIG_FTDI_MODEM_CTRL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + #ifdef LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); break; #else @@ -1835,8 +1855,8 @@ static void cp210x_process_config(tuh_xfer_t * xfer) { #endif case CONFIG_CP210X_SET_DTR_RTS: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + #ifdef LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; @@ -2117,8 +2137,8 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { break; case CONFIG_CH34X_MODEM_CONTROL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + #ifdef LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; @@ -2662,8 +2682,8 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { #endif case CONFIG_PL2303_MODEM_CONTROL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + #ifdef LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_FLOW_CTRL_READ)); break; #else -- cgit v1.3.1 From 2786a61e8b9811b1065cf1f36502eb4744e9d772 Mon Sep 17 00:00:00 2001 From: IngHK Date: Sun, 3 Mar 2024 13:25:04 +0100 Subject: fixed FTDI set control line --- src/class/cdc/cdc_host.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 5b74d031d..6121e59f0 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -82,7 +82,6 @@ ( CFG_TUH_CDC_RTS_CONTROL_ON_ENUM ? CDC_CONTROL_LINE_STATE_RTS : 0 ) ) #endif - //--------------------------------------------------------------------+ // Host CDC Interface //--------------------------------------------------------------------+ @@ -1172,19 +1171,21 @@ static bool ftdi_change_speed(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_c static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); uint16_t value = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xf) | // data bit quantity is stored in bits 0-3 - ((uint32_t) p_cdc->requested_line_coding.parity & 0x7) << 8 | // parity is stored in bits 8-10, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0x3) << 11 ); // stop bits quantity is stored in bits 11-12, same coding - // not each FTDI supports 1.5 stop bits + ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) | // data bit quantity is stored in bits 0-3 + ((uint32_t) p_cdc->requested_line_coding.parity & 0x7u) << 8 | // parity is stored in bits 8-10, same coding + ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0x3u) << 11 ); // stop bits quantity is stored in bits 11-12, same coding + // not each FTDI supports 1.5 stop bits return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, value, p_cdc->ftdi.channel, complete_cb, user_data); } static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // FTDI has the same bit coding + uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? (uint32_t) FTDI_SIO_SET_DTR_HIGH : (uint32_t) FTDI_SIO_SET_DTR_LOW) | + (p_cdc->requested_line_state.rts ? (uint32_t) FTDI_SIO_SET_RTS_HIGH : (uint32_t) FTDI_SIO_SET_RTS_LOW)); + return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, - p_cdc->requested_line_state.all, p_cdc->ftdi.channel, complete_cb, user_data); + value, p_cdc->ftdi.channel, complete_cb, user_data); } //------------- Driver API -------------// @@ -1704,9 +1705,9 @@ static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 9, 0); uint16_t lcr = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xf) << 8 | // data bit quantity is stored in bits 8-11 - ((uint32_t) p_cdc->requested_line_coding.parity & 0xf) << 4 | // parity is stored in bits 4-7, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0xf)); // parity is stored in bits 0-3, same coding + ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) << 8 | // data bit quantity is stored in bits 8-11 + ((uint32_t) p_cdc->requested_line_coding.parity & 0xfu) << 4 | // parity is stored in bits 4-7, same coding + ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0xfu)); // parity is stored in bits 0-3, same coding return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } -- cgit v1.3.1 From cb69ed0d0423b8e09ae77307fcc01165ae4c9386 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 21 Mar 2024 08:29:28 +0100 Subject: code style and clean up CDC serial header files --- src/class/cdc/serial/ch34x.h | 70 ++++++++-------- src/class/cdc/serial/cp210x.h | 86 ++++++++++---------- src/class/cdc/serial/ftdi_sio.h | 172 ++++++++++++++++++++-------------------- src/class/cdc/serial/pl2303.h | 146 +++++++++++++++++----------------- 4 files changed, 237 insertions(+), 237 deletions(-) (limited to 'src') diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index c18066f57..7d91f01fe 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _CH34X_H_ -#define _CH34X_H_ +#ifndef TUSB_CH34X_H +#define TUSB_CH34X_H // There is no official documentation for the CH34x (CH340, CH341) chips. Reference can be found // - https://github.com/WCHSoftGroup/ch341ser_linux @@ -40,45 +40,45 @@ #endif // USB requests -#define CH34X_REQ_READ_VERSION 0x5F // dec 95 -#define CH34X_REQ_WRITE_REG 0x9A // dec 154 -#define CH34X_REQ_READ_REG 0x95 // dec 149 -#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161 -#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164 +#define CH34X_REQ_READ_VERSION 0x5F // dec 95 +#define CH34X_REQ_WRITE_REG 0x9A // dec 154 +#define CH34X_REQ_READ_REG 0x95 // dec 149 +#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161 +#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164 // registers -#define CH34X_REG_BREAK 0x05 -#define CH34X_REG_PRESCALER 0x12 -#define CH34X_REG_DIVISOR 0x13 -#define CH34X_REG_LCR 0x18 -#define CH34X_REG_LCR2 0x25 -#define CH34X_REG_MCR_MSR 0x06 -#define CH34X_REG_MCR_MSR2 0x07 -#define CH34X_NBREAK_BITS 0x01 +#define CH34X_REG_BREAK 0x05 +#define CH34X_REG_PRESCALER 0x12 +#define CH34X_REG_DIVISOR 0x13 +#define CH34X_REG_LCR 0x18 +#define CH34X_REG_LCR2 0x25 +#define CH34X_REG_MCR_MSR 0x06 +#define CH34X_REG_MCR_MSR2 0x07 +#define CH34X_NBREAK_BITS 0x01 -#define CH341_REG_0x0F 0x0F // undocumented register -#define CH341_REG_0x2C 0x2C // undocumented register -#define CH341_REG_0x27 0x27 // hardware flow control (cts/rts) +#define CH341_REG_0x0F 0x0F // undocumented register +#define CH341_REG_0x2C 0x2C // undocumented register +#define CH341_REG_0x27 0x27 // hardware flow control (cts/rts) -#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER) -#define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR) +#define CH34X_REG16_DIVISOR_PRESCALER TU_U16(CH34X_REG_DIVISOR, CH34X_REG_PRESCALER) +#define CH32X_REG16_LCR2_LCR TU_U16(CH34X_REG_LCR2, CH34X_REG_LCR) // modem control bits -#define CH34X_BIT_RTS ( 1 << 6 ) -#define CH34X_BIT_DTR ( 1 << 5 ) +#define CH34X_BIT_RTS (1 << 6) +#define CH34X_BIT_DTR (1 << 5) // line control bits -#define CH34X_LCR_ENABLE_RX 0x80 -#define CH34X_LCR_ENABLE_TX 0x40 -#define CH34X_LCR_MARK_SPACE 0x20 -#define CH34X_LCR_PAR_EVEN 0x10 -#define CH34X_LCR_ENABLE_PAR 0x08 -#define CH34X_LCR_PAR_MASK 0x38 // all parity bits -#define CH34X_LCR_STOP_BITS_2 0x04 -#define CH34X_LCR_CS8 0x03 -#define CH34X_LCR_CS7 0x02 -#define CH34X_LCR_CS6 0x01 -#define CH34X_LCR_CS5 0x00 -#define CH34X_LCR_CS_MASK 0x03 // all CSx bits +#define CH34X_LCR_ENABLE_RX 0x80 +#define CH34X_LCR_ENABLE_TX 0x40 +#define CH34X_LCR_MARK_SPACE 0x20 +#define CH34X_LCR_PAR_EVEN 0x10 +#define CH34X_LCR_ENABLE_PAR 0x08 +#define CH34X_LCR_PAR_MASK 0x38 // all parity bits +#define CH34X_LCR_STOP_BITS_2 0x04 +#define CH34X_LCR_CS8 0x03 +#define CH34X_LCR_CS7 0x02 +#define CH34X_LCR_CS6 0x01 +#define CH34X_LCR_CS5 0x00 +#define CH34X_LCR_CS_MASK 0x03 // all CSx bits -#endif /* _CH34X_H_ */ +#endif // TUSB_CH34X_H diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index e18da7d51..a553a54da 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -31,7 +31,7 @@ // parts are overtaken from vendors driver // https://www.silabs.com/documents/public/software/cp210x-3.1.0.tar.gz -/* Config request codes */ +// Config request codes #define CP210X_IFC_ENABLE 0x00 #define CP210X_SET_BAUDDIV 0x01 #define CP210X_GET_BAUDDIV 0x02 @@ -60,56 +60,56 @@ #define CP210X_SET_BAUDRATE 0x1E #define CP210X_VENDOR_SPECIFIC 0xFF // GPIO, Recipient must be Device -/* SILABSER_IFC_ENABLE_REQUEST_CODE */ -#define CP210X_UART_ENABLE 0x0001 -#define CP210X_UART_DISABLE 0x0000 +// SILABSER_IFC_ENABLE_REQUEST_CODE +#define CP210X_UART_ENABLE 0x0001 +#define CP210X_UART_DISABLE 0x0000 -/* SILABSER_SET_BAUDDIV_REQUEST_CODE */ -#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 +// SILABSER_SET_BAUDDIV_REQUEST_CODE +#define CP210X_BAUD_RATE_GEN_FREQ 0x384000 -/*SILABSER_SET_LINE_CTL_REQUEST_CODE */ -#define CP210X_BITS_DATA_MASK 0x0f00 -#define CP210X_BITS_DATA_5 0x0500 -#define CP210X_BITS_DATA_6 0x0600 -#define CP210X_BITS_DATA_7 0x0700 -#define CP210X_BITS_DATA_8 0x0800 -#define CP210X_BITS_DATA_9 0x0900 +// SILABSER_SET_LINE_CTL_REQUEST_CODE +#define CP210X_BITS_DATA_MASK 0x0f00 +#define CP210X_BITS_DATA_5 0x0500 +#define CP210X_BITS_DATA_6 0x0600 +#define CP210X_BITS_DATA_7 0x0700 +#define CP210X_BITS_DATA_8 0x0800 +#define CP210X_BITS_DATA_9 0x0900 -#define CP210X_BITS_PARITY_MASK 0x00f0 -#define CP210X_BITS_PARITY_NONE 0x0000 -#define CP210X_BITS_PARITY_ODD 0x0010 -#define CP210X_BITS_PARITY_EVEN 0x0020 -#define CP210X_BITS_PARITY_MARK 0x0030 -#define CP210X_BITS_PARITY_SPACE 0x0040 +#define CP210X_BITS_PARITY_MASK 0x00f0 +#define CP210X_BITS_PARITY_NONE 0x0000 +#define CP210X_BITS_PARITY_ODD 0x0010 +#define CP210X_BITS_PARITY_EVEN 0x0020 +#define CP210X_BITS_PARITY_MARK 0x0030 +#define CP210X_BITS_PARITY_SPACE 0x0040 -#define CP210X_BITS_STOP_MASK 0x000f -#define CP210X_BITS_STOP_1 0x0000 -#define CP210X_BITS_STOP_1_5 0x0001 -#define CP210X_BITS_STOP_2 0x0002 +#define CP210X_BITS_STOP_MASK 0x000f +#define CP210X_BITS_STOP_1 0x0000 +#define CP210X_BITS_STOP_1_5 0x0001 +#define CP210X_BITS_STOP_2 0x0002 -/* SILABSER_SET_BREAK_REQUEST_CODE */ -#define CP210X_BREAK_ON 0x0001 -#define CP210X_BREAK_OFF 0x0000 +// SILABSER_SET_BREAK_REQUEST_CODE +#define CP210X_BREAK_ON 0x0001 +#define CP210X_BREAK_OFF 0x0000 -/* SILABSER_SET_MHS_REQUEST_CODE */ -#define CP210X_MCR_DTR 0x0001 -#define CP210X_MCR_RTS 0x0002 -#define CP210X_MCR_ALL 0x0003 -#define CP210X_MSR_CTS 0x0010 -#define CP210X_MSR_DSR 0x0020 -#define CP210X_MSR_RING 0x0040 -#define CP210X_MSR_DCD 0x0080 -#define CP210X_MSR_ALL 0x00F0 +// SILABSER_SET_MHS_REQUEST_CODE +#define CP210X_MCR_DTR 0x0001 +#define CP210X_MCR_RTS 0x0002 +#define CP210X_MCR_ALL 0x0003 +#define CP210X_MSR_CTS 0x0010 +#define CP210X_MSR_DSR 0x0020 +#define CP210X_MSR_RING 0x0040 +#define CP210X_MSR_DCD 0x0080 +#define CP210X_MSR_ALL 0x00F0 -#define CP210X_CONTROL_WRITE_DTR 0x0100 -#define CP210X_CONTROL_WRITE_RTS 0x0200 +#define CP210X_CONTROL_WRITE_DTR 0x0100 +#define CP210X_CONTROL_WRITE_RTS 0x0200 -#define CP210X_LSR_BREAK 0x0001 -#define CP210X_LSR_FRAMING_ERROR 0x0002 -#define CP210X_LSR_HW_OVERRUN 0x0004 -#define CP210X_LSR_QUEUE_OVERRUN 0x0008 -#define CP210X_LSR_PARITY_ERROR 0x0010 -#define CP210X_LSR_ALL 0x001F +#define CP210X_LSR_BREAK 0x0001 +#define CP210X_LSR_FRAMING_ERROR 0x0002 +#define CP210X_LSR_HW_OVERRUN 0x0004 +#define CP210X_LSR_QUEUE_OVERRUN 0x0008 +#define CP210X_LSR_PARITY_ERROR 0x0010 +#define CP210X_LSR_ALL 0x001F // supported baudrates // reference: datasheets and AN205 "CP210x Baud Rate Support" diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index 42716f73e..4afedec9b 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -28,43 +28,43 @@ #include // Commands -#define FTDI_SIO_RESET 0 // Reset the port -#define FTDI_SIO_MODEM_CTRL 1 // Set the modem control register -#define FTDI_SIO_SET_FLOW_CTRL 2 // Set flow control register -#define FTDI_SIO_SET_BAUD_RATE 3 // Set baud rate -#define FTDI_SIO_SET_DATA 4 // Set the data characteristics of the port -#define FTDI_SIO_GET_MODEM_STATUS 5 // Retrieve current value of modem status register -#define FTDI_SIO_SET_EVENT_CHAR 6 // Set the event character -#define FTDI_SIO_SET_ERROR_CHAR 7 // Set the error character -#define FTDI_SIO_SET_LATENCY_TIMER 9 // Set the latency timer -#define FTDI_SIO_GET_LATENCY_TIMER 10 // Get the latency timer -#define FTDI_SIO_SET_BITMODE 11 // Set bitbang mode -#define FTDI_SIO_READ_PINS 12 // Read immediate value of pins -#define FTDI_SIO_READ_EEPROM 0x90 // Read EEPROM +#define FTDI_SIO_RESET 0 // Reset the port +#define FTDI_SIO_MODEM_CTRL 1 // Set the modem control register +#define FTDI_SIO_SET_FLOW_CTRL 2 // Set flow control register +#define FTDI_SIO_SET_BAUD_RATE 3 // Set baud rate +#define FTDI_SIO_SET_DATA 4 // Set the data characteristics of the port +#define FTDI_SIO_GET_MODEM_STATUS 5 // Retrieve current value of modem status register +#define FTDI_SIO_SET_EVENT_CHAR 6 // Set the event character +#define FTDI_SIO_SET_ERROR_CHAR 7 // Set the error character +#define FTDI_SIO_SET_LATENCY_TIMER 9 // Set the latency timer +#define FTDI_SIO_GET_LATENCY_TIMER 10 // Get the latency timer +#define FTDI_SIO_SET_BITMODE 11 // Set bitbang mode +#define FTDI_SIO_READ_PINS 12 // Read immediate value of pins +#define FTDI_SIO_READ_EEPROM 0x90 // Read EEPROM // Channel indices for FT2232, FT2232H and FT4232H devices -#define CHANNEL_A 1 -#define CHANNEL_B 2 -#define CHANNEL_C 3 -#define CHANNEL_D 4 +#define CHANNEL_A 1 +#define CHANNEL_B 2 +#define CHANNEL_C 3 +#define CHANNEL_D 4 // Port Identifier Table -#define PIT_DEFAULT 0 // SIOA -#define PIT_SIOA 1 // SIOA +#define PIT_DEFAULT 0 // SIOA +#define PIT_SIOA 1 // SIOA // The device this driver is tested with one has only one port -#define PIT_SIOB 2 // SIOB -#define PIT_PARALLEL 3 // Parallel +#define PIT_SIOB 2 // SIOB +#define PIT_PARALLEL 3 // Parallel // FTDI_SIO_RESET -#define FTDI_SIO_RESET_REQUEST FTDI_SIO_RESET -#define FTDI_SIO_RESET_REQUEST_TYPE 0x40 -#define FTDI_SIO_RESET_SIO 0 -#define FTDI_SIO_RESET_PURGE_RX 1 -#define FTDI_SIO_RESET_PURGE_TX 2 +#define FTDI_SIO_RESET_REQUEST FTDI_SIO_RESET +#define FTDI_SIO_RESET_REQUEST_TYPE 0x40 +#define FTDI_SIO_RESET_SIO 0 +#define FTDI_SIO_RESET_PURGE_RX 1 +#define FTDI_SIO_RESET_PURGE_TX 2 // FTDI_SIO_SET_BAUDRATE -#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_BAUDRATE_REQUEST 3 +#define FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_BAUDRATE_REQUEST 3 enum ftdi_sio_baudrate { ftdi_sio_b300 = 0, @@ -80,89 +80,89 @@ enum ftdi_sio_baudrate { }; // FTDI_SIO_SET_DATA -#define FTDI_SIO_SET_DATA_REQUEST FTDI_SIO_SET_DATA -#define FTDI_SIO_SET_DATA_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) -#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) -#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) -#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) -#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) -#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) -#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) -#define FTDI_SIO_SET_BREAK (0x1 << 14) +#define FTDI_SIO_SET_DATA_REQUEST FTDI_SIO_SET_DATA +#define FTDI_SIO_SET_DATA_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_DATA_PARITY_NONE (0x0 << 8) +#define FTDI_SIO_SET_DATA_PARITY_ODD (0x1 << 8) +#define FTDI_SIO_SET_DATA_PARITY_EVEN (0x2 << 8) +#define FTDI_SIO_SET_DATA_PARITY_MARK (0x3 << 8) +#define FTDI_SIO_SET_DATA_PARITY_SPACE (0x4 << 8) +#define FTDI_SIO_SET_DATA_STOP_BITS_1 (0x0 << 11) // same coding as ACM +#define FTDI_SIO_SET_DATA_STOP_BITS_15 (0x1 << 11) // 1.5 not supported, for future use? +#define FTDI_SIO_SET_DATA_STOP_BITS_2 (0x2 << 11) +#define FTDI_SIO_SET_BREAK (0x1 << 14) // FTDI_SIO_MODEM_CTRL -#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL +#define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL -#define FTDI_SIO_SET_DTR_MASK 0x1 -#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) -#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) -#define FTDI_SIO_SET_RTS_MASK 0x2 -#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) -#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) +#define FTDI_SIO_SET_DTR_MASK 0x1 +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) +#define FTDI_SIO_SET_RTS_MASK 0x2 +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) // FTDI_SIO_SET_FLOW_CTRL -#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL +#define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL #define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 -#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) -#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) -#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) +#define FTDI_SIO_RTS_CTS_HS (0x1 << 8) +#define FTDI_SIO_DTR_DSR_HS (0x2 << 8) +#define FTDI_SIO_XON_XOFF_HS (0x4 << 8) // FTDI_SIO_GET_LATENCY_TIMER -#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST FTDI_SIO_GET_LATENCY_TIMER -#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE 0xC0 +#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST FTDI_SIO_GET_LATENCY_TIMER +#define FTDI_SIO_GET_LATENCY_TIMER_REQUEST_TYPE 0xC0 // FTDI_SIO_SET_LATENCY_TIMER -#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST FTDI_SIO_SET_LATENCY_TIMER -#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST FTDI_SIO_SET_LATENCY_TIMER +#define FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE 0x40 // FTDI_SIO_SET_EVENT_CHAR -#define FTDI_SIO_SET_EVENT_CHAR_REQUEST FTDI_SIO_SET_EVENT_CHAR -#define FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_EVENT_CHAR_REQUEST FTDI_SIO_SET_EVENT_CHAR +#define FTDI_SIO_SET_EVENT_CHAR_REQUEST_TYPE 0x40 // FTDI_SIO_GET_MODEM_STATUS -#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE 0xc0 -#define FTDI_SIO_GET_MODEM_STATUS_REQUEST FTDI_SIO_GET_MODEM_STATUS -#define FTDI_SIO_CTS_MASK 0x10 -#define FTDI_SIO_DSR_MASK 0x20 -#define FTDI_SIO_RI_MASK 0x40 -#define FTDI_SIO_RLSD_MASK 0x80 +#define FTDI_SIO_GET_MODEM_STATUS_REQUEST_TYPE 0xc0 +#define FTDI_SIO_GET_MODEM_STATUS_REQUEST FTDI_SIO_GET_MODEM_STATUS +#define FTDI_SIO_CTS_MASK 0x10 +#define FTDI_SIO_DSR_MASK 0x20 +#define FTDI_SIO_RI_MASK 0x40 +#define FTDI_SIO_RLSD_MASK 0x80 // FTDI_SIO_SET_BITMODE -#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE 0x40 -#define FTDI_SIO_SET_BITMODE_REQUEST FTDI_SIO_SET_BITMODE +#define FTDI_SIO_SET_BITMODE_REQUEST_TYPE 0x40 +#define FTDI_SIO_SET_BITMODE_REQUEST FTDI_SIO_SET_BITMODE // Possible bitmodes for FTDI_SIO_SET_BITMODE_REQUEST -#define FTDI_SIO_BITMODE_RESET 0x00 -#define FTDI_SIO_BITMODE_CBUS 0x20 +#define FTDI_SIO_BITMODE_RESET 0x00 +#define FTDI_SIO_BITMODE_CBUS 0x20 // FTDI_SIO_READ_PINS -#define FTDI_SIO_READ_PINS_REQUEST_TYPE 0xc0 -#define FTDI_SIO_READ_PINS_REQUEST FTDI_SIO_READ_PINS +#define FTDI_SIO_READ_PINS_REQUEST_TYPE 0xc0 +#define FTDI_SIO_READ_PINS_REQUEST FTDI_SIO_READ_PINS // FTDI_SIO_READ_EEPROM -#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE 0xc0 -#define FTDI_SIO_READ_EEPROM_REQUEST FTDI_SIO_READ_EEPROM +#define FTDI_SIO_READ_EEPROM_REQUEST_TYPE 0xc0 +#define FTDI_SIO_READ_EEPROM_REQUEST FTDI_SIO_READ_EEPROM #define FTDI_FTX_CBUS_MUX_GPIO 0x8 #define FTDI_FT232R_CBUS_MUX_GPIO 0xa #define FTDI_RS0_CTS (1 << 4) #define FTDI_RS0_DSR (1 << 5) -#define FTDI_RS0_RI (1 << 6) +#define FTDI_RS0_RI (1 << 6) #define FTDI_RS0_RLSD (1 << 7) -#define FTDI_RS_DR 1 -#define FTDI_RS_OE (1<<1) -#define FTDI_RS_PE (1<<2) -#define FTDI_RS_FE (1<<3) -#define FTDI_RS_BI (1<<4) -#define FTDI_RS_THRE (1<<5) -#define FTDI_RS_TEMT (1<<6) -#define FTDI_RS_FIFO (1<<7) +#define FTDI_RS_DR 1 +#define FTDI_RS_OE (1 << 1) +#define FTDI_RS_PE (1 << 2) +#define FTDI_RS_FE (1 << 3) +#define FTDI_RS_BI (1 << 4) +#define FTDI_RS_THRE (1 << 5) +#define FTDI_RS_TEMT (1 << 6) +#define FTDI_RS_FIFO (1 << 7) // chip types and names enum ftdi_chip_type { @@ -206,14 +206,14 @@ enum ftdi_chip_type { // private interface data typedef struct ftdi_private { - enum ftdi_chip_type chip_type; - uint8_t channel; // channel index, or 0 for legacy types + enum ftdi_chip_type chip_type; + uint8_t channel; // channel index, or 0 for legacy types } ftdi_private_t; -#define FTDI_OK true -#define FTDI_FAIL false +#define FTDI_OK true +#define FTDI_FAIL false #define FTDI_NOT_POSSIBLE -1 -#define FTDI_REQUESTED -2 +#define FTDI_REQUESTED -2 // division and round function overtaken from math.h #define DIV_ROUND_CLOSEST(x, divisor)( \ diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h index bf264191b..d69bdbfae 100644 --- a/src/class/cdc/serial/pl2303.h +++ b/src/class/cdc/serial/pl2303.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _PL2303_H_ -#define _PL2303_H_ +#ifndef TUSB_PL2303_H +#define TUSB_PL2303_H #include #include @@ -36,66 +36,66 @@ // https://github.com/torvalds/linux/blob/master/drivers/usb/serial/pl2303.c // - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uplcom.c -/* quirks */ -#define PL2303_QUIRK_UART_STATE_IDX0 1 -#define PL2303_QUIRK_LEGACY 2 -#define PL2303_QUIRK_ENDPOINT_HACK 4 - -/* requests and bits */ -#define PL2303_SET_LINE_REQUEST_TYPE 0x21 // class request host to device interface -#define PL2303_SET_LINE_REQUEST 0x20 // dec 32 - -#define PL2303_SET_CONTROL_REQUEST_TYPE 0x21 // class request host to device interface -#define PL2303_SET_CONTROL_REQUEST 0x22 // dec 34 -#define PL2303_CONTROL_DTR 0x01 // dec 1 -#define PL2303_CONTROL_RTS 0x02 // dec 2 - -#define PL2303_BREAK_REQUEST_TYPE 0x21 // class request host to device interface -#define PL2303_BREAK_REQUEST 0x23 // dec 35 -#define PL2303_BREAK_ON 0xffff -#define PL2303_BREAK_OFF 0x0000 - -#define PL2303_GET_LINE_REQUEST_TYPE 0xa1 // class request device to host interface -#define PL2303_GET_LINE_REQUEST 0x21 // dec 33 - -#define PL2303_VENDOR_WRITE_REQUEST_TYPE 0x40 // vendor request host to device interface -#define PL2303_VENDOR_WRITE_REQUEST 0x01 // dec 1 -#define PL2303_VENDOR_WRITE_NREQUEST 0x80 // dec 128 - -#define PL2303_VENDOR_READ_REQUEST_TYPE 0xc0 // vendor request device to host interface -#define PL2303_VENDOR_READ_REQUEST 0x01 // dec 1 -#define PL2303_VENDOR_READ_NREQUEST 0x81 // dec 129 - -#define PL2303_UART_STATE_INDEX 8 -#define PL2303_UART_STATE_MSR_MASK 0x8b -#define PL2303_UART_STATE_TRANSIENT_MASK 0x74 -#define PL2303_UART_DCD 0x01 -#define PL2303_UART_DSR 0x02 -#define PL2303_UART_BREAK_ERROR 0x04 -#define PL2303_UART_RING 0x08 -#define PL2303_UART_FRAME_ERROR 0x10 -#define PL2303_UART_PARITY_ERROR 0x20 -#define PL2303_UART_OVERRUN_ERROR 0x40 -#define PL2303_UART_CTS 0x80 - -#define PL2303_FLOWCTRL_MASK 0xf0 - -#define PL2303_CLEAR_HALT_REQUEST_TYPE 0x02 // standard request host to device endpoint - -/* registers via vendor read/write requests */ -#define PL2303_READ_TYPE_HX_STATUS 0x8080 - -#define PL2303_HXN_RESET_REG 0x07 -#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 -#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 - -#define PL2303_HXN_FLOWCTRL_REG 0x0a -#define PL2303_HXN_FLOWCTRL_MASK 0x1c -#define PL2303_HXN_FLOWCTRL_NONE 0x1c -#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 -#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c - -/* type data */ +// quirks +#define PL2303_QUIRK_UART_STATE_IDX0 1 +#define PL2303_QUIRK_LEGACY 2 +#define PL2303_QUIRK_ENDPOINT_HACK 4 + +// requests and bits +#define PL2303_SET_LINE_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_SET_LINE_REQUEST 0x20 // dec 32 + +#define PL2303_SET_CONTROL_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_SET_CONTROL_REQUEST 0x22 // dec 34 +#define PL2303_CONTROL_DTR 0x01 // dec 1 +#define PL2303_CONTROL_RTS 0x02 // dec 2 + +#define PL2303_BREAK_REQUEST_TYPE 0x21 // class request host to device interface +#define PL2303_BREAK_REQUEST 0x23 // dec 35 +#define PL2303_BREAK_ON 0xffff +#define PL2303_BREAK_OFF 0x0000 + +#define PL2303_GET_LINE_REQUEST_TYPE 0xa1 // class request device to host interface +#define PL2303_GET_LINE_REQUEST 0x21 // dec 33 + +#define PL2303_VENDOR_WRITE_REQUEST_TYPE 0x40 // vendor request host to device interface +#define PL2303_VENDOR_WRITE_REQUEST 0x01 // dec 1 +#define PL2303_VENDOR_WRITE_NREQUEST 0x80 // dec 128 + +#define PL2303_VENDOR_READ_REQUEST_TYPE 0xc0 // vendor request device to host interface +#define PL2303_VENDOR_READ_REQUEST 0x01 // dec 1 +#define PL2303_VENDOR_READ_NREQUEST 0x81 // dec 129 + +#define PL2303_UART_STATE_INDEX 8 +#define PL2303_UART_STATE_MSR_MASK 0x8b +#define PL2303_UART_STATE_TRANSIENT_MASK 0x74 +#define PL2303_UART_DCD 0x01 +#define PL2303_UART_DSR 0x02 +#define PL2303_UART_BREAK_ERROR 0x04 +#define PL2303_UART_RING 0x08 +#define PL2303_UART_FRAME_ERROR 0x10 +#define PL2303_UART_PARITY_ERROR 0x20 +#define PL2303_UART_OVERRUN_ERROR 0x40 +#define PL2303_UART_CTS 0x80 + +#define PL2303_FLOWCTRL_MASK 0xf0 + +#define PL2303_CLEAR_HALT_REQUEST_TYPE 0x02 // standard request host to device endpoint + +// registers via vendor read/write requests +#define PL2303_READ_TYPE_HX_STATUS 0x8080 + +#define PL2303_HXN_RESET_REG 0x07 +#define PL2303_HXN_RESET_UPSTREAM_PIPE 0x02 +#define PL2303_HXN_RESET_DOWNSTREAM_PIPE 0x01 + +#define PL2303_HXN_FLOWCTRL_REG 0x0a +#define PL2303_HXN_FLOWCTRL_MASK 0x1c +#define PL2303_HXN_FLOWCTRL_NONE 0x1c +#define PL2303_HXN_FLOWCTRL_RTS_CTS 0x18 +#define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c + +// type data enum pl2303_type { TYPE_H, TYPE_HX, @@ -107,9 +107,9 @@ enum pl2303_type { }; struct pl2303_type_data { - uint8_t const *name; + uint8_t const *name; uint32_t const max_baud_rate; - uint8_t const quirks; + uint8_t const quirks; uint16_t const no_autoxonxoff:1; uint16_t const no_divisors:1; uint16_t const alt_divisors:1; @@ -146,7 +146,7 @@ struct pl2303_type_data { .no_divisors = true, \ } -/* private data types */ +// private data types struct pl2303_serial_private { const struct pl2303_type_data* type; uint8_t quirks; @@ -157,16 +157,16 @@ typedef struct TU_ATTR_PACKED { bool supports_hx_status; } pl2303_private_t; -/* buffer sizes for line coding data */ -#define PL2303_LINE_CODING_BUFSIZE 7 +// buffer sizes for line coding data +#define PL2303_LINE_CODING_BUFSIZE 7 #define PL2303_LINE_CODING_BAUDRATE_BUFSIZE 4 -/* bulk endpoints */ -#define PL2303_OUT_EP 0x02 -#define PL2303_IN_EP 0x83 +// bulk endpoints +#define PL2303_OUT_EP 0x02 +#define PL2303_IN_EP 0x83 -/* return values of pl2303_detect_type() */ +// return values of pl2303_detect_type() #define PL2303_SUPPORTS_HX_STATUS_TRIGGERED -1 -#define PL2303_DETECT_TYPE_FAILED -2 +#define PL2303_DETECT_TYPE_FAILED -2 -#endif /* _PL2303_H_ */ +#endif // TUSB_PL2303_H -- cgit v1.3.1 From 5e67b92b8c398d6fee92010ecd63cf50b51f8f9a Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 4 Apr 2024 14:10:31 +0200 Subject: fixed compile warnings --- src/class/cdc/cdc_host.c | 29 ++++++++++++++++------------- src/class/cdc/serial/cp210x.h | 4 ++-- src/class/cdc/serial/ftdi_sio.h | 14 +++++++------- 3 files changed, 25 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index e6579ad82..2d900a753 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1181,9 +1181,9 @@ static bool ftdi_change_speed(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_c static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); uint16_t value = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) | // data bit quantity is stored in bits 0-3 - ((uint32_t) p_cdc->requested_line_coding.parity & 0x7u) << 8 | // parity is stored in bits 8-10, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0x3u) << 11 ); // stop bits quantity is stored in bits 11-12, same coding + (p_cdc->requested_line_coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 + (p_cdc->requested_line_coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding + (p_cdc->requested_line_coding.stop_bits & 0x3UL) << 11 ); // stop bits quantity is stored in bits 11-12, same coding // not each FTDI supports 1.5 stop bits return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, @@ -1191,8 +1191,8 @@ static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple } static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? (uint32_t) FTDI_SIO_SET_DTR_HIGH : (uint32_t) FTDI_SIO_SET_DTR_LOW) | - (p_cdc->requested_line_state.rts ? (uint32_t) FTDI_SIO_SET_RTS_HIGH : (uint32_t) FTDI_SIO_SET_RTS_LOW)); + uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | + (p_cdc->requested_line_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, value, p_cdc->ftdi.channel, complete_cb, user_data); @@ -1338,7 +1338,10 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { // other interfaces have same type as interface 0 uint8_t const idx_itf0 = tuh_cdc_itf_get_index(xfer->daddr, 0); cdch_interface_t const * p_cdc_itf0 = get_itf(idx_itf0); - p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type; + TU_ASSERT_COMPLETE(p_cdc_itf0); + if (p_cdc_itf0) { + p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type; + } } TU_ATTR_FALLTHROUGH; @@ -1715,9 +1718,9 @@ static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 9, 0); uint16_t lcr = (uint16_t) ( - ((uint32_t) p_cdc->requested_line_coding.data_bits & 0xfu) << 8 | // data bit quantity is stored in bits 8-11 - ((uint32_t) p_cdc->requested_line_coding.parity & 0xfu) << 4 | // parity is stored in bits 4-7, same coding - ((uint32_t) p_cdc->requested_line_coding.stop_bits & 0xfu)); // parity is stored in bits 0-3, same coding + (p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 + (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding + (p_cdc->requested_line_coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } @@ -1725,8 +1728,8 @@ static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, - (uint16_t) ((uint32_t) CP210X_CONTROL_WRITE_DTR | - (uint32_t) CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line_state.all), + (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | + p_cdc->requested_line_state.all), NULL, 0, complete_cb, user_data); } @@ -2327,7 +2330,7 @@ static bool pl2303_vendor_write(cdch_interface_t * p_cdc, uint16_t value, uint16 static inline bool pl2303_supports_hx_status(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t buf; + uint8_t buf = 0; return pl2303_set_request(p_cdc, PL2303_VENDOR_READ_REQUEST, PL2303_VENDOR_READ_REQUEST_TYPE, PL2303_READ_TYPE_HX_STATUS, 0, &buf, 1, complete_cb, user_data); @@ -2519,7 +2522,7 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { cdch_interface_t * p_cdc = get_itf(idx); // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() TU_ASSERT_COMPLETE(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); - uint8_t buf; + uint8_t buf = 0; int8_t type; switch (state) { diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index a553a54da..ac9c27330 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -101,8 +101,8 @@ #define CP210X_MSR_DCD 0x0080 #define CP210X_MSR_ALL 0x00F0 -#define CP210X_CONTROL_WRITE_DTR 0x0100 -#define CP210X_CONTROL_WRITE_RTS 0x0200 +#define CP210X_CONTROL_WRITE_DTR 0x0100UL +#define CP210X_CONTROL_WRITE_RTS 0x0200UL #define CP210X_LSR_BREAK 0x0001 #define CP210X_LSR_FRAMING_ERROR 0x0002 diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index 4afedec9b..f621b3912 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -96,17 +96,17 @@ enum ftdi_sio_baudrate { #define FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE 0x40 #define FTDI_SIO_SET_MODEM_CTRL_REQUEST FTDI_SIO_MODEM_CTRL -#define FTDI_SIO_SET_DTR_MASK 0x1 -#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1) -#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0) -#define FTDI_SIO_SET_RTS_MASK 0x2 -#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2) -#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0) +#define FTDI_SIO_SET_DTR_MASK 0x1UL +#define FTDI_SIO_SET_DTR_HIGH ((FTDI_SIO_SET_DTR_MASK << 8) | 1UL) +#define FTDI_SIO_SET_DTR_LOW ((FTDI_SIO_SET_DTR_MASK << 8) | 0UL) +#define FTDI_SIO_SET_RTS_MASK 0x2UL +#define FTDI_SIO_SET_RTS_HIGH ((FTDI_SIO_SET_RTS_MASK << 8) | 2UL) +#define FTDI_SIO_SET_RTS_LOW ((FTDI_SIO_SET_RTS_MASK << 8) | 0UL) // FTDI_SIO_SET_FLOW_CTRL #define FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE 0x40 #define FTDI_SIO_SET_FLOW_CTRL_REQUEST FTDI_SIO_SET_FLOW_CTRL -#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 +#define FTDI_SIO_DISABLE_FLOW_CTRL 0x0 #define FTDI_SIO_RTS_CTS_HS (0x1 << 8) #define FTDI_SIO_DTR_DSR_HS (0x2 << 8) #define FTDI_SIO_XON_XOFF_HS (0x4 << 8) -- cgit v1.3.1 From e07ee4a7b1f7c7d18f385d605dd41e08962ddba4 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 4 Apr 2024 14:12:14 +0200 Subject: CP210x removed baudrate check, fixed data bits check --- src/class/cdc/cdc_host.c | 12 ++---------- src/class/cdc/serial/cp210x.h | 9 --------- 2 files changed, 2 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 2d900a753..73d800469 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1701,22 +1701,14 @@ static inline bool cp210x_ifc_enable(cdch_interface_t * p_cdc, uint16_t enabled, } static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // Check baudrate is supported. It's only a specific list. reference: datasheets and AN205 "CP210x Baud Rate Support" - uint32_t const supported_baudrates_list[] = CP210X_SUPPORTED_BAUDRATES_LIST; - uint8_t i; - for ( i=0; supported_baudrates_list[i]; i++ ){ - if (p_cdc->requested_line_coding.bit_rate == supported_baudrates_list[i]) { - break; - } - } - TU_VERIFY(supported_baudrates_list[i]); + // Not every baud rate is supported. See datasheets and AN205 "CP210x Baud Rate Support" uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); } static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 9, 0); + TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); uint16_t lcr = (uint16_t) ( (p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding diff --git a/src/class/cdc/serial/cp210x.h b/src/class/cdc/serial/cp210x.h index ac9c27330..a0eff9e40 100644 --- a/src/class/cdc/serial/cp210x.h +++ b/src/class/cdc/serial/cp210x.h @@ -111,13 +111,4 @@ #define CP210X_LSR_PARITY_ERROR 0x0010 #define CP210X_LSR_ALL 0x001F -// supported baudrates -// reference: datasheets and AN205 "CP210x Baud Rate Support" -#define CP210X_SUPPORTED_BAUDRATES_LIST { \ - 300, 600, \ - 1200, 1800, 2400, 4000, 4800, 7200, 9600, \ - 14400, 16000, 19200, 28800, 38400, 51200, 56000, 57600, 64000, 76800, \ - 115200, 128000, 153600, 230400, 250000, 256000, 460800, 500000, 576000, 921600, \ - 0 } - #endif //TUSB_CP210X_H -- cgit v1.3.1 From a1b1c1f552d944da1bf309ce002b7c07f5a270a0 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 4 Apr 2024 14:13:24 +0200 Subject: foxed FTDI flow control config --- src/class/cdc/cdc_host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 73d800469..6006730b7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1382,7 +1382,8 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { case CONFIG_FTDI_FLOW_CONTROL: // disable flow control TU_ASSERT_COMPLETE(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, - 0, FTDI_SIO_DISABLE_FLOW_CTRL, ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); + FTDI_SIO_DISABLE_FLOW_CTRL, p_cdc->ftdi.channel, + ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); break; case CONFIG_FTDI_MODEM_CTRL: -- cgit v1.3.1 From e02a309f1dc09377fe5123c21ecfe36eb6a032c7 Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 4 Apr 2024 14:14:41 +0200 Subject: disable PL2303 flow control config --- src/class/cdc/cdc_host.c | 55 +++++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 6006730b7..b9915f583 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2475,8 +2475,8 @@ enum { CONFIG_PL2303_RESET_ENDP2, CONFIG_PL2303_LINE_CODING, CONFIG_PL2303_MODEM_CONTROL, - CONFIG_PL2303_FLOW_CTRL_READ, - CONFIG_PL2303_FLOW_CTRL_WRITE, +// CONFIG_PL2303_FLOW_CTRL_READ, +// CONFIG_PL2303_FLOW_CTRL_WRITE, CONFIG_PL2303_COMPLETE }; @@ -2691,35 +2691,38 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { case CONFIG_PL2303_MODEM_CONTROL: #ifdef LINE_CONTROL_ON_ENUM p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_FLOW_CTRL_READ)); + TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; #endif - case CONFIG_PL2303_FLOW_CTRL_READ: - // read flow control register for modify & write back in next step - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, pl2303_process_config, - CONFIG_PL2303_FLOW_CTRL_WRITE)); - } else { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0, &buf, pl2303_process_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); - } - break; - - case CONFIG_PL2303_FLOW_CTRL_WRITE: - // no flow control - buf = xfer->buffer[0]; - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { - buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; - buf |= PL2303_HXN_FLOWCTRL_NONE; - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, pl2303_process_config, - CONFIG_PL2303_COMPLETE)); - } else { - buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, buf, pl2303_process_config, CONFIG_PL2303_COMPLETE)); - } - break; +// skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program +// case CONFIG_PL2303_FLOW_CTRL_READ: +// // read flow control register for modify & write back in next step +// if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { +// TU_LOG_P_CDC ( "1\r\n" ); +// TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, pl2303_process_config, +// CONFIG_PL2303_FLOW_CTRL_WRITE)); +// } else { +// TU_LOG_P_CDC ( "2\r\n" ); +// TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0, &buf, pl2303_process_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); +// } +// break; +// +// case CONFIG_PL2303_FLOW_CTRL_WRITE: +// // no flow control +// buf = xfer->buffer[0]; +// if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { +// buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; +// buf |= PL2303_HXN_FLOWCTRL_NONE; +// TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, pl2303_process_config, +// CONFIG_PL2303_COMPLETE)); +// } else { +// buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; +// TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, buf, pl2303_process_config, CONFIG_PL2303_COMPLETE)); +// } +// break; case CONFIG_PL2303_COMPLETE: set_config_complete(idx, 0, true); -- cgit v1.3.1 From 68602e4adda941ab11826afbd7b82e44134a97ae Mon Sep 17 00:00:00 2001 From: IngHK Date: Thu, 4 Apr 2024 14:16:02 +0200 Subject: small change process config complete --- src/class/cdc/cdc_host.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b9915f583..fbe0cc9ca 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1400,7 +1400,7 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { break; default: - set_config_complete(idx, 0, false); + TU_ASSERT_COMPLETE(false); break; } } @@ -1876,7 +1876,7 @@ static void cp210x_process_config(tuh_xfer_t * xfer) { break; default: - set_config_complete(idx, 0, false); + TU_ASSERT_COMPLETE(false); break; } } @@ -2158,7 +2158,7 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { break; default: - set_config_complete(idx, 0, false); + TU_ASSERT_COMPLETE(false); break; } } @@ -2729,7 +2729,7 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { break; default: - set_config_complete(idx, 0, false); + TU_ASSERT_COMPLETE(false); break; } } -- cgit v1.3.1 From 8b4ca69e56860e12596e2bef63fc155f8dce338c Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Apr 2024 01:14:30 +0200 Subject: cdc_device : save rhport. --- src/class/cdc/cdc_device.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 2e0a0c30d..e856963f5 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -47,6 +47,7 @@ typedef struct { + uint8_t rhport; uint8_t itf_num; uint8_t ep_notif; uint8_t ep_in; @@ -84,7 +85,6 @@ CFG_TUD_MEM_SECTION tu_static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; static bool _prep_out_transaction (cdcd_interface_t* p_cdc) { - uint8_t const rhport = 0; uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff); // Prepare for incoming data but only allow what we can store in the ring buffer. @@ -94,18 +94,18 @@ static bool _prep_out_transaction (cdcd_interface_t* p_cdc) TU_VERIFY(available >= sizeof(p_cdc->epout_buf)); // claim endpoint - TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out)); + TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_out)); // fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&p_cdc->rx_ff); if ( available >= sizeof(p_cdc->epout_buf) ) { - return usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); + return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf)); }else { // Release endpoint since we don't make any transfer - usbd_edpt_release(rhport, p_cdc->ep_out); + usbd_edpt_release(p_cdc->rhport, p_cdc->ep_out); return false; } @@ -135,7 +135,6 @@ void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted) _cdcd_itf[itf].wanted_char = wanted; } - //--------------------------------------------------------------------+ // READ API //--------------------------------------------------------------------+ @@ -194,23 +193,21 @@ uint32_t tud_cdc_n_write_flush (uint8_t itf) // No data to send if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0; - uint8_t const rhport = 0; - // Claim the endpoint - TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 ); + TU_VERIFY( usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0 ); // Pull data from FIFO uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf)); if ( count ) { - TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); + TU_ASSERT( usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 ); return count; }else { // Release endpoint since we don't make any transfer // Note: data is dropped if terminal is not connected - usbd_edpt_release(rhport, p_cdc->ep_in); + usbd_edpt_release(p_cdc->rhport, p_cdc->ep_in); return 0; } } @@ -319,6 +316,7 @@ uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 TU_ASSERT(p_cdc, 0); //------------- Control Interface -------------// + p_cdc->rhport = rhport; p_cdc->itf_num = itf_desc->bInterfaceNumber; uint16_t drv_len = sizeof(tusb_desc_interface_t); -- cgit v1.3.1 From 67f32da1b9a460262e028784ffb0386edd507612 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Apr 2024 01:15:46 +0200 Subject: cdc: add uart status notification support. --- src/class/cdc/cdc.h | 29 +++++++++++++++++++++++++++++ src/class/cdc/cdc_device.c | 24 +++++++++++++++++++++++- src/class/cdc/cdc_device.h | 9 +++++++++ 3 files changed, 61 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 5cbd658fe..f92ab9231 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -412,6 +412,35 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct"); +//--------------------------------------------------------------------+ +// Notifications +//--------------------------------------------------------------------+ +typedef struct TU_ATTR_PACKED +{ + uint16_t bRxCarrier : 1; + uint16_t bTxCarrier : 1; + uint16_t bBreak : 1; + uint16_t bRingSignal : 1; + uint16_t bFraming : 1; + uint16_t bParity : 1; + uint16_t bOverRun : 1; + uint16_t : 9; +} cdc_uart_state_t; + +typedef struct TU_ATTR_PACKED +{ + uint8_t bmRequestType; + uint8_t bNotification; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + cdc_uart_state_t bmUartState; +} cdc_notif_serial_state_t; + +TU_VERIFY_STATIC(sizeof(cdc_notif_serial_state_t) == 10, "size is not correct"); + +#define CDC_REQ_TYPE_NOTIF 0xA1 ///< Direction IN; Type Class; Recipient Interface + TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index e856963f5..5057805e2 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -71,6 +71,7 @@ typedef struct OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer + CFG_TUSB_MEM_ALIGN cdc_notif_serial_state_t serial_state_buf; CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; @@ -130,6 +131,27 @@ void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding) (*coding) = _cdcd_itf[itf].line_coding; } +bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state) +{ + cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; + + // Skip if usb is not ready yet + TU_VERIFY( tud_ready(), 0 ); + + // claim endpoint + TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notif)); + + p_cdc->serial_state_buf.bmRequestType = CDC_REQ_TYPE_NOTIF; + p_cdc->serial_state_buf.bNotification = CDC_NOTIF_SERIAL_STATE; + p_cdc->serial_state_buf.wValue = 0; + p_cdc->serial_state_buf.wIndex = p_cdc->itf_num; + p_cdc->serial_state_buf.wLength = 2; + p_cdc->serial_state_buf.bmUartState = state; + + // transfer + return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_notif, (uint8_t *)&p_cdc->serial_state_buf, sizeof(p_cdc->serial_state_buf)); +} + void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted) { _cdcd_itf[itf].wanted_char = wanted; @@ -457,7 +479,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ for (itf = 0; itf < CFG_TUD_CDC; itf++) { p_cdc = &_cdcd_itf[itf]; - if ( ( ep_addr == p_cdc->ep_out ) || ( ep_addr == p_cdc->ep_in ) ) break; + if ( ( ep_addr == p_cdc->ep_out ) || ( ep_addr == p_cdc->ep_in ) || ( ep_addr == p_cdc->ep_notif )) break; } TU_ASSERT(itf < CFG_TUD_CDC); diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index 20e908451..92131f159 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -64,6 +64,9 @@ uint8_t tud_cdc_n_get_line_state (uint8_t itf); // Get current line encoding: bit rate, stop bits parity etc .. void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding); +// Send UART status notification: DCD, DSR etc .. +bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state); + // Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted); @@ -109,6 +112,7 @@ bool tud_cdc_n_write_clear (uint8_t itf); static inline bool tud_cdc_connected (void); static inline uint8_t tud_cdc_get_line_state (void); static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding); +static inline bool tud_cdc_send_uart_state (cdc_uart_state_t state); static inline void tud_cdc_set_wanted_char (char wanted); static inline uint32_t tud_cdc_available (void); @@ -180,6 +184,11 @@ static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding) tud_cdc_n_get_line_coding(0, coding); } +static inline bool tud_cdc_send_uart_state (cdc_uart_state_t state) +{ + return tud_cdc_n_send_uart_state(0, state); +} + static inline void tud_cdc_set_wanted_char (char wanted) { tud_cdc_n_set_wanted_char(0, wanted); -- cgit v1.3.1 From 965e26de1dcbd87c3b0e371857bc4ad0b9b3e840 Mon Sep 17 00:00:00 2001 From: Deadman Date: Wed, 28 Feb 2024 00:00:55 +0100 Subject: add support for native SAMD HCD --- hw/bsp/samd21/family.c | 16 +- hw/bsp/samd21/family.cmake | 1 + hw/bsp/samd21/family.mk | 1 + hw/bsp/samd5x_e5x/family.c | 33 +- hw/bsp/samd5x_e5x/family.cmake | 1 + hw/bsp/samd5x_e5x/family.mk | 1 + src/portable/microchip/samd/hcd_samd.c | 767 +++++++++++++++++++++++++++++++++ 7 files changed, 806 insertions(+), 14 deletions(-) create mode 100644 src/portable/microchip/samd/hcd_samd.c (limited to 'src') diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 7ca20c458..257794058 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -60,7 +60,13 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void USB_Handler(void) { +#if CFG_TUD_ENABLED tud_int_handler(0); +#endif + +#if CFG_TUH_ENABLED && !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + tuh_int_handler(0); +#endif } //--------------------------------------------------------------------+ @@ -140,8 +146,14 @@ void board_init(void) { gpio_set_pin_function(PIN_PA19, PINMUX_PA19F_TCC0_WO3); _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 - max3421_init(); +#if CFG_TUH_ENABLED + #if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + max3421_init(); + #else + // VBUS Power + gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA28, true); + #endif #endif } diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake index c836b85d9..ef9a8adb4 100644 --- a/hw/bsp/samd21/family.cmake +++ b/hw/bsp/samd21/family.cmake @@ -99,6 +99,7 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c + ${TOP}/src/portable/microchip/samd/hcd_samd.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/samd21/family.mk b/hw/bsp/samd21/family.mk index 08c5c5b0e..a2c37b2b6 100644 --- a/hw/bsp/samd21/family.mk +++ b/hw/bsp/samd21/family.mk @@ -23,6 +23,7 @@ LDFLAGS_CLANG += SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ + src/portable/microchip/samd/hcd_samd.c \ ${SDK_DIR}/gcc/gcc/startup_samd21.c \ ${SDK_DIR}/gcc/system_samd21.c \ ${SDK_DIR}/hal/src/hal_atomic.c \ diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index abaee353b..3b842e819 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -56,21 +56,24 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void USB_0_Handler(void) { +TU_ATTR_ALWAYS_INLINE inline void USB_Any_Handler(void) +{ +#if CFG_TUD_ENABLED tud_int_handler(0); -} +#endif -void USB_1_Handler(void) { - tud_int_handler(0); +#if CFG_TUH_ENABLED && !CFG_TUH_MAX3421 + tuh_int_handler(0); +#endif } -void USB_2_Handler(void) { - tud_int_handler(0); -} +void USB_0_Handler(void) { USB_Any_Handler(); } -void USB_3_Handler(void) { - tud_int_handler(0); -} +void USB_1_Handler(void) { USB_Any_Handler(); } + +void USB_2_Handler(void) { USB_Any_Handler(); } + +void USB_3_Handler(void) { USB_Any_Handler(); } //--------------------------------------------------------------------+ // Implementation @@ -138,8 +141,14 @@ void board_init(void) { gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); -#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 - max3421_init(); +#if CFG_TUH_ENABLED + #if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + max3421_init(); + #else + // VBUS Power + gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA28, true); + #endif #endif } diff --git a/hw/bsp/samd5x_e5x/family.cmake b/hw/bsp/samd5x_e5x/family.cmake index fd95ce10e..9a237f0dc 100644 --- a/hw/bsp/samd5x_e5x/family.cmake +++ b/hw/bsp/samd5x_e5x/family.cmake @@ -96,6 +96,7 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c + ${TOP}/src/portable/microchip/samd/hcd_samd.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/samd5x_e5x/family.mk b/hw/bsp/samd5x_e5x/family.mk index 9b1a23db4..f0a4a3f00 100644 --- a/hw/bsp/samd5x_e5x/family.mk +++ b/hw/bsp/samd5x_e5x/family.mk @@ -18,6 +18,7 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/microchip/samd/dcd_samd.c \ + src/portable/microchip/samd/hcd_samd.c \ ${SDK_DIR}/gcc/gcc/startup_${SAM_FAMILY}.c \ ${SDK_DIR}/gcc/system_${SAM_FAMILY}.c \ ${SDK_DIR}/hpl/gclk/hpl_gclk.c \ diff --git a/src/portable/microchip/samd/hcd_samd.c b/src/portable/microchip/samd/hcd_samd.c new file mode 100644 index 000000000..cecaee0b0 --- /dev/null +++ b/src/portable/microchip/samd/hcd_samd.c @@ -0,0 +1,767 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 ChrisDeadman + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && \ + !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) && \ + (CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ + CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21) + +#include "host/hcd.h" +#include "sam.h" + +/*------------------------------------------------------------------*/ +/* MACRO TYPEDEF CONSTANT ENUM + *------------------------------------------------------------------*/ +#define USB_HOST_PTYPE_DIS 0x0 +#define USB_HOST_PTYPE_CTRL 0x1 +#define USB_HOST_PTYPE_ISO 0x2 +#define USB_HOST_PTYPE_BULK 0x3 +#define USB_HOST_PTYPE_INT 0x4 +#define USB_HOST_PTYPE_EXT 0x5 + +#define USB_HOST_PCFG_PTOKEN_SETUP 0x0 +#define USB_HOST_PCFG_PTOKEN_IN 0x1 +#define USB_HOST_PCFG_PTOKEN_OUT 0x2 + +#define USB_PCKSIZE_ENUM(size) \ + ((size) >= 1024 ? 7 \ + : (size) >= 1023 ? 7 \ + : (size) > 256 ? 6 \ + : (size) > 128 ? 5 \ + : (size) > 64 ? 4 \ + : (size) > 32 ? 3 \ + : (size) > 16 ? 2 \ + : (size) > 8 ? 1 \ + : 0) + +// Uncomment to use fake frame number. +// Low-Speed devices stall FNUM during enumeration :/ +// #define HCD_SAMD_FAKE_FNUM + +typedef struct { + uint8_t dev_addr; + uint8_t ep_addr; + uint16_t max_packet_size; + uint16_t xfer_length; + uint16_t xfer_remaining; +} usb_pipe_status_t; + +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM]; + +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile usb_pipe_status_t usb_pipe_status_table[USB_PIPE_NUM]; + +CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static volatile uint32_t fake_fnum; + +static uint8_t samd_configure_pipe(uint8_t dev_addr, uint8_t ep_addr) +{ + uint8_t pipe; + uint8_t token; + volatile usb_pipe_status_t* pipe_status; + bool same_addr = false; + bool same_ep_addr = false; + + // evaluate pipe token + token = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_HOST_PCFG_PTOKEN_IN + : tu_edpt_number(ep_addr) == 0 ? USB_HOST_PCFG_PTOKEN_SETUP + : USB_HOST_PCFG_PTOKEN_OUT; + + TU_LOG3("samd_configure_pipe(token=%02X, dev_addr=%02X, ep_addr=%02X)=", token, dev_addr, ep_addr); + + // find already allocated pipe + for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + pipe_status = &usb_pipe_status_table[pipe]; + same_addr = (pipe_status->dev_addr == dev_addr); + same_ep_addr = (tu_edpt_number(pipe_status->ep_addr) == tu_edpt_number(ep_addr)); + if (same_ep_addr && (same_addr || (tu_edpt_number(ep_addr) == 0))) { + break; + } + } + + // allocate from pool of free pipes + if (pipe >= USB_PIPE_NUM) { + for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + pipe_status = &usb_pipe_status_table[pipe]; + // found a free pipe + if (pipe_status->dev_addr >= UINT8_MAX) { + break; + } + } + } + + // no pipe available :( + if (pipe >= USB_PIPE_NUM) { + TU_LOG3("ERR_NO_PIPE\r\n"); + return pipe; + } + TU_LOG3("%d\r\n", pipe); + + // no transfer should be in progress + TU_ASSERT(((USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE == USB_HOST_PTYPE_DIS) || + USB->HOST.HostPipe[pipe].PSTATUS.bit.PFREEZE == 1), + USB_PIPE_NUM); + + // update addr and ep_addr + pipe_status->dev_addr = dev_addr; + pipe_status->ep_addr = ep_addr; + usb_pipe_table[pipe].HostDescBank[0].CTRL_PIPE.bit.PDADDR = dev_addr; + usb_pipe_table[pipe].HostDescBank[0].CTRL_PIPE.bit.PEPNUM = tu_edpt_number(ep_addr); + + // token specific configuration + USB->HOST.HostPipe[pipe].PCFG.bit.PTOKEN = token; + USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK; + if (token == USB_HOST_PCFG_PTOKEN_SETUP) { + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL; + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } else if (token == USB_HOST_PCFG_PTOKEN_IN) { + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } else { + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + USB->HOST.HostPipe[pipe].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } + + return pipe; +} + +static void samd_free_pipe(uint8_t pipe) +{ + volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe]; + pipe_status->dev_addr = UINT8_MAX; + pipe_status->ep_addr = UINT8_MAX; + pipe_status->max_packet_size = 0; + pipe_status->xfer_length = 0; + pipe_status->xfer_remaining = 0; + + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; + USB->HOST.HostPipe[pipe].PCFG.reg &= ~USB_HOST_PCFG_PTYPE_Msk; + USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK; + memset((uint8_t*) &usb_pipe_table[pipe], 0, sizeof(usb_pipe_table[pipe])); +} + +static void samd_free_all_pipes(void) +{ + for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + samd_free_pipe(pipe); + } +} + +static bool samd_on_xfer(uint8_t pipe, xfer_result_t xfer_result) +{ + uint16_t xfer_delta; + bool xfer_complete; + volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe]; + + // freeze the pipe + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; + + // get number of transferred bytes + if (xfer_result == XFER_RESULT_SUCCESS) { + xfer_delta = usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT; + } else { + xfer_delta = 0; + } + + TU_LOG3( + "samd_on_xfer(%d, result=%d, xdelta=%d, rem=%d)\r\n", xfer_result, pipe, xfer_delta, pipe_status->xfer_remaining); + + // update pipe status + if (xfer_delta > pipe_status->xfer_remaining) { + xfer_delta = pipe_status->xfer_remaining; + } + pipe_status->xfer_remaining -= xfer_delta; + pipe_status->xfer_length += xfer_delta; + + // last packet handling + if (xfer_delta < pipe_status->max_packet_size) { + pipe_status->xfer_remaining = 0; + } + + // transfer complete + xfer_complete = (xfer_result != XFER_RESULT_SUCCESS) || (pipe_status->xfer_remaining == 0); + if (xfer_complete) { + return true; + } + + // continue receiving + if (tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN) { + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0; + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY; + } + // continue sending + else { + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = + (pipe_status->xfer_remaining < pipe_status->max_packet_size) ? pipe_status->xfer_remaining + : pipe_status->max_packet_size; + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; + } + + // advance packet buffer + usb_pipe_table[pipe].HostDescBank[0].ADDR.reg += xfer_delta; + + // start next transfer + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE; + + return false; +} + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport, bool in_isr) +{ + (void) rhport; + + uint16_t int_flags; + uint8_t pint_flags; + xfer_result_t xfer_result; + volatile usb_pipe_status_t* pipe_status; + + // + // Check INTFLAG + // + int_flags = USB->HOST.INTFLAG.reg; + if (int_flags & USB_HOST_INTFLAG_HSOF) { + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; + } + if (int_flags & USB_HOST_INTFLAG_RST) { + TU_LOG2("USB_HOST_INTFLAG_RST\r\n"); + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; + } + if (int_flags & USB_HOST_INTFLAG_WAKEUP) { + TU_LOG3("USB_HOST_INTFLAG_WAKEUP\r\n"); + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; + } + if (int_flags & USB_HOST_INTFLAG_DNRSM) { + TU_LOG3("USB_HOST_INTFLAG_DNRSM\r\n"); + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; + } + if (int_flags & USB_HOST_INTFLAG_UPRSM) { + TU_LOG3("USB_HOST_INTFLAG_UPRSM\r\n"); + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; + } + if (int_flags & USB_HOST_INTFLAG_RAMACER) { + TU_LOG1("USB_HOST_INTFLAG_RAMACER\r\n"); + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; + } + if (int_flags & USB_HOST_INTFLAG_DCONN) { + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; + hcd_event_device_attach(rhport, in_isr); + } + if (int_flags & USB_HOST_INTFLAG_DDISC) { + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; + hcd_event_device_remove(rhport, in_isr); + } + + // handle pipe interrupts + for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + // get pipe handle + pipe_status = &usb_pipe_status_table[pipe]; + if (pipe_status->dev_addr >= UINT8_MAX) { + continue; + } + + // + // Check PINTFLAG + // + pint_flags = USB->HOST.HostPipe[pipe].PINTFLAG.reg; + xfer_result = XFER_RESULT_INVALID; + if (pint_flags & USB_HOST_PINTFLAG_TRCPT0) { + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; + xfer_result = XFER_RESULT_SUCCESS; + } + if (pint_flags & USB_HOST_PINTFLAG_TRCPT1) { + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; + xfer_result = XFER_RESULT_SUCCESS; + } + if (pint_flags & USB_HOST_PINTFLAG_TXSTP) { + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; + xfer_result = XFER_RESULT_SUCCESS; + } + if (pint_flags & USB_HOST_PINTFLAG_STALL) { + TU_LOG2("USB_HOST_PINTFLAG_STALL\r\n"); + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; + xfer_result = XFER_RESULT_STALLED; + } + if (pint_flags & USB_HOST_PINTFLAG_TRFAIL) { + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) { + TU_LOG1("USB_HOST_STATUS_BK_ERRORFLOW\r\n"); + xfer_result = XFER_RESULT_FAILED; + } else if (usb_pipe_table[pipe].HostDescBank[0].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) { + TU_LOG1("USB_HOST_STATUS_BK_CRCERR\r\n"); + xfer_result = XFER_RESULT_FAILED; + } else { + // SAMD Quirk #1: + // Likes to report TRFAIL for no apparent reason -> ignore + } + } + if (pint_flags & USB_HOST_PINTFLAG_PERR) { + USB->HOST.HostPipe[pipe].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; + // Handled by STATUS_PIPE checks below + } + + // + // Check STATUS_PIPE + // + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) { + TU_LOG1("USB_HOST_STATUS_PIPE_DTGLER\r\n"); + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_DTGLER; + xfer_result = XFER_RESULT_FAILED; + } + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) { + TU_LOG1("USB_HOST_STATUS_PIPE_DAPIDER\r\n"); + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_DAPIDER; + xfer_result = XFER_RESULT_FAILED; + } + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) { + TU_LOG1("USB_HOST_STATUS_PIPE_PIDER\r\n"); + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_PIDER; + xfer_result = XFER_RESULT_FAILED; + } + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) { + TU_LOG1("USB_HOST_STATUS_PIPE_CRC16ER\r\n"); + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_CRC16ER; + xfer_result = XFER_RESULT_FAILED; + } + if (usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) { + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.reg &= ~USB_HOST_STATUS_PIPE_TOUTER; + + if ((USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE == USB_HOST_PTYPE_INT) && + (tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN)) { + // ignore timeouts from INT pipes + } else { + if (xfer_result == XFER_RESULT_INVALID) { + xfer_result = XFER_RESULT_TIMEOUT; + } + } + } + + // prevent PERR from too high error counts, that is handled by TinyUSB anyways + usb_pipe_table[pipe].HostDescBank[0].STATUS_PIPE.bit.ERCNT = 0; + + // no updates + if (xfer_result == XFER_RESULT_INVALID) { + continue; + } + + // continue / complete transfer + if (samd_on_xfer(pipe, xfer_result)) { + hcd_event_xfer_complete(pipe_status->dev_addr, pipe_status->ep_addr, pipe_status->xfer_length, xfer_result, true); + } + } +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport) +{ + TU_ASSERT(rhport == 0); + + fake_fnum = 0; + + // reset to get in a clean state. + USB->HOST.CTRLA.bit.SWRST = 1; + while (USB->HOST.SYNCBUSY.bit.SWRST == 0) + ; + while (USB->HOST.SYNCBUSY.bit.SWRST == 1) + ; + + // load pad calibration + USB->HOST.PADCAL.bit.TRANSP = (*((uint32_t*) USB_FUSES_TRANSP_ADDR) & USB_FUSES_TRANSP_Msk) >> USB_FUSES_TRANSP_Pos; + USB->HOST.PADCAL.bit.TRANSN = (*((uint32_t*) USB_FUSES_TRANSN_ADDR) & USB_FUSES_TRANSN_Msk) >> USB_FUSES_TRANSN_Pos; + USB->HOST.PADCAL.bit.TRIM = (*((uint32_t*) USB_FUSES_TRIM_ADDR) & USB_FUSES_TRIM_Msk) >> USB_FUSES_TRIM_Pos; + + USB->HOST.QOSCTRL.bit.CQOS = 3; // High Quality + USB->HOST.QOSCTRL.bit.DQOS = 3; // High Quality + + // configure host-mode + samd_free_all_pipes(); // initializes pipe handles and usb_pipe_table + USB->HOST.DESCADD.reg = (uint32_t) (&usb_pipe_table[0]); + USB->HOST.CTRLB.reg = USB_HOST_CTRLB_SPDCONF_NORMAL | USB_HOST_CTRLB_VBUSOK; + USB->HOST.CTRLA.reg = USB_CTRLA_MODE_HOST | USB_CTRLA_ENABLE | USB_CTRLA_RUNSTDBY; + while (USB->HOST.SYNCBUSY.bit.ENABLE == 1) + ; + + // enable basic USB interrupts + USB->HOST.INTFLAG.reg |= USB->HOST.INTFLAG.reg; // clear pending + USB->HOST.INTENCLR.reg = USB_HOST_INTENCLR_MASK; + USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + USB->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + USB->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + USB->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + + return true; +} + +#if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X + +// Enable USB interrupt +void hcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB_0_IRQn); + NVIC_EnableIRQ(USB_1_IRQn); + NVIC_EnableIRQ(USB_2_IRQn); + NVIC_EnableIRQ(USB_3_IRQn); +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB_3_IRQn); + NVIC_DisableIRQ(USB_2_IRQn); + NVIC_DisableIRQ(USB_1_IRQn); + NVIC_DisableIRQ(USB_0_IRQn); +} + +#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ + CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 + +// Enable USB interrupt +void hcd_int_enable(uint8_t rhport) +{ + (void) rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) +{ + (void) rhport; + NVIC_DisableIRQ(USB_IRQn); +} + +#else + +#error "No implementation available for hcd_int_enable / hcd_int_disable" + +#endif + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) +{ + (void) rhport; + +// SAMD Quirk #2: +// FNUM is stalled before enumeration of Low-Speed devices. +// internal frame counter can be used as workaround (not very accurate) +#ifdef HCD_SAMD_FAKE_FNUM + uint8_t start, current, prev; + uint8_t loop_count = (USB->HOST.STATUS.bit.SPEED == TUSB_SPEED_HIGH) ? 8 : 1; + for (uint8_t i = 0; i < loop_count; i++) { + start = USB->HOST.FLENHIGH.reg; + current = start; + // wait until wrap-around + prev = current; + while (current <= start) { + current = USB->HOST.FLENHIGH.reg; + if (current > prev) + break; + prev = current; + } + // wait until start is reached again + prev = current; + while (current > start) { + current = USB->HOST.FLENHIGH.reg; + if (current > prev) + break; + prev = current; + } + } + fake_fnum += 1; + return fake_fnum; +#else + return USB->HOST.FNUM.bit.FNUM; +#endif // HCD_SAMD_FAKE_FNUM +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) +{ + TU_ASSERT(rhport == 0); + return USB->HOST.STATUS.bit.LINESTATE != 0; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be +// complete. Some port would require hcd_port_reset_end() to be invoked after 10ms to +// complete the reset sequence. +void hcd_port_reset(uint8_t rhport) +{ + hcd_int_disable(rhport); + samd_free_all_pipes(); + USB->HOST.INTFLAG.reg |= USB->HOST.INTFLAG.reg; // clear pending + USB->HOST.CTRLB.bit.BUSRESET = 1; + fake_fnum = 0; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) +{ + while (USB->HOST.INTFLAG.bit.RST == 0) + ; + USB->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; + USB->HOST.CTRLB.bit.SOFE = 1; + hcd_int_enable(rhport); +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) +{ + (void) rhport; + + switch (USB->HOST.STATUS.bit.SPEED) { + case 0: + return TUSB_SPEED_FULL; + case 1: + return TUSB_SPEED_LOW; + case 2: + return TUSB_SPEED_HIGH; + default: + return TUSB_SPEED_INVALID; + } +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +{ + (void) rhport; + + for (uint8_t pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + volatile usb_pipe_status_t* pipe_status = &usb_pipe_status_table[pipe]; + if (pipe_status->dev_addr == dev_addr) { + samd_free_pipe(pipe); + } + } +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc) +{ + TU_ASSERT(rhport == 0); + + uint8_t pipe; + volatile usb_pipe_status_t* pipe_status; + const uint8_t ep_addr = ep_desc->bEndpointAddress; + const uint8_t bmAttributes = (ep_desc->bmAttributes.xfer) | + ((ep_desc->bmAttributes.sync) << 2) | + ((ep_desc->bmAttributes.usage) << 4); + + // configure the pipe + pipe = samd_configure_pipe(dev_addr, ep_addr); + if (pipe >= USB_PIPE_NUM) { + return false; + } + + // initial configuration + pipe_status = &usb_pipe_status_table[pipe]; + USB->HOST.HostPipe[pipe].PCFG.reg &= ~USB_HOST_PCFG_PTYPE_Msk; + USB->HOST.HostPipe[pipe].PCFG.bit.PTYPE = bmAttributes + 1; + USB->HOST.HostPipe[pipe].BINTERVAL.reg = ep_desc->bInterval; + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL; + USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK; + pipe_status->max_packet_size = ep_desc->wMaxPacketSize; + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.SIZE = USB_PCKSIZE_ENUM(pipe_status->max_packet_size); + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = 0; + + return true; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete +// hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) +{ + TU_ASSERT(rhport == 0); + + uint8_t pipe; + volatile usb_pipe_status_t* pipe_status; + + // configure the pipe + pipe = samd_configure_pipe(dev_addr, 0); + if (pipe >= USB_PIPE_NUM) { + return false; + } + + // prepare transfer + pipe_status = &usb_pipe_status_table[pipe]; + usb_pipe_table[pipe].HostDescBank[0].ADDR.reg = (uint32_t) setup_packet; + pipe_status->xfer_remaining = 8; + pipe_status->xfer_length = 0; + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 8; + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0; + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; + + // clear pending interrupts + USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg; + + // begin transfer + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE; + + return true; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t* buffer, uint16_t buflen) +{ + TU_ASSERT(rhport == 0); + + uint8_t pipe; + volatile usb_pipe_status_t* pipe_status; + + // configure the pipe + pipe = samd_configure_pipe(dev_addr, ep_addr); + if (pipe >= USB_PIPE_NUM) { + return false; + } + + // prepare transfer + pipe_status = &usb_pipe_status_table[pipe]; + usb_pipe_table[pipe].HostDescBank[0].ADDR.reg = (uint32_t) buffer; + pipe_status->xfer_remaining = buflen; + pipe_status->xfer_length = 0; + // receive data + if (tu_edpt_dir(pipe_status->ep_addr) == TUSB_DIR_IN) { + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0; + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = pipe_status->max_packet_size; + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY; + } + // send data + else { + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = + (pipe_status->xfer_remaining < pipe_status->max_packet_size) ? pipe_status->xfer_remaining + : pipe_status->max_packet_size; + usb_pipe_table[pipe].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0; + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; + } + + // clear pending interrupts + USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg; + + // begin transfer + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE; + + return true; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been +// started Return true if a queued transfer is aborted, false if there is no transfer +// to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) +{ + TU_ASSERT(rhport == 0); + + uint8_t pipe; + volatile usb_pipe_status_t* pipe_status; + + TU_LOG3("hcd_edpt_abort_xfer(dev_addr=%02X, ep_addr=%02X)=", dev_addr, ep_addr); + + // find the pipe + for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + pipe_status = &usb_pipe_status_table[pipe]; + if ((pipe_status->dev_addr == dev_addr) && (pipe_status->ep_addr == ep_addr)) { + break; + } + } + + // pipe not found + if (pipe >= USB_PIPE_NUM) { + TU_LOG3("ERR_NO_PIPE\r\n"); + return false; + } + TU_LOG3("%d\r\n", pipe); + + // no transfer in progress + if (USB->HOST.HostPipe[pipe].PSTATUS.bit.PFREEZE == 1) { + return false; + } + + // abort the transfer + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; + pipe_status = &usb_pipe_status_table[pipe]; + pipe_status->xfer_length = 0; + pipe_status->xfer_remaining = 0; + + return true; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) +{ + TU_ASSERT(rhport == 0); + + uint8_t pipe; + volatile usb_pipe_status_t* pipe_status; + + TU_LOG3("hcd_edpt_clear_stall(dev_addr=%02X, ep_addr=%02X)=", dev_addr, ep_addr); + + // find the pipe + for (pipe = 0; pipe < USB_PIPE_NUM; pipe++) { + pipe_status = &usb_pipe_status_table[pipe]; + if ((pipe_status->dev_addr == dev_addr) && (pipe_status->ep_addr == ep_addr)) { + break; + } + } + + // pipe not found + if (pipe >= USB_PIPE_NUM) { + TU_LOG3("ERR_NO_PIPE\r\n"); + return false; + } + TU_LOG3("%d\r\n", pipe); + + // clear pending interrupts + USB->HOST.HostPipe[pipe].PINTFLAG.reg |= USB->HOST.HostPipe[pipe].PINTFLAG.reg; + + // clear stalled state + USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; + USB->HOST.HostPipe[pipe].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL; + + return true; +} + +#endif -- cgit v1.3.1 From dee6b369235e3440f9237ae0e74f81edca95f6b7 Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Wed, 11 Dec 2024 11:35:52 +0100 Subject: feature(tusb): Added teardown API --- src/tusb.c | 34 ++++++++++++++++++++++++++++++++++ src/tusb.h | 14 ++++++++++++-- 2 files changed, 46 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/tusb.c b/src/tusb.c index 85ab1d6ae..1549419c8 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -136,6 +136,40 @@ void tusb_int_handler(uint8_t rhport, bool in_isr) { #endif } +bool tusb_rhport_teardown(uint8_t rhport) { + // backward compatible call with tusb_init(void) + #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) + #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) + // deinit device stack, CFG_TUSB_RHPORTx_MODE must be defined + TU_ASSERT( tud_deinit(TUD_OPT_RHPORT) ); + _tusb_rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_INVALID; + #endif + + #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) + // deinit host stack CFG_TUSB_RHPORTx_MODE must be defined + TU_ASSERT( tuh_deinit(TUH_OPT_RHPORT) ); + _tusb_rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_INVALID; + #endif + + return true; + #endif + + // new API with explicit rhport and role + TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM); + + #if CFG_TUD_ENABLED + TU_ASSERT( tud_deinit(rhport) ); + _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + #endif + + #if CFG_TUH_ENABLED + TU_ASSERT( tuh_deinit(rhport) ); + _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + #endif + + return true; +} + //--------------------------------------------------------------------+ // Descriptor helper //--------------------------------------------------------------------+ diff --git a/src/tusb.h b/src/tusb.h index cb6021b33..2b122c302 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -154,14 +154,24 @@ bool tusb_inited(void); // Called to handle usb interrupt/event. tusb_init(rhport, role) must be called before void tusb_int_handler(uint8_t rhport, bool in_isr); -// TODO -// bool tusb_teardown(void); +// Internal helper for backward compatibility with tusb_init(void) +bool tusb_rhport_teardown(uint8_t rhport); + +#if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) + #define _tusb_teardown_arg0() tusb_rhport_teardown(0) +#else + #define _tusb_teardown_arg0() TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined") +#endif + +#define _tusb_teardown_arg1(_rhport) tusb_rhport_teardown(_rhport) +#define tusb_teardown(...) TU_FUNC_OPTIONAL_ARG(_tusb_teardown, __VA_ARGS__) #else #define tusb_init(...) (false) #define tusb_int_handler(...) do {}while(0) #define tusb_inited() (false) +#define tusb_teardown(...) (false) #endif -- cgit v1.3.1 From f6f20e17abc6c0131da7c82e0bfba0690f30bab2 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 24 Jan 2025 16:54:36 +0100 Subject: Add NUCLEO-H7S3L8 BSP. Signed-off-by: HiFiPhile --- docs/reference/boards.rst | 1 + hw/bsp/board_mcu.h | 3 + hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++ .../stm32h7rs/boards/stm32h7s3nucleo/board.cmake | 17 + hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h | 262 +++ hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk | 15 + .../boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt | 6 + .../stm32h7s3nucleo/tcpp0203/Release_Notes.html | 205 +++ .../stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../tcpp0203/_htmresc/mini-st_2020.css | 1703 ++++++++++++++++++++ .../tcpp0203/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c | 888 ++++++++++ .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h | 355 ++++ .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c | 75 + .../boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h | 100 ++ hw/bsp/stm32h7rs/family.c | 313 ++++ hw/bsp/stm32h7rs/family.cmake | 150 ++ hw/bsp/stm32h7rs/family.mk | 92 ++ hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h | 501 ++++++ src/portable/synopsys/dwc2/dwc2_info.md | 116 +- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 21 files changed, 4894 insertions(+), 58 deletions(-) create mode 100644 hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.cmake create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.h create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c create mode 100644 hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h create mode 100644 hw/bsp/stm32h7rs/family.c create mode 100644 hw/bsp/stm32h7rs/family.cmake create mode 100644 hw/bsp/stm32h7rs/family.mk create mode 100644 hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h (limited to 'src') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 4739467bc..2ee40cf7e 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -261,6 +261,7 @@ stm32h743nucleo STM32 H743 Nucleo stm32h7 https://www.st stm32h745disco STM32 H745 Discovery stm32h7 https://www.st.com/en/evaluation-tools/stm32h745i-disco.html stm32h750_weact STM32 H750 WeAct stm32h7 https://www.adafruit.com/product/5032 stm32h750bdk STM32 H750b Discovery Kit stm32h7 https://www.st.com/en/evaluation-tools/stm32h750b-dk.html +stm32h7s3nucleo STM32 H7S3 Nucleo stm32h7rs https://www.st.com/en/evaluation-tools/nucleo-h7s3l8.html waveshare_openh743i Waveshare Open H743i stm32h7 https://www.waveshare.com/openh743i-c-standard.htm stm32l052dap52 STM32 L052 DAP stm32l0 n/a stm32l0538disco STM32 L0538 Discovery stm32l0 https://www.st.com/en/evaluation-tools/32l0538discovery.html diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index e720cd747..4613343d4 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -89,6 +89,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32H7 #include "stm32h7xx.h" +#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS + #include "stm32h7rsxx.h" + #elif CFG_TUSB_MCU == OPT_MCU_STM32L0 #include "stm32l0xx.h" diff --git a/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..9fd3f6c50 --- /dev/null +++ b/hw/bsp/stm32h7rs/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32h7rsxx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 4 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<port, pindef->pin_init.Pin, GPIO_PIN_SET); + + __HAL_RCC_I2C3_CLK_ENABLE(); + __HAL_RCC_I2C3_FORCE_RESET(); + __HAL_RCC_I2C3_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { + return HAL_ERROR; + } + + NVIC_SetPriority(EXTI8_IRQn, 12); + NVIC_EnableIRQ(EXTI8_IRQn); + + return 0; +} + +int32_t board_tcpp0203_deinit(void) { + return 0; +} + +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +static inline void board_init2(void) { + TCPP0203_IO_t io_ctx; + + io_ctx.Address = TCPP0203_I2C_ADDRESS_X68; + io_ctx.Init = board_tcpp0203_init; + io_ctx.DeInit = board_tcpp0203_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + + TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); +} + +void board_vbus_set(uint8_t rhport, bool state) { + (void) state; + if (rhport == 1) { + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +void EXTI8_IRQHandler(void) { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + if (tcpp0203_obj.IsInitialized) { + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk new file mode 100644 index 000000000..164452fb2 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/board.mk @@ -0,0 +1,15 @@ +MCU_VARIANT = stm32h7s3xx +CFLAGS += -DSTM32H7S3xx + +# For flash-jlink target +JLINK_DEVICE = stm32h7s3xx + +# flash target using on-board stlink +flash: flash-stlink + +SRC_C += \ + $(BOARD_PATH)/tcpp0203/tcpp0203.c \ + $(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \ + +INC += \ + $(BOARD_PATH)/tcpp0203 \ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt new file mode 100644 index 000000000..3edc4d146 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html new file mode 100644 index 000000000..6bbba86a4 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/Release_Notes.html @@ -0,0 +1,205 @@ + + + + + + + Release Notes for TCPP0203 Component Driver + + + + + + +
+
+
+

Release Notes for TCPP0203 Component Driver

+

Copyright © 2020 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component

+
+
+

Update History

+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + +
Headline
MISRA Rule-81.13 correction on TCPP0203 component driver files
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MISRA corrections on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.8.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
License updates
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.6.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
CodeSpell correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MCUAstyle correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • First official release of TCPP0203 Type-C port Protection Component drivers
    • +
+
+
+
+
+
+

For complete documentation on STM32,visit: [www.st.com/stm32]

+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png new file mode 100644 index 000000000..06713eec4 Binary files /dev/null and b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/favicon.png differ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css new file mode 100644 index 000000000..3d9e81ad3 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/mini-st_2020.css @@ -0,0 +1,1703 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-location { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M21 10c0 7-9 13-9 13s-9-6-9-13a9 9 0 0 1 18 0z'%3E%3C/path%3E%3Ccircle cx='12' cy='10' r='3'%3E%3C/circle%3E%3C/svg%3E"); } +span.icon-phone { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M22 16.92v3a2 2 0 0 1-2.18 2 19.79 19.79 0 0 1-8.63-3.07 19.5 19.5 0 0 1-6-6 19.79 19.79 0 0 1-3.07-8.67A2 2 0 0 1 4.11 2h3a2 2 0 0 1 2 1.72 12.84 12.84 0 0 0 .7 2.81 2 2 0 0 1-.45 2.11L8.09 9.91a16 16 0 0 0 6 6l1.27-1.27a2 2 0 0 1 2.11-.45 12.84 12.84 0 0 0 2.81.7A2 2 0 0 1 22 16.92z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-rss { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 11a9 9 0 0 1 9 9'%3E%3C/path%3E%3Cpath d='M4 4a16 16 0 0 1 16 16'%3E%3C/path%3E%3Ccircle cx='5' cy='19' r='1'%3E%3C/circle%3E%3C/svg%3E"); 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+ overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} \ No newline at end of file diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png new file mode 100644 index 000000000..d6cebb5ac Binary files /dev/null and b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/_htmresc/st_logo_2020.png differ diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c new file mode 100644 index 000000000..abc86bd68 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.c @@ -0,0 +1,888 @@ +/** + ****************************************************************************** + * @file tcpp0203.c + * @author MCD Application Team + * @brief This file provides the TCPP02/03 Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203.h" + +#if defined(_TRACE) +#include "usbpd_core.h" +#include "usbpd_trace.h" +#include "string.h" +#include "stdio.h" +#endif /* _TRACE */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection. + * @{ + */ + +/** @defgroup TCPP0203_Private_Constants Private Constants + * @{ + */ + +/* Compilation option in order to enable/disable a concistency check performed + after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0 + is properly reflected into reg1 register content. + To enable register consistency check, please uncomment below definition. + To disable it, comment below line */ +/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** @defgroup TCPP0203_Private_Types Private Types + * @{ + */ +/* TCPP02/03 Type-C port protection driver structure initialization */ +TCPP0203_Drv_t TCPP0203_Driver = +{ + TCPP0203_Init, + TCPP0203_DeInit, + TCPP0203_Reset, + TCPP0203_SetVConnSwitch, + TCPP0203_SetGateDriverProvider, + TCPP0203_SetGateDriverConsumer, + TCPP0203_SetPowerMode, + TCPP0203_SetVBusDischarge, + TCPP0203_SetVConnDischarge, + TCPP0203_GetVConnSwitchAck, + TCPP0203_GetGateDriverProviderAck, + TCPP0203_GetGateDriverConsumerAck, + TCPP0203_GetPowerModeAck, + TCPP0203_GetVBusDischargeAck, + TCPP0203_GetVConnDischargeAck, + TCPP0203_GetOCPVConnFlag, + TCPP0203_GetOCPVBusFlag, + TCPP0203_GetOVPVBusFlag, + TCPP0203_GetOVPCCFlag, + TCPP0203_GetOTPFlag, + TCPP0203_GetVBusOkFlag, + TCPP0203_ReadTCPPType, + TCPP0203_ReadVCONNPower, + TCPP0203_WriteCtrlRegister, + TCPP0203_ReadAckRegister, + TCPP0203_ReadFlagRegister, +}; + +/** + * @} + */ + +/** @defgroup TCPP0203_Private_Variables Private Variables + * @{ + */ +static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static uint8_t Reg0_Expected_Value = 0x00; +static uint8_t Reg1_LastRead_Value = 0x00; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes + * @{ + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); + +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/** + * @brief Register Bus Io to component + * @param Component object pointer + * @retval Status of execution + */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO) +{ + int32_t ret; + + if (pObj == NULL) + { + ret = TCPP0203_ERROR; + } + else + { + pObj->IO.Init = pIO->Init; + pObj->IO.DeInit = pIO->DeInit; + pObj->IO.Address = pIO->Address; + pObj->IO.WriteReg = pIO->WriteReg; + pObj->IO.ReadReg = pIO->ReadReg; + pObj->IO.GetTick = pIO->GetTick; + + pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap; + pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap; + pObj->Ctx.handle = pObj; + + if (pObj->IO.Init != NULL) + { + ret = pObj->IO.Init(); + } + else + { + ret = TCPP0203_ERROR; + } + } + + return ret; +} + +/** + * @brief Initializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj) +{ + int32_t ret = 0; + uint8_t tmp; + + if (pObj->IsInitialized == 0U) + { + /* Read TCPP Device type */ + ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1); + + if (ret == TCPP0203_OK) + { + TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + } + else + { + TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02; + } + pObj->IsInitialized = 1U; + } + + if (ret != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + + return ret; +} + +/** + * @brief Deinitializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj) +{ + if (pObj->IsInitialized == 1U) + { + /* De-Initialize IO BUS layer */ + pObj->IO.DeInit(); + + pObj->IsInitialized = 0U; + } + + return TCPP0203_OK; +} + +/** + * @brief Resets TCPP0203 register (Reg0) + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj) +{ + int32_t ret = TCPP0203_OK; + uint8_t tmp = TCPP0203_REG0_RST_VALUE; + + /* Write reset values in Reg0 register */ + if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE; + Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Configure TCPP0203 VConn Switch + * @param pObj Pointer to component object + * @param VConnSwitch VConn Switch requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 + * @retval Component status + */ +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn switch setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param GateDriverProvider GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open + * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider) +{ + int32_t ret = TCPP0203_OK; + + if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN) + && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDP Switch Load setting in Writing register Reg0 */ + if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED) + { + /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Consumer path + * @param pObj Pointer to component object + * @param GateDriverConsumer GDC switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open + * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer) +{ + int32_t ret = TCPP0203_OK; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN) + && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDC Switch Load setting in Writing register Reg0 */ + if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED) + { + /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Power Mode + * @param pObj Pointer to component object + * @param PowerMode Power mode requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate + * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power + * @arg TCPP0203_POWER_MODE_NORMAL Normal + * @retval Component status + */ +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode) +{ + int32_t ret = TCPP0203_OK; + + if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE) + && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER) + && (PowerMode != TCPP0203_POWER_MODE_NORMAL)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update Power Mode setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VBusDischarge VBUS Discharge requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off + * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF) + && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VBUS Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VConnDischarge GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off + * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF) + && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Get VConn switch Ack value + * @param pObj Pointer to component object + * @param pVConnSwitchAck Pointer on VConn switch Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Provider Ack value + * @param pObj Pointer to component object + * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Consumer Ack value + * @param pObj Pointer to component object + * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck) +{ + int32_t ret; + uint8_t tmp; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Power Mode Ack value + * @param pObj Pointer to component object + * @param pPowerModeAck Pointer on Power Mode Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack + * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack + * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack + * @retval Component status + */ +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VBUS Discharge Ack value + * @param pObj Pointer to component object + * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack + * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VConn Discharge Ack value + * @param pObj Pointer to component object + * @param pVConnDischargeAck Pointer on VConn Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack + * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get OCP VConn Flag value + * @param pObj Pointer to component object + * @param pOCPVConnFlag Pointer on OCP VConn Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set + * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK); + + return ret; +} + +/** + * @brief Get OCP VBUS Flag value + * @param pObj Pointer to component object + * @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set + * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP VBUS Flag value + * @param pObj Pointer to component object + * @param pOVPVBusFlag Pointer on OVP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set + * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP CC Flag value + * @param pObj Pointer to component object + * @param pOVPCCFlag Pointer on OVP CC Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set + * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK); + + return ret; +} + +/** + * @brief Get Over Temperature Flag value + * @param pObj Pointer to component object + * @param pOTPFlag Pointer on Over Temperature Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set + * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set + * @retval Component status + */ +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK); + + return ret; +} + +/** + * @brief Get VBUS OK Flag value + * @param pObj Pointer to component object + * @param pVBusOkFlag Pointer on VBUS OK Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set + * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set + * @retval Component status + */ +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK); + + return ret; +} + +/** + * @brief Get TCPP0203 Device Type value + * @param pObj Pointer to component object + * @param pTCPPType Pointer on TCPP0203 Device Type value + * This output parameter can be one of the following values: + * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type + * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type + * @retval Component status + */ +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + + return ret; +} + +/** + * @brief Get VConn Power value + * @param pObj Pointer to component object + * @param pVCONNPower Pointer on VConn Power value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set + * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK); + + return ret; +} + +/** + * @brief Set complete Ctrl register value (Reg 0) + * @param pObj Pointer to component object + * @param pCtrlRegister Pointer on Ctrl register value + * @retval Component status + */ +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister) +{ + int32_t ret; + + /* Update value in writing register (reg0) */ + ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pCtrlRegister; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Get complete Ack register value + * @param pObj Pointer to component object + * @param pAckRegister Pointer on Ack register value + * @retval Component status + */ +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1); + + return ret; +} + +/** + * @brief Get complete Flag register value + * @param pObj Pointer to component object + * @param pFlagRegister Pointer on Flag register value + * @retval Component status + */ +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1); + + return ret; +} + +/******************** Static functions ****************************************/ +/** + * @brief Wrap TCPP0203 read function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to read + * @param pData Buffer where Target register value should be stored + * @param Length buffer size to be read + * @retval error status + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + + return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief Wrap TCPP0203 write function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pData; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief TCPP0203 register update function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask) +{ + int32_t ret; + uint8_t tmp; + + /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + + /* Update only the area dedicated to Mask */ + tmp &= ~(Mask); + tmp |= (Value & Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = tmp; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + /* Update value in writing register (reg0) */ + ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +/** + * @brief TCPP0203 register control function between Reg0 and Reg1 value + * @param handle Component object handle + * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions) + * @retval error status + */ +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue) +{ + int32_t ret; + + /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1); + +#ifdef _TRACE + char str[12]; + sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); + sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); +#endif /* _TRACE */ + + /* Control if Reg1 value is same as Reg0 expected one */ + if (Reg1_LastRead_Value != Reg0ExpectedValue) + { + while (1); + } + + return ret; +} +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h new file mode 100644 index 000000000..f2933f758 --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203.h @@ -0,0 +1,355 @@ +/** + ****************************************************************************** + * @file tcpp0203.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * tcpp0203.c driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_H +#define TCPP0203_H + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types + * @{ + */ +typedef int32_t (*TCPP0203_Init_Func)(void); +typedef int32_t (*TCPP0203_DeInit_Func)(void); +typedef int32_t (*TCPP0203_GetTick_Func)(void); +typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); +typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); + +typedef struct +{ + TCPP0203_Init_Func Init; + TCPP0203_DeInit_Func DeInit; + uint16_t Address; + TCPP0203_WriteReg_Func WriteReg; + TCPP0203_ReadReg_Func ReadReg; + TCPP0203_GetTick_Func GetTick; +} TCPP0203_IO_t; + + +typedef struct +{ + TCPP0203_IO_t IO; + TCPP0203_ctx_t Ctx; + uint8_t IsInitialized; +} TCPP0203_Object_t; + +typedef struct +{ + int32_t (*Init)(TCPP0203_Object_t *); + int32_t (*DeInit)(TCPP0203_Object_t *); + int32_t (*Reset)(TCPP0203_Object_t *); + int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *); + int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *); +} TCPP0203_Drv_t; + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/** + * @brief TCPP0203 Driver Response codes + */ +#define TCPP0203_OK (0) +#define TCPP0203_ERROR (-1) + +/** + * @brief TCPP0203 possible I2C Addresses + */ +#define TCPP0203_I2C_ADDRESS_X68 (0x68U) +#define TCPP0203_I2C_ADDRESS_X6A (0x6AU) + +/** + * @brief TCPP0203 Reg0 Reset Value + */ +#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED + +/** + * @brief TCPP0203 VCONN Switch + */ +#define TCPP0203_VCONN_SWITCH_POS (0U) +#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS) + +/** + * @brief TCPP0203 Gate Driver Provider values + */ +#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer values + */ +#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK) + +/** + * @brief TCPP0203 Power Mode values + */ +#define TCPP0203_POWER_MODE_POS (4U) +#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS) + +/** + * @brief TCPP0203 VBUS Discharge management + */ +#define TCPP0203_VBUS_DISCHARGE_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS) +#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VConn Discharge management + */ +#define TCPP0203_VCONN_DISCHARGE_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS) +#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VCONN Switch Acknowledge + */ +#define TCPP0203_VCONN_SWITCH_ACK_POS (0U) +#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS) + +/** + * @brief TCPP0203 Gate Driver Provider Acknowledge + */ +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer Acknowledge + */ +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Power Mode Acknowledge + */ +#define TCPP0203_POWER_MODE_ACK_POS (4U) +#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS) + +/** + * @brief TCPP0203 VBUS Discharge Acknowledge + */ +#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS) +#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 VConn Discharge Acknowledge + */ +#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS) +#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 OCP Vconn Flag management + */ +#define TCPP0203_FLAG_OCP_VCONN_POS (0U) +#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS) +#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK) +#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U) + +/** + * @brief TCPP0203 OCP VBUS Flag management + */ +#define TCPP0203_FLAG_OCP_VBUS_POS (1U) +#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS) +#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK) +#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP VBUS Flag management + */ +#define TCPP0203_FLAG_OVP_VBUS_POS (2U) +#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS) +#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK) +#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP CC Flag management + */ +#define TCPP0203_FLAG_OVP_CC_POS (3U) +#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS) +#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK) +#define TCPP0203_FLAG_OVP_CC_RESET (0x00U) + +/** + * @brief TCPP0203 OTP Flag management + */ +#define TCPP0203_FLAG_OTP_POS (4U) +#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS) +#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK) +#define TCPP0203_FLAG_OTP_RESET (0x00U) + +/** + * @brief TCPP0203 VBUS OK Flag management + */ +#define TCPP0203_FLAG_VBUS_OK_POS (5U) +#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS) +#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK) +#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U) + +/** + * @brief TCPP0203 VConn Power + */ +#define TCPP0203_FLAG_VCONN_PWR_POS (6U) +#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS) +#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK) +#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U) + +/** + * @brief TCPP0203 Device Type + */ +#define TCPP0203_DEVICE_TYPE_POS (7U) +#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS) +#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK) +#define TCPP0203_DEVICE_TYPE_03 (0x00U) + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/*------------------------------------------------------------------------------ + TCPP02/03 Type-C port protection functions +------------------------------------------------------------------------------*/ +/* High Layer codec functions */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO); +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj); +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj); +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj); +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch); +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider); +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer); +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode); +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge); +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge); +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck); +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck); +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck); +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck); +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck); +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck); +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag); +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag); +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag); +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag); +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag); +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag); +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType); +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower); +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister); +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister); +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister); + +/** + * @} + */ + +/* TCPP02/03 Type-C port protection driver structure */ +extern TCPP0203_Drv_t TCPP0203_Driver; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TCPP0203_H */ + + diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c new file mode 100644 index 000000000..5194172db --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.c @@ -0,0 +1,75 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.c + * @author MCD Application Team + * @brief This file provides unitary register function to control the TCPP02-03 + * Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection codec. + * @{ + */ + +/************** Generic Function *******************/ +/******************************************************************************* + * Function Name : tcpp0203_read_reg + * Description : Generic Reading function. It must be fulfilled with either + * I2C or SPI reading functions + * Input : Register Address, length of buffer + * Output : data Read + *******************************************************************************/ +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->ReadReg(ctx->handle, reg, data, length); +} + +/******************************************************************************* + * Function Name : tcpp0203_write_reg + * Description : Generic Writing function. It must be fulfilled with either + * I2C or SPI writing function + * Input : Register Address, data to be written, length of buffer + * Output : None + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->WriteReg(ctx->handle, reg, data, length); +} + +/******************************************************************************/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h new file mode 100644 index 000000000..29edc62db --- /dev/null +++ b/hw/bsp/stm32h7rs/boards/stm32h7s3nucleo/tcpp0203/tcpp0203_reg.h @@ -0,0 +1,100 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.h + * @author MCD Application Team + * @brief Header of tcpp0203_reg.c + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_REG_H +#define TCPP0203_REG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/******************************************************************************/ +/****************************** REGISTER MAPPING ******************************/ +/******************************************************************************/ +#define TCPP0203_WRITE_REG 0x00U +#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG +#define TCPP0203_READ_REG1 0x01U +#define TCPP0203_ACK_REG TCPP0203_READ_REG1 +#define TCPP0203_READ_REG2 0x02U +#define TCPP0203_FLAG_REG TCPP0203_READ_REG2 + +/** + * @} + */ + +/************** Generic Function *******************/ + +typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t); +typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t); + +typedef struct +{ + TCPP0203_Write_Func WriteReg; + TCPP0203_Read_Func ReadReg; + void *handle; +} TCPP0203_ctx_t; + +/******************************************************************************* + * Register : Generic - All + * Address : Generic - All + * Bit Group Name: None + * Permission : W + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* TCPP0203_REG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/hw/bsp/stm32h7rs/family.c b/hw/bsp/stm32h7rs/family.c new file mode 100644 index 000000000..1fbbd3cdb --- /dev/null +++ b/hw/bsp/stm32h7rs/family.c @@ -0,0 +1,313 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 + * William D. Jones (thor0505@comcast.net), + * Ha Thach (tinyusb.org) + * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: STMicroelectronics +*/ + +#include "stm32h7rsxx_hal.h" +#include "bsp/board_api.h" + +TU_ATTR_UNUSED static void Error_Handler(void) { } + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + +#include "board.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// Despite being call USB2_OTG_FS on some MCUs +// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port +void OTG_FS_IRQHandler(void) { + tusb_int_handler(0, true); +} + +// Despite being call USB1_OTG_HS on some MCUs +// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port +void OTG_HS_IRQHandler(void) { + tusb_int_handler(1, true); +} + +#ifdef TRACE_ETM +void trace_etm_init(void) { + // H7 trace pin is PE2 to PE6 + GPIO_InitTypeDef gpio_init; + gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + gpio_init.Alternate = GPIO_AF0_TRACE; + HAL_GPIO_Init(GPIOE, &gpio_init); + + // Enable trace clk, also in D1 and D3 domain + DBGMCU->CR |= DBGMCU_CR_DBG_TRACECKEN | DBGMCU_CR_DBG_CKD1EN | DBGMCU_CR_DBG_CKD3EN; +} +#else + #define trace_etm_init() +#endif + +void board_init(void) { + HAL_Init(); + + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + // Implemented in board.h + SystemClock_Config(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOM_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + + trace_etm_init(); + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + #ifdef USB_OTG_FS_PERIPH_BASE + NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + #endif + + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + + +#ifdef UART_DEV + UART_CLK_EN(); + HAL_UART_Init(&UartHandle); +#endif + + //------------- USB FS -------------// +#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0) + // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port + + HAL_PWREx_EnableUSBVoltageDetector(); + HAL_PWREx_EnableUSBReg(); + + __HAL_RCC_USB2_OTG_FS_CLK_ENABLE(); + + // PM14 VUSB, PM10 ID, PM11 DM, PM12 DP + // Configure DM DP Pins + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // This for ID line debug + GPIO_InitStruct.Pin = GPIO_PIN_10; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + +#if OTG_FS_VBUS_SENSE + // Configure VBUS Pin + GPIO_InitStruct.Pin = GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // Enable VBUS sense (B device) via pin PM14 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +#else + // Disable VBUS sense (B device) + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; +#endif // vbus sense +#endif + + //------------- USB HS -------------// +#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1) + + // Enable USB HS & ULPI Clocks + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USBPHYC_CLK_ENABLE(); + + // Enable USB power + HAL_PWREx_EnableUSBVoltageDetector(); + HAL_PWREx_EnableUSBHSregulator(); + +#if OTG_HS_VBUS_SENSE + // Configure VBUS Pin + GPIO_InitStruct.Pin = GPIO_PIN_9; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; + HAL_GPIO_Init(GPIOM, &GPIO_InitStruct); + + // Enable VBUS sense (B device) via pin PM9 + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBDEN; +#else + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + +#if CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1 + // B-peripheral session valid override enable + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; +#else + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; +#endif + +#endif +#endif + + board_init2(); + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif +} + +uint32_t board_button_read(void) { +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) + buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; + return -1; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake new file mode 100644 index 000000000..add0dc43d --- /dev/null +++ b/hw/bsp/stm32h7rs/family.cmake @@ -0,0 +1,150 @@ +include_guard() + +set(ST_FAMILY h7rs) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32H7 CACHE INTERNAL "") + +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + if(NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld) + endif() + set(LD_FILE_Clang ${LD_FILE_GNU}) + if(NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + endif() + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32H7RS ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_stlink(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk new file mode 100644 index 000000000..e2d6d40e4 --- /dev/null +++ b/hw/bsp/stm32h7rs/family.mk @@ -0,0 +1,92 @@ +ST_FAMILY = h7rs +ST_PREFIX = stm32${ST_FAMILY}xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver + +UF2_FAMILY_ID = 0x6db66083 + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m7 + +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32H7RS \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += \ + -Wno-error=cast-align \ + -Wno-error=unused-parameter \ + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC = $(ST_CMSIS)/Source/Templates/gcc/linker/$(MCU_VARIANT)_flash.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h new file mode 100644 index 000000000..ea074f7d7 --- /dev/null +++ b/hw/bsp/stm32h7rs/stm32h7rsxx_hal_conf.h @@ -0,0 +1,501 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32h7rsxx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h7rsxx_hal_conf.h. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H7RSxx_HAL_CONF_H +#define STM32H7RSxx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CEC_MODULE_ENABLED */ +/* #define HAL_CORDIC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_DCMIPP_MODULE_ENABLED */ +/* #define HAL_DMA2D_MODULE_ENABLED */ +/* #define HAL_DTS_MODULE_ENABLED */ +/* #define HAL_ETH_MODULE_ENABLED */ +/* #define HAL_FDCAN_MODULE_ENABLED */ +/* #define HAL_GFXMMU_MODULE_ENABLED */ +/* #define HAL_GFXTIM_MODULE_ENABLED */ +/* #define HAL_GPU2D_MODULE_ENABLED */ +/* #define HAL_HASH_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_I3C_MODULE_ENABLED */ +/* #define HAL_ICACHE_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_JPEG_MODULE_ENABLED */ +/* #define HAL_LPTIM_MODULE_ENABLED */ +/* #define HAL_LTDC_MODULE_ENABLED */ +/* #define HAL_MCE_MODULE_ENABLED */ +/* #define HAL_MDF_MODULE_ENABLED */ +/* #define HAL_MMC_MODULE_ENABLED */ +/* #define HAL_NAND_MODULE_ENABLED */ +/* #define HAL_NOR_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_PKA_MODULE_ENABLED */ +/* #define HAL_PSSI_MODULE_ENABLED */ +/* #define HAL_RAMECC_MODULE_ENABLED */ +/* #define HAL_RCC_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SAI_MODULE_ENABLED */ +/* #define HAL_SD_MODULE_ENABLED */ +/* #define HAL_SDRAM_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPDIFRX_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_SRAM_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_XSPI_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up (in ms) */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low-power oscillator (CSI) default value. + * This value is the default CSI range value after Reset. + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB OTG FS and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ + #if !defined (HSI48_VALUE) + #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB OTG FS/RNG in Hz. + The real value my vary depending on manufacturing process variations. */ + #endif /* HSI48_VALUE */ + +/** +* @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz. + Value of the Internal Low Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature.*/ +#endif /* LSI_VALUE */ + +/** +* @brief External Low Speed oscillator (LSE) value. +*/ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up (in ms) */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for digital audio interfaces: SPI/I2S, SAI and ADF + * This value is used by the RCC HAL module to provide the digital audio interfaces + * frequency. This clock source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 48000UL /*!< Value of the external clock source in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY (15UL)/*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** +* @brief Uncomment the line below to expanse the "assert_param" macro in the +* HAL drivers code +*/ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** +* @brief Set below the peripheral configuration to "1U" to add the support +* of HAL callback registration/unregistration feature for the HAL +* driver(s). This allows user application to provide specific callback +* functions thanks to HAL_PPP_RegisterCallback() rather than overwriting +* the default weak callback functions (see each stm32h7rsxx_hal_ppp.h file +* for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef +* for each PPP peripheral). +*/ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32h7rsxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32h7rsxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED + #include "stm32h7rsxx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32h7rsxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32h7rsxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED + #include "stm32h7rsxx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED + #include "stm32h7rsxx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32h7rsxx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32h7rsxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED + #include "stm32h7rsxx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED + #include "stm32h7rsxx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32h7rsxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32h7rsxx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED + #include "stm32h7rsxx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED + #include "stm32h7rsxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32h7rsxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32h7rsxx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED + #include "stm32h7rsxx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED + #include "stm32h7rsxx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32h7rsxx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32h7rsxx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32h7rsxx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32h7rsxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED + #include "stm32h7rsxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED + #include "stm32h7rsxx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32h7rsxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMECC_MODULE_ENABLED + #include "stm32h7rsxx_hal_ramecc.h" +#endif /* HAL_RAMECC_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32h7rsxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32h7rsxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32h7rsxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32h7rsxx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32h7rsxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32h7rsxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32h7rsxx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32h7rsxx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32h7rsxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32h7rsxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32h7rsxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32h7rsxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED + #include "stm32h7rsxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t *file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H7RSxx_HAL_CONF_H */ + diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index dec021f59..76bd251c7 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | XMC4500 | GD32VF103 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | ST H7S3 HS | XMC4500 | GD32VF103 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:-------------|:------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | hub | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 25edcf22d..6ab4e0641 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -22,6 +22,7 @@ dwc2_reg_value = { 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'ST H7S3 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], } -- cgit v1.3.1 From d1ee2bf18fced22364537949c4a18e1c15c99b6d Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Wed, 29 Jan 2025 15:14:25 +0100 Subject: Fix Auto speed display. Signed-off-by: HiFiPhile --- src/device/usbd.c | 23 ++++++++++++++++++++--- src/host/usbh.c | 23 ++++++++++++++++++++--- 2 files changed, 40 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 2a6081673..8435b5c02 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -464,13 +464,30 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; // skip if already initialized } TU_ASSERT(rh_init); - - TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport, - rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full"); +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL + char const* speed_str = 0; + switch (rh_init->speed) { + case TUSB_SPEED_HIGH: + speed_str = "High"; + break; + case TUSB_SPEED_FULL: + speed_str = "Full"; + break; + case TUSB_SPEED_LOW: + speed_str = "Low"; + break; + case TUSB_SPEED_AUTO: + speed_str = "Auto"; + break; + default: + break; + } + TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport, speed_str); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_edpt_stream_t)); +#endif tu_varclr(&_usbd_dev); _usbd_queued_setup = 0; diff --git a/src/host/usbh.c b/src/host/usbh.c index a2994cde7..f022d93f1 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -365,9 +365,26 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { if (tuh_rhport_is_active(rhport)) { return true; // skip if already initialized } - - TU_LOG_USBH("USBH init on controller %u, speed = %s\r\n", rhport, - rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full"); +#if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL + char const* speed_str = 0; + switch (rh_init->speed) { + case TUSB_SPEED_HIGH: + speed_str = "High"; + break; + case TUSB_SPEED_FULL: + speed_str = "Full"; + break; + case TUSB_SPEED_LOW: + speed_str = "Low"; + break; + case TUSB_SPEED_AUTO: + speed_str = "Auto"; + break; + default: + break; + } + TU_LOG_USBH("USBH init on controller %u, speed = %s\r\n", rhport, speed_str); +#endif // Init host stack if not already if (!tuh_inited()) { -- cgit v1.3.1 From cc626f35d212aef86b0aa7275eea016ae69b5de4 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Wed, 29 Jan 2025 15:16:02 +0100 Subject: msc_device: add async IO support. Signed-off-by: HiFiPhile --- src/class/msc/msc_device.c | 180 ++++++++++++++++++++++++++++++++------------- src/class/msc/msc_device.h | 16 ++++ 2 files changed, 145 insertions(+), 51 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index dd66bfb6f..c7c926f4e 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -52,10 +52,18 @@ enum { MSC_STAGE_NEED_RESET, }; +enum { + MSC_NEXT_OP_NONE = 0, + MSC_NEXT_OP_READ10, + MSC_NEXT_OP_WRITE10, + MSC_NEXT_OP_STATUS +}; + typedef struct { TU_ATTR_ALIGNED(4) msc_cbw_t cbw; TU_ATTR_ALIGNED(4) msc_csw_t csw; + uint8_t rhport; uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; @@ -70,6 +78,10 @@ typedef struct { uint8_t sense_key; uint8_t add_sense_code; uint8_t add_sense_qualifier; +#if CFG_TUD_MSC_ASYNC_IO + uint8_t next_op; + uint32_t xferred_bytes; +#endif }mscd_interface_t; static mscd_interface_t _mscd_itf; @@ -82,31 +94,39 @@ CFG_TUD_MEM_SECTION static struct { // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize); -static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); - -static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); -static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); +static void proc_read10_cmd(mscd_interface_t* p_msc); +static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes); +static void proc_write10_cmd(mscd_interface_t* p_msc); +static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_bytes); +static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes); +static bool proc_stage_status(mscd_interface_t* p_msc); +#if CFG_TUD_MSC_ASYNC_IO +static void tud_msc_async_io_done_cb(void* bytes_processed); +#endif TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); } -static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { +static inline bool send_csw(mscd_interface_t* p_msc) { // Data residue is always = host expect - actual transferred + uint8_t rhport = p_msc->rhport; p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; p_msc->stage = MSC_STAGE_STATUS_SENT; memcpy(_mscd_epbuf.buf, &p_msc->csw, sizeof(msc_csw_t)); return usbd_edpt_xfer(rhport, p_msc->ep_in , _mscd_epbuf.buf, sizeof(msc_csw_t)); } -static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) { +static inline bool prepare_cbw(mscd_interface_t* p_msc) { + uint8_t rhport = p_msc->rhport; p_msc->stage = MSC_STAGE_CMD; return usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_epbuf.buf, sizeof(msc_cbw_t)); } -static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) { +static void fail_scsi_op(mscd_interface_t* p_msc, uint8_t status) { msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; + uint8_t rhport = p_msc->rhport; p_csw->status = status; p_csw->data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; @@ -177,6 +197,32 @@ static uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { return status; } +static bool proc_stage_status(mscd_interface_t* p_msc) { + uint8_t rhport = p_msc->rhport; + msc_cbw_t const* p_cbw = &p_msc->cbw; + // skip status if epin is currently stalled, will do it when received Clear Stall request + if (!usbd_edpt_stalled(rhport, p_msc->ep_in)) { + if ((p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir)) { + // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status + // TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); + usbd_edpt_stall(rhport, p_msc->ep_in); + } else { + TU_ASSERT(send_csw(p_msc)); + } + } + + #if TU_CHECK_MCU(OPT_MCU_CXD56) + // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. + // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and + // hope everything will work + if ( usbd_edpt_stalled(rhport, p_msc->ep_in) ) { + usbd_edpt_clear_stall(rhport, p_msc->ep_in); + send_csw(p_msc); + } + #endif + return true; +} + //--------------------------------------------------------------------+ // Debug //--------------------------------------------------------------------+ @@ -219,6 +265,32 @@ static inline void set_sense_medium_not_present(uint8_t lun) { tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00); } +#if CFG_TUD_MSC_ASYNC_IO +void tud_msc_async_io_done(int32_t bytes_processed) { + // Precheck to avoid queueing multiple RW done callback + TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); + // Call usbd_edpt_xfer() in tud_task() to avoid racing condition + usbd_defer_func(tud_msc_async_io_done_cb, (void*) bytes_processed, false); +} + +static void tud_msc_async_io_done_cb(void* bytes_processed) { + TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); + uint8_t next_op = _mscd_itf.next_op; + _mscd_itf.next_op = MSC_NEXT_OP_NONE; + int32_t nbytes = (int32_t)bytes_processed; + // READ10 + if (next_op == MSC_NEXT_OP_READ10) { + proc_read10_next(&_mscd_itf, nbytes); + } else if (next_op == MSC_NEXT_OP_WRITE10) { + proc_write10_next(&_mscd_itf, _mscd_itf.xferred_bytes, nbytes); + // Need to manually invoke CSW transfer + if (_mscd_itf.stage == MSC_STAGE_STATUS) { + proc_stage_status(&_mscd_itf); + } + } +} +#endif + //--------------------------------------------------------------------+ // USBD Driver API //--------------------------------------------------------------------+ @@ -245,12 +317,13 @@ uint16_t mscd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 mscd_interface_t * p_msc = &_mscd_itf; p_msc->itf_num = itf_desc->bInterfaceNumber; + p_msc->rhport = rhport; // Open endpoint pair TU_ASSERT(usbd_open_edpt_pair(rhport, tu_desc_next(itf_desc), 2, TUSB_XFER_BULK, &p_msc->ep_out, &p_msc->ep_in), 0); // Prepare for Command Block Wrapper - TU_ASSERT(prepare_cbw(rhport, p_msc), drv_len); + TU_ASSERT(prepare_cbw(p_msc), drv_len); return drv_len; } @@ -289,14 +362,14 @@ bool mscd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t if (ep_addr == p_msc->ep_in) { if (p_msc->stage == MSC_STAGE_STATUS) { // resume sending SCSI status if we are in this stage previously before stalled - TU_ASSERT(send_csw(rhport, p_msc)); + TU_ASSERT(send_csw(p_msc)); } } else if (ep_addr == p_msc->ep_out) { if (p_msc->stage == MSC_STAGE_CMD) { // part of reset recovery (probably due to invalid CBW) -> prepare for new command // Note: skip if already queued previously if (usbd_edpt_ready(rhport, p_msc->ep_out)) { - TU_ASSERT(prepare_cbw(rhport, p_msc)); + TU_ASSERT(prepare_cbw(p_msc)); } } } @@ -344,7 +417,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t msc_csw_t * p_csw = &p_msc->csw; switch (p_msc->stage) { - case MSC_STAGE_CMD: + case MSC_STAGE_CMD: { //------------- new CBW received -------------// // Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it if (ep_addr != p_msc->ep_out) { @@ -382,12 +455,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t uint8_t const status = rdwr10_validate_cmd(p_cbw); if (status != MSC_CSW_STATUS_PASSED) { - fail_scsi_op(rhport, p_msc, status); + fail_scsi_op(p_msc, status); } else if (p_cbw->total_bytes) { if (SCSI_CMD_READ_10 == p_cbw->command[0]) { - proc_read10_cmd(rhport, p_msc); + proc_read10_cmd(p_msc); } else { - proc_write10_cmd(rhport, p_msc); + proc_write10_cmd(p_msc); } } else { // no data transfer, only exist in complaint test suite @@ -400,7 +473,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ((p_cbw->total_bytes > 0) && !is_data_in(p_cbw->dir)) { if (p_cbw->total_bytes > CFG_TUD_MSC_EP_BUFSIZE) { TU_LOG_DRV(" SCSI reject non READ10/WRITE10 with large data\r\n"); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else { // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first // but it is OK to just receive data then responded with failed status @@ -418,12 +491,12 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if (resplen < 0) { // unsupported command TU_LOG_DRV(" SCSI unsupported or failed command\r\n"); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else if (resplen == 0) { if (p_cbw->total_bytes) { // 6.7 The 13 Cases: case 4 (Hi > Dn) // TU_LOG(MSC_DEBUG, " SCSI case 4 (Hi > Dn): %lu\r\n", p_cbw->total_bytes); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else { // case 1 Hn = Dn: all good p_msc->stage = MSC_STAGE_STATUS; @@ -432,7 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if (p_cbw->total_bytes == 0) { // 6.7 The 13 Cases: case 2 (Hn < Di) // TU_LOG(MSC_DEBUG, " SCSI case 2 (Hn < Di): %lu\r\n", p_cbw->total_bytes); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else { // cannot return more than host expect p_msc->total_len = tu_min32((uint32_t)resplen, p_cbw->total_bytes); @@ -441,6 +514,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } } } + } break; case MSC_STAGE_DATA: @@ -454,10 +528,10 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // Data Stage is complete p_msc->stage = MSC_STAGE_STATUS; }else { - proc_read10_cmd(rhport, p_msc); + proc_read10_cmd(p_msc); } } else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) { - proc_write10_new_data(rhport, p_msc, xferred_bytes); + proc_write10_new_data(p_msc, xferred_bytes); } else { p_msc->xferred_len += xferred_bytes; @@ -468,7 +542,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t if ( cb_result < 0 ) { // unsupported command TU_LOG_DRV(" SCSI unsupported command\r\n"); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); }else { // TODO haven't implement this scenario any further yet } @@ -517,7 +591,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t break; } - TU_ASSERT(prepare_cbw(rhport, p_msc)); + TU_ASSERT(prepare_cbw(p_msc)); } else { // Any xfer ended here is consider unknown error, ignore it TU_LOG1(" Warning expect SCSI Status but received unknown data\r\n"); @@ -528,26 +602,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } if (p_msc->stage == MSC_STAGE_STATUS) { - // skip status if epin is currently stalled, will do it when received Clear Stall request - if (!usbd_edpt_stalled(rhport, p_msc->ep_in)) { - if ((p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir)) { - // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status - // TU_LOG(MSC_DEBUG, " SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); - usbd_edpt_stall(rhport, p_msc->ep_in); - } else { - TU_ASSERT(send_csw(rhport, p_msc)); - } - } - - #if TU_CHECK_MCU(OPT_MCU_CXD56) - // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. - // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and - // hope everything will work - if ( usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - usbd_edpt_clear_stall(rhport, p_msc->ep_in); - send_csw(rhport, p_msc); - } - #endif + TU_ASSERT(proc_stage_status(p_msc)); } return true; @@ -751,7 +806,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ return resplen; } -static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { +static void proc_read10_cmd(mscd_interface_t* p_msc) { msc_cbw_t const* p_cbw = &p_msc->cbw; // block size already verified not zero @@ -765,16 +820,27 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { // Application can consume smaller bytes uint32_t const offset = p_msc->xferred_len % block_sz; + +#if CFG_TUD_MSC_ASYNC_IO + p_msc->next_op = MSC_NEXT_OP_READ10; + tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes); +#else nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes); + proc_read10_next(p_msc, nbytes); +#endif +} +static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes) { + uint8_t rhport = p_msc->rhport; if (nbytes < 0) { // negative means error -> endpoint is stalled & status in CSW set to failed TU_LOG_DRV(" tud_msc_read10_cb() return -1\r\n"); // set sense + msc_cbw_t const* p_cbw = &p_msc->cbw; set_sense_medium_not_present(p_cbw->lun); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else if (nbytes == 0) { // zero means not ready -> simulate an transfer complete so that this driver callback will fired again dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false); @@ -783,7 +849,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { } } -static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { +static void proc_write10_cmd(mscd_interface_t* p_msc) { msc_cbw_t const* p_cbw = &p_msc->cbw; bool writable = true; @@ -795,19 +861,19 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) { // Not writable, complete this SCSI op with error // Sense = Write protected tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_DATA_PROTECT, 0x27, 0x00); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); return; } // remaining bytes capped at class buffer uint16_t nbytes = (uint16_t)tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes - p_msc->xferred_len); - // Write10 callback will be called later when usb transfer complete + uint8_t rhport = p_msc->rhport; TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_epbuf.buf, nbytes),); } // process new data arrived from WRITE10 -static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes) { +static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_bytes) { msc_cbw_t const* p_cbw = &p_msc->cbw; // block size already verified not zero @@ -818,8 +884,18 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); +#if CFG_TUD_MSC_ASYNC_IO + p_msc->next_op = MSC_NEXT_OP_WRITE10; + p_msc->xferred_bytes = xferred_bytes; + tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); +#else + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); + proc_write10_next(p_msc, xferred_bytes, nbytes); +#endif +} + +static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes) { if (nbytes < 0) { // negative means error -> failed this scsi op TU_LOG_DRV(" tud_msc_write10_cb() return -1\r\n"); @@ -828,9 +904,10 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 p_msc->xferred_len += xferred_bytes; // Set sense + msc_cbw_t const* p_cbw = &p_msc->cbw; set_sense_medium_not_present(p_cbw->lun); - fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else { // Application consume less than what we got (including zero) if ((uint32_t)nbytes < xferred_bytes) { @@ -841,6 +918,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 } // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter + uint8_t rhport = p_msc->rhport; dcd_event_xfer_complete(rhport, p_msc->ep_out, left_over, XFER_RESULT_SUCCESS, false); } else { // Application consume all bytes in our buffer @@ -851,7 +929,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 p_msc->stage = MSC_STAGE_STATUS; } else { // prepare to receive more data from host - proc_write10_cmd(rhport, p_msc); + proc_write10_cmd(p_msc); } } } diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 29acd280a..407fe241c 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -48,6 +48,11 @@ #error CFG_TUD_MSC_EP_BUFSIZE must be defined, value of a block size should work well, the more the better #endif +// Enable asynchronous read/write, once operation is finished tud_msc_async_io_done() must be called +#ifndef CFG_TUD_MSC_ASYNC_IO +#define CFG_TUD_MSC_ASYNC_IO 0 +#endif + TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); //--------------------------------------------------------------------+ @@ -73,6 +78,9 @@ bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, u // // - read < 0 : Indicate application error e.g invalid address. This request will be STALLed // and return failed status in command status wrapper phase. +// +// - In case of asynchronous IO enabled, application should passing reading parameters to background IO +// task and return immediately. Once reading is done, tud_msc_async_io_done() must be called. int32_t tud_msc_read10_cb (uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize); // Invoked when received SCSI WRITE10 command @@ -88,6 +96,8 @@ int32_t tud_msc_read10_cb (uint8_t lun, uint32_t lba, uint32_t offset, void* buf // - write < 0 : Indicate application error e.g invalid address. This request will be STALLed // and return failed status in command status wrapper phase. // +// - In case of asynchronous IO enabled, application should passing writing parameters to background IO +// task and return immediately. Once writing is done, tud_msc_async_io_done() must be called. // TODO change buffer to const uint8_t* int32_t tud_msc_write10_cb (uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize); @@ -121,6 +131,12 @@ void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_siz */ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize); +#if CFG_TUD_MSC_ASYNC_IO +// Called once asynchronous read/write operation is done +// bytes_processed has the same meaning of tud_msc_read10_cb() / +// tud_msc_write10_cb() return value +void tud_msc_async_io_done(int32_t bytes_processed); +#endif /*------------- Optional callbacks -------------*/ // Invoked when received GET_MAX_LUN request, required for multiple LUNs implementation -- cgit v1.3.1 From 84f8876c7c3639ef4ac707956831311791aefd76 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 31 Jan 2025 16:26:10 +0100 Subject: Use return code to choose async io. Signed-off-by: HiFiPhile --- src/class/msc/msc_device.c | 26 +++++++++------------ src/class/msc/msc_device.h | 56 +++++++++++++++++++++++++--------------------- 2 files changed, 41 insertions(+), 41 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index c7c926f4e..e3fe5a078 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -78,10 +78,10 @@ typedef struct { uint8_t sense_key; uint8_t add_sense_code; uint8_t add_sense_qualifier; -#if CFG_TUD_MSC_ASYNC_IO + + // Async IO uint8_t next_op; uint32_t xferred_bytes; -#endif }mscd_interface_t; static mscd_interface_t _mscd_itf; @@ -100,9 +100,7 @@ static void proc_write10_cmd(mscd_interface_t* p_msc); static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_bytes); static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes); static bool proc_stage_status(mscd_interface_t* p_msc); -#if CFG_TUD_MSC_ASYNC_IO static void tud_msc_async_io_done_cb(void* bytes_processed); -#endif TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); @@ -265,7 +263,6 @@ static inline void set_sense_medium_not_present(uint8_t lun) { tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00); } -#if CFG_TUD_MSC_ASYNC_IO void tud_msc_async_io_done(int32_t bytes_processed) { // Precheck to avoid queueing multiple RW done callback TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); @@ -289,7 +286,6 @@ static void tud_msc_async_io_done_cb(void* bytes_processed) { } } } -#endif //--------------------------------------------------------------------+ // USBD Driver API @@ -821,13 +817,12 @@ static void proc_read10_cmd(mscd_interface_t* p_msc) { // Application can consume smaller bytes uint32_t const offset = p_msc->xferred_len % block_sz; -#if CFG_TUD_MSC_ASYNC_IO p_msc->next_op = MSC_NEXT_OP_READ10; - tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes); -#else nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes); - proc_read10_next(p_msc, nbytes); -#endif + if (nbytes != TUD_MSC_RET_ASYNC) { + p_msc->next_op = MSC_NEXT_OP_NONE; + proc_read10_next(p_msc, nbytes); + } } static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes) { @@ -885,14 +880,13 @@ static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_byte // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; -#if CFG_TUD_MSC_ASYNC_IO p_msc->next_op = MSC_NEXT_OP_WRITE10; p_msc->xferred_bytes = xferred_bytes; - tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); -#else int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); - proc_write10_next(p_msc, xferred_bytes, nbytes); -#endif + if (nbytes != TUD_MSC_RET_ASYNC) { + p_msc->next_op = MSC_NEXT_OP_NONE; + proc_write10_next(p_msc, xferred_bytes, nbytes); + } } static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes) { diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 407fe241c..7162b11e4 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -48,10 +48,11 @@ #error CFG_TUD_MSC_EP_BUFSIZE must be defined, value of a block size should work well, the more the better #endif -// Enable asynchronous read/write, once operation is finished tud_msc_async_io_done() must be called -#ifndef CFG_TUD_MSC_ASYNC_IO -#define CFG_TUD_MSC_ASYNC_IO 0 -#endif +// Return value of callback functions +// Error +#define TUD_MSC_RET_ERROR -1 +// Asynchronous IO +#define TUD_MSC_RET_ASYNC -16 TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); @@ -62,6 +63,11 @@ TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); // Set SCSI sense response bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, uint8_t add_sense_qualifier); +// Called once asynchronous read/write operation is done +// bytes_processed has the same meaning of tud_msc_read10_cb() / +// tud_msc_write10_cb() return value +void tud_msc_async_io_done(int32_t bytes_processed); + //--------------------------------------------------------------------+ // Application Callbacks (WEAK is optional) //--------------------------------------------------------------------+ @@ -70,34 +76,40 @@ bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, u // - Address = lba * BLOCK_SIZE + offset // - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. // -// - Application fill the buffer (up to bufsize) with address contents and return number of read byte. If -// - read < bufsize : These bytes are transferred first and callback invoked again for remaining data. +// - Application fill the buffer (up to bufsize) with address contents and return number of bytes read or status. +// +// - ret < bufsize : These bytes are transferred first and callback will be invoked again for remaining data. // -// - read == 0 : Indicate application is not ready yet e.g disk I/O busy. -// Callback invoked again with the same parameters later on. +// - ret == 0 : Indicate application is not ready yet e.g disk I/O busy. +// Callback will be invoked again with the same parameters later on. // -// - read < 0 : Indicate application error e.g invalid address. This request will be STALLed +// - ret == TUD_MSC_RET_ERROR (-1) +// : Indicate application error e.g invalid address. This request will be STALLed // and return failed status in command status wrapper phase. // -// - In case of asynchronous IO enabled, application should passing reading parameters to background IO -// task and return immediately. Once reading is done, tud_msc_async_io_done() must be called. +// - ret == TUD_MSC_RET_ASYNC (-16) +// : Data reading will be done asynchronously in a background task. Application should return immediately. +// tud_msc_async_io_done() must be called once reading is done to signal completion. int32_t tud_msc_read10_cb (uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize); // Invoked when received SCSI WRITE10 command // - Address = lba * BLOCK_SIZE + offset // - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. // -// - Application write data from buffer to address contents (up to bufsize) and return number of written byte. If -// - write < bufsize : callback invoked again with remaining data later on. +// - Application writes data from buffer to address contents (up to bufsize) and returns the number of bytes written or status. // -// - write == 0 : Indicate application is not ready yet e.g disk I/O busy. -// Callback invoked again with the same parameters later on. +// - ret < bufsize : Callback will be invoked again with remaining data later on. // -// - write < 0 : Indicate application error e.g invalid address. This request will be STALLed -// and return failed status in command status wrapper phase. +// - ret == 0 : Indicate application is not ready yet e.g disk I/O busy. +// Callback will be invoked again with the same parameters later on. // -// - In case of asynchronous IO enabled, application should passing writing parameters to background IO -// task and return immediately. Once writing is done, tud_msc_async_io_done() must be called. +// - ret == TUD_MSC_RET_ERROR (-1) +// : Indicate application error e.g invalid address. This request will be STALLed +// and return failed status in command status wrapper phase. +// +// - ret == TUD_MSC_RET_ASYNC (-16) +// : Data writing will be done asynchronously in a background task. Application should return immediately. +// tud_msc_async_io_done() must be called once writing is done to signal completion. // TODO change buffer to const uint8_t* int32_t tud_msc_write10_cb (uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize); @@ -131,12 +143,6 @@ void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_siz */ int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize); -#if CFG_TUD_MSC_ASYNC_IO -// Called once asynchronous read/write operation is done -// bytes_processed has the same meaning of tud_msc_read10_cb() / -// tud_msc_write10_cb() return value -void tud_msc_async_io_done(int32_t bytes_processed); -#endif /*------------- Optional callbacks -------------*/ // Invoked when received GET_MAX_LUN request, required for multiple LUNs implementation -- cgit v1.3.1 From 8d2310247c47160bf8de6e5f754284360ad7e937 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 31 Jan 2025 16:31:47 +0100 Subject: Fix CI. Signed-off-by: HiFiPhile --- examples/device/cdc_msc_freertos/src/msc_disk.c | 2 ++ src/class/msc/msc_device.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index c75b9ae34..c2aaca847 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -166,8 +166,10 @@ static void io_task(void *params) { uint8_t const* addr = msc_disk[io_ops.lba] + io_ops.offset; memcpy(io_ops.buffer, addr, io_ops.bufsize); } else { +#ifndef CFG_EXAMPLE_MSC_READONLY uint8_t* addr = msc_disk[io_ops.lba] + io_ops.offset; memcpy(addr, io_ops.buffer, io_ops.bufsize); +#endif } tusb_time_delay_ms_api(CFG_EXAMPLE_MSC_IO_DELAY_MS); diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index e3fe5a078..72c3747fc 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -267,14 +267,14 @@ void tud_msc_async_io_done(int32_t bytes_processed) { // Precheck to avoid queueing multiple RW done callback TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); // Call usbd_edpt_xfer() in tud_task() to avoid racing condition - usbd_defer_func(tud_msc_async_io_done_cb, (void*) bytes_processed, false); + usbd_defer_func(tud_msc_async_io_done_cb, (void*) (intptr_t)bytes_processed, false); } static void tud_msc_async_io_done_cb(void* bytes_processed) { TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); uint8_t next_op = _mscd_itf.next_op; _mscd_itf.next_op = MSC_NEXT_OP_NONE; - int32_t nbytes = (int32_t)bytes_processed; + int32_t nbytes = (int32_t)(intptr_t)bytes_processed; // READ10 if (next_op == MSC_NEXT_OP_READ10) { proc_read10_next(&_mscd_itf, nbytes); -- cgit v1.3.1 From ea38115d6c65463b8c12f2da661855d2b4f263bd Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 11 Feb 2025 16:43:36 +0700 Subject: make sure TOTAL_DRIVER_COUNT is not overflow 8-bit --- src/device/usbd.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 2a6081673..b3af84086 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -317,26 +317,24 @@ enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) }; tu_static usbd_class_driver_t const * _app_driver = NULL; tu_static uint8_t _app_driver_count = 0; -#define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) +#define TOTAL_DRIVER_COUNT ((uint8_t) (_app_driver_count + BUILTIN_DRIVER_COUNT)) // virtually joins built-in and application drivers together. // Application is positioned first to allow overwriting built-in ones. TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8_t drvid) { - usbd_class_driver_t const * driver = NULL; - if ( drvid < _app_driver_count ) { + usbd_class_driver_t const *driver = NULL; + if (drvid < _app_driver_count) { // Application drivers driver = &_app_driver[drvid]; - } else if ( drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0 ){ + } else if (drvid < TOTAL_DRIVER_COUNT && BUILTIN_DRIVER_COUNT > 0) { driver = &_usbd_driver[drvid - _app_driver_count]; } return driver; } - //--------------------------------------------------------------------+ // DCD Event //--------------------------------------------------------------------+ - enum { RHPORT_INVALID = 0xFFu }; tu_static uint8_t _usbd_rhport = RHPORT_INVALID; @@ -488,6 +486,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Get application driver if available if (usbd_app_driver_get_cb) { _app_driver = usbd_app_driver_get_cb(&_app_driver_count); + TU_ASSERT(_app_driver_count + BUILTIN_DRIVER_COUNT <= UINT8_MAX); } // Init class drivers -- cgit v1.3.1 From b80800f18205ae23d571438d55e078a1dcc295e8 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Thu, 13 Mar 2025 10:04:56 -0700 Subject: Only clear stream_read & stream_write if they are defined --- src/class/midi/midi_host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 03144eb45..4d824e04c 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -153,9 +153,10 @@ void midih_close(uint8_t daddr) { p_midi->tx_cable_count = 0; p_midi->daddr = 0; p_midi->mounted = false; +#if CFG_TUH_MIDI_STREAM_API tu_memclr(&p_midi->stream_read, sizeof(p_midi->stream_read)); tu_memclr(&p_midi->stream_write, sizeof(p_midi->stream_write)); - +#endif tu_edpt_stream_close(&p_midi->ep_stream.rx); tu_edpt_stream_close(&p_midi->ep_stream.tx); } -- cgit v1.3.1 From de45e4b01a55182f494577a8bf8b46ad51d6eb9f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 15 Mar 2025 23:49:11 +0100 Subject: Add ctrl buffer alignment. Signed-off-by: HiFiPhile --- src/class/audio/audio_device.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 388168424..7a6fd453f 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -208,15 +208,15 @@ tu_static CFG_TUD_MEM_SECTION struct { #endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) // Control buffers -tu_static uint8_t ctrl_buf_1[CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ]; - -#if CFG_TUD_AUDIO > 1 -tu_static uint8_t ctrl_buf_2[CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ]; -#endif - -#if CFG_TUD_AUDIO > 2 -tu_static uint8_t ctrl_buf_3[CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ]; -#endif +tu_static CFG_TUD_MEM_SECTION struct { + TUD_EPBUF_DEF(buf1, CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ); + #if CFG_TUD_AUDIO > 1 + TUD_EPBUF_DEF(buf2, CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ); + #endif + #if CFG_TUD_AUDIO > 2 + TUD_EPBUF_DEF(buf3, CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ); + #endif +} ctrl_buf; // Active alternate setting of interfaces tu_static uint8_t alt_setting_1[CFG_TUD_AUDIO_FUNC_1_N_AS_INT]; @@ -1223,18 +1223,18 @@ void audiod_init(void) { // Initialize control buffers switch (i) { case 0: - audio->ctrl_buf = ctrl_buf_1; + audio->ctrl_buf = ctrl_buf.buf1; audio->ctrl_buf_sz = CFG_TUD_AUDIO_FUNC_1_CTRL_BUF_SZ; break; #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ > 0 case 1: - audio->ctrl_buf = ctrl_buf_2; + audio->ctrl_buf = ctrl_buf.buf2; audio->ctrl_buf_sz = CFG_TUD_AUDIO_FUNC_2_CTRL_BUF_SZ; break; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ > 0 case 2: - audio->ctrl_buf = ctrl_buf_3; + audio->ctrl_buf = ctrl_buf.buf3; audio->ctrl_buf_sz = CFG_TUD_AUDIO_FUNC_3_CTRL_BUF_SZ; break; #endif -- cgit v1.3.1 From 585bcbfcdd5e24e25dd8d42b51446824b8143602 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 16 Mar 2025 00:07:15 +0100 Subject: Fix 2 IAR warnings. Signed-off-by: HiFiPhile --- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 7d5cfb5b0..7c637ce0c 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -297,7 +297,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_reg->EPLISTSTART = (uint32_t) _dcd.ep; dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment - dcd_reg->INTSTAT |= dcd_reg->INTSTAT; // clear all pending interrupt + dcd_reg->INTSTAT = dcd_reg->INTSTAT; // clear all pending interrupt dcd_reg->INTEN = INT_DEVICE_STATUS_MASK; dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK | DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK; @@ -563,7 +563,8 @@ void dcd_int_handler(uint8_t rhport) uint32_t const cmd_stat = dcd_reg->DEVCMDSTAT; - uint32_t int_status = dcd_reg->INTSTAT & dcd_reg->INTEN; + uint32_t int_status = dcd_reg->INTSTAT; + int_status &= dcd_reg->INTEN; dcd_reg->INTSTAT = int_status; // Acknowledge handled interrupt if (int_status == 0) return; -- cgit v1.3.1 From c61dfc7c7a4744458b77caa4043af8b05a65fadc Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Mon, 9 Sep 2024 18:04:00 +0900 Subject: Add ch32v20x usbfs hcd initial support. --- hw/bsp/ch32v20x/family.c | 3 + hw/bsp/ch32v20x/family.mk | 3 + src/portable/wch/hcd_ch32_usbfs.c | 618 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 624 insertions(+) create mode 100644 src/portable/wch/hcd_ch32_usbfs.c (limited to 'src') diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 5f52d9447..8a9ee6819 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -32,6 +32,9 @@ void USBHD_IRQHandler(void) { #if CFG_TUD_WCH_USBIP_USBFS tud_int_handler(0); #endif + #if CFG_TUH_WCH_USBIP_USBFS + tuh_int_handler(0); + #endif } __attribute__((interrupt)) __attribute__((used)) diff --git a/hw/bsp/ch32v20x/family.mk b/hw/bsp/ch32v20x/family.mk index 08761dc0d..16fc537ac 100644 --- a/hw/bsp/ch32v20x/family.mk +++ b/hw/bsp/ch32v20x/family.mk @@ -30,6 +30,8 @@ CFLAGS += -Wno-error=strict-prototypes ifeq ($(PORT),0) $(info "Using FSDEV driver") CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1 + $(info "Using USBFS Host driver") + CFLAGS += -DCFG_TUH_WCH_USBIP_USBFS=1 else $(info "Using USBFS driver") CFLAGS += -DCFG_TUD_WCH_USBIP_USBFS=1 @@ -43,6 +45,7 @@ LD_FILE = $(FAMILY_PATH)/linker/${CH32_FAMILY}.ld SRC_C += \ src/portable/wch/dcd_ch32_usbfs.c \ + src/portable/wch/hcd_ch32_usbfs.c \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ $(SDK_SRC_DIR)/Core/core_riscv.c \ $(SDK_SRC_DIR)/Peripheral/src/${CH32_FAMILY}_gpio.c \ diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c new file mode 100644 index 000000000..534edb22b --- /dev/null +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -0,0 +1,618 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Mitsumine Suzu (verylowfreq) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(TUP_USBIP_WCH_USBFS) && CFG_TUH_WCH_USBIP_USBFS + +#include "host/hcd.h" +#include "host/usbh.h" +#include "host/usbh_pvt.h" + +#include "bsp/board_api.h" + +#include "ch32v20x.h" +#include "ch32v20x_usb.h" + + +#define USBFS_RX_BUF_LEN 64 +#define USBFS_TX_BUF_LEN 64 +__attribute__((aligned(4))) static uint8_t USBFS_RX_Buf[USBFS_RX_BUF_LEN]; +__attribute__((aligned(4))) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; + +#define USB_XFER_TIMEOUT_MILLIS 500 + +#define PANIC(...) do { printf("\r\nPANIC: " __VA_ARGS__); while (true) { } } while (false) + +#define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) + +// Busywait for delay microseconds/nanoseconds +// static void loopdelay(uint32_t count) +// { +// volatile uint32_t c = count / 3; +// // while (c-- != 0); +// asm volatile( +// "1: \n" // loop label +// " addi %0, %0, -1 \n" // c-- +// " bne %0, zero, 1b \n" // if (c != 0) goto loop +// : "+r"(c) // c is input/output operand +// ); +// } + + +// Endpoint status +typedef struct usb_edpt +{ + // Is this a valid struct + bool configured; + + uint8_t dev_addr; + uint8_t ep_addr; + uint16_t max_packet_size; + + // Data toggle (0 or not 0) for DATA0/1 + uint8_t data_toggle; + + // Xfer started time in millis for timeout + uint32_t current_xfer_packet_start_millis; + uint8_t* current_xfer_buffer; + uint16_t current_xfer_bufferlen; + uint16_t current_xfer_xferred_len; + +} usb_edpt_t; + + +static usb_edpt_t usb_edpt_list[8] = { }; + + +static usb_edpt_t* get_edpt_record(uint8_t dev_addr, uint8_t ep_addr) +{ + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) + { + usb_edpt_t* cur = &usb_edpt_list[i]; + if (cur->configured && cur->dev_addr == dev_addr && cur->ep_addr == ep_addr) + { + return cur; + } + } + return NULL; +} + +static usb_edpt_t* get_empty_record_slot(void) +{ + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) + { + if (!usb_edpt_list[i].configured) + { + return &usb_edpt_list[i]; + } + } + return NULL; +} + +static usb_edpt_t* add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size) +{ + usb_edpt_t* slot = get_empty_record_slot(); + TU_ASSERT(slot != NULL, NULL); + + slot->dev_addr = dev_addr; + slot->ep_addr = ep_addr; + slot->max_packet_size = max_packet_size; + slot->data_toggle = 0; + slot->current_xfer_packet_start_millis = 0; + slot->current_xfer_buffer = NULL; + slot->current_xfer_bufferlen = 0; + slot->current_xfer_xferred_len = 0; + + slot->configured = true; + + return slot; +} + +static usb_edpt_t* get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size) +{ + usb_edpt_t* ret = get_edpt_record(dev_addr, ep_addr); + if (ret != NULL) + { + return ret; + } + else + { + return add_edpt_record(dev_addr, ep_addr, max_packet_size); + } +} + + +static void remove_edpt_record_for_device(uint8_t dev_addr) +{ + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) + { + if (usb_edpt_list[i].configured && usb_edpt_list[i].dev_addr == dev_addr) + { + usb_edpt_list[i].configured = false; + } + } +} + + +/** Enable or disable USBFS Host function */ +static void hardware_init_host(bool enabled) +{ + // Reset USBOTG module + USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; + + osal_task_delay(1); + USBOTG_H_FS->BASE_CTRL = 0; + + if (!enabled) + { + // Disable all feature + USBOTG_H_FS->BASE_CTRL = 0; + } + else + { + // Enable USB Host features + NVIC_DisableIRQ(USBFS_IRQn); + USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN; + USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf; + USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf; + USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; + } +} + +static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggle) +{ + LOG_CH32_USBFSH("hardware_start_xfer(pid=%s(0x%02x), ep_addr=0x%02x, toggle=%d)\r\n", + pid == USB_PID_IN ? "IN" : pid == USB_PID_OUT ? "OUT" : pid == USB_PID_SETUP ? "SETUP" : "(other)", + pid, ep_addr, data_toggle); + + if (pid == USB_PID_IN) + { // FIXME: long delay needed (at release build) about 30msec + // loopdelay(SystemCoreClock / 1000 * 30); + } + + uint8_t pid_edpt = (pid << 4) | (tu_edpt_number(ep_addr) & 0x0f); + USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; + USBOTG_H_FS->HOST_RX_CTRL = (data_toggle != 0) ? USBFS_UH_R_TOG : 0; + USBOTG_H_FS->HOST_EP_PID = pid_edpt; + USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; + return true; +} + + +/** Set device address to communicate */ +static void update_device_address(uint8_t dev_addr) +{ + // Keep the bit of GP_BIT. Other 7bits are actual device address. + USBOTG_H_FS->DEV_ADDR = (USBOTG_H_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | (dev_addr & USBFS_USB_ADDR_MASK); +} + +/** Set port speed */ +static void update_port_speed(tusb_speed_t speed) +{ + LOG_CH32_USBFSH("update_port_speed(%s)\r\n", speed == TUSB_SPEED_FULL ? "Full" : speed == TUSB_SPEED_LOW ? "Low" : "(invalid)"); + switch (speed) { + case TUSB_SPEED_LOW: + USBOTG_H_FS->BASE_CTRL |= USBFS_UC_LOW_SPEED; + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_LOW_SPEED; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_PRE_PID_EN; + return; + case TUSB_SPEED_FULL: + USBOTG_H_FS->BASE_CTRL &= ~USBFS_UC_LOW_SPEED; + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; + USBOTG_H_FS->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN; + return; + default: + PANIC("update_port_speed(%d)\r\n", speed); + } +} + +static bool hardware_device_attached(void) +{ + return USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH; +} + + +//--------------------------------------------------------------------+ +// HCD API +//--------------------------------------------------------------------+ +bool hcd_init(uint8_t rhport) +{ + (void)rhport; + hardware_init_host(true); + + return true; +} + +bool hcd_deinit(uint8_t rhport) +{ + (void)rhport; + hardware_init_host(false); + + return true; +} + +void hcd_port_reset(uint8_t rhport) +{ + (void)rhport; + LOG_CH32_USBFSH("hcd_port_reset()\r\n"); + NVIC_DisableIRQ(USBFS_IRQn); + update_device_address( 0x00 ); + + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_BUS_RESET; + osal_task_delay(15); + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_BUS_RESET; + osal_task_delay(2); + + if ((USBOTG_H_FS->HOST_CTRL & USBFS_UH_PORT_EN) == 0) + { + if (hcd_port_speed_get(0) == TUSB_SPEED_LOW) + { + update_port_speed(TUSB_SPEED_LOW); + } + } + + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; + + return; +} + +void hcd_port_reset_end(uint8_t rhport) +{ + (void)rhport; + LOG_CH32_USBFSH("hcd_port_reset_end()\r\n"); + // Suppress the attached event + USBOTG_H_FS->INT_FG |= USBFS_UIF_DETECT; + NVIC_EnableIRQ(USBFS_IRQn); + + return; +} + +bool hcd_port_connect_status(uint8_t rhport) +{ + (void)rhport; + + return hardware_device_attached(); +} + +tusb_speed_t hcd_port_speed_get(uint8_t rhport) +{ + (void)rhport; + if (USBOTG_H_FS->MIS_ST & USBFS_UMS_DM_LEVEL) + { + return TUSB_SPEED_LOW; + } + else + { + return TUSB_SPEED_FULL; + } +} + +// Close all opened endpoint belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + LOG_CH32_USBFSH("hcd_device_close(%d, 0x%02x)\r\n", rhport, dev_addr); + remove_edpt_record_for_device(dev_addr); + + return; +} + +uint32_t hcd_frame_number(uint8_t rhport) +{ + (void)rhport; + + return board_millis(); +} + +void hcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USBFS_IRQn); + + return; +} + +void hcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USBFS_IRQn); + + return; +} + +void hcd_int_handler(uint8_t rhport, bool in_isr) +{ + (void)rhport; + (void)in_isr; + + if (USBOTG_H_FS->INT_FG & USBFS_UIF_DETECT) + { + // Clear the flag + USBOTG_H_FS->INT_FG = USBFS_UIF_DETECT; + // Read the detection state + bool attached = hardware_device_attached(); + LOG_CH32_USBFSH("hcd_int_handler() attached = %d\r\n", attached ? 1 : 0); + if (attached) + { + hcd_event_device_attach(rhport, true); + } + else + { + hcd_event_device_remove(rhport, true); + } + return; + } + + if (USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) + { + // Copy PID and Endpoint + uint8_t pid_edpt = USBOTG_H_FS->HOST_EP_PID; + uint8_t status = USBOTG_H_FS->INT_ST; + // Clear register to stop transfer + USBOTG_H_FS->HOST_EP_PID = 0; + // Clear the flag + USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; + + LOG_CH32_USBFSH("hcd_int_handler() pid_edpt=0x%02x\r\n", pid_edpt); + + uint8_t request_pid = pid_edpt >> 4; + uint8_t response_pid = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; + uint8_t dev_addr = USBOTG_H_FS->DEV_ADDR; + uint8_t ep_addr = pid_edpt & 0x0f; + if (request_pid == USB_PID_IN) + { + ep_addr |= 0x80; + } + + usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); + if (edpt_info == NULL) + { + PANIC("\r\nget_edpt_record() returned NULL in USBHD_IRQHandler\r\n"); + } + + if (status & USBFS_UIS_TOG_OK) + { + edpt_info->data_toggle ^= 0x01; + + switch (request_pid) + { + case USB_PID_SETUP: + case USB_PID_OUT: + { + uint16_t xferred_len = edpt_info->current_xfer_bufferlen; + hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); + return; + } + case USB_PID_IN: + { + uint16_t received_len = USBOTG_H_FS->RX_LEN; + edpt_info->current_xfer_xferred_len += received_len; + uint16_t xferred_len = edpt_info->current_xfer_xferred_len; + LOG_CH32_USBFSH("Read %d bytes\r\n", received_len); + // if (received_len > 0 && (edpt_info->current_xfer_buffer == NULL || edpt_info->current_xfer_bufferlen == 0)) { + // PANIC("Data received but buffer not set\r\n"); + // } + memcpy(edpt_info->current_xfer_buffer, USBFS_RX_Buf, received_len); + edpt_info->current_xfer_buffer += received_len; + if ((received_len < edpt_info->max_packet_size) || (xferred_len == edpt_info->current_xfer_bufferlen)) + { + // USB device sent all data. + LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); + hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); + return; + } + else + { + // USB device may send more data. + LOG_CH32_USBFSH("Read more data\r\n"); + hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); + return; + } + } + default: + { + PANIC("Unknown PID: 0x%02x\n", request_pid); + } + } + } + else + { + if (response_pid == USB_PID_STALL) + { + LOG_CH32_USBFSH("Data toggle mismatched and STALL\r\n"); + hcd_edpt_clear_stall(0, dev_addr, ep_addr); + edpt_info->data_toggle = 0; + hardware_start_xfer(request_pid, ep_addr, 0); + return; + } + else if (response_pid == USB_PID_NAK) + { + LOG_CH32_USBFSH("Data toggle mismatched and NAK\r\n"); + uint32_t elapsed_time = board_millis() - edpt_info->current_xfer_packet_start_millis; + if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) + { + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + } + else + { + hardware_start_xfer(request_pid, ep_addr, edpt_info->data_toggle); + } + return; + } + else if (response_pid == USB_PID_DATA0 || response_pid == USB_PID_DATA1) + { + LOG_CH32_USBFSH("Data toggle mismatched and DATA0/1 (not STALL). RX_LEN=%d\r\n", USBOTG_H_FS->RX_LEN); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + return; + } + else + { + LOG_CH32_USBFSH("\r\nIn USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + return; + } + } + } +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ + +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) +{ + (void)rhport; + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint8_t ep_num = tu_edpt_number(ep_addr); + uint16_t max_packet_size = ep_desc->wMaxPacketSize; + LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size); + + if (ep_num == 0x00) + { + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size) != NULL, false); + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size) != NULL, false); + } + else + { + TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size) != NULL, false); + } + + update_device_address(dev_addr); + + if (dev_addr == 0x00 && ep_num == 0x00) + { + // It assumes first open for the device, so make the port enable + tusb_speed_t device_speed = hcd_port_speed_get(rhport); + update_port_speed(device_speed); + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; + } + + return true; +} + +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) +{ + (void)rhport; + + usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); + if (edpt_info == NULL) + { + PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); + } + + edpt_info->current_xfer_buffer = buffer; + edpt_info->current_xfer_bufferlen = buflen; + + edpt_info->current_xfer_packet_start_millis = board_millis(); + edpt_info->current_xfer_xferred_len = 0; + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) + { + LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, ep_addr=0x%02x, len=%d\r\n", ep_addr, buflen); + return hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); + } + else + { + LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, ep_addr=0x%02x, len=%d\r\n", ep_addr, buflen); + USBOTG_H_FS->HOST_TX_LEN = buflen; + memcpy(USBFS_TX_Buf, buffer, buflen); + return hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); + } +} + +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) +{ + (void) rhport; + (void) dev_addr; + (void) ep_addr; + LOG_CH32_USBFSH("hcd_edpt_abort_xfer(%d, 0x%02x, 0x%02x)\r\n", rhport, dev_addr, ep_addr); + + return false; +} + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) +{ + (void)rhport; + LOG_CH32_USBFSH("hcd_setup_send(rhport=%d, dev_addr=0x%02x, %p)\r\n", rhport, dev_addr, setup_packet); + + + usb_edpt_t* edpt_info_tx = get_edpt_record(dev_addr, 0x00); + usb_edpt_t* edpt_info_rx = get_edpt_record(dev_addr, 0x80); + TU_ASSERT(edpt_info_tx != NULL, false); + TU_ASSERT(edpt_info_rx != NULL, false); + + // Initialize data toggle (SETUP always starts with DATA0) + // Data toggle for OUT is toggled in hcd_int_handler() + edpt_info_tx->data_toggle = 0; + // Data toggle for IN must be set 0x01 manually. + edpt_info_rx->data_toggle = 0x01; + const uint16_t setup_packet_datalen = 8; + memcpy(USBFS_TX_Buf, setup_packet, setup_packet_datalen); + USBOTG_H_FS->HOST_TX_LEN = setup_packet_datalen; + + edpt_info_tx->current_xfer_packet_start_millis = board_millis(); + edpt_info_tx->current_xfer_buffer = USBFS_TX_Buf; + edpt_info_tx->current_xfer_bufferlen = setup_packet_datalen; + edpt_info_tx->current_xfer_xferred_len = 0; + + hardware_start_xfer(USB_PID_SETUP, 0, 0); + + return true; +} + +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) +{ + (void) rhport; + (void) dev_addr; + LOG_CH32_USBFSH("hcd_edpt_clear_stall(rhport=%d, dev_addr=0x%02x, ep_addr=0x%02x)\r\n", rhport, dev_addr, ep_addr); + // PANIC("\r\nstall\r\n"); + uint8_t edpt_num = tu_edpt_number(ep_addr); + uint8_t setup_request_clear_stall[8] = { + 0x02, 0x01, 0x00, 0x00, edpt_num, 0x00, 0x00, 0x00 + }; + memcpy(USBFS_TX_Buf, setup_request_clear_stall, 8); + USBOTG_H_FS->HOST_TX_LEN = 8; + + hcd_int_disable(0); + + USBOTG_H_FS->HOST_EP_PID = (USB_PID_SETUP << 4) | 0x00; + USBOTG_H_FS->INT_FG |= USBFS_UIF_TRANSFER; + while ((USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) == 0) { } + USBOTG_H_FS->HOST_EP_PID = 0; + uint8_t response_pid = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; + (void)response_pid; + LOG_CH32_USBFSH("hcd_edpt_clear_stall() response pid=0x%02x\r\n", response_pid); + + hcd_int_enable(0); + + return true; +} + +#endif -- cgit v1.3.1 From dc3e6a59a9f50182c09e6301a4f8fcc9a4089722 Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Mon, 9 Sep 2024 19:00:46 +0900 Subject: Repeat xfer on USB_PID_OUT if data is larger than MaxPacketSize --- src/portable/wch/hcd_ch32_usbfs.c | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 534edb22b..93c5ce519 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -405,9 +405,28 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) case USB_PID_SETUP: case USB_PID_OUT: { - uint16_t xferred_len = edpt_info->current_xfer_bufferlen; - hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); - return; + uint16_t tx_len = USBOTG_H_FS->HOST_TX_LEN; + edpt_info->current_xfer_bufferlen -= tx_len; + edpt_info->current_xfer_xferred_len += tx_len; + if (edpt_info->current_xfer_bufferlen == 0) + { + LOG_CH32_USBFSH("USB_PID_OUT completed %d bytes\r\n", edpt_info->current_xfer_xferred_len); + hcd_event_xfer_complete(dev_addr, ep_addr, edpt_info->current_xfer_xferred_len, XFER_RESULT_SUCCESS, true); + return; + } + else + { + LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); + edpt_info->current_xfer_buffer += tx_len; + uint16_t copylen = USBFS_TX_BUF_LEN; + if (copylen > edpt_info->current_xfer_bufferlen) + { + copylen = edpt_info->current_xfer_bufferlen; + } + memcpy(USBFS_TX_Buf, edpt_info->current_xfer_buffer, copylen); + hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); + return; + } } case USB_PID_IN: { @@ -541,8 +560,13 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * else { LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, ep_addr=0x%02x, len=%d\r\n", ep_addr, buflen); - USBOTG_H_FS->HOST_TX_LEN = buflen; - memcpy(USBFS_TX_Buf, buffer, buflen); + uint16_t copylen = USBFS_TX_BUF_LEN; + if (copylen > buflen) + { + copylen = buflen; + } + USBOTG_H_FS->HOST_TX_LEN = copylen; + memcpy(USBFS_TX_Buf, buffer, copylen); return hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); } } -- cgit v1.3.1 From 879f78a91df08f0b3c6df7f56d6dd2293455dbcd Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 11 Sep 2024 18:34:48 +0700 Subject: fix pre-commmit --- src/portable/wch/hcd_ch32_usbfs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 93c5ce519..b775d6eee 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -186,7 +186,7 @@ static void hardware_init_host(bool enabled) static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggle) { - LOG_CH32_USBFSH("hardware_start_xfer(pid=%s(0x%02x), ep_addr=0x%02x, toggle=%d)\r\n", + LOG_CH32_USBFSH("hardware_start_xfer(pid=%s(0x%02x), ep_addr=0x%02x, toggle=%d)\r\n", pid == USB_PID_IN ? "IN" : pid == USB_PID_OUT ? "OUT" : pid == USB_PID_SETUP ? "SETUP" : "(other)", pid, ep_addr, data_toggle); @@ -342,7 +342,7 @@ void hcd_int_disable(uint8_t rhport) { (void)rhport; NVIC_DisableIRQ(USBFS_IRQn); - + return; } @@ -492,7 +492,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) } else { - LOG_CH32_USBFSH("\r\nIn USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); + LOG_CH32_USBFSH("In USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); return; } @@ -616,7 +616,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) (void) rhport; (void) dev_addr; LOG_CH32_USBFSH("hcd_edpt_clear_stall(rhport=%d, dev_addr=0x%02x, ep_addr=0x%02x)\r\n", rhport, dev_addr, ep_addr); - // PANIC("\r\nstall\r\n"); + // PANIC("\r\install\r\n"); uint8_t edpt_num = tu_edpt_number(ep_addr); uint8_t setup_request_clear_stall[8] = { 0x02, 0x01, 0x00, 0x00, edpt_num, 0x00, 0x00, 0x00 -- cgit v1.3.1 From 7ed5503a5c2bc0b755d97303064614275e74ffb2 Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Wed, 11 Sep 2024 23:25:49 +0900 Subject: Fix the condition related to CFG_TUH_WCH_USBIP_USBFS macro --- hw/bsp/ch32v20x/family.c | 2 +- src/portable/wch/hcd_ch32_usbfs.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 8a9ee6819..d674ccd6f 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -32,7 +32,7 @@ void USBHD_IRQHandler(void) { #if CFG_TUD_WCH_USBIP_USBFS tud_int_handler(0); #endif - #if CFG_TUH_WCH_USBIP_USBFS + #if defined(CFG_TUH_WCH_USBIP_USBFS) && CFG_TUH_WCH_USBIP_USBFS tuh_int_handler(0); #endif } diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index b775d6eee..7e73f686f 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && defined(TUP_USBIP_WCH_USBFS) && CFG_TUH_WCH_USBIP_USBFS +#if CFG_TUH_ENABLED && defined(TUP_USBIP_WCH_USBFS) && defined(CFG_TUH_WCH_USBIP_USBFS) && CFG_TUH_WCH_USBIP_USBFS #include "host/hcd.h" #include "host/usbh.h" -- cgit v1.3.1 From 426588d947b5c9ac789571019fc2b8da5d756669 Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Mon, 28 Oct 2024 21:28:15 +0900 Subject: Fix for timing, timeout, and device switching issues --- src/portable/wch/hcd_ch32_usbfs.c | 193 +++++++++++++++++++++++++------------- 1 file changed, 127 insertions(+), 66 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 7e73f686f..ddd366b4f 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -43,24 +43,26 @@ __attribute__((aligned(4))) static uint8_t USBFS_RX_Buf[USBFS_RX_BUF_LEN]; __attribute__((aligned(4))) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; -#define USB_XFER_TIMEOUT_MILLIS 500 +#define USB_XFER_TIMEOUT_MILLIS 100 +#define USB_INTERRUPT_XFER_TIMEOUT_MILLIS 1 #define PANIC(...) do { printf("\r\nPANIC: " __VA_ARGS__); while (true) { } } while (false) #define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) // Busywait for delay microseconds/nanoseconds -// static void loopdelay(uint32_t count) -// { -// volatile uint32_t c = count / 3; -// // while (c-- != 0); -// asm volatile( -// "1: \n" // loop label -// " addi %0, %0, -1 \n" // c-- -// " bne %0, zero, 1b \n" // if (c != 0) goto loop -// : "+r"(c) // c is input/output operand -// ); -// } +static void loopdelay(uint32_t count) +{ + volatile uint32_t c = count / 3; + if (c == 0) { return; } + // while (c-- != 0); + asm volatile( + "1: \n" // loop label + " addi %0, %0, -1 \n" // c-- + " bne %0, zero, 1b \n" // if (c != 0) goto loop + : "+r"(c) // c is input/output operand + ); +} // Endpoint status @@ -71,21 +73,30 @@ typedef struct usb_edpt uint8_t dev_addr; uint8_t ep_addr; - uint16_t max_packet_size; + uint8_t max_packet_size; + + uint8_t xfer_type; // Data toggle (0 or not 0) for DATA0/1 uint8_t data_toggle; +} usb_edpt_t; + + +static usb_edpt_t usb_edpt_list[CFG_TUH_DEVICE_MAX * 6] = {}; + +typedef struct usb_current_xfer_st { + bool is_busy; + uint8_t dev_addr; + uint8_t ep_addr; // Xfer started time in millis for timeout uint32_t current_xfer_packet_start_millis; uint8_t* current_xfer_buffer; uint16_t current_xfer_bufferlen; uint16_t current_xfer_xferred_len; +} usb_current_xfer_t; -} usb_edpt_t; - - -static usb_edpt_t usb_edpt_list[8] = { }; +static volatile usb_current_xfer_t usb_current_xfer_info = {}; static usb_edpt_t* get_edpt_record(uint8_t dev_addr, uint8_t ep_addr) @@ -113,26 +124,26 @@ static usb_edpt_t* get_empty_record_slot(void) return NULL; } -static usb_edpt_t* add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size) +static usb_edpt_t* add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) { usb_edpt_t* slot = get_empty_record_slot(); + if (slot == NULL) { + PANIC("add_edpt_record(0x%02x, 0x%02x, ...) no slot for new record\r\n", dev_addr, ep_addr); + } TU_ASSERT(slot != NULL, NULL); slot->dev_addr = dev_addr; slot->ep_addr = ep_addr; slot->max_packet_size = max_packet_size; + slot->xfer_type = xfer_type; slot->data_toggle = 0; - slot->current_xfer_packet_start_millis = 0; - slot->current_xfer_buffer = NULL; - slot->current_xfer_bufferlen = 0; - slot->current_xfer_xferred_len = 0; slot->configured = true; return slot; } -static usb_edpt_t* get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size) +static usb_edpt_t* get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) { usb_edpt_t* ret = get_edpt_record(dev_addr, ep_addr); if (ret != NULL) @@ -141,7 +152,7 @@ static usb_edpt_t* get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uin } else { - return add_edpt_record(dev_addr, ep_addr, max_packet_size); + return add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type); } } @@ -157,6 +168,17 @@ static void remove_edpt_record_for_device(uint8_t dev_addr) } } +// static void dump_edpt_record_list() { +// for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) { +// usb_edpt_t* cur = &usb_edpt_list[i]; +// if (cur->configured) { +// printf("[%2d] Device 0x%02x Endpoint 0x%02x\r\n", i, cur->dev_addr, cur->ep_addr); +// } else { +// printf("[%2d] not configured\r\n", i); +// } +// } +// } + /** Enable or disable USBFS Host function */ static void hardware_init_host(bool enabled) @@ -180,7 +202,8 @@ static void hardware_init_host(bool enabled) USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN; USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf; USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf; - USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; + // USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; + USBOTG_H_FS->INT_EN = USBFS_UIE_DETECT; } } @@ -199,6 +222,7 @@ static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggl USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; USBOTG_H_FS->HOST_RX_CTRL = (data_toggle != 0) ? USBFS_UH_R_TOG : 0; USBOTG_H_FS->HOST_EP_PID = pid_edpt; + USBOTG_H_FS->INT_EN |= USBFS_UIE_TRANSFER; USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; return true; } @@ -371,19 +395,21 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) if (USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) { + // Disable transfer interrupt + USBOTG_H_FS->INT_EN &= ~USBFS_UIE_TRANSFER; + // Clear the flag + // USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; // Copy PID and Endpoint uint8_t pid_edpt = USBOTG_H_FS->HOST_EP_PID; uint8_t status = USBOTG_H_FS->INT_ST; + uint8_t dev_addr = USBOTG_H_FS->DEV_ADDR & USBFS_USB_ADDR_MASK; // Clear register to stop transfer - USBOTG_H_FS->HOST_EP_PID = 0; - // Clear the flag - USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; + // USBOTG_H_FS->HOST_EP_PID = 0x00; LOG_CH32_USBFSH("hcd_int_handler() pid_edpt=0x%02x\r\n", pid_edpt); uint8_t request_pid = pid_edpt >> 4; - uint8_t response_pid = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; - uint8_t dev_addr = USBOTG_H_FS->DEV_ADDR; + uint8_t response_pid = status & USBFS_UIS_H_RES_MASK; uint8_t ep_addr = pid_edpt & 0x0f; if (request_pid == USB_PID_IN) { @@ -393,7 +419,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); if (edpt_info == NULL) { - PANIC("\r\nget_edpt_record() returned NULL in USBHD_IRQHandler\r\n"); + PANIC("\r\nget_edpt_record(0x%02x, 0x%02x) returned NULL in USBHD_IRQHandler\r\n", dev_addr, ep_addr); } if (status & USBFS_UIS_TOG_OK) @@ -406,24 +432,25 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) case USB_PID_OUT: { uint16_t tx_len = USBOTG_H_FS->HOST_TX_LEN; - edpt_info->current_xfer_bufferlen -= tx_len; - edpt_info->current_xfer_xferred_len += tx_len; - if (edpt_info->current_xfer_bufferlen == 0) + usb_current_xfer_info.current_xfer_bufferlen -= tx_len; + usb_current_xfer_info.current_xfer_xferred_len += tx_len; + if (usb_current_xfer_info.current_xfer_bufferlen == 0) { - LOG_CH32_USBFSH("USB_PID_OUT completed %d bytes\r\n", edpt_info->current_xfer_xferred_len); - hcd_event_xfer_complete(dev_addr, ep_addr, edpt_info->current_xfer_xferred_len, XFER_RESULT_SUCCESS, true); + LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.current_xfer_xferred_len); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.current_xfer_xferred_len, XFER_RESULT_SUCCESS, true); return; } else { LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); - edpt_info->current_xfer_buffer += tx_len; + usb_current_xfer_info.current_xfer_buffer += tx_len; uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > edpt_info->current_xfer_bufferlen) + if (copylen > usb_current_xfer_info.current_xfer_bufferlen) { - copylen = edpt_info->current_xfer_bufferlen; + copylen = usb_current_xfer_info.current_xfer_bufferlen; } - memcpy(USBFS_TX_Buf, edpt_info->current_xfer_buffer, copylen); + memcpy(USBFS_TX_Buf, usb_current_xfer_info.current_xfer_buffer, copylen); hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); return; } @@ -431,18 +458,19 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) case USB_PID_IN: { uint16_t received_len = USBOTG_H_FS->RX_LEN; - edpt_info->current_xfer_xferred_len += received_len; - uint16_t xferred_len = edpt_info->current_xfer_xferred_len; + usb_current_xfer_info.current_xfer_xferred_len += received_len; + uint16_t xferred_len = usb_current_xfer_info.current_xfer_xferred_len; LOG_CH32_USBFSH("Read %d bytes\r\n", received_len); - // if (received_len > 0 && (edpt_info->current_xfer_buffer == NULL || edpt_info->current_xfer_bufferlen == 0)) { + // if (received_len > 0 && (usb_current_xfer_info.current_xfer_buffer == NULL || usb_current_xfer_info.current_xfer_bufferlen == 0)) { // PANIC("Data received but buffer not set\r\n"); // } - memcpy(edpt_info->current_xfer_buffer, USBFS_RX_Buf, received_len); - edpt_info->current_xfer_buffer += received_len; - if ((received_len < edpt_info->max_packet_size) || (xferred_len == edpt_info->current_xfer_bufferlen)) + memcpy(usb_current_xfer_info.current_xfer_buffer, USBFS_RX_Buf, received_len); + usb_current_xfer_info.current_xfer_buffer += received_len; + if ((received_len < edpt_info->max_packet_size) || (xferred_len == usb_current_xfer_info.current_xfer_bufferlen)) { // USB device sent all data. LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); + usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); return; } @@ -464,7 +492,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (response_pid == USB_PID_STALL) { - LOG_CH32_USBFSH("Data toggle mismatched and STALL\r\n"); + LOG_CH32_USBFSH("STALL response\r\n"); hcd_edpt_clear_stall(0, dev_addr, ep_addr); edpt_info->data_toggle = 0; hardware_start_xfer(request_pid, ep_addr, 0); @@ -472,10 +500,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) } else if (response_pid == USB_PID_NAK) { - LOG_CH32_USBFSH("Data toggle mismatched and NAK\r\n"); - uint32_t elapsed_time = board_millis() - edpt_info->current_xfer_packet_start_millis; - if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) + LOG_CH32_USBFSH("NAK reposense\r\n"); + uint32_t elapsed_time = board_millis() - usb_current_xfer_info.current_xfer_packet_start_millis; + if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT && (elapsed_time > USB_INTERRUPT_XFER_TIMEOUT_MILLIS)) { + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); + } + else if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) + { + usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); } else @@ -487,12 +521,14 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) else if (response_pid == USB_PID_DATA0 || response_pid == USB_PID_DATA1) { LOG_CH32_USBFSH("Data toggle mismatched and DATA0/1 (not STALL). RX_LEN=%d\r\n", USBOTG_H_FS->RX_LEN); + usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); return; } else { LOG_CH32_USBFSH("In USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); + usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); return; } @@ -510,16 +546,17 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const uint8_t ep_addr = ep_desc->bEndpointAddress; uint8_t ep_num = tu_edpt_number(ep_addr); uint16_t max_packet_size = ep_desc->wMaxPacketSize; - LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size); + uint8_t xfer_type = ep_desc->bmAttributes.xfer; + LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d,xfer_type=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size, xfer_type); if (ep_num == 0x00) { - TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size) != NULL, false); - TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size) != NULL, false); + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size, xfer_type) != NULL, false); + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size, xfer_type) != NULL, false); } else { - TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size) != NULL, false); + TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type) != NULL, false); } update_device_address(dev_addr); @@ -540,26 +577,36 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * { (void)rhport; + while (usb_current_xfer_info.is_busy) { + osal_task_delay(1); + } + usb_current_xfer_info.is_busy = true; + usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); if (edpt_info == NULL) { PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); } + + update_device_address(dev_addr); + tusb_speed_t device_speed = hcd_port_speed_get(rhport); + update_port_speed(device_speed); - edpt_info->current_xfer_buffer = buffer; - edpt_info->current_xfer_bufferlen = buflen; - - edpt_info->current_xfer_packet_start_millis = board_millis(); - edpt_info->current_xfer_xferred_len = 0; + usb_current_xfer_info.dev_addr = dev_addr; + usb_current_xfer_info.ep_addr = ep_addr; + usb_current_xfer_info.current_xfer_buffer = buffer; + usb_current_xfer_info.current_xfer_bufferlen = buflen; + usb_current_xfer_info.current_xfer_packet_start_millis = board_millis(); + usb_current_xfer_info.current_xfer_xferred_len = 0; if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { - LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, ep_addr=0x%02x, len=%d\r\n", ep_addr, buflen); + LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); return hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); } else { - LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, ep_addr=0x%02x, len=%d\r\n", ep_addr, buflen); + LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); uint16_t copylen = USBFS_TX_BUF_LEN; if (copylen > buflen) { @@ -584,8 +631,20 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void)rhport; + + if (usb_current_xfer_info.is_busy) { + osal_task_delay(1); + } + usb_current_xfer_info.is_busy = true; + LOG_CH32_USBFSH("hcd_setup_send(rhport=%d, dev_addr=0x%02x, %p)\r\n", rhport, dev_addr, setup_packet); + // loopdelay(SystemCoreClock / 1000000 * 100); + loopdelay(1); + + update_device_address(dev_addr); + tusb_speed_t device_speed = hcd_port_speed_get(rhport); + update_port_speed(device_speed); usb_edpt_t* edpt_info_tx = get_edpt_record(dev_addr, 0x00); usb_edpt_t* edpt_info_rx = get_edpt_record(dev_addr, 0x80); @@ -600,11 +659,13 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet const uint16_t setup_packet_datalen = 8; memcpy(USBFS_TX_Buf, setup_packet, setup_packet_datalen); USBOTG_H_FS->HOST_TX_LEN = setup_packet_datalen; - - edpt_info_tx->current_xfer_packet_start_millis = board_millis(); - edpt_info_tx->current_xfer_buffer = USBFS_TX_Buf; - edpt_info_tx->current_xfer_bufferlen = setup_packet_datalen; - edpt_info_tx->current_xfer_xferred_len = 0; + uint8_t ep_addr = (setup_packet[0] & 0x80) ? 0x80 : 0x00; + usb_current_xfer_info.dev_addr = dev_addr; + usb_current_xfer_info.ep_addr = ep_addr; + usb_current_xfer_info.current_xfer_packet_start_millis = board_millis(); + usb_current_xfer_info.current_xfer_buffer = USBFS_TX_Buf; + usb_current_xfer_info.current_xfer_bufferlen = setup_packet_datalen; + usb_current_xfer_info.current_xfer_xferred_len = 0; hardware_start_xfer(USB_PID_SETUP, 0, 0); -- cgit v1.3.1 From 9ca4bc89a7e285796e8102eb7a8fd1bbc6fb9938 Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Thu, 12 Dec 2024 09:53:58 +0900 Subject: Update hcd_init() signature. Add osal_task_delay() implementation for none os. --- src/portable/wch/hcd_ch32_usbfs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index ddd366b4f..cbbf90da6 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -37,6 +37,10 @@ #include "ch32v20x.h" #include "ch32v20x_usb.h" +void osal_task_delay(uint32_t msec) { + unsigned long start = board_millis(); + while (board_millis() - start < msec) {} +} #define USBFS_RX_BUF_LEN 64 #define USBFS_TX_BUF_LEN 64 @@ -264,9 +268,10 @@ static bool hardware_device_attached(void) //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ -bool hcd_init(uint8_t rhport) +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void)rhport; + (void)rh_init; hardware_init_host(true); return true; -- cgit v1.3.1 From cd2b3a53217857930bd8519d074b355ae8933982 Mon Sep 17 00:00:00 2001 From: verylowfreq <60875431+verylowfreq@users.noreply.github.com> Date: Sun, 16 Mar 2025 10:06:27 +0900 Subject: Fix interupt, LowSpeed switching and rename --- src/portable/wch/hcd_ch32_usbfs.c | 194 +++++++++++++++++++++----------------- 1 file changed, 106 insertions(+), 88 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index cbbf90da6..800390989 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -38,7 +38,7 @@ #include "ch32v20x_usb.h" void osal_task_delay(uint32_t msec) { - unsigned long start = board_millis(); + uint32_t start = board_millis(); while (board_millis() - start < msec) {} } @@ -48,25 +48,25 @@ __attribute__((aligned(4))) static uint8_t USBFS_RX_Buf[USBFS_RX_BUF_LEN]; __attribute__((aligned(4))) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; #define USB_XFER_TIMEOUT_MILLIS 100 -#define USB_INTERRUPT_XFER_TIMEOUT_MILLIS 1 +// #define USB_INTERRUPT_XFER_TIMEOUT_MILLIS 1 -#define PANIC(...) do { printf("\r\nPANIC: " __VA_ARGS__); while (true) { } } while (false) +#define PANIC(...) do { printf("%s() L%d: ", __func__, __LINE__); printf("\r\n[PANIC] " __VA_ARGS__); while (true) { } } while (false) #define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) // Busywait for delay microseconds/nanoseconds -static void loopdelay(uint32_t count) -{ - volatile uint32_t c = count / 3; - if (c == 0) { return; } - // while (c-- != 0); - asm volatile( - "1: \n" // loop label - " addi %0, %0, -1 \n" // c-- - " bne %0, zero, 1b \n" // if (c != 0) goto loop - : "+r"(c) // c is input/output operand - ); -} +// static void loopdelay(uint32_t count) +// { +// volatile uint32_t c = count / 3; +// if (c == 0) { return; } +// // while (c-- != 0); +// asm volatile( +// "1: \n" // loop label +// " addi %0, %0, -1 \n" // c-- +// " bne %0, zero, 1b \n" // if (c != 0) goto loop +// : "+r"(c) // c is input/output operand +// ); +// } // Endpoint status @@ -94,10 +94,10 @@ typedef struct usb_current_xfer_st { uint8_t dev_addr; uint8_t ep_addr; // Xfer started time in millis for timeout - uint32_t current_xfer_packet_start_millis; - uint8_t* current_xfer_buffer; - uint16_t current_xfer_bufferlen; - uint16_t current_xfer_xferred_len; + uint32_t start_ms; + uint8_t* buffer; + uint16_t bufferlen; + uint16_t xferred_len; } usb_current_xfer_t; static volatile usb_current_xfer_t usb_current_xfer_info = {}; @@ -184,6 +184,8 @@ static void remove_edpt_record_for_device(uint8_t dev_addr) // } +static bool interrupt_enabled = false; + /** Enable or disable USBFS Host function */ static void hardware_init_host(bool enabled) { @@ -201,7 +203,8 @@ static void hardware_init_host(bool enabled) else { // Enable USB Host features - NVIC_DisableIRQ(USBFS_IRQn); + // NVIC_DisableIRQ(USBFS_IRQn); + hcd_int_disable(0); USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN; USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf; @@ -217,10 +220,10 @@ static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggl pid == USB_PID_IN ? "IN" : pid == USB_PID_OUT ? "OUT" : pid == USB_PID_SETUP ? "SETUP" : "(other)", pid, ep_addr, data_toggle); - if (pid == USB_PID_IN) - { // FIXME: long delay needed (at release build) about 30msec - // loopdelay(SystemCoreClock / 1000 * 30); - } + // if (pid == USB_PID_IN) + // { // FIXME: long delay needed (at release build) about 30msec + // loopdelay(SystemCoreClock / 1000 * 30); + // } uint8_t pid_edpt = (pid << 4) | (tu_edpt_number(ep_addr) & 0x0f); USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; @@ -233,16 +236,16 @@ static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggl /** Set device address to communicate */ -static void update_device_address(uint8_t dev_addr) +static void hardware_update_device_address(uint8_t dev_addr) { // Keep the bit of GP_BIT. Other 7bits are actual device address. USBOTG_H_FS->DEV_ADDR = (USBOTG_H_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | (dev_addr & USBFS_USB_ADDR_MASK); } /** Set port speed */ -static void update_port_speed(tusb_speed_t speed) +static void hardware_update_port_speed(tusb_speed_t speed) { - LOG_CH32_USBFSH("update_port_speed(%s)\r\n", speed == TUSB_SPEED_FULL ? "Full" : speed == TUSB_SPEED_LOW ? "Low" : "(invalid)"); + LOG_CH32_USBFSH("hardware_update_port_speed(%s)\r\n", speed == TUSB_SPEED_FULL ? "Full" : speed == TUSB_SPEED_LOW ? "Low" : "(invalid)"); switch (speed) { case TUSB_SPEED_LOW: USBOTG_H_FS->BASE_CTRL |= USBFS_UC_LOW_SPEED; @@ -255,10 +258,22 @@ static void update_port_speed(tusb_speed_t speed) USBOTG_H_FS->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN; return; default: - PANIC("update_port_speed(%d)\r\n", speed); + PANIC("hardware_update_port_speed(%d)\r\n", speed); } } + +static void hardware_set_port_address_speed(uint8_t dev_addr) { + hardware_update_device_address(dev_addr); + tusb_speed_t rhport_speed = hcd_port_speed_get(0); + tusb_speed_t dev_speed = tuh_speed_get(dev_addr); + hardware_update_port_speed(dev_speed); + if (rhport_speed == TUSB_SPEED_FULL && dev_speed == TUSB_SPEED_LOW) { + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; + } +} + + static bool hardware_device_attached(void) { return USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH; @@ -285,15 +300,30 @@ bool hcd_deinit(uint8_t rhport) return true; } + +static bool int_state_for_portreset = false; + void hcd_port_reset(uint8_t rhport) { (void)rhport; LOG_CH32_USBFSH("hcd_port_reset()\r\n"); - NVIC_DisableIRQ(USBFS_IRQn); - update_device_address( 0x00 ); + int_state_for_portreset = interrupt_enabled; + // NVIC_DisableIRQ(USBFS_IRQn); + hcd_int_disable(rhport); + hardware_update_device_address(0x00); + + // USBOTG_H_FS->HOST_SETUP = 0x00; USBOTG_H_FS->HOST_CTRL |= USBFS_UH_BUS_RESET; - osal_task_delay(15); + + return; +} + +void hcd_port_reset_end(uint8_t rhport) +{ + (void)rhport; + LOG_CH32_USBFSH("hcd_port_reset_end()\r\n"); + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_BUS_RESET; osal_task_delay(2); @@ -301,23 +331,19 @@ void hcd_port_reset(uint8_t rhport) { if (hcd_port_speed_get(0) == TUSB_SPEED_LOW) { - update_port_speed(TUSB_SPEED_LOW); + hardware_update_port_speed(TUSB_SPEED_LOW); } } USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; - return; -} - -void hcd_port_reset_end(uint8_t rhport) -{ - (void)rhport; - LOG_CH32_USBFSH("hcd_port_reset_end()\r\n"); // Suppress the attached event USBOTG_H_FS->INT_FG |= USBFS_UIF_DETECT; - NVIC_EnableIRQ(USBFS_IRQn); + + if (int_state_for_portreset) { + hcd_int_enable(rhport); + } return; } @@ -363,6 +389,7 @@ void hcd_int_enable(uint8_t rhport) { (void)rhport; NVIC_EnableIRQ(USBFS_IRQn); + interrupt_enabled = true; return; } @@ -371,6 +398,7 @@ void hcd_int_disable(uint8_t rhport) { (void)rhport; NVIC_DisableIRQ(USBFS_IRQn); + interrupt_enabled = false; return; } @@ -437,25 +465,25 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) case USB_PID_OUT: { uint16_t tx_len = USBOTG_H_FS->HOST_TX_LEN; - usb_current_xfer_info.current_xfer_bufferlen -= tx_len; - usb_current_xfer_info.current_xfer_xferred_len += tx_len; - if (usb_current_xfer_info.current_xfer_bufferlen == 0) + usb_current_xfer_info.bufferlen -= tx_len; + usb_current_xfer_info.xferred_len += tx_len; + if (usb_current_xfer_info.bufferlen == 0) { - LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.current_xfer_xferred_len); + LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.xferred_len); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.current_xfer_xferred_len, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.xferred_len, XFER_RESULT_SUCCESS, true); return; } else { LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); - usb_current_xfer_info.current_xfer_buffer += tx_len; + usb_current_xfer_info.buffer += tx_len; uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > usb_current_xfer_info.current_xfer_bufferlen) + if (copylen > usb_current_xfer_info.bufferlen) { - copylen = usb_current_xfer_info.current_xfer_bufferlen; + copylen = usb_current_xfer_info.bufferlen; } - memcpy(USBFS_TX_Buf, usb_current_xfer_info.current_xfer_buffer, copylen); + memcpy(USBFS_TX_Buf, usb_current_xfer_info.buffer, copylen); hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); return; } @@ -463,15 +491,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) case USB_PID_IN: { uint16_t received_len = USBOTG_H_FS->RX_LEN; - usb_current_xfer_info.current_xfer_xferred_len += received_len; - uint16_t xferred_len = usb_current_xfer_info.current_xfer_xferred_len; + usb_current_xfer_info.xferred_len += received_len; + uint16_t xferred_len = usb_current_xfer_info.xferred_len; LOG_CH32_USBFSH("Read %d bytes\r\n", received_len); - // if (received_len > 0 && (usb_current_xfer_info.current_xfer_buffer == NULL || usb_current_xfer_info.current_xfer_bufferlen == 0)) { + // if (received_len > 0 && (usb_current_xfer_info.buffer == NULL || usb_current_xfer_info.bufferlen == 0)) { // PANIC("Data received but buffer not set\r\n"); // } - memcpy(usb_current_xfer_info.current_xfer_buffer, USBFS_RX_Buf, received_len); - usb_current_xfer_info.current_xfer_buffer += received_len; - if ((received_len < edpt_info->max_packet_size) || (xferred_len == usb_current_xfer_info.current_xfer_bufferlen)) + memcpy(usb_current_xfer_info.buffer, USBFS_RX_Buf, received_len); + usb_current_xfer_info.buffer += received_len; + if ((received_len < edpt_info->max_packet_size) || (xferred_len == usb_current_xfer_info.bufferlen)) { // USB device sent all data. LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); @@ -506,8 +534,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) else if (response_pid == USB_PID_NAK) { LOG_CH32_USBFSH("NAK reposense\r\n"); - uint32_t elapsed_time = board_millis() - usb_current_xfer_info.current_xfer_packet_start_millis; - if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT && (elapsed_time > USB_INTERRUPT_XFER_TIMEOUT_MILLIS)) + uint32_t elapsed_time = board_millis() - usb_current_xfer_info.start_ms; + if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT) { usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); @@ -564,16 +592,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type) != NULL, false); } - update_device_address(dev_addr); - if (dev_addr == 0x00 && ep_num == 0x00) - { - // It assumes first open for the device, so make the port enable - tusb_speed_t device_speed = hcd_port_speed_get(rhport); - update_port_speed(device_speed); USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; - } + + hardware_set_port_address_speed(dev_addr); return true; } @@ -582,9 +605,10 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * { (void)rhport; - while (usb_current_xfer_info.is_busy) { - osal_task_delay(1); - } + LOG_CH32_USBFSH("hcd_edpt_xfer(%d, 0x%02x, 0x%02x, ...)\r\n", rhport, dev_addr, ep_addr); + + while (usb_current_xfer_info.is_busy) { } + usb_current_xfer_info.is_busy = true; usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); @@ -593,16 +617,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); } - update_device_address(dev_addr); - tusb_speed_t device_speed = hcd_port_speed_get(rhport); - update_port_speed(device_speed); + hardware_set_port_address_speed(dev_addr); usb_current_xfer_info.dev_addr = dev_addr; usb_current_xfer_info.ep_addr = ep_addr; - usb_current_xfer_info.current_xfer_buffer = buffer; - usb_current_xfer_info.current_xfer_bufferlen = buflen; - usb_current_xfer_info.current_xfer_packet_start_millis = board_millis(); - usb_current_xfer_info.current_xfer_xferred_len = 0; + usb_current_xfer_info.buffer = buffer; + usb_current_xfer_info.bufferlen = buflen; + usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.xferred_len = 0; if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { @@ -628,7 +650,6 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) (void) rhport; (void) dev_addr; (void) ep_addr; - LOG_CH32_USBFSH("hcd_edpt_abort_xfer(%d, 0x%02x, 0x%02x)\r\n", rhport, dev_addr, ep_addr); return false; } @@ -637,19 +658,13 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet { (void)rhport; - if (usb_current_xfer_info.is_busy) { - osal_task_delay(1); - } + while (usb_current_xfer_info.is_busy) { } + usb_current_xfer_info.is_busy = true; LOG_CH32_USBFSH("hcd_setup_send(rhport=%d, dev_addr=0x%02x, %p)\r\n", rhport, dev_addr, setup_packet); - // loopdelay(SystemCoreClock / 1000000 * 100); - loopdelay(1); - - update_device_address(dev_addr); - tusb_speed_t device_speed = hcd_port_speed_get(rhport); - update_port_speed(device_speed); + hardware_set_port_address_speed(dev_addr); usb_edpt_t* edpt_info_tx = get_edpt_record(dev_addr, 0x00); usb_edpt_t* edpt_info_rx = get_edpt_record(dev_addr, 0x80); @@ -667,10 +682,10 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet uint8_t ep_addr = (setup_packet[0] & 0x80) ? 0x80 : 0x00; usb_current_xfer_info.dev_addr = dev_addr; usb_current_xfer_info.ep_addr = ep_addr; - usb_current_xfer_info.current_xfer_packet_start_millis = board_millis(); - usb_current_xfer_info.current_xfer_buffer = USBFS_TX_Buf; - usb_current_xfer_info.current_xfer_bufferlen = setup_packet_datalen; - usb_current_xfer_info.current_xfer_xferred_len = 0; + usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.buffer = USBFS_TX_Buf; + usb_current_xfer_info.bufferlen = setup_packet_datalen; + usb_current_xfer_info.xferred_len = 0; hardware_start_xfer(USB_PID_SETUP, 0, 0); @@ -690,6 +705,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) memcpy(USBFS_TX_Buf, setup_request_clear_stall, 8); USBOTG_H_FS->HOST_TX_LEN = 8; + bool prev_int_state = interrupt_enabled; hcd_int_disable(0); USBOTG_H_FS->HOST_EP_PID = (USB_PID_SETUP << 4) | 0x00; @@ -700,7 +716,9 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) (void)response_pid; LOG_CH32_USBFSH("hcd_edpt_clear_stall() response pid=0x%02x\r\n", response_pid); + if (prev_int_state) { hcd_int_enable(0); + } return true; } -- cgit v1.3.1 From 31b3a2f63bcf4f1969ada9d0c099444959b37388 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Sat, 15 Mar 2025 11:20:57 -0700 Subject: Fix 3031: implement tuh_midi_itf_get_info() --- src/class/midi/midi_host.c | 23 +++++++++++++++++++++++ src/class/midi/midi_host.h | 4 ++++ 2 files changed, 27 insertions(+) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 4d824e04c..9019d476b 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -346,6 +346,29 @@ uint8_t tuh_midi_itf_get_index(uint8_t daddr, uint8_t itf_num) { return TUSB_INDEX_INVALID_8; } +bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info) +{ + midih_interface_t* p_midi = &_midi_host[idx]; + TU_VERIFY(p_midi && info); + + info->daddr = p_midi->daddr; + + // re-construct descriptor + tusb_desc_interface_t* desc = &info->desc; + desc->bLength = sizeof(tusb_desc_interface_t); + desc->bDescriptorType = TUSB_DESC_INTERFACE; + + desc->bInterfaceNumber = p_midi->bInterfaceNumber; + desc->bAlternateSetting = 0; + desc->bNumEndpoints = (p_midi->ep_in != 0 ? 1:0) + (p_midi->ep_out != 0 ? 1:0); + desc->bInterfaceClass = TUSB_CLASS_AUDIO; + desc->bInterfaceSubClass = AUDIO_SUBCLASS_MIDI_STREAMING; + desc->bInterfaceProtocol = 0; + desc->iInterface = 0; + + return true; +} + uint8_t tuh_midi_get_tx_cable_count (uint8_t idx) { TU_VERIFY(idx < CFG_TUH_MIDI); midih_interface_t *p_midi = &_midi_host[idx]; diff --git a/src/class/midi/midi_host.h b/src/class/midi/midi_host.h index b06bb43d7..67df25a82 100644 --- a/src/class/midi/midi_host.h +++ b/src/class/midi/midi_host.h @@ -90,6 +90,10 @@ bool tuh_midi_mounted(uint8_t idx); // return TUSB_INDEX_INVALID_8 (0xFF) if not found uint8_t tuh_midi_itf_get_index(uint8_t daddr, uint8_t itf_num); +// Get Interface information +// return true if index is correct and interface is currently mounted +bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info); + // return the number of virtual midi cables on the device's IN endpoint uint8_t tuh_midi_get_rx_cable_count(uint8_t idx); -- cgit v1.3.1 From 5ecea4eefe13ea93095da710dfcf3b3fee578c8e Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Tue, 18 Mar 2025 07:41:49 -0700 Subject: fix tuh_midi_itf_get_info() desc->iInterface value --- src/class/midi/midi_host.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 9019d476b..d6d204b7b 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -82,6 +82,7 @@ typedef struct { } ep_stream; bool mounted; + uint8_t iInterface; // for tuh_midi_itf_get_info() }midih_interface_t; typedef struct { @@ -228,6 +229,7 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d TU_LOG_DRV("MIDI opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr); p_midi->bInterfaceNumber = desc_itf->bInterfaceNumber; + p_midi->iInterface = desc_itf->iInterface; p_midi->itf_count++; desc_cb.desc_midi = desc_itf; @@ -346,8 +348,7 @@ uint8_t tuh_midi_itf_get_index(uint8_t daddr, uint8_t itf_num) { return TUSB_INDEX_INVALID_8; } -bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info) -{ +bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { midih_interface_t* p_midi = &_midi_host[idx]; TU_VERIFY(p_midi && info); @@ -364,7 +365,7 @@ bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info) desc->bInterfaceClass = TUSB_CLASS_AUDIO; desc->bInterfaceSubClass = AUDIO_SUBCLASS_MIDI_STREAMING; desc->bInterfaceProtocol = 0; - desc->iInterface = 0; + desc->iInterface = p_midi->iInterface; return true; } -- cgit v1.3.1 From 62f00bdf5d8b2a5941aed3d96865bbe24b117455 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Tue, 18 Mar 2025 07:42:47 -0700 Subject: Fix compiler conversion error warning --- src/class/midi/midi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index d6d204b7b..85253f5ca 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -361,7 +361,7 @@ bool tuh_midi_itf_get_info(uint8_t idx, tuh_itf_info_t* info) { desc->bInterfaceNumber = p_midi->bInterfaceNumber; desc->bAlternateSetting = 0; - desc->bNumEndpoints = (p_midi->ep_in != 0 ? 1:0) + (p_midi->ep_out != 0 ? 1:0); + desc->bNumEndpoints = (uint8_t)((p_midi->ep_in != 0 ? 1:0) + (p_midi->ep_out != 0 ? 1:0)); desc->bInterfaceClass = TUSB_CLASS_AUDIO; desc->bInterfaceSubClass = AUDIO_SUBCLASS_MIDI_STREAMING; desc->bInterfaceProtocol = 0; -- cgit v1.3.1 From 05e4f8b77786a6bbc4a43e3b8574689714ca3138 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Wed, 19 Mar 2025 05:57:01 -0700 Subject: Move iInterface per review comment --- src/class/midi/midi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 85253f5ca..cfea0c080 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -56,6 +56,7 @@ TU_ATTR_WEAK void tuh_midi_tx_cb(uint8_t idx, uint32_t xferred_bytes) { (void) i typedef struct { uint8_t daddr; uint8_t bInterfaceNumber; // interface number of MIDI streaming + uint8_t iInterface; uint8_t itf_count; // number of interface including Audio Control + MIDI streaming uint8_t ep_in; // IN endpoint address @@ -82,7 +83,6 @@ typedef struct { } ep_stream; bool mounted; - uint8_t iInterface; // for tuh_midi_itf_get_info() }midih_interface_t; typedef struct { -- cgit v1.3.1 From 4b46493cb4f8699c95e01783eee5cf90ca7810e2 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Thu, 20 Mar 2025 06:27:23 -0700 Subject: Fix #3033: Increase array bounds and test for overflow --- src/class/midi/midi_host.c | 3 ++- src/class/midi/midi_host.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index cfea0c080..68e46aca3 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -254,7 +254,8 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d TU_LOG_DRV(" Jack %s %s descriptor \r\n", tu_desc_subtype(p_desc) == MIDI_CS_INTERFACE_IN_JACK ? "IN" : "OUT", p_desc[3] == MIDI_JACK_EXTERNAL ? "External" : "Embedded"); - desc_cb.desc_jack[desc_cb.jack_num++] = p_desc; + if (desc_cb.jack_num < TU_ARRAY_SIZE(desc_cb.desc_jack)) + desc_cb.desc_jack[desc_cb.jack_num++] = p_desc; break; } diff --git a/src/class/midi/midi_host.h b/src/class/midi/midi_host.h index 67df25a82..06554a03d 100644 --- a/src/class/midi/midi_host.h +++ b/src/class/midi/midi_host.h @@ -69,7 +69,7 @@ typedef struct { const tusb_desc_endpoint_t* desc_epout; // endpoint OUT descriptor, CS_ENDPOINT is right after uint8_t jack_num; - const uint8_t* desc_jack[16]; // list of jack descriptors (embedded + external) + const uint8_t* desc_jack[32]; // list of jack descriptors (embedded + external) } tuh_midi_descriptor_cb_t; typedef struct { -- cgit v1.3.1 From e54753814befa26742fa8a9805f5b7beac32a963 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 21 Mar 2025 00:11:18 +0700 Subject: enable hil dual for metro m4 with max3421 --- examples/host/device_info/src/main.c | 2 +- src/host/usbh.h | 9 +++------ test/hil/tinyusb.json | 2 +- 3 files changed, 5 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index 775968c16..ac4c46a11 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -81,7 +81,7 @@ void init_freertos_task(void); //-------------------------------------------------------------------- // Main //-------------------------------------------------------------------- -void init_tinyusb(void) { +static void init_tinyusb(void) { // init host stack on configured roothub port tusb_rhport_init_t host_init = { .role = TUSB_ROLE_HOST, diff --git a/src/host/usbh.h b/src/host/usbh.h index 52b4f478c..36bb7c9b2 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -155,8 +155,7 @@ bool tuh_inited(void); void tuh_task_ext(uint32_t timeout_ms, bool in_isr); // Task function should be called in main/rtos loop -TU_ATTR_ALWAYS_INLINE static inline -void tuh_task(void) { +TU_ATTR_ALWAYS_INLINE static inline void tuh_task(void) { tuh_task_ext(UINT32_MAX, false); } @@ -197,16 +196,14 @@ bool tuh_mounted(uint8_t daddr); bool tuh_connected(uint8_t daddr); // Check if device is suspended -TU_ATTR_ALWAYS_INLINE static inline -bool tuh_suspended(uint8_t daddr) { +TU_ATTR_ALWAYS_INLINE static inline bool tuh_suspended(uint8_t daddr) { // TODO implement suspend & resume on host (void) daddr; return false; } // Check if device is ready to communicate with -TU_ATTR_ALWAYS_INLINE static inline -bool tuh_ready(uint8_t daddr) { +TU_ATTR_ALWAYS_INLINE static inline bool tuh_ready(uint8_t daddr) { return tuh_mounted(daddr) && !tuh_suspended(daddr); } diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 7393226eb..c2bbdf5a3 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -60,7 +60,7 @@ "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", "tests": { - "device": true, "host": false, "dual": false, + "device": true, "host": false, "dual": true, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] }, "flasher": { -- cgit v1.3.1 From b0def52f45439c3dc41a0c370115deb54cd443e4 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Fri, 21 Mar 2025 07:13:01 -0700 Subject: Move misplaced statement --- src/class/midi/midi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 68e46aca3..b252e8466 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -591,8 +591,8 @@ uint32_t tuh_midi_stream_read(uint8_t idx, uint8_t *p_cable_num, uint8_t *p_buff break; default: break; - cable_sysex_in_progress &= (uint16_t) ~cable_mask; } + cable_sysex_in_progress &= (uint16_t) ~cable_mask; } else { // Real-time message: can be inserted into a sysex message, // so do don't clear cable_sysex_in_progress bit -- cgit v1.3.1 From 3324a327cbd82d18305030ba2247cbbc71dc9f19 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Fri, 21 Mar 2025 07:14:10 -0700 Subject: Fix #3033: address review comment --- src/class/midi/midi_host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index b252e8466..cd6e115ee 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -254,8 +254,9 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d TU_LOG_DRV(" Jack %s %s descriptor \r\n", tu_desc_subtype(p_desc) == MIDI_CS_INTERFACE_IN_JACK ? "IN" : "OUT", p_desc[3] == MIDI_JACK_EXTERNAL ? "External" : "Embedded"); - if (desc_cb.jack_num < TU_ARRAY_SIZE(desc_cb.desc_jack)) + if (desc_cb.jack_num < TU_ARRAY_SIZE(desc_cb.desc_jack)) { desc_cb.desc_jack[desc_cb.jack_num++] = p_desc; + } break; } -- cgit v1.3.1 From 9f541a3d961e1a75a9c6441cb3564c726292731b Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Mar 2025 22:55:04 +0700 Subject: host: add tuh_enum_descriptor_device_cb() and tuh_enum_descriptor_configuration_cb() callback host: support device with multiple configurations --- src/host/usbh.c | 75 +++++++++++++++++++++++++++++++++------------------------ src/host/usbh.h | 7 ++++-- 2 files changed, 48 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index c87f058cd..308916c9b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -52,21 +52,25 @@ enum { // Weak stubs: invoked if no strong implementation is available //--------------------------------------------------------------------+ TU_ATTR_WEAK bool hcd_deinit(uint8_t rhport) { - (void) rhport; - return false; + (void) rhport; return false; } TU_ATTR_WEAK bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { - (void) rhport; - (void) cfg_id; - (void) cfg_param; + (void) rhport; (void) cfg_id; (void) cfg_param; return false; } +TU_ATTR_WEAK void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device) { + (void) daddr; (void) desc_device; +} + +TU_ATTR_WEAK bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config) { + (void) daddr; (void) cfg_index; (void) desc_config; + return true; +} + TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { - (void) rhport; - (void) eventid; - (void) in_isr; + (void) rhport; (void) eventid; (void) in_isr; } TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) { @@ -126,6 +130,7 @@ typedef struct { uint8_t i_manufacturer; uint8_t i_product; uint8_t i_serial; + uint8_t bNumConfigurations; // Configuration Descriptor // uint8_t interface_count; // bNumInterfaces alias @@ -230,7 +235,6 @@ static usbh_class_driver_t const usbh_class_drivers[] = { }; enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; -enum { CONFIG_NUM = 1 }; // default to use configuration 1 // Additional class drivers implemented by application tu_static usbh_class_driver_t const * _app_driver = NULL; @@ -1372,8 +1376,8 @@ enum { ENUM_CONFIG_DRIVER }; -static bool enum_request_set_addr(void); -static bool _parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg); +static bool enum_request_set_addr(tusb_desc_device_t const* desc_device); +static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg); static void enum_full_complete(void); // process device enumeration @@ -1489,7 +1493,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { #endif case ENUM_SET_ADDR: - enum_request_set_addr(); + enum_request_set_addr((tusb_desc_device_t*) _usbh_epbuf.ctrl); break; case ENUM_GET_DEVICE_DESC: { @@ -1523,6 +1527,9 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_manufacturer = desc_device->iManufacturer; dev->i_product = desc_device->iProduct; dev->i_serial = desc_device->iSerialNumber; + dev->bNumConfigurations = desc_device->bNumConfigurations; + + tuh_enum_descriptor_device_cb(daddr, desc_device); // callback tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE, process_enumeration, ENUM_GET_STRING_MANUFACTURER); @@ -1574,8 +1581,8 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_GET_9BYTE_CONFIG_DESC: { // Get 9-byte for total length - uint8_t const config_idx = CONFIG_NUM - 1; - TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n"); + uint8_t const config_idx = 0; + TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx); TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); break; @@ -1585,25 +1592,32 @@ static void process_enumeration(tuh_xfer_t* xfer) { uint8_t const* desc_config = _usbh_epbuf.ctrl; // Use offsetof to avoid pointer to the odd/misaligned address - uint16_t const total_len = tu_le16toh( - tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))); + uint16_t const total_len = tu_le16toh(tu_unaligned_read16(desc_config + offsetof(tusb_desc_configuration_t, wTotalLength))); // TODO not enough buffer to hold configuration descriptor TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE,); // Get full configuration descriptor - uint8_t const config_idx = CONFIG_NUM - 1; - TU_LOG_USBH("Get Configuration[0] Descriptor\r\n"); + uint8_t const config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex); + TU_LOG_USBH("Get Configuration[%u] Descriptor\r\n", config_idx); TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len, process_enumeration, ENUM_SET_CONFIG),); break; } - case ENUM_SET_CONFIG: - // tuh_desc_configuration_cb(daddr, CONFIG_NUM-1, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl); - - TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),); + case ENUM_SET_CONFIG: { + uint8_t config_idx = (uint8_t) tu_le16toh(xfer->setup->wIndex); + if (tuh_enum_descriptor_configuration_cb(daddr, config_idx, (const tusb_desc_configuration_t*) _usbh_epbuf.ctrl)) { + TU_ASSERT(tuh_configuration_set(daddr, config_idx+1, process_enumeration, ENUM_CONFIG_DRIVER),); + } else { + config_idx++; + TU_ASSERT(config_idx < dev->bNumConfigurations,); + TU_LOG_USBH("Get Configuration[%u] Descriptor (9 bytes)\r\n", config_idx); + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9, + process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); + } break; + } case ENUM_CONFIG_DRIVER: { TU_LOG_USBH("Device configured\r\n"); @@ -1613,7 +1627,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Parse configuration & set up drivers // driver_open() must not make any usb transfer - TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),); + TU_ASSERT(enum_parse_configuration_desc(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),); // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. @@ -1624,14 +1638,11 @@ static void process_enumeration(tuh_xfer_t* xfer) { } default: - // stop enumeration if unknown state - enum_full_complete(); + enum_full_complete(); // stop enumeration if unknown state break; } } - - static bool enum_new_device(hcd_event_t* event) { _dev0.rhport = event->rhport; _dev0.hub_addr = event->connection.hub_addr; @@ -1701,9 +1712,7 @@ static uint8_t get_new_address(bool is_hub) { return 0; // invalid address } -static bool enum_request_set_addr(void) { - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; - +static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) { // Get new address uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); TU_ASSERT(new_addr != 0); @@ -1741,7 +1750,7 @@ static bool enum_request_set_addr(void) { return true; } -static bool _parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) { +static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) { usbh_device_t* dev = get_device(dev_addr); uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength); uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + total_len; @@ -1858,7 +1867,9 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { TU_LOG_USBH("HUB address = %u is mounted\r\n", dev_addr); }else { // Invoke callback if available - if (tuh_mount_cb) tuh_mount_cb(dev_addr); + if (tuh_mount_cb) { + tuh_mount_cb(dev_addr); + } } } } diff --git a/src/host/usbh.h b/src/host/usbh.h index 36bb7c9b2..d95bb9b57 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -100,10 +100,13 @@ typedef union { //--------------------------------------------------------------------+ // Invoked when enumeration get device descriptor -// TU_ATTR_WEAK void tuh_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device); +// Device is not ready to communicate yet, application can copy the descriptor if needed +void tuh_enum_descriptor_device_cb(uint8_t daddr, const tusb_desc_device_t *desc_device); // Invoked when enumeration get configuration descriptor -// TU_ATTR_WEAK void tuh_desc_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config); +// For multi-configuration device return false to skip, true to proceed with this configuration (may not be implemented yet) +// Device is not ready to communicate yet, application can copy the descriptor if needed +bool tuh_enum_descriptor_configuration_cb(uint8_t daddr, uint8_t cfg_index, const tusb_desc_configuration_t *desc_config); // Invoked when a device is mounted (configured) TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr); -- cgit v1.3.1 From db537861b2e39debe09009762a968edfcd4a9618 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 24 Mar 2025 22:58:21 +0700 Subject: device cdc: rename tud_cdc_configure_fifo/_t to tud_cdc_configure/_t add tx_overwritabe_if_not_connected for cdc driver configure --- src/class/cdc/cdc_device.c | 38 ++++++++++++++++++++------------------ src/class/cdc/cdc_device.h | 22 ++++++++++++++++------ src/common/tusb_fifo.c | 7 +++++-- 3 files changed, 41 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index efb672201..4d19adeb4 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -82,7 +82,7 @@ typedef struct { static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC]; CFG_TUD_MEM_SECTION static cdcd_epbuf_t _cdcd_epbuf[CFG_TUD_CDC]; -static tud_cdc_configure_fifo_t _cdcd_fifo_cfg; +static tud_cdc_configure_t _cdcd_cfg = TUD_CDC_CONFIGURE_DEFAULT(); static bool _prep_out_transaction(uint8_t itf) { const uint8_t rhport = 0; @@ -119,9 +119,9 @@ static bool _prep_out_transaction(uint8_t itf) { // APPLICATION API //--------------------------------------------------------------------+ -bool tud_cdc_configure_fifo(const tud_cdc_configure_fifo_t* cfg) { - TU_VERIFY(cfg); - _cdcd_fifo_cfg = (*cfg); +bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg) { + TU_VERIFY(driver_cfg); + _cdcd_cfg = *driver_cfg; return true; } @@ -175,7 +175,7 @@ void tud_cdc_n_read_flush(uint8_t itf) { //--------------------------------------------------------------------+ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; - uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); + uint16_t wr_count = tu_fifo_write_n(&p_cdc->tx_ff, buffer, (uint16_t) TU_MIN(bufsize, UINT16_MAX)); // flush if queue more than packet size if (tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE @@ -186,7 +186,7 @@ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) { tud_cdc_n_write_flush(itf); } - return ret; + return wr_count; } uint32_t tud_cdc_n_write_flush(uint8_t itf) { @@ -233,8 +233,6 @@ bool tud_cdc_n_write_clear(uint8_t itf) { //--------------------------------------------------------------------+ void cdcd_init(void) { tu_memclr(_cdcd_itf, sizeof(_cdcd_itf)); - tu_memclr(&_cdcd_fifo_cfg, sizeof(_cdcd_fifo_cfg)); - for (uint8_t i = 0; i < CFG_TUD_CDC; i++) { cdcd_interface_t* p_cdc = &_cdcd_itf[i]; @@ -249,10 +247,10 @@ void cdcd_init(void) { // Config RX fifo tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false); - // Config TX fifo as overwritable at initialization and will be changed to non-overwritable - // if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal. - // In this way, the most current data is prioritized. - tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true); + // TX fifo can be configured to change to overwritable if not connected (DTR bit not set). Without DTR we do not + // know if data is actually polled by terminal. This way the most current data is prioritized. + // Default: is overwritable + tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, _cdcd_cfg.tx_overwritabe_if_not_connected); #if OSAL_MUTEX_REQUIRED osal_mutex_t mutex_rd = osal_mutex_create(&p_cdc->rx_ff_mutex); @@ -294,13 +292,13 @@ void cdcd_reset(uint8_t rhport) { cdcd_interface_t* p_cdc = &_cdcd_itf[i]; tu_memclr(p_cdc, ITF_MEM_RESET_SIZE); - if (!_cdcd_fifo_cfg.rx_persistent) { + if (!_cdcd_cfg.rx_persistent) { tu_fifo_clear(&p_cdc->rx_ff); } - if (!_cdcd_fifo_cfg.tx_persistent) { + if (!_cdcd_cfg.tx_persistent) { tu_fifo_clear(&p_cdc->tx_ff); } - tu_fifo_set_overwritable(&p_cdc->tx_ff, true); + tu_fifo_set_overwritable(&p_cdc->tx_ff, _cdcd_cfg.tx_overwritabe_if_not_connected); } } @@ -414,8 +412,12 @@ bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_requ p_cdc->line_state = (uint8_t) request->wValue; - // Disable fifo overwriting if DTR bit is set - tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); + // If enabled: fifo overwriting is disabled if DTR bit is set and vice versa + if (_cdcd_cfg.tx_overwritabe_if_not_connected) { + tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr); + } else { + tu_fifo_set_overwritable(&p_cdc->tx_ff, false); + } TU_LOG_DRV(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts); @@ -496,7 +498,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ // xferred_bytes is multiple of EP Packet size and not zero if (!tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE - 1)))) { if (usbd_edpt_claim(rhport, p_cdc->ep_in)) { - usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0); + TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0)); } } } diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index 2d5ba2575..b653ebd74 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -48,14 +48,24 @@ //--------------------------------------------------------------------+ // Driver Configuration //--------------------------------------------------------------------+ - typedef struct TU_ATTR_PACKED { - uint8_t rx_persistent : 1; // keep rx fifo on bus reset or disconnect - uint8_t tx_persistent : 1; // keep tx fifo on bus reset or disconnect -} tud_cdc_configure_fifo_t; + uint8_t rx_persistent : 1; // keep rx fifo data even with bus reset or disconnect + uint8_t tx_persistent : 1; // keep tx fifo data even with reset or disconnect + uint8_t tx_overwritabe_if_not_connected : 1; // if not connected, tx fifo can be overwritten +} tud_cdc_configure_t; + +#define TUD_CDC_CONFIGURE_DEFAULT() { \ + .rx_persistent = 0, \ + .tx_persistent = 0, \ + .tx_overwritabe_if_not_connected = 1, \ +} + +// Configure CDC driver behavior +bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg); -// Configure CDC FIFOs behavior -bool tud_cdc_configure_fifo(tud_cdc_configure_fifo_t const* cfg); +// Backward compatible +#define tud_cdc_configure_fifo_t tud_cdc_configure_t +#define tud_cdc_configure_fifo tud_cdc_configure //--------------------------------------------------------------------+ // Application API (Multiple Ports) i.e. CFG_TUD_CDC > 1 diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index 5f2dcabad..ecf002b09 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -916,8 +916,11 @@ bool tu_fifo_clear(tu_fifo_t *f) Overwritable mode the fifo is set to */ /******************************************************************************/ -bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) -{ +bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable) { + if (f->overwritable == overwritable) { + return true; + } + _ff_lock(f->mutex_wr); _ff_lock(f->mutex_rd); -- cgit v1.3.1 From 65e01fff2e7ab5302baa45bdd81a1d774e269452 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Mar 2025 16:15:58 +0700 Subject: add tuh_edpt_close() API, it will abort any pending transfer implement hcd_edpt_close() for pio-usb and max3421e, also move max3421e api into its own header. --- examples/host/bare_api/src/main.c | 254 +++++++++++-------------- src/host/hcd.h | 3 + src/host/usbh.c | 6 + src/host/usbh.h | 7 + src/portable/analog/max3421/hcd_max3421.c | 40 ++-- src/portable/analog/max3421/hcd_max3421.h | 63 ++++++ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 5 + tools/get_deps.py | 4 +- 8 files changed, 218 insertions(+), 164 deletions(-) create mode 100644 src/portable/analog/max3421/hcd_max3421.h (limited to 'src') diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index f582f4f5a..0c76ff0c9 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -55,16 +55,15 @@ uint8_t* get_hid_buf(uint8_t daddr); void free_hid_buf(uint8_t daddr); /*------------- MAIN -------------*/ -int main(void) -{ +int main(void) { board_init(); printf("TinyUSB Bare API Example\r\n"); // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .role = TUSB_ROLE_HOST, - .speed = TUSB_SPEED_AUTO + .role = TUSB_ROLE_HOST, + .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUH_RHPORT, &host_init); @@ -72,8 +71,7 @@ int main(void) board_init_after_tusb(); } - while (1) - { + while (1) { // tinyusb host task tuh_task(); led_blinking_task(); @@ -85,8 +83,7 @@ int main(void) /*------------- TinyUSB Callbacks -------------*/ // Invoked when device is mounted (configured) -void tuh_mount_cb (uint8_t daddr) -{ +void tuh_mount_cb(uint8_t daddr) { printf("Device attached, address = %d\r\n", daddr); // Get Device Descriptor @@ -95,8 +92,7 @@ void tuh_mount_cb (uint8_t daddr) } /// Invoked when device is unmounted (bus reset/unplugged) -void tuh_umount_cb(uint8_t daddr) -{ +void tuh_umount_cb(uint8_t daddr) { printf("Device removed, address = %d\r\n", daddr); free_hid_buf(daddr); } @@ -104,11 +100,8 @@ void tuh_umount_cb(uint8_t daddr) //--------------------------------------------------------------------+ // Device Descriptor //--------------------------------------------------------------------+ - -void print_device_descriptor(tuh_xfer_t* xfer) -{ - if ( XFER_RESULT_SUCCESS != xfer->result ) - { +void print_device_descriptor(tuh_xfer_t *xfer) { + if (XFER_RESULT_SUCCESS != xfer->result) { printf("Failed to get device descriptor\r\n"); return; } @@ -131,33 +124,29 @@ void print_device_descriptor(tuh_xfer_t* xfer) // Get String descriptor using Sync API uint16_t temp_buf[128]; - printf(" iManufacturer %u " , desc_device.iManufacturer); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)) ) - { + printf(" iManufacturer %u ", desc_device.iManufacturer); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iProduct %u " , desc_device.iProduct); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iProduct %u ", desc_device.iProduct); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iSerialNumber %u " , desc_device.iSerialNumber); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iSerialNumber %u ", desc_device.iSerialNumber); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations); + printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations); // Get configuration descriptor with sync API - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) - { - parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) { + parse_config_descriptor(daddr, (tusb_desc_configuration_t *) temp_buf); } } @@ -171,37 +160,33 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); // simple configuration parser to open and listen to HID Endpoint IN -void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) -{ - uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); - uint8_t const* p_desc = tu_desc_next(desc_cfg); +void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const *desc_cfg) { + uint8_t const *desc_end = ((uint8_t const *) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); + uint8_t const *p_desc = tu_desc_next(desc_cfg); // parse each interfaces - while( p_desc < desc_end ) - { + while (p_desc < desc_end) { uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor - if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) - { - tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) { + tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; assoc_itf_count = desc_iad->bInterfaceCount; - p_desc = tu_desc_next(p_desc); // next to Interface + p_desc = tu_desc_next(p_desc);// next to Interface } // must be interface from now - if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return; - tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc; + if (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) { return; } + tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *) p_desc; - uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc)); + uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end - p_desc)); // probably corrupted descriptor - if(drv_len < sizeof(tusb_desc_interface_t)) return; + if (drv_len < sizeof(tusb_desc_interface_t)) { return; } // only open and listen to HID endpoint IN - if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) - { + if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) { open_hid_interface(dev_addr, desc_itf, drv_len); } @@ -210,25 +195,21 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* } } -uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) -{ - uint8_t const* p_desc = (uint8_t const*) desc_itf; +uint16_t count_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len) { + uint8_t const *p_desc = (uint8_t const *) desc_itf; uint16_t len = 0; - while (itf_count--) - { + while (itf_count--) { // Next on interface desc len += tu_desc_len(desc_itf); p_desc = tu_desc_next(p_desc); - while (len < max_len) - { + while (len < max_len) { // return on IAD regardless of itf count - if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; + if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) { return len; } - if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) - { + if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == 0) { break; } @@ -246,46 +227,45 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void hid_report_received(tuh_xfer_t* xfer); -void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) -{ +void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); // corrupted descriptor - if (max_len < drv_len) return; + if (max_len < drv_len) { return; } uint8_t const *p_desc = (uint8_t const *) desc_itf; // HID descriptor p_desc = tu_desc_next(p_desc); tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc; - if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return; + if (HID_DESC_TYPE_HID != desc_hid->bDescriptorType) { return; } // Endpoint descriptor p_desc = tu_desc_next(p_desc); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; - - for(int i = 0; i < desc_itf->bNumEndpoints; i++) - { - if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return; - - if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) - { - // skip if failed to open endpoint - if ( ! tuh_edpt_open(daddr, desc_ep) ) return; - - uint8_t* buf = get_hid_buf(daddr); - if (!buf) return; // out of memory - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = desc_ep->bEndpointAddress, - .buflen = 64, - .buffer = buf, - .complete_cb = hid_report_received, - .user_data = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + + for (int i = 0; i < desc_itf->bNumEndpoints; i++) { + if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) { return; } + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + if (!tuh_edpt_open(daddr, desc_ep)) { + return; // skip if failed to open endpoint + } + + uint8_t *buf = get_hid_buf(daddr); + if (!buf) { + return;// out of memory + } + + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = desc_ep->bEndpointAddress, + .buflen = 64, + .buffer = buf, + .complete_cb = hid_report_received, + .user_data = (uintptr_t) buf,// since buffer is not available in callback, use user data to store the buffer }; // submit transfer for this EP @@ -299,18 +279,17 @@ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, ui } } -void hid_report_received(tuh_xfer_t* xfer) -{ +void hid_report_received(tuh_xfer_t *xfer) { // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback - uint8_t* buf = (uint8_t*) xfer->user_data; + uint8_t *buf = (uint8_t *) xfer->user_data; - if (xfer->result == XFER_RESULT_SUCCESS) - { + if (xfer->result == XFER_RESULT_SUCCESS) { printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr); - for(uint32_t i=0; iactual_len; i++) - { - if (i%16 == 0) printf("\r\n "); + for (uint32_t i = 0; i < xfer->actual_len; i++) { + if (i % 16 == 0) { + printf("\r\n "); + } printf("%02X ", buf[i]); } printf("\r\n"); @@ -329,12 +308,9 @@ void hid_report_received(tuh_xfer_t* xfer) //--------------------------------------------------------------------+ // get an buffer from pool -uint8_t* get_hid_buf(uint8_t daddr) -{ - for(size_t i=0; i> 6 & 0x1F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } else { - // TODO: Verify surrogate. - *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } - // TODO: Handle UTF-16 code points that take two entries. + // TODO: Check for runover. + (void) utf8_len; + // Get the UTF-16 length out of the data itself. + + for (size_t i = 0; i < utf16_len; i++) { + uint16_t chr = utf16[i]; + if (chr < 0x80) { + *utf8++ = chr & 0xffu; + } else if (chr < 0x800) { + *utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); + } else { + // TODO: Verify surrogate. + *utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); } + // TODO: Handle UTF-16 code points that take two entries. + } } // Count how many bytes a utf-16-le encoded string will take in utf-8. static int _count_utf8_bytes(const uint16_t *buf, size_t len) { - size_t total_bytes = 0; - for (size_t i = 0; i < len; i++) { - uint16_t chr = buf[i]; - if (chr < 0x80) { - total_bytes += 1; - } else if (chr < 0x800) { - total_bytes += 2; - } else { - total_bytes += 3; - } - // TODO: Handle UTF-16 code points that take two entries. + size_t total_bytes = 0; + for (size_t i = 0; i < len; i++) { + uint16_t chr = buf[i]; + if (chr < 0x80) { + total_bytes += 1; + } else if (chr < 0x800) { + total_bytes += 2; + } else { + total_bytes += 3; } - return (int) total_bytes; + // TODO: Handle UTF-16 code points that take two entries. + } + return (int) total_bytes; } static void print_utf16(uint16_t *temp_buf, size_t buf_len) { - if ((temp_buf[0] & 0xff) == 0) return; // empty - size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); - size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); - _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); - ((uint8_t*) temp_buf)[utf8_len] = '\0'; + if ((temp_buf[0] & 0xff) == 0) return;// empty + size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); + size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); + _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); + ((uint8_t *) temp_buf)[utf8_len] = '\0'; - printf("%s", (char*)temp_buf); + printf("%s", (char *) temp_buf); } diff --git a/src/host/hcd.h b/src/host/hcd.h index 56b6fdb5d..aa9e9cf3b 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -165,6 +165,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); +// Close an endpoint +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr); + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); diff --git a/src/host/usbh.c b/src/host/usbh.c index 308916c9b..5925a7be0 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -994,6 +994,12 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) { return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep); } +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr) { + TU_VERIFY(0 != tu_edpt_number(ep_addr)); // cannot close EP0 + tuh_edpt_abort_xfer(daddr, ep_addr); // abort any pending transfer + return hcd_edpt_close(usbh_get_rhport(daddr), daddr, ep_addr); +} + bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { usbh_device_t* dev = get_device(dev_addr); TU_VERIFY(dev); diff --git a/src/host/usbh.h b/src/host/usbh.h index d95bb9b57..4829a8183 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -33,6 +33,10 @@ #include "common/tusb_common.h" +#if CFG_TUH_MAX3421 +#include "portable/analog/max3421/hcd_max3421.h" +#endif + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -227,6 +231,9 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer); // Open a non-control endpoint bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep); +// Close a non-control endpoint, it will abort any pending transfer +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr); + // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index c5e924266..3fbf950a4 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -252,28 +252,6 @@ static tuh_configure_max3421_t _tuh_cfg = { .pinctl = 0, // default: negative edge interrupt }; -//--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E -// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application -// - reg_read(), reg_write(): is implemented by this driver, can be used by application -//--------------------------------------------------------------------+ - -// API to control MAX3421 SPI CS -extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); - -// API to transfer data with MAX3421 SPI -// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only -extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); - -// API to enable/disable MAX3421 INTR pin interrupt -extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); - -// API to read MAX3421's register. Implemented by TinyUSB -uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); - -// API to write MAX3421's register. Implemented by TinyUSB -bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); - //--------------------------------------------------------------------+ // SPI Commands and Helper //--------------------------------------------------------------------+ @@ -632,6 +610,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e if (daddr == 0 && ep_num == 0) { ep = &_hcd_data.ep[0]; }else { + if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) { + return false; // endpoint already opened + } ep = allocate_ep(); TU_ASSERT(ep); ep->daddr = daddr; @@ -645,6 +626,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; + uint8_t const ep_num = tu_edpt_number(ep_addr); + tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr); + max3421_ep_t * ep = find_ep_not_addr0(daddr, ep_num, ep_dir); + + if (!ep) { + return false; // not opened + } + + tu_memclr(ep, sizeof(max3421_ep_t)); + + return true; +} + /* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes. * Then the microcontroller writes the SNDBC register, which this does three things: * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send. diff --git a/src/portable/analog/max3421/hcd_max3421.h b/src/portable/analog/max3421/hcd_max3421.h new file mode 100644 index 000000000..4631fa21a --- /dev/null +++ b/src/portable/analog/max3421/hcd_max3421.h @@ -0,0 +1,63 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef TUSB_HCD_MAX3421_H +#define TUSB_HCD_MAX3421_H + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// SPI transfer API with MAX3421E are implemented by application +// - spi_cs_api(), spi_xfer_api(), int_api() +//--------------------------------------------------------------------+ + +// API to control MAX3421 SPI CS +extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); + +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); + +// API to enable/disable MAX3421 INTR pin interrupt +extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); + +//--------------------------------------------------------------------+ +// API for read/write MAX3421 registers +// are implemented by this driver, can be used by application +//--------------------------------------------------------------------+ + +// API to read MAX3421's register. Implemented by TinyUSB +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 6422afff1..225a44dcf 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -122,6 +122,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre); } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + uint8_t const pio_rhport = RHPORT_PIO(rhport); + return pio_usb_host_endpoint_close(pio_rhport, daddr, ep_addr); +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen); diff --git a/tools/get_deps.py b/tools/get_deps.py index 3f529bd7e..ba9dc23ce 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -58,8 +58,8 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], - 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '0ca3657d55ea20e7fa4483bbd21ce951bc1d6fa5', + 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', + '810653f66adadba3e0e4b4b56d5167ac4f7fdbf7', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 901ce2ad93b39c08e8e6b7e5b3f4dbd0b9df879e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 21:13:01 +0700 Subject: hcd/ehci: hcd_edpt_open() return false if ep is already opened. implement hcd_edpt_close() --- hw/bsp/imxrt/family.c | 4 +- src/device/usbd.c | 9 +- src/host/usbh.c | 2 +- src/portable/ehci/ehci.c | 259 ++++++++++++++++++++------------------ src/portable/ehci/ehci.h | 314 +++++++++++++++++++++++------------------------ test/hil/hil_test.py | 3 +- 6 files changed, 301 insertions(+), 290 deletions(-) (limited to 'src') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 7b89cc76d..7e4734a66 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -61,7 +61,7 @@ - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) */ -static void BOARD_ConfigMPU(void); +// static void BOARD_ConfigMPU(void); // needed by fsl_flexspi_nor_boot TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; @@ -456,7 +456,7 @@ static void BOARD_ConfigMPU(void) { #elif __CORTEX_M == 4 -void BOARD_ConfigMPU(void) { +static void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$RW_m_ncache$$Base[]; /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ diff --git a/src/device/usbd.c b/src/device/usbd.c index fb5cec49d..9c381d5e0 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -561,8 +561,7 @@ static void usbd_reset(uint8_t rhport) { } bool tud_task_event_ready(void) { - // Skip if stack is not initialized - if (!tud_inited()) return false; + TU_VERIFY(tud_inited()); // Skip if stack is not initialized return !osal_queue_empty(_usbd_q); } @@ -684,7 +683,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { case USBD_EVENT_FUNC_CALL: TU_LOG_USBD("\r\n"); - if (event.func_call.func) event.func_call.func(event.func_call.param); + if (event.func_call.func) { + event.func_call.func(event.func_call.param); + } break; case DCD_EVENT_SOF: @@ -701,7 +702,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO // return if there is no more events, for application to run other background - if (osal_queue_empty(_usbd_q)) return; + if (osal_queue_empty(_usbd_q)) { return; } #endif } } diff --git a/src/host/usbh.c b/src/host/usbh.c index 5925a7be0..e60db53da 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -520,7 +520,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // Loop until there is no more events in the queue while (1) { hcd_event_t event; - if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return; + if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; } switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 01bbf62bf..292a352fb 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -62,8 +62,7 @@ #define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) #define QTD_MAX QHD_MAX -typedef struct -{ +typedef struct { ehci_link_t period_framelist[FRAMELIST_SIZE]; // TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) @@ -139,6 +138,12 @@ static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); static void qhd_remove_qtd(ehci_qhd_t *qhd); +TU_ATTR_ALWAYS_INLINE static inline bool qhd_is_periodic(ehci_qhd_t const *qhd) { + return qhd->int_smask != 0; +} +TU_ATTR_ALWAYS_INLINE static inline uint8_t qhd_ep_addr(ehci_qhd_t const *qhd) { + return tu_edpt_addr(qhd->ep_number, qhd->pid); +} TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr); TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void); @@ -146,9 +151,10 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); -TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link); -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr); +TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *entry, uint8_t type); +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd); +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr); static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) { // maybe have a timeout for status @@ -175,15 +181,12 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ - -uint32_t hcd_frame_number(uint8_t rhport) -{ +uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3; } -void hcd_port_reset(uint8_t rhport) -{ +void hcd_port_reset(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -204,8 +207,7 @@ void hcd_port_reset(uint8_t rhport) regs->portsc = portsc; } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -221,32 +223,29 @@ void hcd_port_reset_end(uint8_t rhport) regs->portsc = portsc; } -bool hcd_port_connect_status(uint8_t rhport) -{ +bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; return ehci_data.regs->portsc_bm.current_connect_status; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t daddr) -{ +void hcd_device_close(uint8_t rhport, uint8_t daddr) { // skip dev0 if (daddr == 0) { return; } - // Remove from async list - list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr); + // Remove from async list all endpoints of this device + list_remove_qhd_by_addr((ehci_link_t *) list_get_async_head(rhport), daddr, TUSB_INDEX_INVALID_8); - // Remove from all interval period list - for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { - list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr); + // Remove from all interval period list of this device + for (uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { + list_remove_qhd_by_addr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr, TUSB_INDEX_INVALID_8); } // Async doorbell (EHCI 4.8.2 for operational details) @@ -358,12 +357,10 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) } #if 0 -static void ehci_stop(uint8_t rhport) -{ +static void ehci_stop(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; - regs->command_bm.run_stop = 0; // USB Spec: controller has to stop within 16 uframe = 2 frames @@ -375,41 +372,44 @@ static void ehci_stop(uint8_t rhport) // Endpoint API //--------------------------------------------------------------------+ -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // TODO not support ISO yet TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); //------------- Prepare Queue Head -------------// - ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free(); + ehci_qhd_t *p_qhd; + if (ep_desc->bEndpointAddress == 0) { + p_qhd = qhd_control(dev_addr); + } else { + TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet + p_qhd = qhd_find_free(); + } TU_ASSERT(p_qhd); - qhd_init(p_qhd, dev_addr, ep_desc); - // control of dev0 is always present as async head - if ( dev_addr == 0 ) return true; + // control of dev0 always exists as async head + if (dev_addr == 0) { + return true; + } // Insert to list ehci_link_t * list_head = NULL; - - switch (ep_desc->bmAttributes.xfer) - { + switch (ep_desc->bmAttributes.xfer) { case TUSB_XFER_CONTROL: case TUSB_XFER_BULK: - list_head = (ehci_link_t*) list_get_async_head(rhport); - break; + list_head = (ehci_link_t *) list_get_async_head(rhport); + break; case TUSB_XFER_INTERRUPT: list_head = list_get_period_head(rhport, p_qhd->interval_ms); - break; + break; case TUSB_XFER_ISOCHRONOUS: // TODO iso is not supported - break; + break; - default: break; + default: + break; } TU_ASSERT(list_head); @@ -421,8 +421,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + ehci_qhd_t* qhd = qhd_get_from_addr(daddr, ep_addr); + TU_VERIFY(qhd != NULL); + + ehci_link_t * list_head; + if (qhd_is_periodic(qhd)) { + // interrupt endpoint + list_head = list_get_period_head(rhport, qhd->interval_ms);; + } else { + list_head = (ehci_link_t *) list_get_async_head(rhport); + } + + list_remove_qhd_by_addr(list_head, daddr, ep_addr); + return true; +} + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd; @@ -444,14 +459,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet return true; } -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) -{ +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr); + TU_VERIFY(qhd != NULL); ehci_qtd_t* qtd; if (epnum == 0) { @@ -540,8 +555,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { // This isr mean it is safe to modify previously removed queue head from async list. // In tinyusb, queue head is only removed when device is unplugged. TU_ATTR_ALWAYS_INLINE static inline -void async_advance_isr(uint8_t rhport) -{ +void async_advance_isr(uint8_t rhport) { (void) rhport; ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; @@ -612,8 +626,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { } TU_ATTR_ALWAYS_INLINE static inline -void proccess_async_xfer_isr(ehci_qhd_t * const list_head) -{ +void proccess_async_xfer_isr(ehci_qhd_t * const list_head) { ehci_qhd_t *qhd = list_head; do { @@ -623,8 +636,7 @@ void proccess_async_xfer_isr(ehci_qhd_t * const list_head) } TU_ATTR_ALWAYS_INLINE static inline -void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) -{ +void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) { uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); ehci_link_t next_link = *list_get_period_head(rhport, interval_ms); @@ -726,51 +738,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_ return (ehci_link_t*) tu_align32(p_link->address); } -TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) -{ - new->address = current->address; - current->address = ((uint32_t) new) | (new_type << 1); +TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *entry, uint8_t type) { + entry->address = current->address; + current->address = ((uint32_t) entry) | (type << 1); +} + +// Remove a queue head from the list. +// Per EHCI 4.8.2 the removed qhd's next is linked to list head (which always reachable by Host Controller) +// TODO support iTD/siTD +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd) { + // TODO deactivate all TD, wait for QHD to inactive before removal + prev->address = qhd->next.address; + + // link the removed qhd's next to list head + qhd->next.address = ((uint32_t) head) | (EHCI_QTYPE_QHD << 1); + + if (qhd_is_periodic(qhd)) { + // period list queue element is guarantee to be free in the next frame (1 ms) + qhd->used = 0; + } else { + // async list use async advance handshake. Mark as removing, will completely re-usable when async advance isr occurs + qhd->removing = 1; + } + + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); } -// Remove all queue head belong to this device address -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { - ehci_link_t* prev = list_head; +// Remove queue head belong to this device address +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr) { + ehci_link_t *prev = list_head; while (prev && !prev->terminate) { - ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); + ehci_qhd_t *qhd = (ehci_qhd_t *) (uintptr_t) list_next(prev); // done if loop back to head - if ( (uintptr_t) qhd == (uintptr_t) list_head) { + if ((uintptr_t) qhd == (uintptr_t) list_head) { break; } - if ( qhd->dev_addr == dev_addr ) { - // TODO deactivate all TD, wait for QHD to inactive before removal - prev->address = qhd->next.address; - - // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) - qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); - - if ( qhd->int_smask ) - { - // period list queue element is guarantee to be free in the next frame (1 ms) - qhd->used = 0; - }else - { - // async list use async advance handshake - // mark as removing, will completely re-usable when async advance isr occurs - qhd->removing = 1; - } - - hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); - }else { + // ep_addr is 0xff means all endpoints of this device address + if (qhd->dev_addr == dev_addr && + (ep_addr == TUSB_INDEX_INVALID_8 || qhd_ep_addr(qhd) == ep_addr)) { + list_remove(list_head, prev, qhd); + } else { prev = list_next(prev); } } } - //--------------------------------------------------------------------+ // Queue Header helper //--------------------------------------------------------------------+ @@ -782,8 +798,10 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) { // Find a free queue head TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) { - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i]; + for (uint32_t i = 0; i < QHD_MAX; i++) { + if (!ehci_data.qhd_pool[i].used) { + return &ehci_data.qhd_pool[i]; + } } return NULL; } @@ -800,10 +818,9 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; - - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( (qhd_pool[i].dev_addr == dev_addr) && - ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) { + for (uint32_t i = 0; i < QHD_MAX; i++) { + if ((qhd_pool[i].dev_addr == dev_addr) && + ep_addr == qhd_ep_addr(&qhd_pool[i])) { return &qhd_pool[i]; } } @@ -812,8 +829,7 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } // Init queue head with endpoint descriptor -static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ +static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) if (dev_addr != 0) { tu_memclr(p_qhd, sizeof(ehci_qhd_t)); @@ -830,39 +846,43 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->ep_number = tu_edpt_number(ep_desc->bEndpointAddress); p_qhd->ep_speed = devtree_info.speed; p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0; - p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head + p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc); p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0; p_qhd->nak_reload = 0; - // Bulk/Control -> smask = cmask = 0 - // TODO Isochronous - if (TUSB_XFER_INTERRUPT == xfer_type) - { - if (TUSB_SPEED_HIGH == p_qhd->ep_speed) - { - TU_ASSERT( interval <= 16, ); - if ( interval < 4) // sub millisecond interval - { - p_qhd->interval_ms = 0; - p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : - (interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100); - }else - { - p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 ); - p_qhd->int_smask = TU_BIT(interval % 8); + switch (xfer_type) { + case TUSB_XFER_CONTROL: + case TUSB_XFER_BULK: + p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_INTERRUPT: + if (TUSB_SPEED_HIGH == p_qhd->ep_speed) { + TU_ASSERT(interval <= 16, ); + if (interval < 4) { + // sub millisecond interval + p_qhd->interval_ms = 0; + p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : + (interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100); + } else { + p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255); + p_qhd->int_smask = TU_BIT(interval % 8); + } + } else { + TU_ASSERT(0 != interval, ); + // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes + p_qhd->int_smask = 0x01; + p_qhd->fl_int_cmask = TU_BIN8(11100); + p_qhd->interval_ms = interval; } - }else - { - TU_ASSERT( 0 != interval, ); - // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes - p_qhd->int_smask = 0x01; - p_qhd->fl_int_cmask = TU_BIN8(11100); - p_qhd->interval_ms = interval; - } - }else - { - p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_ISOCHRONOUS: + // TODO not support ISO yet + break; + + default: break; } p_qhd->fl_hub_addr = devtree_info.hub_addr; @@ -880,8 +900,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->qtd_overlay.next.terminate = 1; p_qhd->qtd_overlay.alternate.terminate = 1; - if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) - { + if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) { p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11 } } diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 457adc1d3..87659701b 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -49,15 +49,14 @@ // TODO merge OHCI with EHCI enum { - EHCI_MAX_ITD = 4, + EHCI_MAX_ITD = 4, EHCI_MAX_SITD = 16 }; //--------------------------------------------------------------------+ // EHCI Data Structure //--------------------------------------------------------------------+ -enum -{ +enum { EHCI_QTYPE_ITD = 0 , EHCI_QTYPE_QHD , EHCI_QTYPE_SITD , @@ -65,8 +64,7 @@ enum }; /// EHCI PID -enum -{ +enum { EHCI_PID_OUT = 0 , EHCI_PID_IN , EHCI_PID_SETUP @@ -74,187 +72,182 @@ enum /// Link pointer typedef union { - uint32_t address; - struct { - uint32_t terminate : 1; - uint32_t type : 2; - }; -}ehci_link_t; + uint32_t address; + struct { + uint32_t terminate : 1; + uint32_t type : 2; + }; +} ehci_link_t; TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" ); /// Queue Element Transfer Descriptor /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32) -typedef struct -{ - // Word 0: Next QTD Pointer - ehci_link_t next; - - // Word 1: Alternate Next QTD Pointer (not used) - union{ - ehci_link_t alternate; - struct { - uint32_t : 5; - uint32_t used : 1; - uint32_t : 10; - uint32_t expected_bytes : 16; - }; - }; - - // Word 2: qTQ Token - volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator - volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of split transaction - volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete split transaction - volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... ) - volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1 - volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error - volatile uint32_t halted : 1 ; ///< Serious error or STALL received - volatile uint32_t active : 1 ; ///< Start transfer, clear by HC when complete - - uint32_t pid : 2 ; ///< 0: OUT, 1: IN, 2 Setup - volatile uint32_t err_count : 2 ; ///< Error Counter of consecutive errors - volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list - uint32_t int_on_complete : 1 ; ///< Interrupt on complete - volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction - volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit - - - /// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page - uint32_t buffer[5]; +typedef struct { + // Word 0 Next QTD Pointer + ehci_link_t next; + + // Word 1 Alternate Next QTD Pointer (not used) + union { + ehci_link_t alternate; + struct { + uint32_t : 5; + uint32_t used : 1; + uint32_t : 10; + uint32_t expected_bytes : 16; + }; + }; + + // Word 2 qTQ Token + volatile uint32_t ping_err : 1; // For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator + volatile uint32_t non_hs_split_state : 1; // Used by HC to track the state of split transaction + volatile uint32_t non_hs_missed_uframe : 1; // HC misses a complete split transaction + volatile uint32_t xact_err : 1; // Error (Timeout, CRC, Bad PID ... ) + volatile uint32_t babble_err : 1; // Babble detected, also set Halted bit to 1 + volatile uint32_t buffer_err : 1; // Data overrun/underrun error + volatile uint32_t halted : 1; // Serious error or STALL received + volatile uint32_t active : 1; // Start transfer, clear by HC when complete + + uint32_t pid : 2; // 0: OUT, 1: IN, 2 Setup + volatile uint32_t err_count : 2; // Error Counter of consecutive errors + volatile uint32_t current_page : 3; // Index into the qTD buffer pointer list + uint32_t int_on_complete : 1; // Interrupt on complete + volatile uint32_t total_bytes : 15; // Transfer bytes, decreased during transaction + volatile uint32_t data_toggle : 1; // Data Toggle bit + + // Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. + // The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page + uint32_t buffer[5]; } ehci_qtd_t; TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" ); /// Queue Head -typedef struct TU_ATTR_ALIGNED(32) -{ - // Word 0: Next QHD - ehci_link_t next; - - // Word 1: Endpoint Characteristics - uint32_t dev_addr : 7 ; ///< device address - uint32_t fl_inactive_next_xact : 1 ; ///< Only valid for Periodic with Full/Slow speed - uint32_t ep_number : 4 ; ///< EP number - uint32_t ep_speed : 2 ; ///< 0: Full, 1: Low, 2: High - uint32_t data_toggle_control : 1 ; ///< 0: use DT in qHD, 1: use DT in qTD - uint32_t head_list_flag : 1 ; ///< Head of the queue - uint32_t max_packet_size : 11 ; ///< Max packet size - uint32_t fl_ctrl_ep_flag : 1 ; ///< 1 if is Full/Low speed control endpoint - uint32_t nak_reload : 4 ; ///< Used by HC - - // Word 2: Endpoint Capabilities - uint32_t int_smask : 8 ; ///< Interrupt Schedule Mask - uint32_t fl_int_cmask : 8 ; ///< Split Completion Mask for Full/Slow speed - uint32_t fl_hub_addr : 7 ; ///< Hub Address for Full/Slow speed - uint32_t fl_hub_port : 7 ; ///< Hub Port for Full/Slow speed - uint32_t mult : 2 ; ///< Transaction per micro frame - - // Word 3: Current qTD Pointer - volatile uint32_t qtd_addr; - - // Word 4-11: Transfer Overlay - volatile ehci_qtd_t qtd_overlay; - - //--------------------------------------------------------------------+ +typedef struct TU_ATTR_ALIGNED(32) { + // Word 0 Next QHD + ehci_link_t next; + + // Word 1 Endpoint Characteristics + uint32_t dev_addr : 7; // device address + uint32_t fl_inactive_next_xact : 1; // Only valid for Periodic with Full/Slow speed + uint32_t ep_number : 4; // EP number + uint32_t ep_speed : 2; // Full (0), Low (1), High (2) + uint32_t data_toggle_control : 1; // 0 use DT in qHD, 1 use DT in qTD + uint32_t head_list_flag : 1; // Head of the queue + uint32_t max_packet_size : 11; // Max packet size + uint32_t fl_ctrl_ep_flag : 1; // 1 if is Full/Low speed control endpoint + uint32_t nak_reload : 4; // Used by HC + + // Word 2 Endpoint Capabilities + uint32_t int_smask : 8; // Interrupt Schedule Mask + uint32_t fl_int_cmask : 8; // Split Completion Mask for Full/Slow speed + uint32_t fl_hub_addr : 7; // Hub Address for Full/Slow speed + uint32_t fl_hub_port : 7; // Hub Port for Full/Slow speed + uint32_t mult : 2; // Transaction per micro frame + + // Word 3 Current qTD Pointer + volatile uint32_t qtd_addr; + + // Word 4-11 Transfer Overlay + volatile ehci_qtd_t qtd_overlay; + + //--------------------------------------------------------------------+ /// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes - /// thus there are 16 bytes padding free that we can make use of. + /// thus there are 16 bytes padding free that we can make use of. //--------------------------------------------------------------------+ - uint8_t used; - uint8_t removing; // removed from asyn list, waiting for async advance - uint8_t pid; - uint8_t interval_ms; // polling interval in frames (or millisecond) + uint8_t used; + uint8_t removing;// removed from asyn list, waiting for async advance + uint8_t pid; + uint8_t interval_ms;// polling interval in frames (or millisecond) - uint8_t TU_RESERVED[4]; + uint8_t TU_RESERVED[4]; // Attached TD management, note usbh will only queue 1 TD per QHD. // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial uint32_t attached_buffer; - ehci_qtd_t * volatile attached_qtd; + ehci_qtd_t *volatile attached_qtd; } ehci_qhd_t; - TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); /// Highspeed Isochronous Transfer Descriptor (section 3.3) typedef struct TU_ATTR_ALIGNED(32) { - // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1-8: iTD Transaction Status and Control List - struct { - // iTD Control - volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. - volatile uint32_t page_select : 3 ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 - uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold - volatile uint32_t length : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer - ///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count - // iTD Status - volatile uint32_t error : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. - volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction - volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). - volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller - } xact[8]; - - // Word 9-15 Buffer Page Pointer List (Plus) - uint32_t BufferPointer[7]; - -// // FIXME: Store meta data into buffer pointer reserved for saving memory -// /*---------- HCD Area ----------*/ -// uint32_t used; -// uint32_t IhdIdx; -// uint32_t reserved[6]; + // Word 0: Next Link Pointer + ehci_link_t next; + + // Word 1-8: iTD Transaction Status and Control List + struct { + // iTD Control + volatile uint32_t offset : 12; // offset in bytes, from the beginning of a buffer. + volatile uint32_t page_select : 3; // buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 + uint32_t int_on_complete : 1; // If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold + volatile uint32_t length : 12; // For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer + // For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count + // iTD Status + volatile uint32_t error : 1; // Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. + volatile uint32_t babble_err : 1; // Set to a 1 by the Host Controller during status update when a babble is detected during the transaction + volatile uint32_t buffer_err : 1; // Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). + volatile uint32_t active : 1; // Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller + } xact[8]; + + // Word 9-15 Buffer Page Pointer List (Plus) + uint32_t BufferPointer[7]; + + // FIXME: Store meta data into buffer pointer reserved for saving memory + //---------- HCD Area ---------- + // uint32_t used; + // uint32_t IhdIdx; + // uint32_t reserved[6]; } ehci_itd_t; - TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" ); /// Split (Full-Speed) Isochronous Transfer Descriptor -typedef struct TU_ATTR_ALIGNED(32) -{ +typedef struct TU_ATTR_ALIGNED(32) { // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1: siTD Endpoint Characteristics - uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. - uint32_t : 1; ///< reserved - uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. - uint32_t : 4; ///< This field is reserved and should be set to zero. - uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. - uint32_t : 1; ///< reserved - uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. - uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. - - // Word 2: Micro-frame Schedule Control - uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions - uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. - uint16_t reserved ; ///< reserved - - // Word 3: siTD Transfer Status and Control - // Status [7:0] TODO identical to qTD Token'status --> refactor later - volatile uint32_t : 1 ; // reserved - volatile uint32_t split_state : 1 ; - volatile uint32_t missed_uframe : 1 ; - volatile uint32_t xact_err : 1 ; - volatile uint32_t babble_err : 1 ; - volatile uint32_t buffer_err : 1 ; - volatile uint32_t error : 1 ; - volatile uint32_t active : 1 ; - // Micro-frame Schedule Control - volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. - volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 - volatile uint32_t : 4 ; ///< reserved - volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer - uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete - uint32_t : 0 ; // padding to the end of current storage unit - - /// Word 4-5: Buffer Pointer List - uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count - - /*---------- Word 6 ----------*/ - ehci_link_t back; - - /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data - uint8_t used; - uint8_t ihd_idx; - uint8_t reserved2[2]; + ehci_link_t next; + + // Word 1: siTD Endpoint Characteristics + uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. + uint32_t : 1; ///< reserved + uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. + uint32_t : 4; ///< This field is reserved and should be set to zero. + uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. + uint32_t : 1; ///< reserved + uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. + uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. + + // Word 2: Micro-frame Schedule Control + uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions + uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. + uint16_t reserved ; ///< reserved + + // Word 3: siTD Transfer Status and Control + // Status [7:0] TODO identical to qTD Token'status --> refactor later + volatile uint32_t : 1 ; // reserved + volatile uint32_t split_state : 1 ; + volatile uint32_t missed_uframe : 1 ; + volatile uint32_t xact_err : 1 ; + volatile uint32_t babble_err : 1 ; + volatile uint32_t buffer_err : 1 ; + volatile uint32_t error : 1 ; + volatile uint32_t active : 1 ; + // Micro-frame Schedule Control + volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. + volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 + volatile uint32_t : 4 ; ///< reserved + volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer + uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete + uint32_t : 0 ; // padding to the end of current storage unit + + /// Word 4-5: Buffer Pointer List + uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count + + /*---------- Word 6 ----------*/ + ehci_link_t back; + + /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data + uint8_t used; + uint8_t ihd_idx; + uint8_t reserved2[2]; } ehci_sitd_t; TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" ); @@ -315,8 +308,7 @@ enum { EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE }; -typedef volatile struct -{ +typedef volatile struct { union { uint32_t command; // 0x00 diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 662bb3a1f..8b89de66c 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -340,8 +340,8 @@ def test_host_device_info(board): ser.close() if len(data) == 0: assert False, 'No data from device' - lines = data.decode('utf-8', errors='ignore').splitlines() + enum_dev_sn = [] for l in lines: vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) @@ -353,7 +353,6 @@ def test_host_device_info(board): failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' print('\n'.join(lines)) assert False, failed_msg - return 0 -- cgit v1.3.1 From e511d00f34b2832ae32ad0b2418a0878c7c4e7d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 22:11:44 +0700 Subject: added hcd_edpt_close() stub for other ports --- src/portable/mentor/musb/hcd_musb.c | 5 +++ src/portable/nxp/khci/hcd_khci.c | 5 +++ src/portable/ohci/ohci.c | 6 +++- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 6 +++- src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++ src/portable/synopsys/dwc2/hcd_dwc2.c | 5 +++ src/portable/template/hcd_template.c | 49 ++++++++-------------------- 7 files changed, 44 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 1c0740193..811043d74 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -804,6 +804,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { (void)rhport; diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 056dbf40b..c3c901c5d 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -541,6 +541,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + /* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long. * DMA writes data in 4 byte unit */ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index ce35eab70..672ad0443 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -451,7 +451,6 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ - bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; @@ -486,6 +485,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 478c6e789..cd8c905d5 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -514,7 +514,6 @@ void hcd_int_disable(uint8_t rhport) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ - bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; @@ -535,6 +534,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 4c81b05be..3e4b36981 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -718,6 +718,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { bool r; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b13479b02..f0cea529e 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -506,6 +506,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + // clean up channel after part of transfer is done but the whole urb is not complete static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index d8bca196f..1202c4ef4 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -36,24 +36,19 @@ // optional hcd configuration, called by tuh_configure() bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { - (void) rhport; - (void) cfg_id; - (void) cfg_param; - + (void) rhport; (void) cfg_id; (void) cfg_param; return false; } // Initialize controller to host mode bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; - (void) rh_init; + (void) rhport; (void) rh_init; return false; } // Interrupt Handler void hcd_int_handler(uint8_t rhport, bool in_isr) { - (void) rhport; - (void) in_isr; + (void) rhport; (void) in_isr; } // Enable USB interrupt @@ -69,7 +64,6 @@ void hcd_int_disable(uint8_t rhport) { // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return 0; } @@ -80,7 +74,6 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; - return false; } @@ -98,14 +91,12 @@ void hcd_port_reset_end(uint8_t rhport) { // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; - return TUSB_SPEED_FULL; } // HCD closes all opened endpoints belong to this device void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; + (void) rhport; (void) dev_addr; } //--------------------------------------------------------------------+ @@ -114,49 +105,37 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - (void) dev_addr; - (void) ep_desc; - + (void) rhport; (void) dev_addr; (void) ep_desc; return false; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - (void) buffer; - (void) buflen; - + (void) rhport; (void) dev_addr; (void) ep_addr; (void) buffer; (void) buflen; return false; } // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - + (void) rhport; (void) dev_addr; (void) ep_addr; return false; } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void) rhport; - (void) dev_addr; - (void) setup_packet; - + (void) rhport; (void) dev_addr; (void) setup_packet; return false; } // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - + (void) rhport; (void) dev_addr; (void) ep_addr; return false; } -- cgit v1.3.1 From 4787cd5f546eabad630fc5c22f37f67a076ac37e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Apr 2025 18:11:33 +0700 Subject: fix(hcd) hcd_edpt_open() return true if endpoint is already opened. --- examples/host/device_info/src/main.c | 31 ++++++++++++++++++++----------- src/host/hcd.h | 1 + src/portable/analog/max3421/hcd_max3421.c | 2 +- src/portable/ehci/ehci.c | 4 +++- 4 files changed, 25 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index ac4c46a11..e924a137b 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -124,13 +124,18 @@ void tuh_mount_cb(uint8_t daddr) { } printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct); - xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial)); + + xfer_result = XFER_RESULT_FAILED; + if (desc.device.iSerialNumber != 0) { + xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial)); + } if (XFER_RESULT_SUCCESS != xfer_result) { uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial; - serial[0] = 'n'; - serial[1] = '/'; - serial[2] = 'a'; - serial[3] = 0; + serial[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * 3 + 2)); + serial[1] = 'n'; + serial[2] = '/'; + serial[3] = 'a'; + serial[4] = 0; } print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2); printf("\r\n"); @@ -150,16 +155,20 @@ void tuh_mount_cb(uint8_t daddr) { // Get String descriptor using Sync API printf(" iManufacturer %u ", desc.device.iManufacturer); - xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); - if (XFER_RESULT_SUCCESS == xfer_result) { - print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + if (desc.device.iManufacturer != 0) { + xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); + if (XFER_RESULT_SUCCESS == xfer_result) { + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + } } printf("\r\n"); printf(" iProduct %u ", desc.device.iProduct); - xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); - if (XFER_RESULT_SUCCESS == xfer_result) { - print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + if (desc.device.iProduct != 0) { + xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); + if (XFER_RESULT_SUCCESS == xfer_result) { + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + } } printf("\r\n"); diff --git a/src/host/hcd.h b/src/host/hcd.h index aa9e9cf3b..b20d96d54 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -163,6 +163,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); //--------------------------------------------------------------------+ // Open an endpoint +// return true if successfully opened or endpoint is currently opened bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); // Close an endpoint diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 3fbf950a4..bb33200f2 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -611,7 +611,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e ep = &_hcd_data.ep[0]; }else { if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) { - return false; // endpoint already opened + return true; // already opened } ep = allocate_ep(); TU_ASSERT(ep); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 292a352fb..7451f69a3 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -381,7 +381,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const if (ep_desc->bEndpointAddress == 0) { p_qhd = qhd_control(dev_addr); } else { - TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet + if (NULL != qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)) { + return true; // already opened + } p_qhd = qhd_find_free(); } TU_ASSERT(p_qhd); -- cgit v1.3.1 From 255ccf26ea29eb16be41f7715426c10be69b6e30 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Fri, 4 Apr 2025 14:21:20 +0200 Subject: dwc2/host: clear SOF flag in handle_sof_irq() --- src/portable/synopsys/dwc2/hcd_dwc2.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f0cea529e..7cbef05b7 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1182,6 +1182,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { static bool handle_sof_irq(uint8_t rhport, bool in_isr) { (void) in_isr; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2->gintsts = GINTSTS_SOF; // Clear the SOF interrupt flag bool more_isr = false; -- cgit v1.3.1 From 7d8433abab25734981f1b5eab3c5724a945df711 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Mon, 7 Apr 2025 11:36:02 +0200 Subject: dwc2/host: enable disconnect interrupt + handle it Signed-off-by: Maxime Vincent --- src/portable/synopsys/dwc2/hcd_dwc2.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7cbef05b7..4c3d23b65 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -381,7 +381,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT; + dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT | GINTSTS_DISCINT; // NPTX can hold at least 2 packet, change interrupt level to half-empty uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL; @@ -1330,6 +1330,14 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_channel_irq(rhport, in_isr); } + if (gintsts & GINTSTS_DISCINT) { + // Device disconnected + dwc2->gintsts = GINTSTS_DISCINT; + if (!(dwc2->hprt & HPRT_CONN_STATUS)) { + hcd_event_device_remove(rhport, in_isr); + } + } + #if CFG_TUH_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling if (gintsts & GINTSTS_RXFLVL) { -- cgit v1.3.1 From 6607b76c761a3a64a7c43ceba27ae42cdb368e52 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Tue, 8 Apr 2025 14:34:11 +0200 Subject: dwc2/host: remove hcd_event_device_remove() call from handle_hptr_irq to prevent double removal Signed-off-by: Maxime Vincent --- src/portable/synopsys/dwc2/hcd_dwc2.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 4c3d23b65..4aa42759f 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1266,8 +1266,6 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { if (hprt_bm.conn_status) { hcd_event_device_attach(rhport, in_isr); - } else { - hcd_event_device_remove(rhport, in_isr); } } -- cgit v1.3.1 From 084c0802c310c836e0c3e972b724a5a0d17057ba Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Wed, 9 Apr 2025 01:31:16 +0200 Subject: dwc2: refactor bitfields. Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/dcd_dwc2.c | 86 ++- src/portable/synopsys/dwc2/dwc2_common.c | 16 +- src/portable/synopsys/dwc2/dwc2_type.h | 953 +++++++++++++++---------------- src/portable/synopsys/dwc2/hcd_dwc2.c | 202 ++++--- 4 files changed, 647 insertions(+), 610 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c461d9a79..83ebc18cb 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -44,7 +44,7 @@ #if TU_CHECK_MCU(OPT_MCU_GD32VF103) #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX #else - #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1) + #define DWC2_EP_COUNT(_dwc2) ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2}; ghwcfg2.num_dev_ep + 1;}) #endif //--------------------------------------------------------------------+ @@ -102,7 +102,8 @@ bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return CFG_TUD_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; } static void dma_setup_prepare(uint8_t rhport) { @@ -250,20 +251,15 @@ static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint xfer->interval = p_endpoint_desc->bInterval; // Endpoint control - union { - uint32_t value; - dwc2_depctl_t bm; - } depctl; - depctl.value = 0; - - depctl.bm.mps = xfer->max_size; - depctl.bm.active = 1; - depctl.bm.type = p_endpoint_desc->bmAttributes.xfer; + dwc2_depctl_t depctl = {.value = 0}; + depctl.mps = xfer->max_size; + depctl.active = 1; + depctl.type = p_endpoint_desc->bmAttributes.xfer; if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) { - depctl.bm.set_data0_iso_even = 1; + depctl.set_data0_iso_even = 1; } if (dir == TUSB_DIR_IN) { - depctl.bm.tx_fifo_num = epnum; + depctl.tx_fifo_num = epnum; } dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; @@ -343,31 +339,22 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin } // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC. - union { - uint32_t value; - dwc2_ep_tsize_t bm; - } deptsiz; - deptsiz.value = 0; - deptsiz.bm.xfer_size = total_bytes; - deptsiz.bm.packet_count = num_packets; - + dwc2_ep_tsize_t deptsiz = {.value = 0}; + deptsiz.xfer_size = total_bytes; + deptsiz.packet_count = num_packets; dep->tsiz = deptsiz.value; // control - union { - dwc2_depctl_t bm; - uint32_t value; - } depctl; - depctl.value = dep->ctl; - - depctl.bm.clear_nak = 1; - depctl.bm.enable = 1; - if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { - const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u); + dwc2_depctl_t depctl = {.value = dep->ctl}; + depctl.clear_nak = 1; + depctl.enable = 1; + if (depctl.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { + const dwc2_dsts_t dsts = {.value = dwc2->dsts}; + const uint32_t odd_now = dsts.frame_number & 1u; if (odd_now) { - depctl.bm.set_data0_iso_even = 1; + depctl.set_data0_iso_even = 1; } else { - depctl.bm.set_data1_iso_odd = 1; + depctl.set_data1_iso_odd = 1; } } @@ -410,7 +397,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + if (ghwcfg2.hs_phy_type == GHWCFG2_HSPHY_ULPI) { dcfg |= DCFG_XCVRDLY; } } else { @@ -671,7 +659,9 @@ static void handle_bus_reset(uint8_t rhport) { dfifo_device_init(rhport); // 5. Reset device address - dwc2->dcfg_bm.address = 0; + dwc2_dcfg_t dcfg = {.value = dwc2->dcfg}; + dcfg.address = 0; + dwc2->dcfg = dcfg.value; // Fixed both control EP0 size to 64 bytes dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); @@ -691,8 +681,9 @@ static void handle_bus_reset(uint8_t rhport) { static void handle_enum_done(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); + const dwc2_dsts_t dsts = {.value = dwc2->dsts}; tusb_speed_t speed; - switch (dwc2->dsts_bm.enum_speed) { + switch (dsts.enum_speed) { case DCFG_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; @@ -737,12 +728,12 @@ static void handle_rxflvl_irq(uint8_t rhport) { const volatile uint32_t* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; - const uint8_t epnum = grxstsp_bm.ep_ch_num; + const dwc2_grxstsp_t grxstsp = {.value = dwc2->grxstsp}; + const uint8_t epnum = grxstsp.ep_ch_num; dwc2_dep_t* epout = &dwc2->epout[epnum]; - switch (grxstsp_bm.packet_status) { + switch (grxstsp.packet_status) { case GRXSTS_PKTSTS_GLOBAL_OUT_NAK: // Global OUT NAK: do nothing break; @@ -764,7 +755,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_RX_DATA: { // Out packet received - const uint16_t byte_count = grxstsp_bm.byte_count; + const uint16_t byte_count = grxstsp.byte_count; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); if (byte_count) { @@ -778,7 +769,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { // short packet, minus remaining bytes (xfer_size) if (byte_count < xfer->max_size) { - xfer->total_len -= epout->tsiz_bm.xfer_size; + const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz}; + xfer->total_len -= tsiz.xfer_size; if (epnum == 0) { xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT]; _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0; @@ -840,11 +832,13 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep // - 64 bytes or // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) { - const uint16_t remain_packets = epin->tsiz_bm.packet_count; + dwc2_ep_tsize_t tsiz = {.value = epin->tsiz}; + const uint16_t remain_packets = tsiz.packet_count; // Process every single packet (only whole packets can be written to fifo) for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size; + tsiz.value = epin->tsiz; + const uint16_t remain_bytes = (uint16_t) tsiz.xfer_size; const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); // Check if dtxfsts has enough space available @@ -863,7 +857,8 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep } // Turn off TXFE if all bytes are written. - if (epin->tsiz_bm.xfer_size == 0) { + tsiz.value = epin->tsiz; + if (tsiz.xfer_size == 0) { dwc2->diepempmsk &= ~(1 << epnum); } } @@ -894,7 +889,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); // determine actual received bytes - const uint16_t remain = epout->tsiz_bm.xfer_size; + const dwc2_ep_tsize_t tsiz = {.value = epout->tsiz}; + const uint16_t remain = tsiz.xfer_size; xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index f80ae9acb..989a833ff 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -88,11 +88,13 @@ static void phy_fs_init(dwc2_regs_t* dwc2) { static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + const dwc2_ghwcfg4_t ghwcfg4 = {.value = dwc2->ghwcfg4}; // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + if (ghwcfg2.hs_phy_type == GHWCFG2_HSPHY_ULPI) { TU_LOG(DWC2_COMMON_DEBUG, "Highspeed ULPI PHY init\r\n"); // Select ULPI PHY (external) @@ -116,7 +118,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.phy_data_width) { + if (ghwcfg4.phy_data_width) { gusbcfg |= GUSBCFG_PHYIF16; // 16 bit } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit @@ -127,7 +129,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { dwc2->gusbcfg = gusbcfg; // mcu specific phy init - dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + dwc2_phy_init(dwc2, ghwcfg2.hs_phy_type); // Reset core after selecting PHY reset_core(dwc2); @@ -136,11 +138,11 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + gusbcfg |= (ghwcfg4.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset - dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + dwc2_phy_update(dwc2, ghwcfg2.hs_phy_type); } static bool check_dwc2(dwc2_regs_t* dwc2) { @@ -171,7 +173,7 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { (void)dwc2; - + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; #if CFG_TUD_ENABLED if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { return false; @@ -183,7 +185,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { } #endif - return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; + return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; } /* dwc2 has several PHYs option diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 812096759..5ecf9d487 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -184,415 +184,470 @@ enum { //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- -typedef struct TU_ATTR_PACKED { - uint32_t ses_req_scs : 1; // 0 Session request success - uint32_t ses_req : 1; // 1 Session request - uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable - uint32_t vbval_ov_val : 1; // 3 VBUS valid override value - uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable - uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value - uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable - uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value - uint32_t hng_scs : 1; // 8 Host negotiation success - uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request - uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable - uint32_t dev_hnp_en : 1; // 11 Device HNP enabled - uint32_t embedded_host_en : 1; // 12 Embedded host enable - uint32_t rsv13_14 : 2; // 13.14 Reserved - uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass - uint32_t cid_status : 1; // 16 Connector ID status - uint32_t dbnc_done : 1; // 17 Debounce done - uint32_t ases_valid : 1; // 18 A-session valid - uint32_t bses_valid : 1; // 19 B-session valid - uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0 - uint32_t current_mode : 1; // 21 Current mode of operation. Only from v3.00a - uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger - uint32_t chirp_en : 1; // 27 Chirp detection enable - uint32_t rsv28_30 : 3; // 28.30: Reserved - uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t ses_req_scs : 1; // 0 Session request success + uint32_t ses_req : 1; // 1 Session request + uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable + uint32_t vbval_ov_val : 1; // 3 VBUS valid override value + uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable + uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value + uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable + uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value + uint32_t hng_scs : 1; // 8 Host negotiation success + uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request + uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable + uint32_t dev_hnp_en : 1; // 11 Device HNP enabled + uint32_t embedded_host_en : 1; // 12 Embedded host enable + uint32_t rsv13_14 : 2; // 13.14 Reserved + uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass + uint32_t cid_status : 1; // 16 Connector ID status + uint32_t dbnc_done : 1; // 17 Debounce done + uint32_t ases_valid : 1; // 18 A-session valid + uint32_t bses_valid : 1; // 19 B-session valid + uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0 + uint32_t current_mode : 1; // 21 Current mode of operation. Only from v3.00a + uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger + uint32_t chirp_en : 1; // 27 Chirp detection enable + uint32_t rsv28_30 : 3; // 28.30: Reserved + uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY + }; } dwc2_gotgctl_t; TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t rsv0_1 : 2; // 0..1 Reserved - uint32_t ses_end_det : 1; // 2 Session end detected - uint32_t rsv3_7 : 5; // 3..7 Reserved - uint32_t srs_status_change : 1; // 8 Session request success status change - uint32_t hns_status_change : 1; // 9 Host negotiation success status change - uint32_t rsv10_16 : 7; // 10..16 Reserved - uint32_t hng_det : 1; // 17 Host negotiation detected - uint32_t adev_timeout_change : 1; // 18 A-device timeout change - uint32_t dbnc_done : 1; // 19 Debounce done - uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change - uint32_t rsv21_31 :11; // 21..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t rsv0_1 : 2; // 0..1 Reserved + uint32_t ses_end_det : 1; // 2 Session end detected + uint32_t rsv3_7 : 5; // 3..7 Reserved + uint32_t srs_status_change : 1; // 8 Session request success status change + uint32_t hns_status_change : 1; // 9 Host negotiation success status change + uint32_t rsv10_16 : 7; // 10..16 Reserved + uint32_t hng_det : 1; // 17 Host negotiation detected + uint32_t adev_timeout_change : 1; // 18 A-device timeout change + uint32_t dbnc_done : 1; // 19 Debounce done + uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change + uint32_t rsv21_31 :11; // 21..31 Reserved + }; } dwc2_gotgint_t; TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t gintmask : 1; // 0 Global interrupt mask - uint32_t hbst_len : 4; // 1..4 Burst length/type - uint32_t dma_en : 1; // 5 DMA enable - uint32_t rsv6 : 1; // 6 Reserved - uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level - uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level - uint32_t rsv9_20 : 12; // 9.20: Reserved - uint32_t remote_mem_support : 1; // 21 Remote memory support - uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes - uint32_t ahb_single : 1; // 23 AHB single - uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian - uint32_t rsv25_31 : 7; // 25..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t gintmask : 1; // 0 Global interrupt mask + uint32_t hbst_len : 4; // 1..4 Burst length/type + uint32_t dma_en : 1; // 5 DMA enable + uint32_t rsv6 : 1; // 6 Reserved + uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level + uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level + uint32_t rsv9_20 : 12; // 9.20: Reserved + uint32_t remote_mem_support : 1; // 21 Remote memory support + uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes + uint32_t ahb_single : 1; // 23 AHB single + uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian + uint32_t rsv25_31 : 7; // 25..31 Reserved + }; } dwc2_gahbcfg_t; TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t timeout_cal : 3; /* 0..2 Timeout calibration. - The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard - timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field - based on the speed of enumeration. The number of bit times added per PHY clock are as follows: - - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times - - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ - uint32_t phy_if16 : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits - uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI - uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin - uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver - uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit - uint32_t srp_capable : 1; // 8 SRP-capable - uint32_t hnp_capable : 1; // 9 HNP-capable - uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+ - uint32_t rsv14 : 1; // 14 Reserved - uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode. - In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs. - - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit) - - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */ - uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals - uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS. - valid only when the FS serial transceiver is selected on the ULPI PHY. */ - uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume - uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM - uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive - uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator - uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing - uint32_t indicator_complement : 1; // 23 Indicator complement - uint32_t indicator_pass_through : 1; // 24 Indicator pass through - uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable - uint32_t ic_usb_capable : 1; // 26 IC_USB Capable - uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control - uint32_t tx_end_delay : 1; // 28 TX end delay - uint32_t force_host_mode : 1; // 29 Force host mode - uint32_t force_dev_mode : 1; // 30 Force device mode - uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t timeout_cal : 3; /* 0..2 Timeout calibration. + The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard + timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field + based on the speed of enumeration. The number of bit times added per PHY clock are as follows: + - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times + - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ + uint32_t phy_if16 : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits + uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI + uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin + uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver + uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit + uint32_t srp_capable : 1; // 8 SRP-capable + uint32_t hnp_capable : 1; // 9 HNP-capable + uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+ + uint32_t rsv14 : 1; // 14 Reserved + uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode. + In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs. + - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit) + - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */ + uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals + uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS. + valid only when the FS serial transceiver is selected on the ULPI PHY. */ + uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume + uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM + uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive + uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator + uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing + uint32_t indicator_complement : 1; // 23 Indicator complement + uint32_t indicator_pass_through : 1; // 24 Indicator pass through + uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable + uint32_t ic_usb_capable : 1; // 26 IC_USB Capable + uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control + uint32_t tx_end_delay : 1; // 28 TX end delay + uint32_t force_host_mode : 1; // 29 Force host mode + uint32_t force_dev_mode : 1; // 30 Force device mode + uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug + }; } dwc2_gusbcfg_t; TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t core_soft_rst : 1; // 0 Core Soft Reset - uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset - uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host) - uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush - uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush - uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush - uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number - uint32_t rsv11_28 :18; // 11..28 Reserved - uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a - uint32_t dma_req : 1; // 30 DMA Request - uint32_t ahb_idle : 1; // 31 AHB Idle +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t core_soft_rst : 1; // 0 Core Soft Reset + uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset + uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host) + uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush + uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush + uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush + uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number + uint32_t rsv11_28 :18; // 11..28 Reserved + uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a + uint32_t dma_req : 1; // 30 DMA Request + uint32_t ahb_idle : 1; // 31 AHB Idle + }; } dwc2_grstctl_t; TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number - uint32_t byte_count :11; // 4..14 Byte Count - uint32_t dpid : 2; // 15..16 Data PID - uint32_t packet_status : 4; // 17..20 Packet Status - uint32_t frame_number : 4; // 21..24 Frame Number - uint32_t rsv25_31 : 7; // 25..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number + uint32_t byte_count :11; // 4..14 Byte Count + uint32_t dpid : 2; // 15..16 Data PID + uint32_t packet_status : 4; // 17..20 Packet Status + uint32_t frame_number : 4; // 21..24 Frame Number + uint32_t rsv25_31 : 7; // 25..31 Reserved + }; } dwc2_grxstsp_t; TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size"); -// Hardware Configuration -typedef struct TU_ATTR_PACKED { - uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode - uint32_t arch : 2; // 3..4 Slave/External/Internal DMA - uint32_t single_point : 1; // 5 0: support hub and split | 1: no hub, no split - uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI - uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI - uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0) - uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control) - uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel - uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled - uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT) - uint32_t reserved21 : 1; // 21 reserved - uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 - uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 - uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30 - uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode + uint32_t arch : 2; // 3..4 Slave/External/Internal DMA + uint32_t single_point : 1; // 5 0: support hub and split | 1: no hub, no split + uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI + uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI + uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0) + uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control) + uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel + uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled + uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT) + uint32_t reserved21 : 1; // 21 reserved + uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30 + uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation + }; } dwc2_ghwcfg2_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits) - uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits) - uint32_t otg_enable : 1; // 7 OTG capable - uint32_t i2c_enable : 1; // 8 I2C interface is available - uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available - uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count - uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset - uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller - uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC - uint32_t battery_charger_support : 1; // s14 upport battery charger - uint32_t lpm_mode : 1; // 15 LPM mode - uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words -}dwc2_ghwcfg3_t; +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits) + uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits) + uint32_t otg_enable : 1; // 7 OTG capable + uint32_t i2c_enable : 1; // 8 I2C interface is available + uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available + uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count + uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset + uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller + uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC + uint32_t battery_charger_support : 1; // s14 upport battery charger + uint32_t lpm_mode : 1; // 15 LPM mode + uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words + }; +} dwc2_ghwcfg3_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints - uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled - uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz - uint32_t hibernation : 1; // 6 Hibernation feature is enabled - uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled - uint32_t reserved8 : 1; // 8 Reserved - uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1 - uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported - uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported - uint32_t acg_support : 1; // 12 Active clock gating is supported - uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support - uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable - uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0 - uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled - uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled - uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled - uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled - uint32_t session_end_filter : 1; // 24 Session End Filter Enabled - uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint - uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0 - uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled - uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA -}dwc2_ghwcfg4_t; +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints + uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled + uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz + uint32_t hibernation : 1; // 6 Hibernation feature is enabled + uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled + uint32_t reserved8 : 1; // 8 Reserved + uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1 + uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported + uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported + uint32_t acg_support : 1; // 12 Active clock gating is supported + uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support + uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable + uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0 + uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled + uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled + uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled + uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled + uint32_t session_end_filter : 1; // 24 Session End Filter Enabled + uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint + uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0 + uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled + uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA + }; +} dwc2_ghwcfg4_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); -//-------------------------------------------------------------------- -// Host Register Bitfield -//-------------------------------------------------------------------- - -typedef struct TU_ATTR_PACKED { - uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO - uint32_t req_queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU - // 24..31 is top entry in the request queue that is currently being processed by the MAC - uint32_t qtop_terminate : 1; // 24 Last entry for selected channel - uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command - uint32_t qtop_ch_num : 4; // 27..30 Channel number +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t req_queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU + // 24..31 is top entry in the request queue that is currently being processed by the MAC + uint32_t qtop_terminate : 1; // 24 Last entry for selected channel + uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command + uint32_t qtop_ch_num : 4; // 27..30 Channel number + }; } dwc2_hnptxsts_t; TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO - uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue - uint32_t qtop_terminate : 1; // 23 Last entry for selected channel - uint32_t qtop_last_period : 1; // 24 Last entry for selected channel is a periodic entry - uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command - uint32_t qtop_ch_num : 4; // 27..30 Channel number - uint32_t qtop_odd_frame : 1; // 31 Send in odd frame +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue + uint32_t qtop_terminate : 1; // 23 Last entry for selected channel + uint32_t qtop_last_period : 1; // 24 Last entry for selected channel is a periodic entry + uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command + uint32_t qtop_ch_num : 4; // 27..30 Channel number + uint32_t qtop_odd_frame : 1; // 31 Send in odd frame + }; } dwc2_hptxsts_t; TU_VERIFY_STATIC(sizeof(dwc2_hptxsts_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t conn_status : 1; // 0 Port connect status - uint32_t conn_detected : 1; // 1 Port connect detected - uint32_t enable : 1; // 2 Port enable status - uint32_t enable_change : 1; // 3 Port enable change - uint32_t over_current_active : 1; // 4 Port Over-current active - uint32_t over_current_change : 1; // 5 Port Over-current change - uint32_t resume : 1; // 6 Port resume - uint32_t suspend : 1; // 7 Port suspend - uint32_t reset : 1; // 8 Port reset - uint32_t rsv9 : 1; // 9 Reserved - uint32_t line_status : 2; // 10..11 Line status - uint32_t power : 1; // 12 Port power - uint32_t test_control : 4; // 13..16 Port Test control - uint32_t speed : 2; // 17..18 Port speed - uint32_t rsv19_31 :13; // 19..31 Reserved -}dwc2_hprt_t; +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t conn_status : 1; // 0 Port connect status + uint32_t conn_detected : 1; // 1 Port connect detected + uint32_t enable : 1; // 2 Port enable status + uint32_t enable_change : 1; // 3 Port enable change + uint32_t over_current_active : 1; // 4 Port Over-current active + uint32_t over_current_change : 1; // 5 Port Over-current change + uint32_t resume : 1; // 6 Port resume + uint32_t suspend : 1; // 7 Port suspend + uint32_t reset : 1; // 8 Port reset + uint32_t rsv9 : 1; // 9 Reserved + uint32_t line_status : 2; // 10..11 Line status + uint32_t power : 1; // 12 Port power + uint32_t test_control : 4; // 13..16 Port Test control + uint32_t speed : 2; // 17..18 Port speed + uint32_t rsv19_31 :13; // 19..31 Reserved + }; +} dwc2_hprt_t; TU_VERIFY_STATIC(sizeof(dwc2_hprt_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t ep_size : 11; // 0..10 Maximum packet size - uint32_t ep_num : 4; // 11..14 Endpoint number - uint32_t ep_dir : 1; // 15 Endpoint direction - uint32_t rsv16 : 1; // 16 Reserved - uint32_t low_speed_dev : 1; // 17 Low-speed device - uint32_t ep_type : 2; // 18..19 Endpoint type - uint32_t err_multi_count : 2; // 20..21 Error (splitEn = 1) / Multi (SplitEn = 0) count - uint32_t dev_addr : 7; // 22..28 Device address - uint32_t odd_frame : 1; // 29 Odd frame - uint32_t disable : 1; // 30 Channel disable - uint32_t enable : 1; // 31 Channel enable +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t ep_size : 11; // 0..10 Maximum packet size + uint32_t ep_num : 4; // 11..14 Endpoint number + uint32_t ep_dir : 1; // 15 Endpoint direction + uint32_t rsv16 : 1; // 16 Reserved + uint32_t low_speed_dev : 1; // 17 Low-speed device + uint32_t ep_type : 2; // 18..19 Endpoint type + uint32_t err_multi_count : 2; // 20..21 Error (splitEn = 1) / Multi (SplitEn = 0) count + uint32_t dev_addr : 7; // 22..28 Device address + uint32_t odd_frame : 1; // 29 Odd frame + uint32_t disable : 1; // 30 Channel disable + uint32_t enable : 1; // 31 Channel enable + }; } dwc2_channel_char_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_char_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t hub_port : 7; // 0..6 Hub port number - uint32_t hub_addr : 7; // 7..13 Hub address - uint32_t xact_pos : 2; // 14..15 Transaction position - uint32_t split_compl : 1; // 16 Split completion - uint32_t rsv17_30 : 14; // 17..30 Reserved - uint32_t split_en : 1; // 31 Split enable +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t hub_port : 7; // 0..6 Hub port number + uint32_t hub_addr : 7; // 7..13 Hub address + uint32_t xact_pos : 2; // 14..15 Transaction position + uint32_t split_compl : 1; // 16 Split completion + uint32_t rsv17_30 : 14; // 17..30 Reserved + uint32_t split_en : 1; // 31 Split enable + }; } dwc2_channel_split_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t xfer_size : 19; // 0..18 Transfer size in bytes - uint32_t packet_count : 10; // 19..28 Number of packets - uint32_t pid : 2; // 29..30 Packet ID - uint32_t do_ping : 1; // 31 Do PING +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t pid : 2; // 29..30 Packet ID + uint32_t do_ping : 1; // 31 Do PING + }; } dwc2_channel_tsize_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t num : 16; // 0..15 Frame number - uint32_t remainning : 16; // 16..31 Frame remaining +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t num : 16; // 0..15 Frame number + uint32_t remainning : 16; // 16..31 Frame remaining + }; } dwc2_hfnum_t; TU_VERIFY_STATIC(sizeof(dwc2_hfnum_t) == 4, "incorrect size"); // Host Channel typedef struct { - union { - volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics - volatile dwc2_channel_char_t hcchar_bm; - }; - union { - volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control - volatile dwc2_channel_split_t hcsplt_bm; - }; - volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt - volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask - union { - volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size - volatile dwc2_channel_tsize_t hctsiz_bm; - }; - volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address - uint32_t reserved518; // 518 + 20*ch - volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address + volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics + volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control + volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt + volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask + volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size + volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address + uint32_t reserved518; // 518 + 20*ch + volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address } dwc2_channel_t; //-------------------------------------------------------------------- // Device Register Bitfield //-------------------------------------------------------------------- -typedef struct TU_ATTR_PACKED { - uint32_t speed : 2; // 0..1 Speed - uint32_t nzsts_out_handshake : 1; // 2 Non-zero-length status OUT handshake - uint32_t en_32khz_suspsend : 1; // 3 Enable 32-kHz SUSPEND mode - uint32_t address : 7; // 4..10 Device address - uint32_t period_frame_interval : 2; // 11..12 Periodic frame interval - uint32_t en_out_nak : 1; // 13 Enable Device OUT NAK - uint32_t xcvr_delay : 1; // 14 Transceiver delay - uint32_t erratic_int_mask : 1; // 15 Erratic interrupt mask - uint32_t rsv16 : 1; // 16 Reserved - uint32_t ipg_iso_support : 1; // 17 Interpacket gap ISO support - uint32_t epin_mismatch_count : 5; // 18..22 EP IN mismatch count - uint32_t dma_desc : 1; // 23 Enable scatter/gatter DMA descriptor - uint32_t period_schedule_interval : 2; // 24..25 Periodic schedule interval for scatter/gatter DMA - uint32_t resume_valid : 6; // 26..31 Resume valid period +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t speed : 2; // 0..1 Speed + uint32_t nzsts_out_handshake : 1; // 2 Non-zero-length status OUT handshake + uint32_t en_32khz_suspsend : 1; // 3 Enable 32-kHz SUSPEND mode + uint32_t address : 7; // 4..10 Device address + uint32_t period_frame_interval : 2; // 11..12 Periodic frame interval + uint32_t en_out_nak : 1; // 13 Enable Device OUT NAK + uint32_t xcvr_delay : 1; // 14 Transceiver delay + uint32_t erratic_int_mask : 1; // 15 Erratic interrupt mask + uint32_t rsv16 : 1; // 16 Reserved + uint32_t ipg_iso_support : 1; // 17 Interpacket gap ISO support + uint32_t epin_mismatch_count : 5; // 18..22 EP IN mismatch count + uint32_t dma_desc : 1; // 23 Enable scatter/gather DMA descriptor + uint32_t period_schedule_interval : 2; // 24..25 Periodic schedule interval for scatter/gather DMA + uint32_t resume_valid : 6; // 26..31 Resume valid period + }; } dwc2_dcfg_t; TU_VERIFY_STATIC(sizeof(dwc2_dcfg_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t remote_wakeup_signal : 1; // 0 Remote wakeup signal - uint32_t soft_disconnet : 1; // 1 Soft disconnect - uint32_t gnp_in_nak_status : 1; // 2 Global non-periodic NAK IN status - uint32_t gout_nak_status : 1; // 3 Global OUT NAK status - uint32_t test_control : 3; // 4..6 Test control - uint32_t set_gnp_in_nak : 1; // 7 Set global non-periodic IN NAK - uint32_t clear_gnp_in_nak : 1; // 8 Clear global non-periodic IN NAK - uint32_t set_gout_nak : 1; // 9 Set global OUT NAK - uint32_t clear_gout_nak : 1; // 10 Clear global OUT NAK - uint32_t poweron_prog_done : 1; // 11 Power-on programming done - uint32_t rsv12 : 1; // 12 Reserved - uint32_t global_multi_count : 2; // 13..14 Global multi-count - uint32_t ignore_frame_number : 1; // 15 Ignore frame number - uint32_t nak_on_babble : 1; // 16 NAK on babble - uint32_t en_cont_on_bna : 1; // 17 Enable continue on BNA - uint32_t deep_sleep_besl_reject : 1; // 18 Deep sleep BESL reject - uint32_t service_interval : 1; // 19 Service interval for ISO IN endpoint - uint32_t rsv20_31 :12; // 20..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t remote_wakeup_signal : 1; // 0 Remote wakeup signal + uint32_t soft_disconnet : 1; // 1 Soft disconnect + uint32_t gnp_in_nak_status : 1; // 2 Global non-periodic NAK IN status + uint32_t gout_nak_status : 1; // 3 Global OUT NAK status + uint32_t test_control : 3; // 4..6 Test control + uint32_t set_gnp_in_nak : 1; // 7 Set global non-periodic IN NAK + uint32_t clear_gnp_in_nak : 1; // 8 Clear global non-periodic IN NAK + uint32_t set_gout_nak : 1; // 9 Set global OUT NAK + uint32_t clear_gout_nak : 1; // 10 Clear global OUT NAK + uint32_t poweron_prog_done : 1; // 11 Power-on programming done + uint32_t rsv12 : 1; // 12 Reserved + uint32_t global_multi_count : 2; // 13..14 Global multi-count + uint32_t ignore_frame_number : 1; // 15 Ignore frame number + uint32_t nak_on_babble : 1; // 16 NAK on babble + uint32_t en_cont_on_bna : 1; // 17 Enable continue on BNA + uint32_t deep_sleep_besl_reject : 1; // 18 Deep sleep BESL reject + uint32_t service_interval : 1; // 19 Service interval for ISO IN endpoint + uint32_t rsv20_31 :12; // 20..31 Reserved + }; } dwc2_dctl_t; TU_VERIFY_STATIC(sizeof(dwc2_dctl_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t suspend_status : 1; // 0 Suspend status - uint32_t enum_speed : 2; // 1..2 Enumerated speed - uint32_t erratic_err : 1; // 3 Erratic error - uint32_t rsv4_7 : 4; // 4..7 Reserved - uint32_t frame_number : 14; // 8..21 Frame/MicroFrame number - uint32_t line_status : 2; // 22..23 Line status - uint32_t rsv24_31 : 8; // 24..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t suspend_status : 1; // 0 Suspend status + uint32_t enum_speed : 2; // 1..2 Enumerated speed + uint32_t erratic_err : 1; // 3 Erratic error + uint32_t rsv4_7 : 4; // 4..7 Reserved + uint32_t frame_number : 14; // 8..21 Frame/MicroFrame number + uint32_t line_status : 2; // 22..23 Line status + uint32_t rsv24_31 : 8; // 24..31 Reserved + }; } dwc2_dsts_t; TU_VERIFY_STATIC(sizeof(dwc2_dsts_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t xfer_complete : 1; // 0 Transfer complete - uint32_t disabled : 1; // 1 Endpoint disabled - uint32_t ahb_err : 1; // 2 AHB error - uint32_t timeout : 1; // 3 Timeout - uint32_t in_rx_txfe : 1; // 4 IN token received when TxFIFO is empty - uint32_t in_rx_ep_mismatch : 1; // 5 IN token received with EP mismatch - uint32_t in_ep_nak_effective : 1; // 6 IN endpoint NAK effective - uint32_t txfifo_empty : 1; // 7 TX FIFO empty - uint32_t txfifo_underrun : 1; // 8 Tx FIFO under run - uint32_t bna : 1; // 9 Buffer not available - uint32_t rsv10 : 1; // 10 Reserved - uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status - uint32_t babble_err : 1; // 12 Babble error - uint32_t nak : 1; // 13 NAK - uint32_t nyet : 1; // 14 NYET - uint32_t rsv14_31 :17; // 15..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t xfer_complete : 1; // 0 Transfer complete + uint32_t disabled : 1; // 1 Endpoint disabled + uint32_t ahb_err : 1; // 2 AHB error + uint32_t timeout : 1; // 3 Timeout + uint32_t in_rx_txfe : 1; // 4 IN token received when TxFIFO is empty + uint32_t in_rx_ep_mismatch : 1; // 5 IN token received with EP mismatch + uint32_t in_ep_nak_effective : 1; // 6 IN endpoint NAK effective + uint32_t txfifo_empty : 1; // 7 TX FIFO empty + uint32_t txfifo_underrun : 1; // 8 Tx FIFO under run + uint32_t bna : 1; // 9 Buffer not available + uint32_t rsv10 : 1; // 10 Reserved + uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status + uint32_t babble_err : 1; // 12 Babble error + uint32_t nak : 1; // 13 NAK + uint32_t nyet : 1; // 14 NYET + uint32_t rsv14_31 :17; // 15..31 Reserved + }; } dwc2_diepint_t; TU_VERIFY_STATIC(sizeof(dwc2_diepint_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t mps : 11; // 0..10 Maximum packet size, EP0 only use 2 bit - uint32_t next_ep : 4; // 11..14 Next endpoint number - uint32_t active : 1; // 15 Active - const uint32_t dpid_iso_odd : 1; // 16 DATA0/DATA1 for bulk/interrupt, odd frame for isochronous - const uint32_t nak_status : 1; // 17 NAK status - uint32_t type : 2; // 18..19 Endpoint type - uint32_t rsv20 : 1; // 20 Reserved - uint32_t stall : 1; // 21 Stall - uint32_t tx_fifo_num : 4; // 22..25 Tx FIFO number (IN) - uint32_t clear_nak : 1; // 26 Clear NAK - uint32_t set_nak : 1; // 27 Set NAK - uint32_t set_data0_iso_even : 1; // 28 Set DATA0 if bulk/interrupt, even frame for isochronous - uint32_t set_data1_iso_odd : 1; // 29 Set DATA1 if bulk/interrupt, odd frame for isochronous - uint32_t disable : 1; // 30 Disable - uint32_t enable : 1; // 31 Enable +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t mps : 11; // 0..10 Maximum packet size, EP0 only use 2 bits + uint32_t next_ep : 4; // 11..14 Next endpoint number + uint32_t active : 1; // 15 Active + uint32_t dpid_iso_odd : 1; // 16 DATA0/DATA1 for bulk/interrupt, odd frame for isochronous + uint32_t nak_status : 1; // 17 NAK status + uint32_t type : 2; // 18..19 Endpoint type + uint32_t rsv20 : 1; // 20 Reserved + uint32_t stall : 1; // 21 Stall + uint32_t tx_fifo_num : 4; // 22..25 Tx FIFO number (IN) + uint32_t clear_nak : 1; // 26 Clear NAK + uint32_t set_nak : 1; // 27 Set NAK + uint32_t set_data0_iso_even : 1; // 28 Set DATA0 if bulk/interrupt, even frame for isochronous + uint32_t set_data1_iso_odd : 1; // 29 Set DATA1 if bulk/interrupt, odd frame for isochronous + uint32_t disable : 1; // 30 Disable + uint32_t enable : 1; // 31 Enable + }; } dwc2_depctl_t; TU_VERIFY_STATIC(sizeof(dwc2_depctl_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t xfer_complete : 1; // 0 Transfer complete - uint32_t disabled : 1; // 1 Endpoint disabled - uint32_t ahb_err : 1; // 2 AHB error - uint32_t setup_phase_done : 1; // 3 Setup phase done - uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled - uint32_t status_phase_rx : 1; // 5 Status phase received - uint32_t setup_b2b : 1; // 6 Setup packet back-to-back - uint32_t rsv7 : 1; // 7 Reserved - uint32_t out_packet_err : 1; // 8 OUT packet error - uint32_t bna : 1; // 9 Buffer not available - uint32_t rsv10 : 1; // 10 Reserved - uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status - uint32_t babble_err : 1; // 12 Babble error - uint32_t nak : 1; // 13 NAK - uint32_t nyet : 1; // 14 NYET - uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) - uint32_t rsv16_31 :16; // 16..31 Reserved +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t xfer_complete : 1; // 0 Transfer complete + uint32_t disabled : 1; // 1 Endpoint disabled + uint32_t ahb_err : 1; // 2 AHB error + uint32_t setup_phase_done : 1; // 3 Setup phase done + uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled + uint32_t status_phase_rx : 1; // 5 Status phase received + uint32_t setup_b2b : 1; // 6 Setup packet back-to-back + uint32_t rsv7 : 1; // 7 Reserved + uint32_t out_packet_err : 1; // 8 OUT packet error + uint32_t bna : 1; // 9 Buffer not available + uint32_t rsv10 : 1; // 10 Reserved + uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status + uint32_t babble_err : 1; // 12 Babble error + uint32_t nak : 1; // 13 NAK + uint32_t nyet : 1; // 14 NYET + uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) + uint32_t rsv16_31 :16; // 16..31 Reserved + }; } dwc2_doepint_t; TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED { - uint32_t xfer_size : 19; // 0..18 Transfer size in bytes - uint32_t packet_count : 10; // 19..28 Number of packets - uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID +typedef union { + uint32_t value; + struct TU_ATTR_PACKED { + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID + }; } dwc2_ep_tsize_t; TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size"); @@ -601,26 +656,19 @@ typedef struct { union { volatile uint32_t diepctl; volatile uint32_t doepctl; - volatile uint32_t ctl; - volatile dwc2_depctl_t ctl_bm; }; uint32_t rsv04; union { volatile uint32_t intr; - volatile uint32_t diepint; - volatile dwc2_diepint_t diepint_bm; - volatile uint32_t doepint; - volatile dwc2_doepint_t doepint_bm; }; uint32_t rsv0c; union { volatile uint32_t dieptsiz; volatile uint32_t doeptsiz; volatile uint32_t tsiz; - volatile dwc2_ep_tsize_t tsiz_bm; }; union { volatile uint32_t diepdma; @@ -628,7 +676,7 @@ typedef struct { }; volatile uint32_t dtxfsts; uint32_t rsv1c; -}dwc2_dep_t; +} dwc2_dep_t; TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); @@ -637,156 +685,107 @@ TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); //-------------------------------------------------------------------- typedef struct { //------------- Core Global -------------// - union { - volatile uint32_t gotgctl; // 000 OTG Control and Status - volatile dwc2_gotgctl_t gotgctl_bm; - }; - union { - volatile uint32_t gotgint; // 004 OTG Interrupt - volatile dwc2_gotgint_t gotgint_bm; - }; - union { - volatile uint32_t gahbcfg; // 008 AHB Configuration - volatile dwc2_gahbcfg_t gahbcfg_bm; - }; - union { - volatile uint32_t gusbcfg; // 00c USB Configuration - volatile dwc2_gusbcfg_t gusbcfg_bm; - }; - union { - volatile uint32_t grstctl; // 010 Reset - volatile dwc2_grstctl_t grstctl_bm; - }; - volatile uint32_t gintsts; // 014 Interrupt - volatile uint32_t gintmsk; // 018 Interrupt Mask - volatile uint32_t grxstsr; // 01c Receive Status Debug Read - union { - volatile uint32_t grxstsp; // 020 Receive Status Read/Pop - volatile dwc2_grxstsp_t grxstsp_bm; - }; - volatile uint32_t grxfsiz; // 024 Receive FIFO Size + volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile uint32_t gotgint; // 004 OTG Interrupt + volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile uint32_t gusbcfg; // 00c USB Configuration + volatile uint32_t grstctl; // 010 Reset + volatile uint32_t gintsts; // 014 Interrupt + volatile uint32_t gintmsk; // 018 Interrupt Mask + volatile uint32_t grxstsr; // 01c Receive Status Debug Read + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile uint32_t grxfsiz; // 024 Receive FIFO Size union { volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size }; union { volatile uint32_t hnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status - volatile dwc2_hnptxsts_t hnptxsts_bm; volatile uint32_t gnptxsts; }; - volatile uint32_t gi2cctl; // 030 I2C Address - volatile uint32_t gpvndctl; // 034 PHY Vendor Control + volatile uint32_t gi2cctl; // 030 I2C Address + volatile uint32_t gpvndctl; // 034 PHY Vendor Control union { volatile uint32_t ggpio; // 038 General Purpose IO volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration }; - volatile uint32_t guid; // 03C User (Application programmable) ID - volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version - volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) - union { - volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 - volatile dwc2_ghwcfg2_t ghwcfg2_bm; - }; - union { - volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 - volatile dwc2_ghwcfg3_t ghwcfg3_bm; - }; + volatile uint32_t guid; // 03C User (Application programmable) ID + volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 union { volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 volatile dwc2_ghwcfg4_t ghwcfg4_bm; }; - volatile uint32_t glpmcfg; // 054 Core LPM Configuration - volatile uint32_t gpwrdn; // 058 Power Down - volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration - volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status - uint32_t reserved64[39]; // 064..0FF - volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size - volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size - uint32_t reserved140[176]; // 140..3FF - - //------------ Host -------------// - volatile uint32_t hcfg; // 400 Host Configuration - volatile uint32_t hfir; // 404 Host Frame Interval - union { - volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining - volatile dwc2_hfnum_t hfnum_bm; - }; - uint32_t reserved40c; // 40C - union { - volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status - volatile dwc2_hptxsts_t hptxsts_bm; - }; - volatile uint32_t haint; // 414 Host All Channels Interrupt - volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask - volatile uint32_t hflbaddr; // 41C Host Frame List Base Address - uint32_t reserved420[8]; // 420..43F - union { - volatile uint32_t hprt; // 440 Host Port Control and Status - volatile dwc2_hprt_t hprt_bm; - }; - uint32_t reserved444[47]; // 444..4FF - - //------------- Host Channel -------------// - dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 - uint32_t reserved700[64]; // 700..7FF - - //------------- Device -----------// - union { - volatile uint32_t dcfg; // 800 Device Configuration - volatile dwc2_dcfg_t dcfg_bm; - }; + volatile uint32_t glpmcfg; // 054 Core LPM Configuration + volatile uint32_t gpwrdn; // 058 Power Down + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status + uint32_t reserved64[39]; // 064..0FF + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size + uint32_t reserved140[176]; // 140..3FF + + //------------ Host -------------// + volatile uint32_t hcfg; // 400 Host Configuration + volatile uint32_t hfir; // 404 Host Frame Interval + volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining + uint32_t reserved40c; // 40C + volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status + volatile uint32_t haint; // 414 Host All Channels Interrupt + volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask + volatile uint32_t hflbaddr; // 41C Host Frame List Base Address + uint32_t reserved420[8]; // 420..43F + volatile uint32_t hprt; // 440 Host Port Control and Status + uint32_t reserved444[47]; // 444..4FF + + //------------- Host Channel -------------// + dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 + uint32_t reserved700[64]; // 700..7FF + + //------------- Device -----------// + volatile uint32_t dcfg; // 800 Device Configuration + volatile uint32_t dctl; // 804 Device Control + volatile uint32_t dsts; // 808 Device Status (RO) + uint32_t reserved80c; // 80C + volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile uint32_t daint; // 818 Device All Endpoints Interrupt + volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time + volatile uint32_t dthrctl; // 830 Device threshold Control + volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + + // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line + // require OTG_MULTI_PROC_INTRPT=1 + volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask + volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask + volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask + uint32_t reserved8c0[16]; // 8C0..8FF + + //------------- Device Endpoint -------------// union { - volatile uint32_t dctl; // 804 Device Control - volatile dwc2_dctl_t dctl_bm; - }; - union { - volatile uint32_t dsts; // 808 Device Status (RO) - volatile dwc2_dsts_t dsts_bm; - }; - uint32_t reserved80c; // 80C - union { - volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask - volatile dwc2_diepint_t diepmsk_bm; - }; - union { - volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask - volatile dwc2_doepint_t doepmsk_bm; - }; - volatile uint32_t daint; // 818 Device All Endpoints Interrupt - volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask - volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 - volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 - volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time - volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time - volatile uint32_t dthrctl; // 830 Device threshold Control - volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask - - // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line - // require OTG_MULTI_PROC_INTRPT=1 - volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask - volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask - volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask - uint32_t reserved8c0[16]; // 8C0..8FF - - //------------- Device Endpoint -------------// - union { - dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT - struct { - dwc2_dep_t epin[16]; // 900..AFF IN Endpoints - dwc2_dep_t epout[16]; // B00..CFF OUT Endpoints - }; + dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT + struct { + dwc2_dep_t epin[16]; // 900..AFF IN Endpoints + dwc2_dep_t epout[16]; // B00..CFF OUT Endpoints }; - uint32_t reservedd00[64]; // D00..DFF + }; + uint32_t reservedd00[64]; // D00..DFF - //------------- Power Clock -------------// - volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control - volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 - uint32_t reservede08[126]; // E08..FFF + //------------- Power Clock -------------// + volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control + volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 + uint32_t reservede08[126]; // E08..FFF - //------------- FIFOs -------------// - // Word-accessed only using first pointer since it auto shift - volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO + //------------- FIFOs -------------// + // Word-accessed only using first pointer since it auto shift + volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO } dwc2_regs_t; TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b13479b02..af17bb59a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -44,7 +44,7 @@ #endif #define DWC2_CHANNEL_COUNT_MAX 16 // absolute max channel count -#define DWC2_CHANNEL_COUNT(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX) +#define DWC2_CHANNEL_COUNT(_dwc2) ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2}; tu_min8(ghwcfg2.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX);}) TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index"); @@ -118,7 +118,8 @@ hcd_data_t _hcd_data; //-------------------------------------------------------------------- TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc2) { tusb_speed_t speed; - switch(dwc2->hprt_bm.speed) { + const dwc2_hprt_t hprt = {.value = dwc2->hprt}; + switch(hprt.speed) { case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break; case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break; @@ -133,7 +134,8 @@ TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; } #if CFG_TUH_MEM_DCACHE_ENABLE @@ -168,15 +170,18 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { } // Check if is periodic (interrupt/isochronous) -TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) { - return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; +TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(uint32_t hcchar) { + const dwc2_channel_char_t hcchar_bm = {.value = hcchar}; + return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; } TU_ATTR_ALWAYS_INLINE static inline uint8_t req_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { if (is_period) { - return dwc2->hptxsts_bm.req_queue_available; + const dwc2_hptxsts_t hptxsts = {.value = dwc2->hptxsts}; + return hptxsts.req_queue_available; } else { - return dwc2->hnptxsts_bm.req_queue_available; + const dwc2_hnptxsts_t hnptxsts = {.value = dwc2->hnptxsts}; + return hnptxsts.req_queue_available; } } @@ -188,7 +193,7 @@ TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) { // disable also require request queue - TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type))); + TU_ASSERT(req_queue_avail(dwc2, channel_is_periodic(channel->hcchar))); channel->hcintmsk |= HCINT_HALTED; channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA return true; @@ -196,7 +201,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2 // attempt to send IN token to receive data TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) { - TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type))); + TU_ASSERT(req_queue_avail(dwc2, channel_is_periodic(channel->hcchar))); channel->hcchar |= HCCHAR_CHENA; return true; } @@ -206,8 +211,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dw const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (_hcd_data.xfer[ch_id].allocated) { - const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; - if (hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num && (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) { + const dwc2_channel_char_t hcchar = {.value = dwc2->channel[ch_id].hcchar}; + if (hcchar.dev_addr == dev_addr && hcchar.ep_num == ep_num && (ep_num == 0 || hcchar.ep_dir == ep_dir)) { return ch_id; } } @@ -304,12 +309,13 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t pa static void dfifo_host_init(uint8_t rhport) { const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per channel const bool is_dma = dma_host_enabled(dwc2); uint16_t dfifo_top = dwc2_controller->ep_fifo_size/4; if (is_dma) { - dfifo_top -= dwc2->ghwcfg2_bm.num_host_ch; + dfifo_top -= ghwcfg2.num_host_ch; } // fixed allocation for now, improve later: @@ -319,7 +325,7 @@ static void dfifo_host_init(uint8_t rhport) { uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4; uint16_t nptxfsiz = 2 * nptx_largest; - uint16_t rxfsiz = 2 * (ptx_largest + 2) + dwc2->ghwcfg2_bm.num_host_ch; + uint16_t rxfsiz = 2 * (ptx_largest + 2) + ghwcfg2.num_host_ch; TU_ASSERT(dfifo_top >= (nptxfsiz + rxfsiz),); uint16_t ptxfsiz = dfifo_top - (nptxfsiz + rxfsiz); @@ -509,10 +515,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* // clean up channel after part of transfer is done but the whole urb is not complete static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - dwc2_channel_t* channel = &dwc2->channel[ch_id]; + const dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - edpt->next_pid = channel->hctsiz_bm.pid; // save PID + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; + edpt->next_pid = hctsiz.pid; // save PID /* Since hctsiz.xfersize field reflects the number of bytes transferred via the AHB, not the USB) * For IN: we can use hctsiz.xfersize as remaining bytes. @@ -520,9 +527,10 @@ static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { * number of packets that have been transferred via the USB. This is always an integral number of packets if the * transfer was halted before its normal completion. */ - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); - const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + const uint16_t remain_packets = hctsiz.packet_count; + const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; + const uint16_t total_packets = cal_packet_count(edpt->buflen, hcchar.ep_size); + const uint16_t actual_bytes = (total_packets - remain_packets) * hcchar.ep_size; xfer->fifo_bytes = 0; xfer->xferred_bytes += actual_bytes; @@ -535,7 +543,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); + bool const is_period = channel_is_periodic(hcchar_bm->ep_type); // clear previous state xfer->fifo_bytes = 0; @@ -548,12 +556,15 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // hctsiz: zero length packet still count as 1 const uint16_t packet_count = cal_packet_count(edpt->buflen, hcchar_bm->ep_size); - uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | edpt->buflen; + dwc2_channel_tsize_t hctsiz = {.value = 0}; + hctsiz.pid = edpt->next_pid; // next PID is set in transfer complete interrupt + hctsiz.packet_count = packet_count; + hctsiz.xfer_size = edpt->buflen; if (edpt->do_ping && edpt->speed == TUSB_SPEED_HIGH && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { - hctsiz |= HCTSIZ_DOPING; + hctsiz.do_ping = 1; } - channel->hctsiz = hctsiz; + channel->hctsiz = hctsiz.value; edpt->do_ping = 0; // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet @@ -699,13 +710,16 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ + if (channel_is_periodic(channel->hcchar)){ + const dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; // retry immediately for periodic split NYET if we haven't reach max retry - if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl && (hcint & HCINT_NYET || xfer->halted_nyet)) { + if (hcsplt.split_en && hcsplt.split_compl && (hcint & HCINT_NYET || xfer->halted_nyet)) { xfer->period_split_nyet_count++; xfer->halted_nyet = 0; if (xfer->period_split_nyet_count < HCD_XFER_PERIOD_SPLIT_NYET_MAX) { - channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + dwc2_channel_char_t hcchar = {.value = channel->hcchar}; + hcchar.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + channel->hcchar = hcchar.value; channel_send_in_token(dwc2, channel); return; } else { @@ -715,7 +729,8 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } // for periodic, de-allocate channel, enable SOF set frame counter for later transfer - edpt->next_pid = channel->hctsiz_bm.pid; // save PID + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; + edpt->next_pid = hctsiz.pid; // save PID edpt->uframe_countdown = edpt->uframe_interval; dwc2->gintmsk |= GINTSTS_SOF; @@ -756,13 +771,13 @@ static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Pop control word off FIFO - const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; - const uint8_t ch_id = grxstsp_bm.ep_ch_num; + const dwc2_grxstsp_t grxstsp = {.value= dwc2->grxstsp}; + const uint8_t ch_id = grxstsp.ep_ch_num; - switch (grxstsp_bm.packet_status) { + switch (grxstsp.packet_status) { case GRXSTS_PKTSTS_RX_DATA: { // In packet received, pop this entry --> ACK interrupt - const uint16_t byte_count = grxstsp_bm.byte_count; + const uint16_t byte_count = grxstsp.byte_count; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; @@ -796,25 +811,26 @@ static void handle_rxflvl_irq(uint8_t rhport) { // return true if there is still pending data and need more ISR static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) - volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); + const dwc2_hptxsts_t txsts = {.value = (is_periodic ? dwc2->hptxsts : dwc2->hnptxsts)}; const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; + const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; // skip writing to FIFO if channel is expecting halted. - if (!(channel->hcintmsk & HCINT_HALTED) && (channel->hcchar_bm.ep_dir == TUSB_DIR_OUT)) { + if (!(channel->hcintmsk & HCINT_HALTED) && (hcchar.ep_dir == TUSB_DIR_OUT)) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; + const uint16_t remain_packets = hctsiz.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { const uint16_t remain_bytes = edpt->buflen - xfer->fifo_bytes; - const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar.ep_size); // skip if there is not enough space in FIFO and RequestQueue. // Packet's last word written to FIFO will trigger a request queue - if ((xact_bytes > (txsts_bm->fifo_available << 2)) || (txsts_bm->req_queue_available == 0)) { + if ((xact_bytes > (txsts.fifo_available << 2)) || (txsts.req_queue_available == 0)) { return true; } @@ -831,23 +847,27 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; + dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; bool is_done = false; - // if (channel->hcsplt_bm.split_en) { + // if (hcsplt.split_en) { // if (edpt->hcchar_bm.ep_num == 1) { - // TU_LOG1("Frame %u, ch %u: ep %u, hcint 0x%04lX ", dwc2->hfnum_bm.num, ch_id, channel->hcchar_bm.ep_num, hcint); + // TU_LOG1("Frame %u, ch %u: ep %u, hcint 0x%04lX ", dwc2->hfnum_bm.num, ch_id, hcsplt.ep_num, hcint); // print_hcint(hcint); // } if (hcint & HCINT_XFER_COMPLETE) { if (edpt->hcchar_bm.ep_num != 0) { - edpt->next_pid = channel->hctsiz_bm.pid; // save pid (already toggled) + edpt->next_pid = hctsiz.pid; // save pid (already toggled) } - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - if (channel->hcsplt_bm.split_en && remain_packets && xfer->fifo_bytes == edpt->hcchar_bm.ep_size) { + const uint16_t remain_packets = hctsiz.packet_count; + if (hcsplt.split_en && remain_packets && xfer->fifo_bytes == edpt->hcchar_bm.ep_size) { // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more - channel->hcsplt_bm.split_compl = 0; + hcsplt.split_compl = 0; + channel->hcsplt = hcsplt.value; } else { xfer->result = XFER_RESULT_SUCCESS; } @@ -866,34 +886,38 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h channel_disable(dwc2, channel); } else if (hcint & HCINT_NYET) { // restart complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; xfer->halted_nyet = 1; channel_disable(dwc2, channel); } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - if (channel->hcsplt_bm.split_en) { - channel->hcsplt_bm.split_compl = 0; // restart with start-split + if (hcsplt.split_en) { + hcsplt.split_compl = 0; // restart with start-split + channel->hcsplt = hcsplt.value; } channel_disable(dwc2, channel); } else if (hcint & HCINT_ACK) { xfer->err_count = 0; - if (channel->hcsplt_bm.split_en) { - if (!channel->hcsplt_bm.split_compl) { + if (hcsplt.split_en) { + if (!hcsplt.split_compl) { // start split is ACK --> do complete split channel->hcintmsk |= HCINT_NYET; - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel_send_in_token(dwc2, channel); } else { // do nothing for complete split with DATA, this will trigger XferComplete and handled there } } else { // ACK with data - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t remain_packets = hctsiz.packet_count; if (remain_packets) { // still more packet to receive, also reset to start split - channel->hcsplt_bm.split_compl = 0; + hcsplt.split_compl = 0; + channel->hcsplt = hcsplt.value; channel_send_in_token(dwc2, channel); } } @@ -922,6 +946,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { @@ -933,9 +958,10 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel_disable(dwc2, channel); } else if (hcint & HCINT_NYET) { xfer->err_count = 0; - if (channel->hcsplt_bm.split_en) { + if (hcsplt.split_en) { // retry complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } else { edpt->do_ping = 1; @@ -968,9 +994,10 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; - if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + if (hcsplt.split_en && !hcsplt.split_compl) { // start split is ACK --> do complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } } @@ -989,6 +1016,9 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + dwc2_channel_char_t hcchar = {.value = channel->hcchar}; + dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; bool is_done = false; @@ -996,8 +1026,8 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci if (hcint & HCINT_HALTED) { if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) { - const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t remain_bytes = (uint16_t) hctsiz.xfer_size; + const uint16_t remain_packets = hctsiz.packet_count; const uint16_t actual_len = edpt->buflen - remain_bytes; xfer->xferred_bytes += actual_len; @@ -1007,13 +1037,14 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci xfer->result = XFER_RESULT_STALLED; } else if (hcint & HCINT_BABBLE_ERR) { xfer->result = XFER_RESULT_FAILED; - } else if (channel->hcsplt_bm.split_en && remain_packets && actual_len == edpt->hcchar_bm.ep_size) { + } else if (hcsplt.split_en && remain_packets && actual_len == hcchar.ep_size) { // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more is_done = false; edpt->buffer += actual_len; edpt->buflen -= actual_len; - channel->hcsplt_bm.split_compl = 0; + hcsplt.split_compl = 0; + channel->hcsplt = hcsplt.value; channel_xfer_in_retry(dwc2, ch_id, hcint); } else { xfer->result = XFER_RESULT_SUCCESS; @@ -1028,33 +1059,38 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci xfer->result = XFER_RESULT_FAILED; } else { channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; - channel->hcsplt_bm.split_compl = 0; + hcsplt.split_compl = 0; + channel->hcsplt = hcsplt.value; channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_NYET) { // Must handle nyet before nak or ack. Could get a nyet at the same time as either of those on a BULK/CONTROL // OUT that started with a PING. The nyet takes precedence. - if (channel->hcsplt_bm.split_en) { + if (hcsplt.split_en) { // split not yet mean hub has no data, retry complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; - if (channel->hcsplt_bm.split_en) { + if (hcsplt.split_en) { // start split is ACK --> do complete split // TODO: for ISO must use xact_pos to plan complete split based on microframe (up to 187.5 bytes/uframe) - channel->hcsplt_bm.split_compl = 1; - if (edpt_is_periodic(channel->hcchar_bm.ep_type)) { - channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; + if (channel_is_periodic(channel->hcchar)) { + hcchar.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + channel->hcchar = hcchar.value; } channel_send_in_token(dwc2, channel); } } else if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { xfer->err_count = 0; channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR); - channel->hcsplt_bm.split_compl = 0; // restart with start-split + hcsplt.split_compl = 0; // restart with start-split + channel->hcsplt = hcsplt.value; channel_xfer_in_retry(dwc2, ch_id, hcint); } else if (hcint & HCINT_FARME_OVERRUN) { // retry start-split in next binterval @@ -1069,6 +1105,8 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; + dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; bool is_done = false; @@ -1104,16 +1142,18 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc } } } else if (hcint & HCINT_NYET) { - if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { + if (hcsplt.split_en && hcsplt.split_compl) { // split not yet mean hub has no data, retry complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; - if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + if (hcsplt.split_en && !hcsplt.split_compl) { // start split is ACK --> do complete split - channel->hcsplt_bm.split_compl = 1; + hcsplt.split_compl = 1; + channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } } @@ -1136,7 +1176,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); - dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + dwc2_channel_char_t hcchar = {.value = channel->hcchar}; const uint32_t hcint = channel->hcint; channel->hcint = hcint; // clear interrupt @@ -1144,7 +1184,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { bool is_done = false; if (is_dma) { #if CFG_TUH_DWC2_DMA_ENABLE - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + if (hcchar.ep_dir == TUSB_DIR_OUT) { is_done = handle_channel_out_dma(dwc2, ch_id, hcint); } else { is_done = handle_channel_in_dma(dwc2, ch_id, hcint); @@ -1156,7 +1196,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { #endif } else { #if CFG_TUH_DWC2_SLAVE_ENABLE - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + if (hcchar.ep_dir == TUSB_DIR_OUT) { is_done = handle_channel_out_slave(dwc2, ch_id, hcint); } else { is_done = handle_channel_in_slave(dwc2, ch_id, hcint); @@ -1165,8 +1205,8 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { } if (is_done) { - const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->xferred_bytes, xfer->result, in_isr); + const uint8_t ep_addr = tu_edpt_addr(hcchar.ep_num, hcchar.ep_dir); + hcd_event_xfer_complete(hcchar.dev_addr, ep_addr, xfer->xferred_bytes, (xfer_result_t)xfer->result, in_isr); channel_dealloc(dwc2, ch_id); } } @@ -1185,7 +1225,7 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { for(uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) { hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->uframe_countdown > 0) { + if (edpt->hcchar_bm.enable && channel_is_periodic(edpt->hcchar) && edpt->uframe_countdown > 0) { edpt->uframe_countdown -= tu_min32(ucount, edpt->uframe_countdown); if (edpt->uframe_countdown == 0) { if (!edpt_xfer_kickoff(dwc2, ep_id)) { @@ -1204,10 +1244,10 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; - const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; + const dwc2_gusbcfg_t gusbcfg = {.value = dwc2->gusbcfg}; uint32_t phy_clock; - if (gusbcfg_bm.phy_sel) { + if (gusbcfg.phy_sel) { phy_clock = 48; // dedicated FS is 48Mhz if (speed == TUSB_SPEED_LOW) { hcfg |= HCFG_FSLS_PHYCLK_SEL_6MHZ; @@ -1215,11 +1255,11 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; } } else { - if (gusbcfg_bm.ulpi_utmi_sel) { + if (gusbcfg.ulpi_utmi_sel) { phy_clock = 60; // ULPI 8-bit is 60Mhz } else { // UTMI+ 16-bit is 30Mhz, 8-bit is 60Mhz - phy_clock = gusbcfg_bm.phy_if16 ? 30 : 60; + phy_clock = gusbcfg.phy_if16 ? 30 : 60; // Enable UTMI+ low power mode 48Mhz external clock if not highspeed if (speed == TUSB_SPEED_HIGH) { @@ -1252,7 +1292,7 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { static void handle_hprt_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; - const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; + const dwc2_hprt_t hprt_bm = {.value = hprt}; if (dwc2->hprt & HPRT_CONN_DETECT) { // Port Connect Detect -- cgit v1.3.1 From 2aff61ccb3797b85b99d6a1f3c3fb04a52f0d4fc Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Wed, 9 Apr 2025 19:40:03 +0200 Subject: Fix CI. Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index af17bb59a..f3dc23b9c 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -847,7 +847,6 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; bool is_done = false; -- cgit v1.3.1 From 72357cdb20ee7dca5a19d02ce9b7f14d237fb29e Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Fri, 11 Apr 2025 12:15:56 +0200 Subject: dwc2/host: HFIR: Fix timing off-by-one --- src/portable/synopsys/dwc2/hcd_dwc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7cbef05b7..6f7551ed7 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1242,9 +1242,9 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; if (speed == TUSB_SPEED_HIGH) { - hfir |= 125*phy_clock; + hfir |= 125*phy_clock - 1; // The "- 1" is the correct value. The Synopsys databook was corrected in 3.30a } else { - hfir |= 1000*phy_clock; + hfir |= 1000*phy_clock - 1; } dwc2->hfir = hfir; -- cgit v1.3.1 From 2064ee470d6c7b434d6b3aafe017ed60c3b17ab5 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Fri, 11 Apr 2025 12:14:07 +0200 Subject: dwc2/host: attach debouncing fixes --- src/host/usbh.c | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 26 +++++++++++++++++++++++--- 2 files changed, 24 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index e60db53da..4b0f4d488 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1038,7 +1038,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) // Check if dev0 is removed if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) && (event->connection.hub_port == _dev0.hub_port)) { - _dev0.enumerating = 0; + //_dev0.enumerating = 0;// Causes assert in dwc2 process_enumeration() -> ENUM_ADDR0_DEVICE_DESC } break; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7cbef05b7..65288e30c 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -109,6 +109,7 @@ typedef struct { typedef struct { hcd_xfer_t xfer[DWC2_CHANNEL_COUNT_MAX]; hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX]; + bool attach_debounce; // if true: wait for the debounce delay before issuing new attach events } hcd_data_t; hcd_data_t _hcd_data; @@ -413,6 +414,11 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { + // this is called from enum_new_device() - after the debouncing delays + if (_hcd_data.attach_debounce) { + _hcd_data.attach_debounce = false; // allow new attach events again + } + dwc2_regs_t* dwc2 = DWC2_REG(rhport); return dwc2->hprt & HPRT_CONN_STATUS; } @@ -1265,9 +1271,10 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { hprt |= HPRT_CONN_DETECT; if (hprt_bm.conn_status) { - hcd_event_device_attach(rhport, in_isr); - } else { - hcd_event_device_remove(rhport, in_isr); + if (!_hcd_data.attach_debounce) { + _hcd_data.attach_debounce = true; // block new attach events until the debounce delay is over + hcd_event_device_attach(rhport, in_isr); + } } } @@ -1330,6 +1337,19 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_channel_irq(rhport, in_isr); } + if (gintsts & GINTSTS_DISCINT) { + // Device disconnected + dwc2->gintsts = GINTSTS_DISCINT; + + // ignore device removal if attach debounce is active + // it will evaluate the port status after the debounce delay + if (!_hcd_data.attach_debounce) { + if (!(dwc2->hprt & HPRT_CONN_STATUS)) { + hcd_event_device_remove(rhport, in_isr); + } + } + } + #if CFG_TUH_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling if (gintsts & GINTSTS_RXFLVL) { -- cgit v1.3.1 From 925010fd841c5442579c503a3b1aa211cc25e8b2 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 11 Apr 2025 17:02:42 +0200 Subject: host/dwc2: resume OUT transfer when PING ACKed Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7cbef05b7..22f3bc70a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -590,7 +590,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | HCINT_ACK; } else { hcintmsk |= HCINT_NYET; - if (edpt->hcsplt_bm.split_en) { + if (edpt->hcsplt_bm.split_en || hctsiz & HCTSIZ_DOPING) { hcintmsk |= HCINT_ACK; } } @@ -973,10 +973,17 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; - if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { - // start split is ACK --> do complete split - channel->hcsplt_bm.split_compl = 1; - channel->hcchar |= HCCHAR_CHENA; + if (channel->hcsplt_bm.split_en) { + if(!channel->hcsplt_bm.split_compl) { + // start split is ACK --> do complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } + } else { + // Device is ready, resume transfer + edpt->do_ping = 0; + xfer->err_count = 0; + TU_ASSERT(channel_xfer_start(dwc2, ch_id)); } } -- cgit v1.3.1 From 937b07cdc0bb9341db35b4d8444827b03d06e84a Mon Sep 17 00:00:00 2001 From: Patrick Plenefisch Date: Fri, 11 Apr 2025 18:19:39 -0400 Subject: Fix version string to actually be the version --- src/tusb_option.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/tusb_option.h b/src/tusb_option.h index 29fdcb0d6..98f1a91b5 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -35,7 +35,7 @@ #define TUSB_VERSION_REVISION 0 #define TUSB_VERSION_NUMBER (TUSB_VERSION_MAJOR * 10000 + TUSB_VERSION_MINOR * 100 + TUSB_VERSION_REVISION) -#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION) +#define TUSB_VERSION_STRING TU_XSTRING(TUSB_VERSION_MAJOR) "." TU_XSTRING(TUSB_VERSION_MINOR) "." TU_XSTRING(TUSB_VERSION_REVISION) //--------------------------------------------------------------------+ // Supported MCUs -- cgit v1.3.1 From aecfd3433c6c235d632636f2936c7df180e9d12a Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 12 Apr 2025 13:36:10 +0200 Subject: Fix handle_hprt_irq Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f3dc23b9c..3acdf580d 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1290,10 +1290,10 @@ static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { */ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; - const dwc2_hprt_t hprt_bm = {.value = hprt}; + const dwc2_hprt_t hprt_bm = {.value = dwc2->hprt}; + uint32_t hprt = hprt_bm.value & ~HPRT_W1_MASK; - if (dwc2->hprt & HPRT_CONN_DETECT) { + if (hprt_bm.conn_detected) { // Port Connect Detect hprt |= HPRT_CONN_DETECT; @@ -1304,7 +1304,7 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { } } - if (dwc2->hprt & HPRT_ENABLE_CHANGE) { + if (hprt_bm.enable_change) { // Port enable change hprt |= HPRT_ENABLE_CHANGE; -- cgit v1.3.1 From af0c47e06ec079ffa80ea55ff5de58c08ac1e750 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 12 Apr 2025 15:21:19 +0200 Subject: Fix typo Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 3acdf580d..8f1103415 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -543,7 +543,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - bool const is_period = channel_is_periodic(hcchar_bm->ep_type); + bool const is_period = channel_is_periodic(edpt->hcchar); // clear previous state xfer->fifo_bytes = 0; -- cgit v1.3.1 From d039d54a89d15b9d11f8f22f94279bedc8b28c09 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 14 Apr 2025 16:31:17 +0700 Subject: channge DWC2_CHANNEL_COUNT/DWC2_EP_COUNT to inline function --- hw/bsp/broadcom_32bit/family.cmake | 2 +- hw/bsp/broadcom_32bit/family.mk | 2 +- hw/bsp/broadcom_64bit/family.cmake | 2 +- hw/bsp/broadcom_64bit/family.mk | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 20 +- src/portable/synopsys/dwc2/dwc2_common.c | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 312 +++++++++++++++---------------- src/portable/synopsys/dwc2/hcd_dwc2.c | 15 +- 8 files changed, 182 insertions(+), 175 deletions(-) (limited to 'src') diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index f1e8d12ff..5e57d8b1e 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -42,7 +42,7 @@ function(add_board_target BOARD_TARGET) -ffreestanding -mgeneral-regs-only -fno-exceptions - -std=gnu17 + -std=c17 ) target_include_directories(${BOARD_TARGET} PUBLIC ${SDK_DIR} diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk index 6acdf1197..a282e9961 100644 --- a/hw/bsp/broadcom_32bit/family.mk +++ b/hw/bsp/broadcom_32bit/family.mk @@ -10,7 +10,7 @@ CFLAGS += \ -nostartfiles \ -mgeneral-regs-only \ -fno-exceptions \ - -std=gnu17 + -std=c17 CROSS_COMPILE = arm-none-eabi- diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index 16f8e1eae..1a088c2c0 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -43,7 +43,7 @@ function(add_board_target BOARD_TARGET) -ffreestanding -mgeneral-regs-only -fno-exceptions - -std=gnu17 + -std=c17 ) target_compile_definitions(${BOARD_TARGET} PUBLIC BCM_VERSION=${BCM_VERSION} diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk index 92b5f69a3..37d381f9f 100644 --- a/hw/bsp/broadcom_64bit/family.mk +++ b/hw/bsp/broadcom_64bit/family.mk @@ -9,7 +9,7 @@ CFLAGS += \ -nostartfiles \ --specs=nosys.specs \ -mgeneral-regs-only \ - -std=gnu17 + -std=c17 CROSS_COMPILE = aarch64-none-elf- diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 83ebc18cb..52d675611 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -41,12 +41,6 @@ #include "device/dcd.h" #include "dwc2_common.h" -#if TU_CHECK_MCU(OPT_MCU_GD32VF103) - #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX -#else - #define DWC2_EP_COUNT(_dwc2) ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2}; ghwcfg2.num_dev_ep + 1;}) -#endif - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -79,6 +73,16 @@ CFG_TUD_MEM_SECTION static struct { TUD_EPBUF_DEF(setup_packet, 8); } _dcd_usbbuf; +TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) { + #if TU_CHECK_MCU(OPT_MCU_GD32VF103) + return DWC2_EP_MAX; + #else + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return ghwcfg2.num_dev_ep + 1; + #endif +} + + //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- @@ -629,7 +633,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // 7.4.1 Initialization on USB Reset static void handle_bus_reset(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); - const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t ep_count = dwc2_ep_count(dwc2); tu_memclr(xfer_status, sizeof(xfer_status)); @@ -926,7 +930,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin static void handle_ep_irq(uint8_t rhport, uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_device_enabled(dwc2); - const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t ep_count = dwc2_ep_count(dwc2); const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos; dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0]; diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 989a833ff..f6ed8fc98 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -173,7 +173,6 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { (void)dwc2; - const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; #if CFG_TUD_ENABLED if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { return false; @@ -185,6 +184,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { } #endif + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 5ecf9d487..34e046346 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -299,17 +299,17 @@ TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t core_soft_rst : 1; // 0 Core Soft Reset - uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset - uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host) - uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush - uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush - uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush - uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number - uint32_t rsv11_28 :18; // 11..28 Reserved - uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a - uint32_t dma_req : 1; // 30 DMA Request - uint32_t ahb_idle : 1; // 31 AHB Idle + uint32_t core_soft_rst : 1; // 0 Core Soft Reset + uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset + uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host) + uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush + uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush + uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush + uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number + uint32_t rsv11_28 :18; // 11..28 Reserved + uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a + uint32_t dma_req : 1; // 30 DMA Request + uint32_t ahb_idle : 1; // 31 AHB Idle }; } dwc2_grstctl_t; TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); @@ -317,12 +317,12 @@ TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number - uint32_t byte_count :11; // 4..14 Byte Count - uint32_t dpid : 2; // 15..16 Data PID - uint32_t packet_status : 4; // 17..20 Packet Status - uint32_t frame_number : 4; // 21..24 Frame Number - uint32_t rsv25_31 : 7; // 25..31 Reserved + uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number + uint32_t byte_count :11; // 4..14 Byte Count + uint32_t dpid : 2; // 15..16 Data PID + uint32_t packet_status : 4; // 17..20 Packet Status + uint32_t frame_number : 4; // 21..24 Frame Number + uint32_t rsv25_31 : 7; // 25..31 Reserved }; } dwc2_grxstsp_t; TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size"); @@ -371,28 +371,28 @@ TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints - uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled - uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz - uint32_t hibernation : 1; // 6 Hibernation feature is enabled - uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled - uint32_t reserved8 : 1; // 8 Reserved - uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1 - uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported - uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported - uint32_t acg_support : 1; // 12 Active clock gating is supported - uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support - uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable - uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0 - uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled - uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled - uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled - uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled - uint32_t session_end_filter : 1; // 24 Session End Filter Enabled - uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint - uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0 - uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled - uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA + uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints + uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled + uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz + uint32_t hibernation : 1; // 6 Hibernation feature is enabled + uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled + uint32_t reserved8 : 1; // 8 Reserved + uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1 + uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported + uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported + uint32_t acg_support : 1; // 12 Active clock gating is supported + uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support + uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable + uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0 + uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled + uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled + uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled + uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled + uint32_t session_end_filter : 1; // 24 Session End Filter Enabled + uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint + uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0 + uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled + uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA }; } dwc2_ghwcfg4_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); @@ -402,7 +402,7 @@ typedef union { struct TU_ATTR_PACKED { uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO uint32_t req_queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU - // 24..31 is top entry in the request queue that is currently being processed by the MAC + // 24..31 is top entry in the request queue that is currently being processed by the MAC uint32_t qtop_terminate : 1; // 24 Last entry for selected channel uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command uint32_t qtop_ch_num : 4; // 27..30 Channel number @@ -413,7 +413,7 @@ TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t fifo_available :16; // 0..15 Number of words available in the Tx FIFO uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue uint32_t qtop_terminate : 1; // 23 Last entry for selected channel uint32_t qtop_last_period : 1; // 24 Last entry for selected channel is a periodic entry @@ -467,12 +467,12 @@ TU_VERIFY_STATIC(sizeof(dwc2_channel_char_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t hub_port : 7; // 0..6 Hub port number - uint32_t hub_addr : 7; // 7..13 Hub address - uint32_t xact_pos : 2; // 14..15 Transaction position - uint32_t split_compl : 1; // 16 Split completion - uint32_t rsv17_30 : 14; // 17..30 Reserved - uint32_t split_en : 1; // 31 Split enable + uint32_t hub_port : 7; // 0..6 Hub port number + uint32_t hub_addr : 7; // 7..13 Hub address + uint32_t xact_pos : 2; // 14..15 Transaction position + uint32_t split_compl : 1; // 16 Split completion + uint32_t rsv17_30 : 14; // 17..30 Reserved + uint32_t split_en : 1; // 31 Split enable }; } dwc2_channel_split_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size"); @@ -480,10 +480,10 @@ TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t xfer_size : 19; // 0..18 Transfer size in bytes - uint32_t packet_count : 10; // 19..28 Number of packets - uint32_t pid : 2; // 29..30 Packet ID - uint32_t do_ping : 1; // 31 Do PING + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t pid : 2; // 29..30 Packet ID + uint32_t do_ping : 1; // 31 Do PING }; } dwc2_channel_tsize_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size"); @@ -499,14 +499,14 @@ TU_VERIFY_STATIC(sizeof(dwc2_hfnum_t) == 4, "incorrect size"); // Host Channel typedef struct { - volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics - volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control - volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt - volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask - volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size - volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address - uint32_t reserved518; // 518 + 20*ch - volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address + volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics + volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control + volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt + volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask + volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size + volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address + uint32_t reserved518; // 518 + 20*ch + volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address } dwc2_channel_t; //-------------------------------------------------------------------- @@ -565,7 +565,7 @@ typedef union { uint32_t enum_speed : 2; // 1..2 Enumerated speed uint32_t erratic_err : 1; // 3 Erratic error uint32_t rsv4_7 : 4; // 4..7 Reserved - uint32_t frame_number : 14; // 8..21 Frame/MicroFrame number + uint32_t frame_number :14; // 8..21 Frame/MicroFrame number uint32_t line_status : 2; // 22..23 Line status uint32_t rsv24_31 : 8; // 24..31 Reserved }; @@ -620,23 +620,23 @@ TU_VERIFY_STATIC(sizeof(dwc2_depctl_t) == 4, "incorrect size"); typedef union { uint32_t value; struct TU_ATTR_PACKED { - uint32_t xfer_complete : 1; // 0 Transfer complete - uint32_t disabled : 1; // 1 Endpoint disabled - uint32_t ahb_err : 1; // 2 AHB error - uint32_t setup_phase_done : 1; // 3 Setup phase done - uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled - uint32_t status_phase_rx : 1; // 5 Status phase received - uint32_t setup_b2b : 1; // 6 Setup packet back-to-back - uint32_t rsv7 : 1; // 7 Reserved - uint32_t out_packet_err : 1; // 8 OUT packet error - uint32_t bna : 1; // 9 Buffer not available - uint32_t rsv10 : 1; // 10 Reserved - uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status - uint32_t babble_err : 1; // 12 Babble error - uint32_t nak : 1; // 13 NAK - uint32_t nyet : 1; // 14 NYET - uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) - uint32_t rsv16_31 :16; // 16..31 Reserved + uint32_t xfer_complete : 1; // 0 Transfer complete + uint32_t disabled : 1; // 1 Endpoint disabled + uint32_t ahb_err : 1; // 2 AHB error + uint32_t setup_phase_done : 1; // 3 Setup phase done + uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled + uint32_t status_phase_rx : 1; // 5 Status phase received + uint32_t setup_b2b : 1; // 6 Setup packet back-to-back + uint32_t rsv7 : 1; // 7 Reserved + uint32_t out_packet_err : 1; // 8 OUT packet error + uint32_t bna : 1; // 9 Buffer not available + uint32_t rsv10 : 1; // 10 Reserved + uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status + uint32_t babble_err : 1; // 12 Babble error + uint32_t nak : 1; // 13 NAK + uint32_t nyet : 1; // 14 NYET + uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) + uint32_t rsv16_31 :16; // 16..31 Reserved }; } dwc2_doepint_t; TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size"); @@ -684,17 +684,17 @@ TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); // CSR Register Map //-------------------------------------------------------------------- typedef struct { - //------------- Core Global -------------// - volatile uint32_t gotgctl; // 000 OTG Control and Status - volatile uint32_t gotgint; // 004 OTG Interrupt - volatile uint32_t gahbcfg; // 008 AHB Configuration - volatile uint32_t gusbcfg; // 00c USB Configuration - volatile uint32_t grstctl; // 010 Reset - volatile uint32_t gintsts; // 014 Interrupt - volatile uint32_t gintmsk; // 018 Interrupt Mask - volatile uint32_t grxstsr; // 01c Receive Status Debug Read - volatile uint32_t grxstsp; // 020 Receive Status Read/Pop - volatile uint32_t grxfsiz; // 024 Receive FIFO Size + //------------- Core Global ------------- + volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile uint32_t gotgint; // 004 OTG Interrupt + volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile uint32_t gusbcfg; // 00c USB Configuration + volatile uint32_t grstctl; // 010 Reset + volatile uint32_t gintsts; // 014 Interrupt + volatile uint32_t gintmsk; // 018 Interrupt Mask + volatile uint32_t grxstsr; // 01c Receive Status Debug Read + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile uint32_t grxfsiz; // 024 Receive FIFO Size union { volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size @@ -703,89 +703,89 @@ typedef struct { volatile uint32_t hnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status volatile uint32_t gnptxsts; }; - volatile uint32_t gi2cctl; // 030 I2C Address - volatile uint32_t gpvndctl; // 034 PHY Vendor Control + volatile uint32_t gi2cctl; // 030 I2C Address + volatile uint32_t gpvndctl; // 034 PHY Vendor Control union { volatile uint32_t ggpio; // 038 General Purpose IO volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration }; - volatile uint32_t guid; // 03C User (Application programmable) ID - volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version - volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) - volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 - volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 + volatile uint32_t guid; // 03C User (Application programmable) ID + volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 union { volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 volatile dwc2_ghwcfg4_t ghwcfg4_bm; }; - volatile uint32_t glpmcfg; // 054 Core LPM Configuration - volatile uint32_t gpwrdn; // 058 Power Down - volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration - volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status - uint32_t reserved64[39]; // 064..0FF - volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size - volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size - uint32_t reserved140[176]; // 140..3FF - - //------------ Host -------------// - volatile uint32_t hcfg; // 400 Host Configuration - volatile uint32_t hfir; // 404 Host Frame Interval - volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining - uint32_t reserved40c; // 40C - volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status - volatile uint32_t haint; // 414 Host All Channels Interrupt - volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask - volatile uint32_t hflbaddr; // 41C Host Frame List Base Address - uint32_t reserved420[8]; // 420..43F - volatile uint32_t hprt; // 440 Host Port Control and Status - uint32_t reserved444[47]; // 444..4FF - - //------------- Host Channel -------------// - dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 - uint32_t reserved700[64]; // 700..7FF - - //------------- Device -----------// - volatile uint32_t dcfg; // 800 Device Configuration - volatile uint32_t dctl; // 804 Device Control - volatile uint32_t dsts; // 808 Device Status (RO) - uint32_t reserved80c; // 80C - volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask - volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask - volatile uint32_t daint; // 818 Device All Endpoints Interrupt - volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask - volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 - volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 - volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time - volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time - volatile uint32_t dthrctl; // 830 Device threshold Control - volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask - - // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line - // require OTG_MULTI_PROC_INTRPT=1 - volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask - volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask - volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask - uint32_t reserved8c0[16]; // 8C0..8FF - - //------------- Device Endpoint -------------// + volatile uint32_t glpmcfg; // 054 Core LPM Configuration + volatile uint32_t gpwrdn; // 058 Power Down + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status + uint32_t reserved64[39]; // 064..0FF + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size + uint32_t reserved140[176]; // 140..3FF + + //------------ Host ------------- + volatile uint32_t hcfg; // 400 Host Configuration + volatile uint32_t hfir; // 404 Host Frame Interval + volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining + uint32_t reserved40c; // 40C + volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status + volatile uint32_t haint; // 414 Host All Channels Interrupt + volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask + volatile uint32_t hflbaddr; // 41C Host Frame List Base Address + uint32_t reserved420[8]; // 420..43F + volatile uint32_t hprt; // 440 Host Port Control and Status + uint32_t reserved444[47]; // 444..4FF + + //------------- Host Channel -------- + dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 + uint32_t reserved700[64]; // 700..7FF + + //------------- Device ----------- + volatile uint32_t dcfg; // 800 Device Configuration + volatile uint32_t dctl; // 804 Device Control + volatile uint32_t dsts; // 808 Device Status (RO) + uint32_t reserved80c; // 80C + volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile uint32_t daint; // 818 Device All Endpoints Interrupt + volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time + volatile uint32_t dthrctl; // 830 Device threshold Control + volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + + // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line require + // OTG_MULTI_PROC_INTRPT=1 + volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask + volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask + volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask + uint32_t reserved8c0[16]; // 8C0..8FF + + //------------- Device Endpoint ----- union { - dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT + dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT struct { - dwc2_dep_t epin[16]; // 900..AFF IN Endpoints - dwc2_dep_t epout[16]; // B00..CFF OUT Endpoints + dwc2_dep_t epin[16]; // 900..AFF IN Endpoints + dwc2_dep_t epout[16]; // B00..CFF OUT Endpoints }; }; - uint32_t reservedd00[64]; // D00..DFF + uint32_t reservedd00[64]; // D00..DFF - //------------- Power Clock -------------// - volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control - volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 - uint32_t reservede08[126]; // E08..FFF + //------------- Power Clock --------- + volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control + volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 + uint32_t reservede08[126]; // E08..FFF - //------------- FIFOs -------------// + //------------- FIFOs ------------- // Word-accessed only using first pointer since it auto shift - volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO + volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO } dwc2_regs_t; TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8f1103415..8d565d174 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -44,8 +44,6 @@ #endif #define DWC2_CHANNEL_COUNT_MAX 16 // absolute max channel count -#define DWC2_CHANNEL_COUNT(_dwc2) ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2}; tu_min8(ghwcfg2.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX);}) - TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index"); enum { @@ -116,6 +114,11 @@ hcd_data_t _hcd_data; //-------------------------------------------------------------------- // //-------------------------------------------------------------------- +TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_channel_count(const dwc2_regs_t* dwc2) { + const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; + return tu_min8(ghwcfg2.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX); +} + TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc2) { tusb_speed_t speed; const dwc2_hprt_t hprt = {.value = dwc2->hprt}; @@ -157,7 +160,7 @@ bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { // Allocate a channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { - const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + const uint8_t max_channel = dwc2_channel_count(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; if (!xfer->allocated) { @@ -208,7 +211,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t // Find currently enabled channel. Note: EP0 is bidirectional TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { - const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + const uint8_t max_channel = dwc2_channel_count(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (_hcd_data.xfer[ch_id].allocated) { const dwc2_channel_char_t hcchar = {.value = dwc2->channel[ch_id].hcchar}; @@ -813,7 +816,7 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) const dwc2_hptxsts_t txsts = {.value = (is_periodic ? dwc2->hptxsts : dwc2->hnptxsts)}; - const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + const uint8_t max_channel = dwc2_channel_count(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar = {.value = channel->hcchar}; @@ -1168,7 +1171,7 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc static void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_host_enabled(dwc2); - const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + const uint8_t max_channel = dwc2_channel_count(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (tu_bit_test(dwc2->haint, ch_id)) { -- cgit v1.3.1 From 384e191fdc9346eb8718f1f3e50f4697f161cc88 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Thu, 10 Apr 2025 10:29:45 +0200 Subject: dwc2/host: immediately retry IN token for bInterval=1 Signed-off-by: Maxime Vincent --- src/portable/synopsys/dwc2/hcd_dwc2.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 33c0edba1..6e2737afd 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -736,6 +736,14 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } } + // immediately retry if bInterval is 1 - otherwise we'd waste a microframe before retrying + if ((hcint & HCINT_HALTED) && (edpt->uframe_interval == 1)) { + edpt->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); + channel_send_in_token(dwc2, channel); + return; + } + // for periodic, de-allocate channel, enable SOF set frame counter for later transfer const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; edpt->next_pid = hctsiz.pid; // save PID -- cgit v1.3.1 From 62d06e7b19d82dbbc3d1089b249913c13eb7fc2a Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Mon, 14 Apr 2025 09:24:54 +0200 Subject: dwc2/host: fix all retry intervals Signed-off-by: Maxime Vincent --- src/portable/synopsys/dwc2/hcd_dwc2.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 6e2737afd..d2070e57c 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -736,23 +736,22 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } } - // immediately retry if bInterval is 1 - otherwise we'd waste a microframe before retrying - if ((hcint & HCINT_HALTED) && (edpt->uframe_interval == 1)) { - edpt->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame - channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); - channel_send_in_token(dwc2, channel); - return; - } - - // for periodic, de-allocate channel, enable SOF set frame counter for later transfer - const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; - edpt->next_pid = hctsiz.pid; // save PID - edpt->uframe_countdown = edpt->uframe_interval; - dwc2->gintmsk |= GINTSTS_SOF; - if (hcint & HCINT_HALTED) { - // already halted, de-allocate channel (called from DMA isr) - channel_dealloc(dwc2, ch_id); + const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8); + if (edpt->uframe_interval == ucount) { + // immediately retry if bInterval is 1 + edpt->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); + channel_send_in_token(dwc2, channel); + } else { + // otherwise, de-allocate channel, enable SOF set frame counter for later transfer + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; + edpt->next_pid = hctsiz.pid; // save PID + edpt->uframe_countdown = edpt->uframe_interval - ucount; + dwc2->gintmsk |= GINTSTS_SOF; + // already halted, de-allocate channel (called from DMA isr) + channel_dealloc(dwc2, ch_id); + } } else { // disable channel first if not halted (called slave isr) xfer->halted_sof_schedule = 1; -- cgit v1.3.1 From 0d2c08efd7145b160ab0ed373b2cf956699cfb74 Mon Sep 17 00:00:00 2001 From: Joel Michael Date: Wed, 16 Apr 2025 20:26:35 +1000 Subject: note potential issues using ep_desc in hcd_edpt_open() --- src/portable/template/hcd_template.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index b073d6057..694fa8550 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -116,6 +116,10 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; (void) dev_addr; + + // NOTE: ep_desc is allocated on the stack when called from usbh_edpt_control_open() + // If you need to persist any ep_desc values across HCD calls (eg ep_desc->wMaxPacketSize), + // then you need to copy the data into another variable inside this function. (void) ep_desc; return false; -- cgit v1.3.1 From b1eedf4d1d95d6e8c7de425080a107a33cbf0e5d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 17 Apr 2025 14:34:55 +0700 Subject: fix iar make build with wb and u5 --- examples/build_system/make/cpu/cortex-m4.mk | 4 ++-- examples/host/msc_file_explorer/Makefile | 2 +- hw/bsp/broadcom_32bit/family.mk | 2 +- hw/bsp/broadcom_64bit/family.mk | 2 +- hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk | 2 +- hw/bsp/lpc15/family.mk | 2 +- hw/bsp/lpc17/family.mk | 2 +- hw/bsp/lpc18/family.mk | 2 +- hw/bsp/lpc40/family.mk | 2 +- hw/bsp/lpc43/family.mk | 6 +++--- hw/bsp/stm32f4/family.mk | 1 - hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk | 4 +--- hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk | 4 +--- hw/bsp/stm32u5/boards/stm32u575eval/board.mk | 4 +--- hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk | 4 +--- hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk | 4 +--- hw/bsp/stm32u5/family.mk | 7 +++++++ hw/bsp/stm32wb/family.mk | 21 +++++++++++++-------- src/class/msc/msc_device.c | 5 +++-- 19 files changed, 41 insertions(+), 39 deletions(-) (limited to 'src') diff --git a/examples/build_system/make/cpu/cortex-m4.mk b/examples/build_system/make/cpu/cortex-m4.mk index 4e16819d1..57d6e126d 100644 --- a/examples/build_system/make/cpu/cortex-m4.mk +++ b/examples/build_system/make/cpu/cortex-m4.mk @@ -12,8 +12,8 @@ else ifeq ($(TOOLCHAIN),clang) -mfpu=fpv4-sp-d16 \ else ifeq ($(TOOLCHAIN),iar) - CFLAGS += --cpu cortex-m4 --fpu VFPv4 - ASFLAGS += --cpu cortex-m4 --fpu VFPv4 + CFLAGS += --cpu cortex-m4 --fpu VFPv4-SP + ASFLAGS += --cpu cortex-m4 --fpu VFPv4-SP else $(error "TOOLCHAIN is not supported") diff --git a/examples/host/msc_file_explorer/Makefile b/examples/host/msc_file_explorer/Makefile index c7d6a7cae..f0872376f 100644 --- a/examples/host/msc_file_explorer/Makefile +++ b/examples/host/msc_file_explorer/Makefile @@ -22,6 +22,6 @@ SRC_C += \ $(FATFS_PATH)/ffunicode.c \ # suppress warning caused by fatfs -CFLAGS += -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=cast-qual include ../../build_system/make/rules.mk diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk index a282e9961..9d4a3b76c 100644 --- a/hw/bsp/broadcom_32bit/family.mk +++ b/hw/bsp/broadcom_32bit/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ CROSS_COMPILE = arm-none-eabi- # mcu driver cause following warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk index 37d381f9f..1ce80e22b 100644 --- a/hw/bsp/broadcom_64bit/family.mk +++ b/hw/bsp/broadcom_64bit/family.mk @@ -14,7 +14,7 @@ CFLAGS += \ CROSS_COMPILE = aarch64-none-elf- # mcu driver cause following warnings -CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls +CFLAGS_GCC += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk index c4dc65b63..fb3eb2a03 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.mk @@ -3,7 +3,7 @@ MCU = K32L2A41A CFLAGS += -DCPU_K32L2A41VLH1A # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=redundant-decls -Wno-error=cast-qual # All source paths should be relative to the top level. LD_FILE = $(MCU_DIR)/gcc/K32L2A41xxxxA_flash.ld diff --git a/hw/bsp/lpc15/family.mk b/hw/bsp/lpc15/family.mk index b83e008e8..3b63580c0 100644 --- a/hw/bsp/lpc15/family.mk +++ b/hw/bsp/lpc15/family.mk @@ -15,7 +15,7 @@ CFLAGS += \ LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=unused-variable -Wno-error=cast-qual MCU_DIR = hw/mcu/nxp/lpcopen/lpc15xx/lpc_chip_15xx diff --git a/hw/bsp/lpc17/family.mk b/hw/bsp/lpc17/family.mk index d719a47b7..551eb9e62 100644 --- a/hw/bsp/lpc17/family.mk +++ b/hw/bsp/lpc17/family.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DRTC_EV_SUPPORT=0 # lpc_types.h cause following errors -CFLAGS += -Wno-error=strict-prototypes -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=cast-qual # caused by freeRTOS port !! CFLAGS += -Wno-error=maybe-uninitialized diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk index f120f63b2..87b831255 100644 --- a/hw/bsp/lpc18/family.mk +++ b/hw/bsp/lpc18/family.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC18XX # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=unused-parameter -Wno-error=cast-qual LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc40/family.mk b/hw/bsp/lpc40/family.mk index ef9fe57b2..06155c760 100644 --- a/hw/bsp/lpc40/family.mk +++ b/hw/bsp/lpc40/family.mk @@ -13,7 +13,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC40XX # mcu driver cause following warnings -CFLAGS += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual +CFLAGS_GCC += -Wno-error=strict-prototypes -Wno-error=unused-parameter -Wno-error=cast-qual LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk index e1406aae7..4a2ba6ec3 100644 --- a/hw/bsp/lpc43/family.mk +++ b/hw/bsp/lpc43/family.mk @@ -5,14 +5,14 @@ include ${TOP}/${BOARD_PATH}/board.mk CPU_CORE ?= cortex-m4 CFLAGS += \ - -flto \ - -nostdlib \ -DCORE_M4 \ -D__USE_LPCOPEN \ -DCFG_TUSB_MCU=OPT_MCU_LPC43XX # mcu driver cause following warnings -CFLAGS += \ +CFLAGS_GCC += \ + -flto \ + -nostdlib \ -Wno-error=unused-parameter \ -Wno-error=cast-qual \ -Wno-error=incompatible-pointer-types \ diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index 51ff43a60..c3c41dc3f 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -1,6 +1,5 @@ UF2_FAMILY_ID = 0x57755a57 ST_FAMILY = f4 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk index ae63afef3..0a2c47030 100644 --- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u585xx CFLAGS += \ -DSTM32U585xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u585xx # For flash-jlink target JLINK_DEVICE = stm32u585zi diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk index 072c595fb..0aba57ce4 100644 --- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u545xx CFLAGS += \ -DSTM32U545xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U545xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u545xx.s - -MCU_VARIANT = stm32u545xx # For flash-jlink target JLINK_DEVICE = stm32u545re diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk index fee56f2ba..4bc9fea10 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u575xx CFLAGS += \ -DSTM32U575xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u575xx # For flash-jlink target JLINK_DEVICE = stm32u575ai diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk index c83ec3999..d09dc5c46 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.mk @@ -1,11 +1,9 @@ +MCU_VARIANT = stm32u575xx CFLAGS += \ -DSTM32U575xx \ # All source paths should be relative to the top level. LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s - -MCU_VARIANT = stm32u575xx # For flash-jlink target JLINK_DEVICE = stm32u575zi diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk index 4bebe3330..c9fdbac1a 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.mk @@ -1,3 +1,4 @@ +MCU_VARIANT = stm32u5a5xx CFLAGS += \ -DSTM32U5A5xx \ -DHSE_VALUE=16000000UL \ @@ -5,8 +6,5 @@ CFLAGS += \ # All source paths should be relative to the top level. LD_FILE = ${BOARD_PATH}/STM32U5A5ZJTXQ_FLASH.ld -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u5a5xx.s - -MCU_VARIANT = stm32u5a5xx # For flash-jlink target JLINK_DEVICE = stm32u575zi diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 05fe4608a..7fc728dcf 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -57,5 +57,12 @@ INC += \ $(TOP)/$(ST_HAL_DRIVER)/Inc \ $(TOP)/$(BOARD_PATH) +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf + # flash target using on-board stlink flash: flash-stlink diff --git a/hw/bsp/stm32wb/family.mk b/hw/bsp/stm32wb/family.mk index de8372eea..a80ff6f5b 100644 --- a/hw/bsp/stm32wb/family.mk +++ b/hw/bsp/stm32wb/family.mk @@ -9,14 +9,12 @@ include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 CFLAGS += \ - -flto \ - -nostdlib -nostartfiles \ -DCFG_TUSB_MCU=OPT_MCU_STM32WB -# suppress warning caused by vendor mcu driver -CFLAGS += -Wno-error=cast-align -Wno-unused-parameter - -LD_FILE ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld +CFLAGS_GCC += \ + -flto \ + -nostdlib -nostartfiles \ + -Wno-error=cast-align -Wno-unused-parameter LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs @@ -25,19 +23,26 @@ SRC_C += \ $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c -SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_${MCU_VARIANT}_cm4.s - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT)_cm4.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT)_cm4.s + +# Linker +LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash_cm4.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm4.icf + # flash target using on-board stlink flash: flash-stlink diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 6670045aa..87c77c9a7 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -344,7 +344,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t msc_csw_t * p_csw = &p_msc->csw; switch (p_msc->stage) { - case MSC_STAGE_CMD: + case MSC_STAGE_CMD: { //------------- new CBW received -------------// // Complete IN while waiting for CMD is usually Status of previous SCSI op, ignore it if (ep_addr != p_msc->ep_out) { @@ -441,7 +441,8 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t } } } - break; + break; + } case MSC_STAGE_DATA: TU_LOG_DRV(" SCSI Data [Lun%u]\r\n", p_cbw->lun); -- cgit v1.3.1 From e8a84f90764f0f2603822f068a9961ceeade873d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 14 Apr 2025 16:09:32 +0700 Subject: enum For string descriptor (langid, manufacturer product, serila): always get the first 2 bytes to determine the length first. otherwise, some device may have buffer overflow. --- .../espressif/boards/espressif_s3_devkitc/board.h | 2 +- hw/bsp/espressif/family.cmake | 2 +- src/common/tusb_debug.h | 6 +- src/host/usbh.c | 122 ++++++++++++--------- 4 files changed, 75 insertions(+), 57 deletions(-) (limited to 'src') diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h index 6d7a94668..d2483c84f 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h @@ -36,7 +36,7 @@ extern "C" { #endif -#define NEOPIXEL_PIN 48 +#define NEOPIXEL_PIN 38 #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index daa12cdb4..b544689d9 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -34,6 +34,6 @@ endif () set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") # set SDKCONFIG for each IDF Target -set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET}) +set(SDKCONFIG ${CMAKE_BINARY_DIR}/sdkconfig) include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/src/common/tusb_debug.h b/src/common/tusb_debug.h index 2e9f1d9cd..1d0c6f1ad 100644 --- a/src/common/tusb_debug.h +++ b/src/common/tusb_debug.h @@ -108,15 +108,13 @@ typedef struct { } tu_lookup_table_t; static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key) { - tu_static char not_found[11]; - for(uint16_t i=0; icount; i++) { - if (p_table->items[i].key == key) return p_table->items[i].data; + if (p_table->items[i].key == key) { return p_table->items[i].data; } } // not found return the key value in hex + static char not_found[11]; snprintf(not_found, sizeof(not_found), "0x%08lX", (unsigned long) key); - return not_found; } diff --git a/src/host/usbh.c b/src/host/usbh.c index e60db53da..157a7ab86 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1372,9 +1372,13 @@ enum { ENUM_HUB_CLEAR_RESET_2, ENUM_SET_ADDR, ENUM_GET_DEVICE_DESC, + ENUM_GET_STRING_LANGUAGE_ID_LEN, ENUM_GET_STRING_LANGUAGE_ID, + ENUM_GET_STRING_MANUFACTURER_LEN, ENUM_GET_STRING_MANUFACTURER, + ENUM_GET_STRING_PRODUCT_LEN, ENUM_GET_STRING_PRODUCT, + ENUM_GET_STRING_SERIAL_LEN, ENUM_GET_STRING_SERIAL, ENUM_GET_9BYTE_CONFIG_DESC, ENUM_GET_FULL_CONFIG_DESC, @@ -1416,6 +1420,9 @@ static void process_enumeration(tuh_xfer_t* xfer) { uint8_t const daddr = xfer->daddr; uintptr_t const state = xfer->user_data; usbh_device_t* dev = get_device(daddr); + if (daddr > 0) { + TU_ASSERT(dev,); + } uint16_t langid = 0x0409; // default is English switch (state) { @@ -1474,30 +1481,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { break; } -#if 0 - case ENUM_RESET_2: - // TODO not used by now, but may be needed for some devices !? - // Reset device again before Set Address - TU_LOG_USBH("Port reset2 \r\n"); - if (_dev0.hub_addr == 0) { - // connected directly to roothub - hcd_port_reset( _dev0.rhport ); - tusb_time_delay_ms_api(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting - hcd_port_reset_end(_dev0.rhport); - // TODO: fall through to SET ADDRESS, refactor later - } -#if CFG_TUH_HUB - else { - // after RESET_DELAY the hub_port_reset() already complete - TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, - process_enumeration, ENUM_HUB_GET_STATUS_2), ); - break; - } -#endif - TU_ATTR_FALLTHROUGH; -#endif - case ENUM_SET_ADDR: enum_request_set_addr((tusb_desc_device_t*) _usbh_epbuf.ctrl); break; @@ -1520,14 +1503,15 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get full device descriptor TU_LOG_USBH("Get Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), - process_enumeration, ENUM_GET_STRING_LANGUAGE_ID),); + process_enumeration, ENUM_GET_STRING_LANGUAGE_ID_LEN),); break; } - case ENUM_GET_STRING_LANGUAGE_ID: { + // For string descriptor (langid, manufacturer, product, serila): always get the first 2 bytes + // to determine the length first. otherwise, some device may have buffer overflow. + case ENUM_GET_STRING_LANGUAGE_ID_LEN: { // save the received device descriptor - TU_ASSERT(dev,); - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; + tusb_desc_device_t const *desc_device = (tusb_desc_device_t const *) _usbh_epbuf.ctrl; dev->vid = desc_device->idVendor; dev->pid = desc_device->idProduct; dev->i_manufacturer = desc_device->iManufacturer; @@ -1535,50 +1519,88 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_serial = desc_device->iSerialNumber; dev->bNumConfigurations = desc_device->bNumConfigurations; - tuh_enum_descriptor_device_cb(daddr, desc_device); // callback + tuh_enum_descriptor_device_cb(daddr, desc_device);// callback - tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE, - process_enumeration, ENUM_GET_STRING_MANUFACTURER); + tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, 2, + process_enumeration, ENUM_GET_STRING_LANGUAGE_ID); break; } - case ENUM_GET_STRING_MANUFACTURER: { - TU_ASSERT(dev,); - const tusb_desc_string_t* desc_langid = (tusb_desc_string_t const*) _usbh_epbuf.ctrl; + case ENUM_GET_STRING_LANGUAGE_ID: { + const uint8_t str_len = xfer->buffer[0]; + tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, str_len, + process_enumeration, ENUM_GET_STRING_MANUFACTURER_LEN); + break; + } + + case ENUM_GET_STRING_MANUFACTURER_LEN: { + const tusb_desc_string_t* desc_langid = (const tusb_desc_string_t *) _usbh_epbuf.ctrl; if (desc_langid->bLength >= 4) { - langid = tu_le16toh(desc_langid->utf16le[0]); + langid = tu_le16toh(desc_langid->utf16le[0]); // previous request is langid } if (dev->i_manufacturer != 0) { - tuh_descriptor_get_string(daddr, dev->i_manufacturer, langid, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE, - process_enumeration, ENUM_GET_STRING_PRODUCT); + tuh_descriptor_get_string(daddr, dev->i_manufacturer, langid, _usbh_epbuf.ctrl, 2, + process_enumeration, ENUM_GET_STRING_MANUFACTURER); + break; + }else { + TU_ATTR_FALLTHROUGH; + } + } + + case ENUM_GET_STRING_MANUFACTURER: { + if (dev->i_manufacturer != 0) { + langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request + const uint8_t str_len = xfer->buffer[0]; + tuh_descriptor_get_string(daddr, dev->i_manufacturer, langid, _usbh_epbuf.ctrl, str_len, + process_enumeration, ENUM_GET_STRING_PRODUCT_LEN); break; } else { TU_ATTR_FALLTHROUGH; } } - case ENUM_GET_STRING_PRODUCT: { - TU_ASSERT(dev,); - if (state == ENUM_GET_STRING_PRODUCT) { - langid = tu_le16toh(xfer->setup->wIndex); // if not fall through, get langid from previous setup packet + case ENUM_GET_STRING_PRODUCT_LEN: + if (dev->i_product != 0) { + if (state == ENUM_GET_STRING_PRODUCT_LEN) { + langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through + } + tuh_descriptor_get_string(daddr, dev->i_product, langid, _usbh_epbuf.ctrl, 2, + process_enumeration, ENUM_GET_STRING_PRODUCT); + break; + } else { + TU_ATTR_FALLTHROUGH; } + + case ENUM_GET_STRING_PRODUCT: { if (dev->i_product != 0) { - tuh_descriptor_get_string(daddr, dev->i_product, 0x0409, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE, - process_enumeration, ENUM_GET_STRING_SERIAL); + langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request + const uint8_t str_len = xfer->buffer[0]; + tuh_descriptor_get_string(daddr, dev->i_product, langid, _usbh_epbuf.ctrl, str_len, + process_enumeration, ENUM_GET_STRING_SERIAL_LEN); break; } else { TU_ATTR_FALLTHROUGH; } } - case ENUM_GET_STRING_SERIAL: { - TU_ASSERT(dev,); - if (state == ENUM_GET_STRING_SERIAL) { - langid = tu_le16toh(xfer->setup->wIndex); // if not fall through, get langid from previous setup packet + case ENUM_GET_STRING_SERIAL_LEN: + if (dev->i_serial != 0) { + if (state == ENUM_GET_STRING_SERIAL_LEN) { + langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through + } + tuh_descriptor_get_string(daddr, dev->i_serial, langid, _usbh_epbuf.ctrl, 2, + process_enumeration, ENUM_GET_STRING_SERIAL); + break; + } else { + TU_ATTR_FALLTHROUGH; } + + case ENUM_GET_STRING_SERIAL: { if (dev->i_serial != 0) { - tuh_descriptor_get_string(daddr, dev->i_serial, langid, _usbh_epbuf.ctrl, CFG_TUH_ENUMERATION_BUFSIZE, - process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC); + langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request + const uint8_t str_len = xfer->buffer[0]; + tuh_descriptor_get_string(daddr, dev->i_serial, langid, _usbh_epbuf.ctrl, str_len, + process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC); break; } else { TU_ATTR_FALLTHROUGH; @@ -1627,8 +1649,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_CONFIG_DRIVER: { TU_LOG_USBH("Device configured\r\n"); - TU_ASSERT(dev,); - dev->configured = 1; // Parse configuration & set up drivers -- cgit v1.3.1 From 713410997326269b4072dce906933f8f44fd0efe Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 18 Apr 2025 11:12:14 +0200 Subject: Update hcd_edpt_open() note. Signed-off-by: HiFiPhile --- src/portable/template/hcd_template.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index 694fa8550..fd870c91e 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -118,8 +118,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const (void) dev_addr; // NOTE: ep_desc is allocated on the stack when called from usbh_edpt_control_open() - // If you need to persist any ep_desc values across HCD calls (eg ep_desc->wMaxPacketSize), - // then you need to copy the data into another variable inside this function. + // You need to copy the data into a local variable who maintains the state of the endpoint and transfer. + // Check _hcd_data in hcd_dwc2.c for example. (void) ep_desc; return false; -- cgit v1.3.1 From 1b888a3311f1c722978d3bcb8ee0f5d5d4debd55 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Apr 2025 16:17:35 +0700 Subject: clean up, remove halted_sof_schedule flags since channel_xfer_in_retry() is only called when channel is halted. --- src/portable/synopsys/dwc2/hcd_dwc2.c | 48 +++++++++++++++-------------------- 1 file changed, 20 insertions(+), 28 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index d2070e57c..a95cc5e10 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -95,7 +95,6 @@ typedef struct { uint8_t err_count : 3; uint8_t period_split_nyet_count : 3; uint8_t halted_nyet : 1; - uint8_t halted_sof_schedule : 1; }; uint8_t result; @@ -713,19 +712,21 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { //-------------------------------------------------------------------- // HCD Event Handler //-------------------------------------------------------------------- + +// retry an IN transfer, channel must be halted static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + dwc2_channel_char_t hcchar = {.value = channel->hcchar}; - if (channel_is_periodic(channel->hcchar)){ + if (channel_is_periodic(hcchar.value)){ const dwc2_channel_split_t hcsplt = {.value = channel->hcsplt}; // retry immediately for periodic split NYET if we haven't reach max retry if (hcsplt.split_en && hcsplt.split_compl && (hcint & HCINT_NYET || xfer->halted_nyet)) { xfer->period_split_nyet_count++; xfer->halted_nyet = 0; if (xfer->period_split_nyet_count < HCD_XFER_PERIOD_SPLIT_NYET_MAX) { - dwc2_channel_char_t hcchar = {.value = channel->hcchar}; hcchar.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame channel->hcchar = hcchar.value; channel_send_in_token(dwc2, channel); @@ -736,26 +737,20 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } } - if (hcint & HCINT_HALTED) { - const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8); - if (edpt->uframe_interval == ucount) { - // immediately retry if bInterval is 1 - edpt->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame - channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); - channel_send_in_token(dwc2, channel); - } else { - // otherwise, de-allocate channel, enable SOF set frame counter for later transfer - const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; - edpt->next_pid = hctsiz.pid; // save PID - edpt->uframe_countdown = edpt->uframe_interval - ucount; - dwc2->gintmsk |= GINTSTS_SOF; - // already halted, de-allocate channel (called from DMA isr) - channel_dealloc(dwc2, ch_id); - } + const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8); + if (edpt->uframe_interval == ucount) { + // retry on next frame if bInterval is 1 + hcchar.odd_frame = 1 - (dwc2->hfnum & 1); + channel->hcchar = hcchar.value; + channel_send_in_token(dwc2, channel); } else { - // disable channel first if not halted (called slave isr) - xfer->halted_sof_schedule = 1; - channel_disable(dwc2, channel); + // otherwise, de-allocate channel, enable SOF set frame counter for later transfer + const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; + edpt->next_pid = hctsiz.pid; // save PID + edpt->uframe_countdown = edpt->uframe_interval - ucount; + dwc2->gintmsk |= GINTSTS_SOF; + // already halted, de-allocate channel (called from DMA isr) + channel_dealloc(dwc2, ch_id); } } else { // for control/bulk: retry immediately @@ -905,7 +900,7 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h xfer->halted_nyet = 1; channel_disable(dwc2, channel); } else if (hcint & HCINT_NAK) { - // NAK received, re-enable channel if request queue is available + // NAK received, disable channel to flush all posted request and try again if (hcsplt.split_en) { hcsplt.split_compl = 0; // restart with start-split channel->hcsplt = hcsplt.value; @@ -937,10 +932,7 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; - if (xfer->halted_sof_schedule) { - // de-allocate channel but does not complete xfer, we schedule it in the SOF interrupt - channel_dealloc(dwc2, ch_id); - } else if (xfer->result != XFER_RESULT_INVALID) { + if (xfer->result != XFER_RESULT_INVALID) { is_done = true; } else if (xfer->err_count == HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; -- cgit v1.3.1 From b7a26cc33c793a3fc03ee54e27f48d276405af0d Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 18 Apr 2025 12:42:18 +0200 Subject: Fix 1st nak retry one frame shorter. Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index a68455daa..be653fab0 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -748,6 +748,7 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; edpt->next_pid = hctsiz.pid; // save PID edpt->uframe_countdown = edpt->uframe_interval - ucount; + dwc2->gintsts = GINTSTS_SOF; // SOF flag is probably pending dwc2->gintmsk |= GINTSTS_SOF; // already halted, de-allocate channel (called from DMA isr) channel_dealloc(dwc2, ch_id); -- cgit v1.3.1 From 8111e53ff067ca3a55f06389e4571fd57554ae5a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Apr 2025 18:21:42 +0700 Subject: minor rename --- src/portable/synopsys/dwc2/hcd_dwc2.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 1238a68e0..e1035fa55 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -75,9 +75,9 @@ typedef struct { struct TU_ATTR_PACKED { uint32_t uframe_interval : 18; // micro-frame interval - uint32_t speed : 2; - uint32_t next_pid : 2; - uint32_t do_ping : 1; + uint32_t speed : 2; + uint32_t next_pid : 2; // PID for next transfer + uint32_t next_do_ping : 1; // Do PING for next transfer if possible (highspeed OUT) // uint32_t : 9; }; @@ -567,12 +567,12 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { hctsiz.pid = edpt->next_pid; // next PID is set in transfer complete interrupt hctsiz.packet_count = packet_count; hctsiz.xfer_size = edpt->buflen; - if (edpt->do_ping && edpt->speed == TUSB_SPEED_HIGH && + if (edpt->next_do_ping && edpt->speed == TUSB_SPEED_HIGH && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { hctsiz.do_ping = 1; } channel->hctsiz = hctsiz.value; - edpt->do_ping = 0; + edpt->next_do_ping = 0; // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet if (hcchar_bm->ep_num == 0) { @@ -970,7 +970,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } else { - edpt->do_ping = 1; + edpt->next_do_ping = 1; channel_xfer_out_wrapup(dwc2, ch_id); channel_disable(dwc2, channel); } @@ -983,7 +983,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel->hcintmsk |= HCINT_ACK; } else { // NAK disable channel to flush all posted request and try again - edpt->do_ping = 1; + edpt->next_do_ping = 1; xfer->err_count = 0; } } else if (hcint & HCINT_HALTED) { @@ -1009,7 +1009,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t } } else { // Device is ready, resume transfer - edpt->do_ping = 0; + edpt->next_do_ping = 0; xfer->err_count = 0; TU_ASSERT(channel_xfer_start(dwc2, ch_id)); } -- cgit v1.3.1 From b3d20442e2252b95f674caf5572d7c392fefb080 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 18 Apr 2025 14:57:53 +0200 Subject: Fix usbh racing later. Signed-off-by: HiFiPhile --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 5ce325762..157a7ab86 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1038,7 +1038,7 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) // Check if dev0 is removed if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) && (event->connection.hub_port == _dev0.hub_port)) { - //_dev0.enumerating = 0;// Causes assert in dwc2 process_enumeration() -> ENUM_ADDR0_DEVICE_DESC + _dev0.enumerating = 0; } break; -- cgit v1.3.1 From d51863d1a006f01f9d4ab9e9863dd6c6fdf8f13b Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Apr 2025 22:39:59 +0700 Subject: - correctly do_ping if received nyet as transfer complete e.g msc 31 byte command - correctly carry out OUT transfer when PING is ack --- src/portable/synopsys/dwc2/dwc2_type.h | 6 +++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 14 +++++++++----- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 34e046346..0a8dacf5f 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -2088,9 +2088,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCTSIZ_DOPING_Pos (31U) #define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 #define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING -#define HCTSIZ_PID_Pos (29U) -#define HCTSIZ_PID_Msk (0x3UL << HCTSIZ_PID_Pos) // 0x60000000 -#define HCTSIZ_PID HCTSIZ_PID_Msk // Data PID +#define HCTSIZ_PID_Pos (29U) +#define HCTSIZ_PID_Msk (0x3UL << HCTSIZ_PID_Pos) // 0x60000000 +#define HCTSIZ_PID HCTSIZ_PID_Msk // Data PID /******************** Bit definition for DIEPDMA register ********************/ #define DIEPDMA_DMAADDR_Pos (0U) diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index e1035fa55..1845c5e19 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -959,6 +959,10 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t is_done = true; xfer->result = XFER_RESULT_SUCCESS; channel->hcintmsk &= ~HCINT_ACK; + if (hcint & HCINT_NYET) { + // complete transfer with NYET, do ping next time + edpt->next_do_ping = 1; + } } else if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; channel_disable(dwc2, channel); @@ -1002,16 +1006,16 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel->hcintmsk &= ~HCINT_ACK; if (hcsplt.split_en) { if (!hcsplt.split_compl) { - // start split is ACK --> do complete split + // ACK for start split --> do complete split hcsplt.split_compl = 1; channel->hcsplt = hcsplt.value; channel->hcchar |= HCCHAR_CHENA; } } else { - // Device is ready, resume transfer - edpt->next_do_ping = 0; - xfer->err_count = 0; - TU_ASSERT(channel_xfer_start(dwc2, ch_id)); + // ACK interrupt is only enabled for Split and PING + // ACK for PING, which mean device is ready to receive data + channel->hctsiz &= ~HCTSIZ_DOPING; // HC already cleared PING bit, but we clear anyway + channel->hcchar |= HCCHAR_CHENA; } } -- cgit v1.3.1 From b3a9b6e37ffb21dba2f6da5fdd4ac5cd90c94442 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 19 Apr 2025 11:43:28 +0200 Subject: enable SOF interrupt only if not already enabled Signed-off-by: HiFiPhile --- src/portable/synopsys/dwc2/hcd_dwc2.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index be653fab0..378c2742b 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -748,8 +748,11 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci const dwc2_channel_tsize_t hctsiz = {.value = channel->hctsiz}; edpt->next_pid = hctsiz.pid; // save PID edpt->uframe_countdown = edpt->uframe_interval - ucount; - dwc2->gintsts = GINTSTS_SOF; // SOF flag is probably pending - dwc2->gintmsk |= GINTSTS_SOF; + // enable SOF interrupt if not already enabled + if (!(dwc2->gintmsk & GINTMSK_SOFM)) { + dwc2->gintsts = GINTSTS_SOF; + dwc2->gintmsk |= GINTMSK_SOFM; + } // already halted, de-allocate channel (called from DMA isr) channel_dealloc(dwc2, ch_id); } -- cgit v1.3.1 From 5725d33121d483162730c7bb06cada3faf0da9af Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Apr 2025 20:39:23 +0700 Subject: improve usbh stability with failed setup send, prevent control stage locked out --- src/host/usbh.c | 43 ++++++++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 157a7ab86..d6d974371 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -647,6 +647,21 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer) { *((xfer_result_t*) xfer->user_data) = xfer->result; } +TU_ATTR_ALWAYS_INLINE static inline void _control_set_xfer_stage(uint8_t stage) { + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + _ctrl_xfer.stage = stage; + (void) osal_mutex_unlock(_usbh_mutex); +} + +TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const uint8_t setup_packet[8]) { + const uint8_t rhport = usbh_get_rhport(daddr); + const bool ret = hcd_setup_send(rhport, daddr, setup_packet); + if (!ret) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } + return ret; +} + // TODO timeout_ms is not supported yet bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); // EP0 with setup packet @@ -673,15 +688,13 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { (void) osal_mutex_unlock(_usbh_mutex); TU_VERIFY(is_idle); - const uint8_t rhport = usbh_get_rhport(daddr); - TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); TU_LOG_BUF_USBH(xfer->setup, 8); if (xfer->complete_cb) { - TU_ASSERT(hcd_setup_send(rhport, daddr, (uint8_t const *) &_usbh_epbuf.request)); + TU_ASSERT(usbh_setup_send(daddr, (uint8_t const *) &_usbh_epbuf.request)); }else { // blocking if complete callback is not provided // change callback to internal blocking, and result as user argument @@ -691,7 +704,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { _ctrl_xfer.user_data = (uintptr_t) &result; _ctrl_xfer.complete_cb = _control_blocking_complete_cb; - TU_ASSERT(hcd_setup_send(rhport, daddr, (uint8_t *) &_usbh_epbuf.request)); + TU_ASSERT(usbh_setup_send(daddr, (uint8_t const *) &_usbh_epbuf.request)); while (result == XFER_RESULT_INVALID) { // Note: this can be called within an callback ie. part of tuh_task() @@ -713,12 +726,6 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { return true; } -TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { - (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _ctrl_xfer.stage = stage; - (void) osal_mutex_unlock(_usbh_mutex); -} - static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); @@ -735,7 +742,7 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { .user_data = _ctrl_xfer.user_data }; - _set_control_xfer_stage(CONTROL_STAGE_IDLE); + _control_set_xfer_stage(CONTROL_STAGE_IDLE); if (xfer_temp.complete_cb) { xfer_temp.complete_cb(&xfer_temp); @@ -764,7 +771,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t _ctrl_xfer.actual_len = 0; // reset actual_len (void) osal_mutex_unlock(_usbh_mutex); - TU_ASSERT(hcd_setup_send(rhport, daddr, (uint8_t const *) request)); + TU_ASSERT(usbh_setup_send(daddr, (uint8_t const *) request)); } else { TU_LOG_USBH("[%u:%u] Control FAILED, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, xferred_bytes); TU_LOG_BUF_USBH(request, 8); @@ -777,8 +784,8 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t case CONTROL_STAGE_SETUP: if (request->wLength) { // DATA stage: initial data toggle is always 1 - _set_control_xfer_stage(CONTROL_STAGE_DATA); - TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength) ); + _control_set_xfer_stage(CONTROL_STAGE_DATA); + TU_ASSERT(hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength)); return true; } TU_ATTR_FALLTHROUGH; @@ -792,7 +799,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t _ctrl_xfer.actual_len = (uint16_t) xferred_bytes; // ACK stage: toggle is always 1 - _set_control_xfer_stage(CONTROL_STAGE_ACK); + _control_set_xfer_stage(CONTROL_STAGE_ACK); TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction), NULL, 0) ); break; @@ -854,7 +861,7 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { // control transfer: only 1 control at a time, check if we are aborting the current one TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE); hcd_edpt_abort_xfer(rhport, daddr, ep_addr); - _set_control_xfer_stage(CONTROL_STAGE_IDLE); // reset control transfer state to idle + _control_set_xfer_stage(CONTROL_STAGE_IDLE); // reset control transfer state to idle } else { usbh_device_t* dev = get_device(daddr); TU_VERIFY(dev); @@ -1321,7 +1328,9 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu clear_device(dev); // abort on-going control xfer on this device if any - if (_ctrl_xfer.daddr == daddr) _set_control_xfer_stage(CONTROL_STAGE_IDLE); + if (_ctrl_xfer.daddr == daddr) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } } } -- cgit v1.3.1 From 9f096ac56b637423ba7c4a4004f6f95006c12e95 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 12 Apr 2025 20:00:00 +0200 Subject: host: fix enumerate racing - if a previous enumeration failed _ctrl_xfer status could stuck, it needs to be cleared before next attempt. - after _dev0.enumerating is reset in hcd_event_handler(), if an attach event arrived before _ctrl_xfer clean up in remove event, a racing condition will happen. Signed-off-by: HiFiPhile --- src/host/usbh.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index d6d974371..69784ed47 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -311,6 +311,12 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) return &_usbh_devices[dev_addr-1]; } +TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + _ctrl_xfer.stage = stage; + (void) osal_mutex_unlock(_usbh_mutex); +} + static bool enum_new_device(hcd_event_t* event); static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); @@ -557,6 +563,13 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); + if ((event.rhport == _dev0.rhport) && (event.connection.hub_addr == _dev0.hub_addr) && + (event.connection.hub_port == _dev0.hub_port)) { + _dev0.enumerating = 0; + if (_ctrl_xfer.daddr == 0) { + _set_control_xfer_stage(CONTROL_STAGE_IDLE); + } + } #if CFG_TUH_HUB // TODO remove if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) { @@ -1042,11 +1055,6 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) // FIXME device remove from a hub need an HCD API for hcd to free up endpoint // mark device as removing to prevent further xfer before the event is processed in usbh task - // Check if dev0 is removed - if ((event->rhport == _dev0.rhport) && (event->connection.hub_addr == _dev0.hub_addr) && - (event->connection.hub_port == _dev0.hub_port)) { - _dev0.enumerating = 0; - } break; default: break; -- cgit v1.3.1 From 3c4e6a779d65ad2d28e0eef0284df88e39bec6bc Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 18 Apr 2025 17:41:41 +0200 Subject: Move decouncing delay before USB reset. Signed-off-by: HiFiPhile --- src/host/usbh.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 69784ed47..c38afa3be 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1692,6 +1692,15 @@ static bool enum_new_device(hcd_event_t* event) { _dev0.hub_port = event->connection.hub_port; if (_dev0.hub_addr == 0) { + // wait until device connection is stable TODO non blocking + tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); + + // device unplugged while delaying + if (!hcd_port_connect_status(_dev0.rhport)) { + enum_full_complete(); + return true; + } + // connected directly to roothub hcd_port_reset(_dev0.rhport); @@ -1701,9 +1710,6 @@ static bool enum_new_device(hcd_event_t* event) { hcd_port_reset_end(_dev0.rhport); - // wait until device connection is stable TODO non blocking - tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); - // device unplugged while delaying if (!hcd_port_connect_status(_dev0.rhport)) { enum_full_complete(); -- cgit v1.3.1 From 7ba63a63022ed5ed2e92daca1cd011dd55547d39 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 18 Apr 2025 17:47:53 +0200 Subject: Also cleanup unaddressed device. Signed-off-by: HiFiPhile --- src/host/usbh.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index c38afa3be..712f10f0d 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -566,6 +566,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { if ((event.rhport == _dev0.rhport) && (event.connection.hub_addr == _dev0.hub_addr) && (event.connection.hub_port == _dev0.hub_port)) { _dev0.enumerating = 0; + hcd_device_close(_dev0.rhport, _dev0.hub_addr); if (_ctrl_xfer.daddr == 0) { _set_control_xfer_stage(CONTROL_STAGE_IDLE); } -- cgit v1.3.1 From 940fe43e68eaa6d8c38404410896574ed8147421 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 22 Apr 2025 17:33:37 +0700 Subject: move removing dev0 to process_removing_device() --- src/host/usbh.c | 59 +++++++++++++++++++-------------------------------------- 1 file changed, 19 insertions(+), 40 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 712f10f0d..0a78177ea 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -311,12 +311,6 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) return &_usbh_devices[dev_addr-1]; } -TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage) { - (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _ctrl_xfer.stage = stage; - (void) osal_mutex_unlock(_usbh_mutex); -} - static bool enum_new_device(hcd_event_t* event); static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); @@ -563,14 +557,6 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); - if ((event.rhport == _dev0.rhport) && (event.connection.hub_addr == _dev0.hub_addr) && - (event.connection.hub_port == _dev0.hub_port)) { - _dev0.enumerating = 0; - hcd_device_close(_dev0.rhport, _dev0.hub_addr); - if (_ctrl_xfer.daddr == 0) { - _set_control_xfer_stage(CONTROL_STAGE_IDLE); - } - } #if CFG_TUH_HUB // TODO remove if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) { @@ -662,9 +648,11 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer) { } TU_ATTR_ALWAYS_INLINE static inline void _control_set_xfer_stage(uint8_t stage) { - (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _ctrl_xfer.stage = stage; - (void) osal_mutex_unlock(_usbh_mutex); + if (_ctrl_xfer.stage != stage) { + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + _ctrl_xfer.stage = stage; + (void) osal_mutex_unlock(_usbh_mutex); + } } TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const uint8_t setup_packet[8]) { @@ -1279,30 +1267,19 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX); } -//static void mark_removing_device_isr(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { -// for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { -// usbh_device_t *dev = &_usbh_devices[dev_id]; -// uint8_t const daddr = dev_id + 1; -// -// // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub -// if (dev->rhport == rhport && dev->connected && -// (hub_addr == 0 || dev->hub_addr == hub_addr) && -// (hub_port == 0 || dev->hub_port == hub_port)) { -// if (is_hub_addr(daddr)) { -// // If the device itself is a usb hub, mark all downstream devices. -// // FIXME recursive calls -// mark_removing_device_isr(rhport, daddr, 0); -// } -// -// dev->removing = 1; -// } -// } -//} - // a device unplugged from rhport:hub_addr:hub_port static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { + // dev0 is unplugged + if (_dev0.enumerating && (rhport == _dev0.rhport) && (hub_addr == _dev0.hub_addr) && (hub_port == _dev0.hub_port)) { + hcd_device_close(_dev0.rhport, 0); + if (_ctrl_xfer.daddr == 0) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } + _dev0.enumerating = 0; + return; + } + //------------- find the all devices (star-network) under port that is unplugged -------------// - // TODO mark as disconnected in ISR, also handle dev0 uint32_t removing_hubs = 0; do { for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { @@ -1343,9 +1320,11 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu } } - // if removing a hub, we need to remove its downstream devices + // if removing a hub, we need to remove all of its downstream devices #if CFG_TUH_HUB - if (removing_hubs == 0) break; + if (removing_hubs == 0) { + break; + } // find a marked hub to process for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) { -- cgit v1.3.1 From 8f9ef7dfbe41e29d4275be4ca2130d70d163f100 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 22 Apr 2025 22:09:06 +0700 Subject: reduce ENUM_DEBOUNCING_DELAY_MS to 200ms replace dev0.enumerating by enumerating_daddr for better clean up on unplugging while enumerating move controller_id & enumerating_daddr into _usbh_data struct --- src/host/usbh.c | 95 +++++++++++++++++++++++++++++---------------------------- 1 file changed, 48 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 0a78177ea..bb4669718 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -96,12 +96,7 @@ typedef struct { uint8_t rhport; uint8_t hub_addr; uint8_t hub_port; - - struct TU_ATTR_PACKED { - uint8_t speed : 4; // packed speed to save footprint - volatile uint8_t enumerating : 1; // enumeration is in progress, false if not connected or all interfaces are configured - uint8_t TU_RESERVED : 3; - }; + uint8_t speed; } usbh_dev0_t; typedef struct { @@ -117,7 +112,6 @@ typedef struct { volatile uint8_t addressed : 1; // After SET_ADDR volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured volatile uint8_t suspended : 1; // Bus suspended - // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh }; @@ -261,8 +255,6 @@ static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) { // sum of end device + hub #define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) -static uint8_t _usbh_controller = TUSB_INDEX_INVALID_8; - // Device with address = 0 for enumeration static usbh_dev0_t _dev0; @@ -279,8 +271,7 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES]; #define _usbh_mutex NULL #endif -// Event queue -// usbh_int_set is used as mutex in OS NONE config +// Event queue: usbh_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; @@ -305,6 +296,15 @@ typedef struct { CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; +typedef struct { + uint8_t controller_id; // controller ID + uint8_t enumerating_daddr; // device address of the device being enumerated +} usbh_data_t; + +static usbh_data_t _usbh_data = { + .controller_id = TUSB_INDEX_INVALID_8, +}; + //------------- Helper Function -------------// TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) { TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL); @@ -334,7 +334,7 @@ bool tuh_mounted(uint8_t dev_addr) { bool tuh_connected(uint8_t daddr) { if (daddr == 0) { - return _dev0.enumerating; // dev0 is connected if still enumerating + return _usbh_data.enumerating_daddr == 0; } else { const usbh_device_t* dev = get_device(daddr); return dev && dev->connected; @@ -359,7 +359,7 @@ tusb_speed_t tuh_speed_get(uint8_t dev_addr) { } bool tuh_rhport_is_active(uint8_t rhport) { - return _usbh_controller == rhport; + return _usbh_data.controller_id == rhport; } bool tuh_rhport_reset_bus(uint8_t rhport, bool active) { @@ -387,7 +387,7 @@ static void clear_device(usbh_device_t* dev) { } bool tuh_inited(void) { - return _usbh_controller != TUSB_INDEX_INVALID_8; + return _usbh_data.controller_id != TUSB_INDEX_INVALID_8; } bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { @@ -427,6 +427,9 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { tu_memclr(_usbh_devices, sizeof(_usbh_devices)); tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); + _usbh_data.controller_id = TUSB_INDEX_INVALID_8; + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + for (uint8_t i = 0; i < TOTAL_DEVICES; i++) { clear_device(&_usbh_devices[i]); } @@ -442,7 +445,7 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } // Init host controller - _usbh_controller = rhport; + _usbh_data.controller_id = rhport; TU_ASSERT(hcd_init(rhport, rh_init)); hcd_int_enable(rhport); @@ -457,7 +460,7 @@ bool tuh_deinit(uint8_t rhport) { // deinit host controller hcd_int_disable(rhport); hcd_deinit(rhport); - _usbh_controller = TUSB_INDEX_INVALID_8; + _usbh_data.controller_id = TUSB_INDEX_INVALID_8; // "unplug" all devices on this rhport (hub_addr = 0, hub_port = 0) process_removing_device(rhport, 0, 0); @@ -524,20 +527,19 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: - // due to the shared control buffer, we must complete enumerating one device before enumerating another one. + // due to the shared control buffer, we must fully complete enumerating one device first. // TODO better to have an separated queue for newly attached devices - if (_dev0.enumerating) { - // Some device can cause multiple duplicated attach events - // drop current enumerating and start over for a proper port reset - if (event.rhport == _dev0.rhport && event.connection.hub_addr == _dev0.hub_addr && - event.connection.hub_port == _dev0.hub_port) { + if (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) { + if (event.rhport == _dev0.rhport && + event.connection.hub_addr == _dev0.hub_addr && event.connection.hub_port == _dev0.hub_port) { + // Some device can cause multiple duplicated attach events + // drop current enumerating and start over for a proper port reset // abort/cancel current enumeration and start new one TU_LOG1("[%u:] USBH Device Attach (duplicated)\r\n", event.rhport); tuh_edpt_abort_xfer(0, 0); enum_new_device(&event); } else { TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); - bool is_empty = osal_queue_empty(_usbh_q); queue_event(&event, in_isr); @@ -548,7 +550,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { } } else { TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport); - _dev0.enumerating = 1; + _usbh_data.enumerating_daddr = 0; enum_new_device(&event); } break; @@ -668,7 +670,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const ui bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); // EP0 with setup packet const uint8_t daddr = xfer->daddr; - TU_VERIFY(tuh_connected(daddr)); // Check if device is still connected (enumerating for dev0) + TU_VERIFY(tuh_connected(daddr)); // pre-check to help reducing mutex lock TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE); @@ -895,9 +897,9 @@ uint8_t *usbh_get_enum_buf(void) { void usbh_int_set(bool enabled) { // TODO all host controller if multiple are used since they shared the same event queue if (enabled) { - hcd_int_enable(_usbh_controller); + hcd_int_enable(_usbh_data.controller_id); } else { - hcd_int_disable(_usbh_controller); + hcd_int_disable(_usbh_data.controller_id); } } @@ -906,7 +908,6 @@ void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { event.event_id = USBH_EVENT_FUNC_CALL; event.func_call.func = func; event.func_call.param = param; - queue_event(&event, in_isr); } @@ -1043,7 +1044,6 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) case HCD_EVENT_DEVICE_REMOVE: // FIXME device remove from a hub need an HCD API for hcd to free up endpoint // mark device as removing to prevent further xfer before the event is processed in usbh task - break; default: break; @@ -1270,12 +1270,13 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { // a device unplugged from rhport:hub_addr:hub_port static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { // dev0 is unplugged - if (_dev0.enumerating && (rhport == _dev0.rhport) && (hub_addr == _dev0.hub_addr) && (hub_port == _dev0.hub_port)) { + if ((_usbh_data.enumerating_daddr == 0) && (rhport == _dev0.rhport) && + (hub_addr == _dev0.hub_addr) && (hub_port == _dev0.hub_port)) { hcd_device_close(_dev0.rhport, 0); if (_ctrl_xfer.daddr == 0) { _control_set_xfer_stage(CONTROL_STAGE_IDLE); } - _dev0.enumerating = 0; + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; return; } @@ -1314,9 +1315,13 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu clear_device(dev); // abort on-going control xfer on this device if any - if (_ctrl_xfer.daddr == daddr) { + if (daddr == _ctrl_xfer.daddr) { _control_set_xfer_stage(CONTROL_STAGE_IDLE); } + + if (daddr == _usbh_data.enumerating_daddr) { + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + } } } @@ -1353,9 +1358,9 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu //--------------------------------------------------------------------+ enum { - ENUM_RESET_DELAY_MS = 50, // USB specs: 10 to 50ms - ENUM_DEBOUNCING_DELAY_MS = 450, // when plug/unplug a device, physical connection can be bouncing and may + ENUM_DEBOUNCING_DELAY_MS = 200, // when plug/unplug a device, physical connection can be bouncing and may // generate a series of attach/detach event. This delay wait for stable connection + ENUM_RESET_DELAY_MS = 50, // USB specs: 10 to 50ms }; enum { @@ -1399,7 +1404,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // retry if not reaching max attempt failed_count++; - bool retry = _dev0.enumerating && (failed_count < ATTEMPT_COUNT_MAX); + bool retry = (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) && (failed_count < ATTEMPT_COUNT_MAX); if (retry) { tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit TU_LOG1("Enumeration attempt %u/%u\r\n", failed_count+1, ATTEMPT_COUNT_MAX); @@ -1409,7 +1414,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { if (!retry) { enum_full_complete(); // complete as failed } - return; } failed_count = 0; @@ -1425,7 +1429,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { switch (state) { #if CFG_TUH_HUB //case ENUM_HUB_GET_STATUS_1: break; - case ENUM_HUB_CLEAR_RESET_1: { hub_port_status_response_t port_status; memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); @@ -1490,14 +1493,12 @@ static void process_enumeration(tuh_xfer_t* xfer) { usbh_device_t* new_dev = get_device(new_addr); TU_ASSERT(new_dev,); new_dev->addressed = 1; + _usbh_data.enumerating_daddr = new_addr; - // Close device 0 - hcd_device_close(_dev0.rhport, 0); + hcd_device_close(_dev0.rhport, 0); // close dev0 - // open control pipe for new address - TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); + TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // open new control endpoint - // Get full device descriptor TU_LOG_USBH("Get Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_STRING_LANGUAGE_ID_LEN),); @@ -1516,8 +1517,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_serial = desc_device->iSerialNumber; dev->bNumConfigurations = desc_device->bNumConfigurations; - tuh_enum_descriptor_device_cb(daddr, desc_device);// callback - + tuh_enum_descriptor_device_cb(daddr, desc_device); // callback tuh_descriptor_get_string_langid(daddr, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_LANGUAGE_ID); break; @@ -1672,6 +1672,8 @@ static bool enum_new_device(hcd_event_t* event) { _dev0.hub_port = event->connection.hub_port; if (_dev0.hub_addr == 0) { + // connected directly to roothub + // wait until device connection is stable TODO non blocking tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); @@ -1681,8 +1683,7 @@ static bool enum_new_device(hcd_event_t* event) { return true; } - // connected directly to roothub - hcd_port_reset(_dev0.rhport); + hcd_port_reset(_dev0.rhport); // reset device // Since we are in middle of rhport reset, frame number is not available yet. // need to depend on tusb_time_millis_api() @@ -1905,7 +1906,7 @@ void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num) { static void enum_full_complete(void) { // mark enumeration as complete - _dev0.enumerating = 0; + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; #if CFG_TUH_HUB if (_dev0.hub_addr) { -- cgit v1.3.1 From b6170c965f83a4f59ec7c165c502d812ceafea3f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Tue, 22 Apr 2025 21:14:04 +0200 Subject: Compile fix. Signed-off-by: HiFiPhile --- src/host/usbh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index bb4669718..0492fb2f2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -692,7 +692,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { (void) osal_mutex_unlock(_usbh_mutex); TU_VERIFY(is_idle); - TU_LOG_USBH("[%u:%u] %s: ", rhport, daddr, + TU_LOG_USBH("[%u:%u] %s: ", usbh_get_rhport(daddr), daddr, (xfer->setup->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME) ? tu_str_std_request[xfer->setup->bRequest] : "Class Request"); TU_LOG_BUF_USBH(xfer->setup, 8); -- cgit v1.3.1 From 741cb3cf029e37682634eeb355c20420c0816c8d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 23 Apr 2025 12:35:32 +0700 Subject: rename hcd_devtree_info_t to tuh_bus_info_t, hcd_devtree_get_info to hcd_bus_info_get streamline bus info to usbh_devies, also replace dev0 (renamed to dev0_bus) --- .idea/debugServers/esp32s2.xml | 14 +++ .idea/debugServers/rp2350.xml | 2 +- .idea/debugServers/stm32f769.xml | 13 +++ .idea/debugServers/stm32h563.xml | 13 +++ .idea/debugServers/stm32h743.xml | 13 +++ examples/host/cdc_msc_hid/src/msc_app.c | 12 +-- src/host/hcd.h | 12 +-- src/host/usbh.c | 127 +++++++++++-------------- src/host/usbh_pvt.h | 2 +- src/portable/ehci/ehci.c | 10 +- src/portable/mentor/musb/hcd_musb.c | 24 ++--- src/portable/ohci/ohci.c | 6 +- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 6 +- src/portable/renesas/rusb2/hcd_rusb2.c | 6 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 18 ++-- 15 files changed, 152 insertions(+), 126 deletions(-) create mode 100644 .idea/debugServers/esp32s2.xml create mode 100644 .idea/debugServers/stm32f769.xml create mode 100644 .idea/debugServers/stm32h563.xml create mode 100644 .idea/debugServers/stm32h743.xml (limited to 'src') diff --git a/.idea/debugServers/esp32s2.xml b/.idea/debugServers/esp32s2.xml new file mode 100644 index 000000000..6a4aff3da --- /dev/null +++ b/.idea/debugServers/esp32s2.xml @@ -0,0 +1,14 @@ + + + + $USER_HOME$/.espressif/tools/xtensa-esp-elf-gdb/14.2_20240403/xtensa-esp-elf-gdb/bin/xtensa-esp32s2-elf-gdb + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/rp2350.xml b/.idea/debugServers/rp2350.xml index 5e092f3c4..52243a297 100644 --- a/.idea/debugServers/rp2350.xml +++ b/.idea/debugServers/rp2350.xml @@ -1,5 +1,5 @@ - + diff --git a/.idea/debugServers/stm32f769.xml b/.idea/debugServers/stm32f769.xml new file mode 100644 index 000000000..2fb322a0f --- /dev/null +++ b/.idea/debugServers/stm32f769.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/stm32h563.xml b/.idea/debugServers/stm32h563.xml new file mode 100644 index 000000000..9bf6db6e9 --- /dev/null +++ b/.idea/debugServers/stm32h563.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/stm32h743.xml b/.idea/debugServers/stm32h743.xml new file mode 100644 index 000000000..63680b78c --- /dev/null +++ b/.idea/debugServers/stm32h743.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/examples/host/cdc_msc_hid/src/msc_app.c b/examples/host/cdc_msc_hid/src/msc_app.c index 1d7e18e6e..0e9c99766 100644 --- a/examples/host/cdc_msc_hid/src/msc_app.c +++ b/examples/host/cdc_msc_hid/src/msc_app.c @@ -30,13 +30,11 @@ //--------------------------------------------------------------------+ static scsi_inquiry_resp_t inquiry_resp; -bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; - if (csw->status != 0) - { + if (csw->status != 0) { printf("Inquiry failed\r\n"); return false; } @@ -55,16 +53,14 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_da } //------------- IMPLEMENTATION -------------// -void tuh_msc_mount_cb(uint8_t dev_addr) -{ +void tuh_msc_mount_cb(uint8_t dev_addr) { printf("A MassStorage device is mounted\r\n"); uint8_t const lun = 0; tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0); } -void tuh_msc_umount_cb(uint8_t dev_addr) -{ +void tuh_msc_umount_cb(uint8_t dev_addr) { (void) dev_addr; printf("A MassStorage device is unmounted\r\n"); } diff --git a/src/host/hcd.h b/src/host/hcd.h index b20d96d54..1f2704a10 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -95,7 +95,7 @@ typedef struct { uint8_t hub_addr; uint8_t hub_port; uint8_t speed; -} hcd_devtree_info_t; +} tuh_bus_info_t; //--------------------------------------------------------------------+ // Memory API @@ -186,12 +186,8 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); // USBH implemented API //--------------------------------------------------------------------+ -// Get device tree information of a device -// USB device tree can be complicated and manged by USBH, this help HCD to retrieve -// needed topology info to carry out its work -extern void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info); - -//------------- Event API -------------// +// Get device port information +extern bool hcd_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info); // Called by HCD to notify stack extern void hcd_event_handler(hcd_event_t const* event, bool in_isr); @@ -239,4 +235,4 @@ void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred } #endif -#endif /* _TUSB_HCD_H_ */ +#endif diff --git a/src/host/usbh.c b/src/host/usbh.c index 0492fb2f2..c063c97f9 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -92,19 +92,7 @@ TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_si // USBH-HCD common data structure //--------------------------------------------------------------------+ typedef struct { - // port - uint8_t rhport; - uint8_t hub_addr; - uint8_t hub_port; - uint8_t speed; -} usbh_dev0_t; - -typedef struct { - // port, must be same layout as usbh_dev0_t - uint8_t rhport; - uint8_t hub_addr; - uint8_t hub_port; - uint8_t speed; + tuh_bus_info_t bus_info; // Device State struct TU_ATTR_PACKED { @@ -231,8 +219,8 @@ static usbh_class_driver_t const usbh_class_drivers[] = { enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) }; // Additional class drivers implemented by application -tu_static usbh_class_driver_t const * _app_driver = NULL; -tu_static uint8_t _app_driver_count = 0; +static usbh_class_driver_t const * _app_driver = NULL; +static uint8_t _app_driver_count = 0; #define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT) @@ -255,9 +243,6 @@ static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) { // sum of end device + hub #define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) -// Device with address = 0 for enumeration -static usbh_dev0_t _dev0; - // all devices excluding zero-address // hub address start from CFG_TUH_DEVICE_MAX+1 // TODO: hub can has its own simpler struct to save memory @@ -299,6 +284,8 @@ CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; typedef struct { uint8_t controller_id; // controller ID uint8_t enumerating_daddr; // device address of the device being enumerated + + tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration } usbh_data_t; static usbh_data_t _usbh_data = { @@ -353,9 +340,10 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { return true; } -tusb_speed_t tuh_speed_get(uint8_t dev_addr) { - usbh_device_t *dev = get_device(dev_addr); - return (tusb_speed_t) (dev ? get_device(dev_addr)->speed : _dev0.speed); +tusb_speed_t tuh_speed_get(uint8_t daddr) { + tuh_bus_info_t bus_info; + hcd_bus_info_get(daddr, &bus_info); + return bus_info.speed; } bool tuh_rhport_is_active(uint8_t rhport) { @@ -423,9 +411,9 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } // Device - tu_memclr(&_dev0, sizeof(_dev0)); tu_memclr(_usbh_devices, sizeof(_usbh_devices)); tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); + tu_memclr(&_usbh_data, sizeof(_usbh_data)); _usbh_data.controller_id = TUSB_INDEX_INVALID_8; _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; @@ -530,8 +518,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // due to the shared control buffer, we must fully complete enumerating one device first. // TODO better to have an separated queue for newly attached devices if (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) { - if (event.rhport == _dev0.rhport && - event.connection.hub_addr == _dev0.hub_addr && event.connection.hub_port == _dev0.hub_port) { + if (event.rhport == _usbh_data.dev0_bus.rhport && + event.connection.hub_addr == _usbh_data.dev0_bus.hub_addr && event.connection.hub_port == _usbh_data.dev0_bus.hub_port) { // Some device can cause multiple duplicated attach events // drop current enumerating and start over for a proper port reset // abort/cancel current enumeration and start new one @@ -859,7 +847,7 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { const uint8_t dir = tu_edpt_dir(ep_addr); if (epnum == 0) { - // Also include dev0 for aborting enumerating + // Also include dev0_bus for aborting enumerating const uint8_t rhport = usbh_get_rhport(daddr); // control transfer: only 1 control at a time, check if we are aborting the current one @@ -871,7 +859,7 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { TU_VERIFY(dev); TU_VERIFY(dev->ep_status[epnum][dir].busy); // non-control skip if not busy - hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); + hcd_edpt_abort_xfer(dev->bus_info.rhport, daddr, ep_addr); // mark as ready and release endpoint if transfer is aborted dev->ep_status[epnum][dir].busy = false; @@ -885,9 +873,10 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { // USBH API For Class Driver //--------------------------------------------------------------------+ -uint8_t usbh_get_rhport(uint8_t dev_addr) { - usbh_device_t *dev = get_device(dev_addr); - return dev ? dev->rhport : _dev0.rhport; +uint8_t usbh_get_rhport(uint8_t daddr) { + tuh_bus_info_t bus_info; + hcd_bus_info_get(daddr, &bus_info); + return bus_info.rhport; } uint8_t *usbh_get_enum_buf(void) { @@ -972,7 +961,7 @@ bool usbh_edpt_xfer_with_callback(uint8_t dev_addr, uint8_t ep_addr, uint8_t* bu dev->ep_callback[epnum][dir].user_data = user_data; #endif - if (hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes)) { + if (hcd_edpt_xfer(dev->bus_info.rhport, dev_addr, ep_addr, buffer, total_bytes)) { TU_LOG_USBH("OK\r\n"); return true; } else { @@ -1024,19 +1013,14 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //--------------------------------------------------------------------+ -void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info) { - usbh_device_t const* dev = get_device(dev_addr); +bool hcd_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info) { + usbh_device_t const* dev = get_device(daddr); if (dev) { - devtree_info->rhport = dev->rhport; - devtree_info->hub_addr = dev->hub_addr; - devtree_info->hub_port = dev->hub_port; - devtree_info->speed = dev->speed; + *bus_info = dev->bus_info; } else { - devtree_info->rhport = _dev0.rhport; - devtree_info->hub_addr = _dev0.hub_addr; - devtree_info->hub_port = _dev0.hub_port; - devtree_info->speed = _dev0.speed; + *bus_info = _usbh_data.dev0_bus; } + return true; } TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) { @@ -1269,10 +1253,10 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { // a device unplugged from rhport:hub_addr:hub_port static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { - // dev0 is unplugged - if ((_usbh_data.enumerating_daddr == 0) && (rhport == _dev0.rhport) && - (hub_addr == _dev0.hub_addr) && (hub_port == _dev0.hub_port)) { - hcd_device_close(_dev0.rhport, 0); + // dev0_bus is unplugged + if ((_usbh_data.enumerating_daddr == 0) && (rhport == _usbh_data.dev0_bus.rhport) && + (hub_addr == _usbh_data.dev0_bus.hub_addr) && (hub_port == _usbh_data.dev0_bus.hub_port)) { + hcd_device_close(_usbh_data.dev0_bus.rhport, 0); if (_ctrl_xfer.daddr == 0) { _control_set_xfer_stage(CONTROL_STAGE_IDLE); } @@ -1288,9 +1272,9 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu uint8_t const daddr = dev_id + 1; // hub_addr = 0 means roothub, hub_port = 0 means all devices of downstream hub - if (dev->rhport == rhport && dev->connected && - (hub_addr == 0 || dev->hub_addr == hub_addr) && - (hub_port == 0 || dev->hub_port == hub_port)) { + if (dev->bus_info.rhport == rhport && dev->connected && + (hub_addr == 0 || dev->bus_info.hub_addr == hub_addr) && + (hub_port == 0 || dev->bus_info.hub_port == hub_port)) { TU_LOG_USBH("[%u:%u:%u] unplugged address = %u\r\n", rhport, hub_addr, hub_port, daddr); if (is_hub_addr(daddr)) { @@ -1439,12 +1423,12 @@ static void process_enumeration(tuh_xfer_t* xfer) { return; } - _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : + _usbh_data.dev0_bus.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; // Acknowledge Port Reset Change if (port_status.change.reset) { - hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, + hub_port_clear_reset_change(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC); } break; @@ -1452,7 +1436,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_GET_STATUS_2: tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, + TU_ASSERT(hub_port_get_status(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_2),); break; @@ -1462,7 +1446,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Acknowledge Port Reset Change if Reset Successful if (port_status.change.reset) { - TU_ASSERT(hub_port_clear_reset_change(_dev0.hub_addr, _dev0.hub_port, + TU_ASSERT(hub_port_clear_reset_change(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, process_enumeration, ENUM_SET_ADDR),); } break; @@ -1495,7 +1479,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { new_dev->addressed = 1; _usbh_data.enumerating_daddr = new_addr; - hcd_device_close(_dev0.rhport, 0); // close dev0 + hcd_device_close(_usbh_data.dev0_bus.rhport, 0); // close dev0_bus TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // open new control endpoint @@ -1667,38 +1651,38 @@ static void process_enumeration(tuh_xfer_t* xfer) { } static bool enum_new_device(hcd_event_t* event) { - _dev0.rhport = event->rhport; - _dev0.hub_addr = event->connection.hub_addr; - _dev0.hub_port = event->connection.hub_port; + _usbh_data.dev0_bus.rhport = event->rhport; + _usbh_data.dev0_bus.hub_addr = event->connection.hub_addr; + _usbh_data.dev0_bus.hub_port = event->connection.hub_port; - if (_dev0.hub_addr == 0) { + if (_usbh_data.dev0_bus.hub_addr == 0) { // connected directly to roothub // wait until device connection is stable TODO non blocking tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // device unplugged while delaying - if (!hcd_port_connect_status(_dev0.rhport)) { + if (!hcd_port_connect_status(_usbh_data.dev0_bus.rhport)) { enum_full_complete(); return true; } - hcd_port_reset(_dev0.rhport); // reset device + hcd_port_reset(_usbh_data.dev0_bus.rhport); // reset device // Since we are in middle of rhport reset, frame number is not available yet. // need to depend on tusb_time_millis_api() tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - hcd_port_reset_end(_dev0.rhport); + hcd_port_reset_end(_usbh_data.dev0_bus.rhport); // device unplugged while delaying - if (!hcd_port_connect_status(_dev0.rhport)) { + if (!hcd_port_connect_status(_usbh_data.dev0_bus.rhport)) { enum_full_complete(); return true; } - _dev0.speed = hcd_port_speed_get(_dev0.rhport); - TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_dev0.speed]); + _usbh_data.dev0_bus.speed = hcd_port_speed_get(_usbh_data.dev0_bus.rhport); + TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_usbh_data.dev0.speed]); // fake transfer to kick-off the enumeration process tuh_xfer_t xfer; @@ -1715,7 +1699,7 @@ static bool enum_new_device(hcd_event_t* event) { tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // ENUM_HUB_GET_STATUS - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, + TU_ASSERT(hub_port_get_status(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } #endif // hub @@ -1749,10 +1733,7 @@ static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) { TU_LOG_USBH("Set Address = %d\r\n", new_addr); usbh_device_t* new_dev = get_device(new_addr); - new_dev->rhport = _dev0.rhport; - new_dev->hub_addr = _dev0.hub_addr; - new_dev->hub_port = _dev0.hub_port; - new_dev->speed = _dev0.speed; + new_dev->bus_info = _usbh_data.dev0_bus; new_dev->connected = 1; new_dev->ep0_size = desc_device->bMaxPacketSize0; @@ -1768,7 +1749,7 @@ static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) { .wLength = 0 }; tuh_xfer_t xfer = { - .daddr = 0, // dev0 + .daddr = 0, .ep_addr = 0, .setup = &request, .buffer = NULL, @@ -1841,7 +1822,7 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat // Find driver for this interface for (uint8_t drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++) { usbh_class_driver_t const * driver = get_driver(drv_id); - if (driver && driver->open(dev->rhport, dev_addr, desc_itf, drv_len) ) { + if (driver && driver->open(dev->bus_info.rhport, dev_addr, desc_itf, drv_len) ) { // open successfully TU_LOG_USBH(" %s opened\r\n", driver->name); @@ -1860,9 +1841,9 @@ static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configurat break; // exit driver find loop } - if ( drv_id == TOTAL_DRIVER_COUNT - 1 ) { + if (drv_id == TOTAL_DRIVER_COUNT - 1) { TU_LOG_USBH("[%u:%u] Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n", - dev->rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); + dev->bus_info.rhport, dev_addr, desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol); } } @@ -1909,8 +1890,8 @@ static void enum_full_complete(void) { _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; #if CFG_TUH_HUB - if (_dev0.hub_addr) { - hub_edpt_status_xfer(_dev0.hub_addr); // get next hub status + if (_usbh_data.dev0_bus.hub_addr != 0) { + hub_edpt_status_xfer(_usbh_data.dev0_bus.hub_addr); // get next hub status } #endif diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index bfa1fb2ba..61b012493 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -63,7 +63,7 @@ usbh_class_driver_t const* usbh_app_driver_get_cb(uint8_t* driver_count) TU_ATTR // Call by class driver to tell USBH that it has complete the enumeration void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num); -uint8_t usbh_get_rhport(uint8_t dev_addr); +uint8_t usbh_get_rhport(uint8_t daddr); uint8_t* usbh_get_enum_buf(void); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 7451f69a3..141a2c026 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -837,8 +837,8 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c tu_memclr(p_qhd, sizeof(ehci_qhd_t)); } - hcd_devtree_info_t devtree_info; - hcd_devtree_get_info(dev_addr, &devtree_info); + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); uint8_t const xfer_type = ep_desc->bmAttributes.xfer; uint8_t const interval = ep_desc->bInterval; @@ -846,7 +846,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->dev_addr = dev_addr; p_qhd->fl_inactive_next_xact = 0; p_qhd->ep_number = tu_edpt_number(ep_desc->bEndpointAddress); - p_qhd->ep_speed = devtree_info.speed; + p_qhd->ep_speed = bus_info.speed; p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0; p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc); @@ -887,8 +887,8 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c default: break; } - p_qhd->fl_hub_addr = devtree_info.hub_addr; - p_qhd->fl_hub_port = devtree_info.hub_port; + p_qhd->fl_hub_addr = bus_info.hub_addr; + p_qhd->fl_hub_port = bus_info.hub_port; p_qhd->mult = 1; // TODO not use high bandwidth/park mode yet //------------- HCD Management Data -------------// diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 811043d74..97ef46152 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -695,16 +695,16 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet _hcd.pipe0.length = 8; _hcd.pipe0.remaining = 0; - hcd_devtree_info_t devtree; - hcd_devtree_get_info(dev_addr, &devtree); - switch (devtree.speed) { + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); + switch (bus_info.speed) { default: return false; case TUSB_SPEED_LOW: USB0->TYPE0 = USB_TYPE0_SPEED_LOW; break; case TUSB_SPEED_FULL: USB0->TYPE0 = USB_TYPE0_SPEED_FULL; break; case TUSB_SPEED_HIGH: USB0->TYPE0 = USB_TYPE0_SPEED_HIGH; break; } - USB0->TXHUBADDR0 = devtree.hub_addr; - USB0->TXHUBPORT0 = devtree.hub_port; + USB0->TXHUBADDR0 = bus_info.hub_addr; + USB0->TXHUBPORT0 = bus_info.hub_port; USB0->TXFUNCADDR0 = dev_addr; USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; return true; @@ -744,9 +744,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const pipe->remaining = 0; uint8_t pipe_type = 0; - hcd_devtree_info_t devtree; - hcd_devtree_get_info(dev_addr, &devtree); - switch (devtree.speed) { + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); + switch (bus_info.speed) { default: return false; case TUSB_SPEED_LOW: pipe_type |= USB_TXTYPE1_SPEED_LOW; break; case TUSB_SPEED_FULL: pipe_type |= USB_TXTYPE1_SPEED_FULL; break; @@ -763,8 +763,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const hw_endpoint_t volatile *regs = edpt_regs(pipenum - 1); if (dir_tx) { fadr->TXFUNCADDR = dev_addr; - fadr->TXHUBADDR = devtree.hub_addr; - fadr->TXHUBPORT = devtree.hub_port; + fadr->TXHUBADDR = bus_info.hub_addr; + fadr->TXHUBPORT = bus_info.hub_port; regs->TXMAXP = mps; regs->TXTYPE = pipe_type | epn; regs->TXINTERVAL = ep_desc->bInterval; @@ -775,8 +775,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const USB0->TXIE |= TU_BIT(pipenum); } else { fadr->RXFUNCADDR = dev_addr; - fadr->RXHUBADDR = devtree.hub_addr; - fadr->RXHUBPORT = devtree.hub_port; + fadr->RXHUBADDR = bus_info.hub_addr; + fadr->RXHUBPORT = bus_info.hub_port; regs->RXMAXP = mps; regs->RXTYPE = pipe_type | epn; regs->RXINTERVAL = ep_desc->bInterval; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 672ad0443..465b6731c 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -328,13 +328,13 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t tu_memclr(p_ed, sizeof(ohci_ed_t)); } - hcd_devtree_info_t devtree_info; - hcd_devtree_get_info(dev_addr, &devtree_info); + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); p_ed->dev_addr = dev_addr; p_ed->ep_number = ep_addr & 0x0F; p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT); - p_ed->speed = devtree_info.speed; + p_ed->speed = bus_info.speed; p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0; p_ed->max_packet_size = ep_size; diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 225a44dcf..0e3d0d31a 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -114,9 +114,9 @@ void hcd_int_disable(uint8_t rhport) { //--------------------------------------------------------------------+ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) { - hcd_devtree_info_t dev_tree; - hcd_devtree_get_info(dev_addr, &dev_tree); - bool const need_pre = (dev_tree.hub_addr && dev_tree.speed == TUSB_SPEED_LOW); + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); + bool const need_pre = (bus_info.hub_addr && bus_info.speed == TUSB_SPEED_LOW); uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 3e4b36981..e6975287d 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -662,13 +662,13 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const if (0 == epn) { rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; - hcd_devtree_info_t devtree; - hcd_devtree_get_info(dev_addr, &devtree); + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0]; devadd += dev_addr; while (rusb->DCPCTR_b.PBUSY) {} rusb->DCPMAXP = (dev_addr << 12) | mps; - *devadd = (TUSB_SPEED_FULL == devtree.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS; + *devadd = (TUSB_SPEED_FULL == bus_info.speed) ? RUSB2_DEVADD_USBSPD_FS : RUSB2_DEVADD_USBSPD_LS; _hcd.ctl_mps[dev_addr] = mps; return true; } diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 53bc0b059..6fd343686 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -475,8 +475,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* dwc2_regs_t* dwc2 = DWC2_REG(rhport); const tusb_speed_t rh_speed = hprt_speed_get(dwc2); - hcd_devtree_info_t devtree_info; - hcd_devtree_get_info(dev_addr, &devtree_info); + tuh_bus_info_t bus_info; + hcd_bus_info_get(dev_addr, &bus_info); // find a free endpoint const uint8_t ep_id = edpt_alloc(); @@ -487,7 +487,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); - hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; + hcchar_bm->low_speed_dev = (bus_info.speed == TUSB_SPEED_LOW) ? 1 : 0; hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* hcchar_bm->err_multi_count = 0; hcchar_bm->dev_addr = dev_addr; @@ -496,21 +496,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcchar_bm->enable = 1; dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm; - hcsplt_bm->hub_port = devtree_info.hub_port; - hcsplt_bm->hub_addr = devtree_info.hub_addr; + hcsplt_bm->hub_port = bus_info.hub_port; + hcsplt_bm->hub_addr = bus_info.hub_addr; hcsplt_bm->xact_pos = 0; hcsplt_bm->split_compl = 0; - hcsplt_bm->split_en = (rh_speed == TUSB_SPEED_HIGH && devtree_info.speed != TUSB_SPEED_HIGH) ? 1 : 0; + hcsplt_bm->split_en = (rh_speed == TUSB_SPEED_HIGH && bus_info.speed != TUSB_SPEED_HIGH) ? 1 : 0; - edpt->speed = devtree_info.speed; + edpt->speed = bus_info.speed; edpt->next_pid = HCTSIZ_PID_DATA0; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { edpt->uframe_interval = 1 << (desc_ep->bInterval - 1); - if (devtree_info.speed == TUSB_SPEED_FULL) { + if (bus_info.speed == TUSB_SPEED_FULL) { edpt->uframe_interval <<= 3; } } else if (desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) { - if (devtree_info.speed == TUSB_SPEED_HIGH) { + if (bus_info.speed == TUSB_SPEED_HIGH) { edpt->uframe_interval = 1 << (desc_ep->bInterval - 1); } else { edpt->uframe_interval = desc_ep->bInterval << 3; -- cgit v1.3.1 From a2da575793a14fdfc5137a02843af0fd8f8b772a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 23 Apr 2025 16:03:40 +0700 Subject: rename and expose tuh_bus_info_get() to application --- src/host/hcd.h | 10 ---------- src/host/usbh.c | 10 +++++----- src/host/usbh.h | 14 +++++++++++++- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 1 + src/portable/ehci/ehci.c | 3 ++- src/portable/mentor/musb/hcd_musb.c | 5 +++-- src/portable/nxp/khci/hcd_khci.c | 1 + src/portable/nxp/lpc17_40/hcd_lpc17_40.c | 1 + src/portable/ohci/ohci.c | 3 ++- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 2 +- src/portable/renesas/rusb2/hcd_rusb2.c | 3 ++- src/portable/synopsys/dwc2/dwc2_common.c | 1 + src/portable/synopsys/dwc2/hcd_dwc2.c | 3 ++- src/portable/template/hcd_template.c | 1 + 14 files changed, 35 insertions(+), 23 deletions(-) (limited to 'src') diff --git a/src/host/hcd.h b/src/host/hcd.h index 1f2704a10..d3551bf5b 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -90,13 +90,6 @@ typedef struct { }; } hcd_event_t; -typedef struct { - uint8_t rhport; - uint8_t hub_addr; - uint8_t hub_port; - uint8_t speed; -} tuh_bus_info_t; - //--------------------------------------------------------------------+ // Memory API //--------------------------------------------------------------------+ @@ -186,9 +179,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr); // USBH implemented API //--------------------------------------------------------------------+ -// Get device port information -extern bool hcd_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info); - // Called by HCD to notify stack extern void hcd_event_handler(hcd_event_t const* event, bool in_isr); diff --git a/src/host/usbh.c b/src/host/usbh.c index c063c97f9..0a208816c 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -28,9 +28,9 @@ #if CFG_TUH_ENABLED -#include "host/hcd.h" +#include "hcd.h" #include "tusb.h" -#include "host/usbh_pvt.h" +#include "usbh_pvt.h" #include "hub.h" //--------------------------------------------------------------------+ @@ -342,7 +342,7 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { tusb_speed_t tuh_speed_get(uint8_t daddr) { tuh_bus_info_t bus_info; - hcd_bus_info_get(daddr, &bus_info); + tuh_bus_info_get(daddr, &bus_info); return bus_info.speed; } @@ -875,7 +875,7 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { uint8_t usbh_get_rhport(uint8_t daddr) { tuh_bus_info_t bus_info; - hcd_bus_info_get(daddr, &bus_info); + tuh_bus_info_get(daddr, &bus_info); return bus_info.rhport; } @@ -1013,7 +1013,7 @@ bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //--------------------------------------------------------------------+ -bool hcd_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info) { +bool tuh_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info) { usbh_device_t const* dev = get_device(daddr); if (dev) { *bus_info = dev->bus_info; diff --git a/src/host/usbh.h b/src/host/usbh.h index 4829a8183..063b20539 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -47,7 +47,6 @@ // forward declaration struct tuh_xfer_s; typedef struct tuh_xfer_s tuh_xfer_t; - typedef void (*tuh_xfer_cb_t)(tuh_xfer_t* xfer); // Note1: layout and order of this will be changed in near future @@ -80,6 +79,14 @@ typedef struct { tusb_desc_interface_t desc; } tuh_itf_info_t; +typedef struct { + uint8_t rhport; + uint8_t hub_addr; + uint8_t hub_port; + uint8_t speed; +} tuh_bus_info_t; + + // ConfigID for tuh_configure() enum { TUH_CFGID_INVALID = 0, @@ -177,6 +184,8 @@ extern void hcd_int_handler(uint8_t rhport, bool in_isr); #define _tuh_int_handler_arg0() TU_VERIFY_STATIC(false, "tuh_int_handler() must have 1 or 2 arguments") #define _tuh_int_handler_arg1(_rhport) hcd_int_handler(_rhport, true) #define _tuh_int_handler_arg2(_rhport, _in_isr) hcd_int_handler(_rhport, _in_isr) + +// 1st argument is rhport (mandatory), 2nd argument in_isr (optional) #define tuh_int_handler(...) TU_FUNC_OPTIONAL_ARG(_tuh_int_handler, __VA_ARGS__) // Check if roothub port is initialized and active as a host @@ -214,6 +223,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_ready(uint8_t daddr) { return tuh_mounted(daddr) && !tuh_suspended(daddr); } +// Get bus information of device +bool tuh_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info); + //--------------------------------------------------------------------+ // Transfer API //--------------------------------------------------------------------+ diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index c4c342a70..22eb22690 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -35,6 +35,7 @@ //--------------------------------------------------------------------+ #include "common/tusb_common.h" #include "host/hcd.h" +#include "host/usbh.h" #include "portable/ehci/ehci_api.h" #include "ci_hs_type.h" diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 141a2c026..da9f49d29 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -34,6 +34,7 @@ #include "osal/osal.h" #include "host/hcd.h" +#include "host/usbh.h" #include "ehci_api.h" #include "ehci.h" @@ -838,7 +839,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c } tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); uint8_t const xfer_type = ep_desc->bmAttributes.xfer; uint8_t const interval = ep_desc->bInterval; diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 97ef46152..dcc023e0b 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -36,6 +36,7 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #endif #include "host/hcd.h" +#include "host/usbh.h" #include "musb_type.h" @@ -696,7 +697,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet _hcd.pipe0.remaining = 0; tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); switch (bus_info.speed) { default: return false; case TUSB_SPEED_LOW: USB0->TYPE0 = USB_TYPE0_SPEED_LOW; break; @@ -745,7 +746,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const uint8_t pipe_type = 0; tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); switch (bus_info.speed) { default: return false; case TUSB_SPEED_LOW: pipe_type |= USB_TXTYPE1_SPEED_LOW; break; diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index c3c901c5d..45732a866 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -36,6 +36,7 @@ #endif #include "host/hcd.h" +#include "host/usbh.h" //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c index 090d1ba69..fea3e2a66 100644 --- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c @@ -31,6 +31,7 @@ #include "chip.h" #include "host/hcd.h" +#include "host/usbh.h" void hcd_int_enable(uint8_t rhport) { diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index 465b6731c..81091c9a7 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -38,6 +38,7 @@ #include "osal/osal.h" #include "host/hcd.h" +#include "host/usbh.h" #include "ohci.h" // TODO remove @@ -329,7 +330,7 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t } tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); p_ed->dev_addr = dev_addr; p_ed->ep_number = ep_addr & 0x0F; diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 0e3d0d31a..d59a2b4ee 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -115,7 +115,7 @@ void hcd_int_disable(uint8_t rhport) { bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *desc_ep) { tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); bool const need_pre = (bus_info.hub_addr && bus_info.speed == TUSB_SPEED_LOW); uint8_t const pio_rhport = RHPORT_PIO(rhport); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index e6975287d..6f6d27d0e 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -30,6 +30,7 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_RUSB2) #include "host/hcd.h" +#include "host/usbh.h" #include "rusb2_type.h" #if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N) @@ -663,7 +664,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const if (0 == epn) { rusb->DCPCTR = RUSB2_PIPE_CTR_PID_NAK; tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &rusb->DEVADD[0]; devadd += dev_addr; while (rusb->DCPCTR_b.PBUSY) {} diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index f6ed8fc98..e1e7d5c1a 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -36,6 +36,7 @@ #if CFG_TUH_ENABLED #include "host/hcd.h" +#include "host/usbh.h" #endif #include "dwc2_common.h" diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 6fd343686..7c29a03cf 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -36,6 +36,7 @@ #define DWC2_DEBUG 2 #include "host/hcd.h" +#include "host/usbh.h" #include "dwc2_common.h" // Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX @@ -476,7 +477,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* const tusb_speed_t rh_speed = hprt_speed_get(dwc2); tuh_bus_info_t bus_info; - hcd_bus_info_get(dev_addr, &bus_info); + tuh_bus_info_get(dev_addr, &bus_info); // find a free endpoint const uint8_t ep_id = edpt_alloc(); diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index 22ea22e63..d2f304407 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -29,6 +29,7 @@ #if CFG_TUH_ENABLED && CFG_TUSB_MCU == OPT_MCU_NONE #include "host/hcd.h" +#include "host/usbh.h" //--------------------------------------------------------------------+ // Controller API -- cgit v1.3.1 From 9a1f690ec44dc7cc3e0dbb35e1db8ba89cd3de88 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 23 Apr 2025 16:50:58 +0700 Subject: move usbh ctrl_xfer into usbh_data --- src/host/usbh.c | 171 ++++++++++++++++++++++++++++---------------------------- 1 file changed, 86 insertions(+), 85 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 0a208816c..9cf07213b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -263,7 +263,7 @@ static osal_queue_t _usbh_q; // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. -static struct { +typedef struct { uint8_t* buffer; tuh_xfer_cb_t complete_cb; uintptr_t user_data; @@ -272,26 +272,25 @@ static struct { uint8_t daddr; volatile uint16_t actual_len; uint8_t failed_count; -} _ctrl_xfer; - -typedef struct { - TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request); - TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); -} usbh_epbuf_t; - -CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; +} usbh_ctrl_xfer_info_t; typedef struct { - uint8_t controller_id; // controller ID - uint8_t enumerating_daddr; // device address of the device being enumerated - - tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration + uint8_t controller_id; // controller ID + uint8_t enumerating_daddr; // device address of the device being enumerated + tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration + usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer } usbh_data_t; static usbh_data_t _usbh_data = { .controller_id = TUSB_INDEX_INVALID_8, }; +typedef struct { + TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request); + TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); +} usbh_epbuf_t; +CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; + //------------- Helper Function -------------// TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) { TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL); @@ -299,7 +298,7 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) } static bool enum_new_device(hcd_event_t* event); -static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); +static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); @@ -388,9 +387,9 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Init host stack if not already if (!tuh_inited()) { + TU_LOG_INT_USBH(sizeof(usbh_data_t)); TU_LOG_INT_USBH(sizeof(usbh_device_t)); TU_LOG_INT_USBH(sizeof(hcd_event_t)); - TU_LOG_INT_USBH(sizeof(_ctrl_xfer)); TU_LOG_INT_USBH(sizeof(tuh_xfer_t)); TU_LOG_INT_USBH(sizeof(tu_fifo_t)); TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t)); @@ -412,7 +411,6 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Device tu_memclr(_usbh_devices, sizeof(_usbh_devices)); - tu_memclr(&_ctrl_xfer, sizeof(_ctrl_xfer)); tu_memclr(&_usbh_data, sizeof(_usbh_data)); _usbh_data.controller_id = TUSB_INDEX_INVALID_8; @@ -451,7 +449,7 @@ bool tuh_deinit(uint8_t rhport) { _usbh_data.controller_id = TUSB_INDEX_INVALID_8; // "unplug" all devices on this rhport (hub_addr = 0, hub_port = 0) - process_removing_device(rhport, 0, 0); + process_removed_device(rhport, 0, 0); // deinit host stack if no controller is active if (!tuh_inited()) { @@ -545,7 +543,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { case HCD_EVENT_DEVICE_REMOVE: TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); - process_removing_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); + process_removed_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); #if CFG_TUH_HUB // TODO remove @@ -638,9 +636,9 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer) { } TU_ATTR_ALWAYS_INLINE static inline void _control_set_xfer_stage(uint8_t stage) { - if (_ctrl_xfer.stage != stage) { + if (_usbh_data.ctrl_xfer_info.stage != stage) { (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _ctrl_xfer.stage = stage; + _usbh_data.ctrl_xfer_info.stage = stage; (void) osal_mutex_unlock(_usbh_mutex); } } @@ -660,23 +658,22 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { const uint8_t daddr = xfer->daddr; TU_VERIFY(tuh_connected(daddr)); - // pre-check to help reducing mutex lock - TU_VERIFY(_ctrl_xfer.stage == CONTROL_STAGE_IDLE); - (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + usbh_ctrl_xfer_info_t* ctrl_info = &_usbh_data.ctrl_xfer_info; - bool const is_idle = (_ctrl_xfer.stage == CONTROL_STAGE_IDLE); + TU_VERIFY(ctrl_info->stage == CONTROL_STAGE_IDLE); // pre-check to help reducing mutex lock + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + bool const is_idle = (ctrl_info->stage == CONTROL_STAGE_IDLE); if (is_idle) { - _ctrl_xfer.stage = CONTROL_STAGE_SETUP; - _ctrl_xfer.daddr = daddr; - _ctrl_xfer.actual_len = 0; - _ctrl_xfer.failed_count = 0; - - _ctrl_xfer.buffer = xfer->buffer; - _ctrl_xfer.complete_cb = xfer->complete_cb; - _ctrl_xfer.user_data = xfer->user_data; + ctrl_info->stage = CONTROL_STAGE_SETUP; + ctrl_info->daddr = daddr; + ctrl_info->actual_len = 0; + ctrl_info->failed_count = 0; + + ctrl_info->buffer = xfer->buffer; + ctrl_info->complete_cb = xfer->complete_cb; + ctrl_info->user_data = xfer->user_data; _usbh_epbuf.request = (*xfer->setup); } - (void) osal_mutex_unlock(_usbh_mutex); TU_VERIFY(is_idle); @@ -693,8 +690,8 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { volatile xfer_result_t result = XFER_RESULT_INVALID; // use user_data to point to xfer_result_t - _ctrl_xfer.user_data = (uintptr_t) &result; - _ctrl_xfer.complete_cb = _control_blocking_complete_cb; + ctrl_info->user_data = (uintptr_t) &result; + ctrl_info->complete_cb = _control_blocking_complete_cb; TU_ASSERT(usbh_setup_send(daddr, (uint8_t const *) &_usbh_epbuf.request)); @@ -712,7 +709,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { *((xfer_result_t*) xfer->user_data) = result; } xfer->result = result; - xfer->actual_len = _ctrl_xfer.actual_len; + xfer->actual_len = ctrl_info->actual_len; } return true; @@ -720,6 +717,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); + usbh_ctrl_xfer_info_t* ctrl_info = &_usbh_data.ctrl_xfer_info; // duplicate xfer since user can execute control transfer within callback tusb_control_request_t const request = _usbh_epbuf.request; @@ -728,10 +726,10 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { .ep_addr = 0, .result = result, .setup = &request, - .actual_len = (uint32_t) _ctrl_xfer.actual_len, - .buffer = _ctrl_xfer.buffer, - .complete_cb = _ctrl_xfer.complete_cb, - .user_data = _ctrl_xfer.user_data + .actual_len = (uint32_t) ctrl_info->actual_len, + .buffer = ctrl_info->buffer, + .complete_cb = ctrl_info->complete_cb, + .user_data = ctrl_info->user_data }; _control_set_xfer_stage(CONTROL_STAGE_IDLE); @@ -746,6 +744,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t const uint8_t rhport = usbh_get_rhport(daddr); tusb_control_request_t const * request = &_usbh_epbuf.request; + usbh_ctrl_xfer_info_t* ctrl_info = &_usbh_data.ctrl_xfer_info; switch (result) { case XFER_RESULT_STALLED: @@ -755,12 +754,12 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t break; case XFER_RESULT_FAILED: - if (tuh_connected(daddr) && _ctrl_xfer.failed_count < USBH_CONTROL_RETRY_MAX) { - TU_LOG_USBH("[%u:%u] Control FAILED %u/%u, retrying\r\n", rhport, daddr, _ctrl_xfer.failed_count+1, USBH_CONTROL_RETRY_MAX); + if (tuh_connected(daddr) && ctrl_info->failed_count < USBH_CONTROL_RETRY_MAX) { + TU_LOG_USBH("[%u:%u] Control FAILED %u/%u, retrying\r\n", rhport, daddr, ctrl_info->failed_count+1, USBH_CONTROL_RETRY_MAX); (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _ctrl_xfer.stage = CONTROL_STAGE_SETUP; - _ctrl_xfer.failed_count++; - _ctrl_xfer.actual_len = 0; // reset actual_len + ctrl_info->stage = CONTROL_STAGE_SETUP; + ctrl_info->failed_count++; + ctrl_info->actual_len = 0; // reset actual_len (void) osal_mutex_unlock(_usbh_mutex); TU_ASSERT(usbh_setup_send(daddr, (uint8_t const *) request)); @@ -772,28 +771,29 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t break; case XFER_RESULT_SUCCESS: - switch(_ctrl_xfer.stage) { + switch(ctrl_info->stage) { case CONTROL_STAGE_SETUP: if (request->wLength) { // DATA stage: initial data toggle is always 1 _control_set_xfer_stage(CONTROL_STAGE_DATA); - TU_ASSERT(hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength)); + const uint8_t ep_data = tu_edpt_addr(0, request->bmRequestType_bit.direction); + TU_ASSERT(hcd_edpt_xfer(rhport, daddr, ep_data, ctrl_info->buffer, request->wLength)); return true; } - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; case CONTROL_STAGE_DATA: if (request->wLength) { TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr); - TU_LOG_MEM_USBH(_ctrl_xfer.buffer, xferred_bytes, 2); + TU_LOG_MEM_USBH(ctrl_info->buffer, xferred_bytes, 2); } + ctrl_info->actual_len = (uint16_t) xferred_bytes; - _ctrl_xfer.actual_len = (uint16_t) xferred_bytes; - - // ACK stage: toggle is always 1 - _control_set_xfer_stage(CONTROL_STAGE_ACK); - TU_ASSERT( hcd_edpt_xfer(rhport, daddr, tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction), NULL, 0) ); - break; + // ACK stage: toggle is always 1 + _control_set_xfer_stage(CONTROL_STAGE_ACK); + const uint8_t ep_status = tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction); + TU_ASSERT(hcd_edpt_xfer(rhport, daddr, ep_status, NULL, 0)); + break; case CONTROL_STAGE_ACK: { // Abort all pending transfers if SET_CONFIGURATION request @@ -842,16 +842,16 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer) { bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr); - const uint8_t epnum = tu_edpt_number(ep_addr); const uint8_t dir = tu_edpt_dir(ep_addr); if (epnum == 0) { - // Also include dev0_bus for aborting enumerating + // Also include dev0 for aborting enumerating const uint8_t rhport = usbh_get_rhport(daddr); // control transfer: only 1 control at a time, check if we are aborting the current one - TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE); + const usbh_ctrl_xfer_info_t* ctrl_info = &_usbh_data.ctrl_xfer_info; + TU_VERIFY(daddr == ctrl_info->daddr && ctrl_info->stage != CONTROL_STAGE_IDLE); hcd_edpt_abort_xfer(rhport, daddr, ep_addr); _control_set_xfer_stage(CONTROL_STAGE_IDLE); // reset control transfer state to idle } else { @@ -859,9 +859,8 @@ bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { TU_VERIFY(dev); TU_VERIFY(dev->ep_status[epnum][dir].busy); // non-control skip if not busy + // abort then mark as ready and release endpoint hcd_edpt_abort_xfer(dev->bus_info.rhport, daddr, ep_addr); - - // mark as ready and release endpoint if transfer is aborted dev->ep_status[epnum][dir].busy = false; tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex); } @@ -1252,16 +1251,18 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { } // a device unplugged from rhport:hub_addr:hub_port -static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { - // dev0_bus is unplugged - if ((_usbh_data.enumerating_daddr == 0) && (rhport == _usbh_data.dev0_bus.rhport) && - (hub_addr == _usbh_data.dev0_bus.hub_addr) && (hub_port == _usbh_data.dev0_bus.hub_port)) { - hcd_device_close(_usbh_data.dev0_bus.rhport, 0); - if (_ctrl_xfer.daddr == 0) { - _control_set_xfer_stage(CONTROL_STAGE_IDLE); +static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { + // if dev0 is unplugged while enumerating (not yet assigned an address) + if (_usbh_data.enumerating_daddr == 0) { + const tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; + if ((rhport == dev0_bus->rhport) && (hub_addr == dev0_bus->hub_addr) && (hub_port == dev0_bus->hub_port)) { + hcd_device_close(dev0_bus->rhport, 0); + if (_usbh_data.ctrl_xfer_info.daddr == 0) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + return; } - _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; - return; } //------------- find the all devices (star-network) under port that is unplugged -------------// @@ -1298,8 +1299,8 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu hcd_device_close(rhport, daddr); clear_device(dev); - // abort on-going control xfer on this device if any - if (daddr == _ctrl_xfer.daddr) { + // abort ongoing control xfer on this device if any + if (daddr == _usbh_data.ctrl_xfer_info.daddr) { _control_set_xfer_stage(CONTROL_STAGE_IDLE); } @@ -1651,45 +1652,45 @@ static void process_enumeration(tuh_xfer_t* xfer) { } static bool enum_new_device(hcd_event_t* event) { - _usbh_data.dev0_bus.rhport = event->rhport; - _usbh_data.dev0_bus.hub_addr = event->connection.hub_addr; - _usbh_data.dev0_bus.hub_port = event->connection.hub_port; + tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; + dev0_bus->rhport = event->rhport; + dev0_bus->hub_addr = event->connection.hub_addr; + dev0_bus->hub_port = event->connection.hub_port; - if (_usbh_data.dev0_bus.hub_addr == 0) { + if (dev0_bus->hub_addr == 0) { // connected directly to roothub // wait until device connection is stable TODO non blocking tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); - // device unplugged while delaying - if (!hcd_port_connect_status(_usbh_data.dev0_bus.rhport)) { + if (!hcd_port_connect_status(dev0_bus->rhport)) { + TU_LOG_USBH("Device unplugged while debouncing\r\n"); enum_full_complete(); return true; } - hcd_port_reset(_usbh_data.dev0_bus.rhport); // reset device + hcd_port_reset(dev0_bus->rhport); // reset device // Since we are in middle of rhport reset, frame number is not available yet. - // need to depend on tusb_time_millis_api() + // need to depend on tusb_time_millis_api() TODO non blocking tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - hcd_port_reset_end(_usbh_data.dev0_bus.rhport); + hcd_port_reset_end(dev0_bus->rhport); // device unplugged while delaying - if (!hcd_port_connect_status(_usbh_data.dev0_bus.rhport)) { + if (!hcd_port_connect_status(dev0_bus->rhport)) { enum_full_complete(); return true; } - _usbh_data.dev0_bus.speed = hcd_port_speed_get(_usbh_data.dev0_bus.rhport); - TU_LOG_USBH("%s Speed\r\n", tu_str_speed[_usbh_data.dev0.speed]); + dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport); + TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]); // fake transfer to kick-off the enumeration process tuh_xfer_t xfer; xfer.daddr = 0; xfer.result = XFER_RESULT_SUCCESS; xfer.user_data = ENUM_ADDR0_DEVICE_DESC; - process_enumeration(&xfer); } #if CFG_TUH_HUB @@ -1699,7 +1700,7 @@ static bool enum_new_device(hcd_event_t* event) { tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // ENUM_HUB_GET_STATUS - TU_ASSERT(hub_port_get_status(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, _usbh_epbuf.ctrl, + TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } #endif // hub -- cgit v1.3.1 From 89f8d0cffbe259baed3163a22a42390c21ba1f53 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Apr 2025 10:41:00 +0700 Subject: add tuh_address_set() API minor rename and move code around --- src/host/usbh.c | 160 ++++++++++++++++++++++++++++---------------------------- src/host/usbh.h | 4 ++ 2 files changed, 83 insertions(+), 81 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 9cf07213b..f4a6e1697 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -105,13 +105,11 @@ typedef struct { // Device Descriptor uint8_t ep0_size; - - uint16_t vid; - uint16_t pid; - - uint8_t i_manufacturer; - uint8_t i_product; - uint8_t i_serial; + uint16_t idVendor; + uint16_t idProduct; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; uint8_t bNumConfigurations; // Configuration Descriptor @@ -331,10 +329,10 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { *vid = *pid = 0; usbh_device_t const *dev = get_device(dev_addr); - TU_VERIFY(dev && dev->addressed && dev->vid != 0); + TU_VERIFY(dev && dev->addressed && dev->idVendor != 0); - *vid = dev->vid; - *pid = dev->pid; + *vid = dev->idVendor; + *pid = dev->idProduct; return true; } @@ -1094,24 +1092,24 @@ bool tuh_descriptor_get_manufacturer_string(uint8_t daddr, uint16_t language_id, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->i_manufacturer); - return tuh_descriptor_get_string(daddr, dev->i_manufacturer, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->iManufacturer); + return tuh_descriptor_get_string(daddr, dev->iManufacturer, language_id, buffer, len, complete_cb, user_data); } // Get product string descriptor bool tuh_descriptor_get_product_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->i_product); - return tuh_descriptor_get_string(daddr, dev->i_product, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->iProduct); + return tuh_descriptor_get_string(daddr, dev->iProduct, language_id, buffer, len, complete_cb, user_data); } // Get serial string descriptor bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { usbh_device_t const* dev = get_device(daddr); - TU_VERIFY(dev && dev->i_serial); - return tuh_descriptor_get_string(daddr, dev->i_serial, language_id, buffer, len, complete_cb, user_data); + TU_VERIFY(dev && dev->iSerialNumber); + return tuh_descriptor_get_string(daddr, dev->iSerialNumber, language_id, buffer, len, complete_cb, user_data); } // Get HID report descriptor @@ -1142,6 +1140,33 @@ bool tuh_descriptor_get_hid_report(uint8_t daddr, uint8_t itf_num, uint8_t desc_ return tuh_control_xfer(&xfer); } +bool tuh_address_set(uint8_t daddr, uint8_t new_addr, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + TU_LOG_USBH("Set Address = %d\r\n", new_addr); + const tusb_control_request_t request = { + .bmRequestType_bit = { + .recipient = TUSB_REQ_RCPT_DEVICE, + .type = TUSB_REQ_TYPE_STANDARD, + .direction = TUSB_DIR_OUT + }, + .bRequest = TUSB_REQ_SET_ADDRESS, + .wValue = tu_htole16(new_addr), + .wIndex = 0, + .wLength = 0 + }; + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = 0, + .setup = &request, + .buffer = NULL, + .complete_cb = complete_cb, + .user_data = user_data + }; + + TU_ASSERT(tuh_control_xfer(&xfer)); + return true; +} + bool tuh_configuration_set(uint8_t daddr, uint8_t config_num, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_LOG_USBH("Set Configuration = %d\r\n", config_num); @@ -1373,7 +1398,7 @@ enum { ENUM_CONFIG_DRIVER }; -static bool enum_request_set_addr(tusb_desc_device_t const* desc_device); +static uint8_t enum_get_new_address(bool is_hub); static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg); static void enum_full_complete(void); @@ -1425,7 +1450,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { } _usbh_data.dev0_bus.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : - (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; + (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; // Acknowledge Port Reset Change if (port_status.change.reset) { @@ -1466,9 +1491,19 @@ static void process_enumeration(tuh_xfer_t* xfer) { break; } - case ENUM_SET_ADDR: - enum_request_set_addr((tusb_desc_device_t*) _usbh_epbuf.ctrl); + case ENUM_SET_ADDR: { + const tusb_desc_device_t *desc_device = (const tusb_desc_device_t *) _usbh_epbuf.ctrl; + const uint8_t new_addr = enum_get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); + TU_ASSERT(new_addr != 0,); + + usbh_device_t* new_dev = get_device(new_addr); + new_dev->bus_info = _usbh_data.dev0_bus; + new_dev->connected = 1; + new_dev->ep0_size = desc_device->bMaxPacketSize0; + + TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC),); break; + } case ENUM_GET_DEVICE_DESC: { // Allow 2ms for address recovery time, Ref USB Spec 9.2.6.3 @@ -1495,11 +1530,11 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_GET_STRING_LANGUAGE_ID_LEN: { // save the received device descriptor tusb_desc_device_t const *desc_device = (tusb_desc_device_t const *) _usbh_epbuf.ctrl; - dev->vid = desc_device->idVendor; - dev->pid = desc_device->idProduct; - dev->i_manufacturer = desc_device->iManufacturer; - dev->i_product = desc_device->iProduct; - dev->i_serial = desc_device->iSerialNumber; + dev->idVendor = desc_device->idVendor; + dev->idProduct = desc_device->idProduct; + dev->iManufacturer = desc_device->iManufacturer; + dev->iProduct = desc_device->iProduct; + dev->iSerialNumber = desc_device->iSerialNumber; dev->bNumConfigurations = desc_device->bNumConfigurations; tuh_enum_descriptor_device_cb(daddr, desc_device); // callback @@ -1520,8 +1555,8 @@ static void process_enumeration(tuh_xfer_t* xfer) { if (desc_langid->bLength >= 4) { langid = tu_le16toh(desc_langid->utf16le[0]); // previous request is langid } - if (dev->i_manufacturer != 0) { - tuh_descriptor_get_string(daddr, dev->i_manufacturer, langid, _usbh_epbuf.ctrl, 2, + if (dev->iManufacturer != 0) { + tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_MANUFACTURER); break; }else { @@ -1530,10 +1565,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_MANUFACTURER: { - if (dev->i_manufacturer != 0) { + if (dev->iManufacturer != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->i_manufacturer, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->iManufacturer, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_STRING_PRODUCT_LEN); break; } else { @@ -1542,11 +1577,11 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_PRODUCT_LEN: - if (dev->i_product != 0) { + if (dev->iProduct != 0) { if (state == ENUM_GET_STRING_PRODUCT_LEN) { langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through } - tuh_descriptor_get_string(daddr, dev->i_product, langid, _usbh_epbuf.ctrl, 2, + tuh_descriptor_get_string(daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_PRODUCT); break; } else { @@ -1554,10 +1589,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_PRODUCT: { - if (dev->i_product != 0) { + if (dev->iProduct != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->i_product, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->iProduct, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_STRING_SERIAL_LEN); break; } else { @@ -1566,11 +1601,11 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_SERIAL_LEN: - if (dev->i_serial != 0) { + if (dev->iSerialNumber != 0) { if (state == ENUM_GET_STRING_SERIAL_LEN) { langid = tu_le16toh(xfer->setup->wIndex); // get langid from previous setup packet if not fall through } - tuh_descriptor_get_string(daddr, dev->i_serial, langid, _usbh_epbuf.ctrl, 2, + tuh_descriptor_get_string(daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, 2, process_enumeration, ENUM_GET_STRING_SERIAL); break; } else { @@ -1578,10 +1613,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_STRING_SERIAL: { - if (dev->i_serial != 0) { + if (dev->iSerialNumber != 0) { langid = tu_le16toh(xfer->setup->wIndex); // langid from length's request const uint8_t str_len = xfer->buffer[0]; - tuh_descriptor_get_string(daddr, dev->i_serial, langid, _usbh_epbuf.ctrl, str_len, + tuh_descriptor_get_string(daddr, dev->iSerialNumber, langid, _usbh_epbuf.ctrl, str_len, process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC); break; } else { @@ -1657,12 +1692,12 @@ static bool enum_new_device(hcd_event_t* event) { dev0_bus->hub_addr = event->connection.hub_addr; dev0_bus->hub_port = event->connection.hub_port; + // wait until device connection is stable TODO non blocking + tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); + if (dev0_bus->hub_addr == 0) { // connected directly to roothub - // wait until device connection is stable TODO non blocking - tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); - if (!hcd_port_connect_status(dev0_bus->rhport)) { TU_LOG_USBH("Device unplugged while debouncing\r\n"); enum_full_complete(); @@ -1696,10 +1731,6 @@ static bool enum_new_device(hcd_event_t* event) { #if CFG_TUH_HUB else { // connected via external hub - // wait until device connection is stable TODO non blocking - tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); - - // ENUM_HUB_GET_STATUS TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } @@ -1708,7 +1739,7 @@ static bool enum_new_device(hcd_event_t* event) { return true; } -static uint8_t get_new_address(bool is_hub) { +static uint8_t enum_get_new_address(bool is_hub) { uint8_t start; uint8_t end; @@ -1721,47 +1752,14 @@ static uint8_t get_new_address(bool is_hub) { } for (uint8_t idx = start; idx < end; idx++) { - if (!_usbh_devices[idx].connected) return (idx+1); + if (!_usbh_devices[idx].connected) { + return (idx + 1); + } } return 0; // invalid address } -static bool enum_request_set_addr(tusb_desc_device_t const* desc_device) { - // Get new address - uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); - TU_ASSERT(new_addr != 0); - TU_LOG_USBH("Set Address = %d\r\n", new_addr); - - usbh_device_t* new_dev = get_device(new_addr); - new_dev->bus_info = _usbh_data.dev0_bus; - new_dev->connected = 1; - new_dev->ep0_size = desc_device->bMaxPacketSize0; - - tusb_control_request_t const request = { - .bmRequestType_bit = { - .recipient = TUSB_REQ_RCPT_DEVICE, - .type = TUSB_REQ_TYPE_STANDARD, - .direction = TUSB_DIR_OUT - }, - .bRequest = TUSB_REQ_SET_ADDRESS, - .wValue = tu_htole16(new_addr), - .wIndex = 0, - .wLength = 0 - }; - tuh_xfer_t xfer = { - .daddr = 0, - .ep_addr = 0, - .setup = &request, - .buffer = NULL, - .complete_cb = process_enumeration, - .user_data = ENUM_GET_DEVICE_DESC - }; - - TU_ASSERT(tuh_control_xfer(&xfer)); - return true; -} - static bool enum_parse_configuration_desc(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) { usbh_device_t* dev = get_device(dev_addr); uint16_t const total_len = tu_le16toh(desc_cfg->wTotalLength); diff --git a/src/host/usbh.h b/src/host/usbh.h index 063b20539..6f09f0c80 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -250,6 +250,10 @@ bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr); // Return true if a queued transfer is aborted, false if there is no transfer to abort bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); +// Set Address (control transfer) +bool tuh_address_set(uint8_t daddr, uint8_t new_addr, + tuh_xfer_cb_t complete_cb, uintptr_t user_data); + // Set Configuration (control transfer) // config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1 // true on success, false if there is on-going control transfer or incorrect parameters -- cgit v1.3.1 From 0f784e8a072d30aaa6f4c6ef0a8f22a085ea2516 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Apr 2025 17:59:45 +0700 Subject: refactor hub driver and move port reset on connection change to usbh. hub: add hub_port_get_status_local(), ignore resp in hub_port_get_status(pot != 0) usbh properly deboucning with hub/rootport accordingly to usb specs, also add 10ms of reset recovery --- src/host/hub.c | 226 ++++++++++++++++++++++++++++---------------------------- src/host/hub.h | 8 +- src/host/usbh.c | 208 +++++++++++++++++++++++++-------------------------- 3 files changed, 223 insertions(+), 219 deletions(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index 61efa8ba5..c87289a14 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -57,9 +57,11 @@ typedef struct { TUH_EPBUF_DEF(ctrl_buf, CFG_TUH_HUB_BUFSIZE); } hub_epbuf_t; +static tuh_xfer_cb_t user_complete_cb = NULL; static hub_interface_t hub_itfs[CFG_TUH_HUB]; CFG_TUH_MEM_SECTION static hub_epbuf_t hub_epbufs[CFG_TUH_HUB]; + TU_ATTR_ALWAYS_INLINE static inline hub_interface_t* get_hub_itf(uint8_t daddr) { return &hub_itfs[daddr-1-CFG_TUH_DEVICE_MAX]; } @@ -142,10 +144,23 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, }; TU_LOG_DRV("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port); - TU_ASSERT( tuh_control_xfer(&xfer) ); + TU_ASSERT(tuh_control_xfer(&xfer)); return true; } +static void port_get_status_complete (tuh_xfer_t* xfer) { + if (xfer->result == XFER_RESULT_SUCCESS) { + hub_interface_t* p_hub = get_hub_itf(xfer->daddr); + p_hub->port_status = *((const hub_port_status_response_t *) (uintptr_t) xfer->buffer); + } + + xfer->complete_cb = user_complete_cb; + user_complete_cb = NULL; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { @@ -169,8 +184,26 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, .user_data = user_data }; + if (hub_port != 0) { + // intercept complete callback to save port status, ignore resp + hub_epbuf_t* p_epbuf = get_hub_epbuf(hub_addr); + xfer.complete_cb = port_get_status_complete; + xfer.buffer = p_epbuf->ctrl_buf; + user_complete_cb = complete_cb; + } else { + user_complete_cb = NULL; + } + TU_LOG_DRV("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port); - TU_VERIFY( tuh_control_xfer(&xfer) ); + TU_VERIFY(tuh_control_xfer(&xfer)); + return true; +} + +bool hub_port_get_status_local(uint8_t hub_addr, uint8_t hub_port, hub_port_status_response_t* resp) { + (void) hub_port; + TU_VERIFY(hub_addr > CFG_TUH_DEVICE_MAX); + hub_interface_t* p_hub = get_hub_itf(hub_addr); + *resp = p_hub->port_status; return true; } @@ -238,10 +271,10 @@ bool hub_edpt_status_xfer(uint8_t daddr) { static void config_set_port_power (tuh_xfer_t* xfer); static void config_port_power_complete (tuh_xfer_t* xfer); -bool hub_set_config(uint8_t dev_addr, uint8_t itf_num) { - hub_interface_t* p_hub = get_hub_itf(dev_addr); +bool hub_set_config(uint8_t daddr, uint8_t itf_num) { + hub_interface_t* p_hub = get_hub_itf(daddr); TU_ASSERT(itf_num == p_hub->itf_num); - hub_epbuf_t* p_epbuf = get_hub_epbuf(dev_addr); + hub_epbuf_t* p_epbuf = get_hub_epbuf(daddr); // Get Hub Descriptor tusb_control_request_t const request = { @@ -257,7 +290,7 @@ bool hub_set_config(uint8_t dev_addr, uint8_t itf_num) { }; tuh_xfer_t xfer = { - .daddr = dev_addr, + .daddr = daddr, .ep_addr = 0, .setup = &request, .buffer = p_epbuf->ctrl_buf, @@ -312,11 +345,15 @@ static void config_port_power_complete (tuh_xfer_t* xfer) { //--------------------------------------------------------------------+ // Connection Changes //--------------------------------------------------------------------+ -static void get_status_complete (tuh_xfer_t* xfer); -static void port_get_status_complete (tuh_xfer_t* xfer); -static void port_clear_feature_complete_stub(tuh_xfer_t* xfer); -static void connection_clear_conn_change_complete (tuh_xfer_t* xfer); -static void connection_port_reset_complete (tuh_xfer_t* xfer); +enum { + STATE_IDLE = 0, + STATE_HUB_STATUS, + STATE_CLEAR_CHANGE, + STATE_CHECK_CONN, + STATE_COMPLETE +}; + +static void process_new_status(tuh_xfer_t* xfer); // callback as response of interrupt endpoint polling bool hub_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { @@ -337,12 +374,12 @@ bool hub_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t processed = false; } else if (tu_bit_test(status_change, 0)) { // Hub bit 0 is for the hub device events - processed = hub_get_status(daddr, p_epbuf->ctrl_buf, get_status_complete, 0); + processed = hub_get_status(daddr, p_epbuf->ctrl_buf, process_new_status, STATE_HUB_STATUS); } else { // Hub bits 1 to n are hub port events for (uint8_t port=1; port <= p_hub->bNbrPorts; port++) { if (tu_bit_test(status_change, port)) { - processed = hub_port_get_status(daddr, port, p_epbuf->ctrl_buf, port_get_status_complete, 0); + processed = hub_port_get_status(daddr, port, NULL, process_new_status, STATE_CLEAR_CHANGE); break; // after completely processed one port, we will re-queue the status poll and handle next one } } @@ -358,117 +395,84 @@ bool hub_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t return true; } -static void port_clear_feature_complete_stub(tuh_xfer_t* xfer) { - hub_edpt_status_xfer(xfer->daddr); -} - -static void get_status_complete(tuh_xfer_t *xfer) { +static void process_new_status(tuh_xfer_t* xfer) { const uint8_t daddr = xfer->daddr; - bool processed = false; // true if new status is processed - if (xfer->result == XFER_RESULT_SUCCESS) { - hub_status_response_t hub_status = *((const hub_status_response_t *) (uintptr_t) xfer->buffer); - - TU_LOG_DRV("HUB Got hub status, addr = %u, status = %04x\r\n", daddr, hub_status.change.value); - - if (hub_status.change.local_power_source) { - TU_LOG_DRV(" Local Power Change\r\n"); - processed = hub_clear_feature(daddr, HUB_FEATURE_HUB_LOCAL_POWER_CHANGE, port_clear_feature_complete_stub, 0); - } else if (hub_status.change.over_current) { - TU_LOG_DRV(" Over Current\r\n"); - processed = hub_clear_feature(daddr, HUB_FEATURE_HUB_OVER_CURRENT_CHANGE, port_clear_feature_complete_stub, 0); - } - } - - if (!processed) { - TU_ASSERT(hub_edpt_status_xfer(daddr), ); + if (xfer->result != XFER_RESULT_SUCCESS) { + TU_ASSERT(hub_edpt_status_xfer(daddr),); + return; } -} -static void port_get_status_complete(tuh_xfer_t *xfer) { - const uint8_t daddr = xfer->daddr; + const uint8_t port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + hub_interface_t *p_hub = get_hub_itf(daddr); + const uintptr_t state = xfer->user_data; bool processed = false; // true if new status is processed - if (xfer->result == XFER_RESULT_SUCCESS) { - const uint8_t port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - hub_interface_t *p_hub = get_hub_itf(daddr); - p_hub->port_status = *((const hub_port_status_response_t *) (uintptr_t) xfer->buffer); - - // Clear port status change interrupts - if (p_hub->port_status.change.connection) { - // Connection change - // Port is powered and enabled - //TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, ); - - // Acknowledge Port Connection Change - processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete, 0); - } else if (p_hub->port_status.change.port_enable) { - processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_ENABLE_CHANGE, port_clear_feature_complete_stub, 0); - } else if (p_hub->port_status.change.suspend) { - processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_SUSPEND_CHANGE, port_clear_feature_complete_stub, 0); - } else if (p_hub->port_status.change.over_current) { - processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_OVER_CURRENT_CHANGE, port_clear_feature_complete_stub, 0); - } else if (p_hub->port_status.change.reset) { - processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_RESET_CHANGE, port_clear_feature_complete_stub, 0); + switch (state) { + case STATE_HUB_STATUS: { + hub_status_response_t hub_status = *((const hub_status_response_t *) (uintptr_t) xfer->buffer); + TU_LOG_DRV("HUB Got hub status, addr = %u, status = %04x\r\n", daddr, hub_status.change.value); + if (hub_status.change.local_power_source) { + TU_LOG_DRV(" Local Power Change\r\n"); + processed = hub_clear_feature(daddr, HUB_FEATURE_HUB_LOCAL_POWER_CHANGE, + process_new_status, STATE_COMPLETE); + } else if (hub_status.change.over_current) { + TU_LOG_DRV(" Over Current\r\n"); + processed = hub_clear_feature(daddr, HUB_FEATURE_HUB_OVER_CURRENT_CHANGE, + process_new_status, STATE_COMPLETE); + } + break; } - } - if (!processed) { - TU_ASSERT(hub_edpt_status_xfer(daddr), ); - } -} - -static void connection_clear_conn_change_complete (tuh_xfer_t* xfer) { - const uint8_t daddr = xfer->daddr; - - if (xfer->result != XFER_RESULT_SUCCESS) { - TU_ASSERT(hub_edpt_status_xfer(daddr), ); - return; - } + case STATE_CLEAR_CHANGE: + // Get port status complete --> clear change + if (p_hub->port_status.change.connection) { + // Connection change + // Port is powered and enabled + //TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, ); + + // Acknowledge Port Connection Change + processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, + process_new_status, STATE_CHECK_CONN); + } else if (p_hub->port_status.change.port_enable) { + processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_ENABLE_CHANGE, + process_new_status, STATE_COMPLETE); + } else if (p_hub->port_status.change.suspend) { + processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_SUSPEND_CHANGE, + process_new_status, STATE_COMPLETE); + } else if (p_hub->port_status.change.over_current) { + processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_OVER_CURRENT_CHANGE, + process_new_status, STATE_COMPLETE); + } else if (p_hub->port_status.change.reset) { + processed = hub_port_clear_feature(daddr, port_num, HUB_FEATURE_PORT_RESET_CHANGE, + process_new_status, STATE_COMPLETE); + } + break; + + case STATE_CHECK_CONN: { + const hcd_event_t event = { + .rhport = usbh_get_rhport(daddr), + .event_id = p_hub->port_status.status.connection ? HCD_EVENT_DEVICE_ATTACH : HCD_EVENT_DEVICE_REMOVE, + .connection = { + .hub_addr = daddr, + .hub_port = port_num + } + }; + hcd_event_handler(&event, false); + processed = true; // usbh queue status after handled this in (de)enumeration + break; + } - hub_interface_t *p_hub = get_hub_itf(daddr); - const uint8_t port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + case STATE_COMPLETE: + default: + processed = false; // complete this status, queue next status + break; - if (p_hub->port_status.status.connection) { - // Reset port if attach event - hub_port_reset(daddr, port_num, connection_port_reset_complete, 0); - } else { - // submit detach event - const hcd_event_t event = { - .rhport = usbh_get_rhport(daddr), - .event_id = HCD_EVENT_DEVICE_REMOVE, - .connection = { - .hub_addr = daddr, - .hub_port = port_num - } - }; - hcd_event_handler(&event, false); } -} - -static void connection_port_reset_complete (tuh_xfer_t* xfer) { - const uint8_t daddr = xfer->daddr; - if (xfer->result != XFER_RESULT_SUCCESS) { - // retry port reset if failed - if (!tuh_control_xfer(xfer)) { - TU_ASSERT(hub_edpt_status_xfer(daddr), ); // back to status poll if failed to queue request - } - return; + if (!processed) { + TU_ASSERT(hub_edpt_status_xfer(daddr),); } - - const uint8_t port_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - - // submit attach event - hcd_event_t event = { - .rhport = usbh_get_rhport(daddr), - .event_id = HCD_EVENT_DEVICE_ATTACH, - .connection = { - .hub_addr = daddr, - .hub_port = port_num - } - }; - hcd_event_handler(&event, false); } #endif diff --git a/src/host/hub.h b/src/host/hub.h index e4e576661..3587f0ee3 100644 --- a/src/host/hub.h +++ b/src/host/hub.h @@ -170,9 +170,13 @@ bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Get port status +// If hub_port != 0, resp is ignored. hub_port_get_status_local() can be used to retrieve the status bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void *resp, tuh_xfer_cb_t complete_cb, uintptr_t user_data); +// Get port status from local cache. This does not send a request to the device +bool hub_port_get_status_local(uint8_t hub_addr, uint8_t hub_port, hub_port_status_response_t* resp); + // Get status from Interrupt endpoint bool hub_edpt_status_xfer(uint8_t daddr); @@ -188,7 +192,7 @@ bool hub_port_clear_reset_change(uint8_t hub_addr, uint8_t hub_port, tuh_xfer_cb return hub_port_clear_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET_CHANGE, complete_cb, user_data); } -// Get Hub status +// Get Hub status (port = 0) TU_ATTR_ALWAYS_INLINE static inline bool hub_get_status(uint8_t hub_addr, void* resp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return hub_port_get_status(hub_addr, 0, resp, complete_cb, user_data); @@ -205,7 +209,7 @@ bool hub_clear_feature(uint8_t hub_addr, uint8_t feature, tuh_xfer_cb_t complete bool hub_init (void); bool hub_deinit (void); bool hub_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len); -bool hub_set_config (uint8_t dev_addr, uint8_t itf_num); +bool hub_set_config (uint8_t daddr, uint8_t itf_num); bool hub_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); void hub_close (uint8_t dev_addr); diff --git a/src/host/usbh.c b/src/host/usbh.c index f4a6e1697..94a1fa247 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -360,7 +360,6 @@ bool tuh_rhport_reset_bus(uint8_t rhport, bool active) { //--------------------------------------------------------------------+ // PUBLIC API (Parameter Verification is required) //--------------------------------------------------------------------+ - bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) { return hcd_configure(rhport, cfg_id, cfg_param); } @@ -534,7 +533,6 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { } } else { TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport); - _usbh_data.enumerating_daddr = 0; enum_new_device(&event); } break; @@ -1022,9 +1020,11 @@ bool tuh_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info) { TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) { switch (event->event_id) { + case HCD_EVENT_DEVICE_ATTACH: + + break; + case HCD_EVENT_DEVICE_REMOVE: - // FIXME device remove from a hub need an HCD API for hcd to free up endpoint - // mark device as removing to prevent further xfer before the event is processed in usbh task break; default: break; @@ -1228,8 +1228,7 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \ return (uint8_t) result -uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len); } @@ -1237,33 +1236,27 @@ uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len); } -uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len); } -uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len); } -uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len); } -uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len); } -uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len); } -uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, - void* buffer, uint16_t len) { +uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len); } @@ -1361,27 +1354,24 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub //--------------------------------------------------------------------+ // Enumeration Process -// is a lengthy process with a series of control transfer to configure -// newly attached device. +// is a lengthy process with a series of control transfer to configure newly attached device. // NOTE: due to the shared control buffer, we must complete enumerating // one device before enumerating another one. //--------------------------------------------------------------------+ - -enum { - ENUM_DEBOUNCING_DELAY_MS = 200, // when plug/unplug a device, physical connection can be bouncing and may - // generate a series of attach/detach event. This delay wait for stable connection - ENUM_RESET_DELAY_MS = 50, // USB specs: 10 to 50ms +enum { // USB 2.0 specs 7.1.7 for timing + ENUM_DEBOUNCING_DELAY_MS = 150, // T(ATTDB) minimum 100 ms for stable connection + ENUM_RESET_ROOT_DELAY_MS = 50, // T(DRSTr) minimum 50 ms for reset from root port + ENUM_RESET_HUB_DELAY_MS = 20, // T(DRST) 10-20 ms for hub reset + ENUM_RESET_RECOVERY_DELAY_MS = 10, // T(RSTRCY) minimum 10 ms for reset recovery }; enum { ENUM_IDLE, - ENUM_RESET_1, // 1st reset when attached - //ENUM_HUB_GET_STATUS_1, - ENUM_HUB_CLEAR_RESET_1, + ENUM_HUB_RERSET, + ENUM_HUB_GET_STATUS_AFTER_RESET, + ENUM_HUB_CLEAR_RESET, + ENUM_ADDR0_DEVICE_DESC, - ENUM_RESET_2, // 2nd reset before set address (not used) - ENUM_HUB_GET_STATUS_2, - ENUM_HUB_CLEAR_RESET_2, ENUM_SET_ADDR, ENUM_GET_DEVICE_DESC, ENUM_GET_STRING_LANGUAGE_ID_LEN, @@ -1401,6 +1391,63 @@ enum { static uint8_t enum_get_new_address(bool is_hub); static bool enum_parse_configuration_desc (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg); static void enum_full_complete(void); +static void process_enumeration(tuh_xfer_t* xfer); + +// start a new enumeration process +static bool enum_new_device(hcd_event_t* event) { + tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; + dev0_bus->rhport = event->rhport; + dev0_bus->hub_addr = event->connection.hub_addr; + dev0_bus->hub_port = event->connection.hub_port; + + _usbh_data.enumerating_daddr = 0; + + // wait until device connection is stable TODO non blocking + tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); + + if (dev0_bus->hub_addr == 0) { + // connected directly to roothub + // USB bus not active and frame number is not available yet. + // need to depend on tusb_time_millis_api() TODO non blocking + + if (!hcd_port_connect_status(dev0_bus->rhport)) { + TU_LOG_USBH("Device unplugged while debouncing\r\n"); + enum_full_complete(); + return true; + } + + // reset device + hcd_port_reset(dev0_bus->rhport); + tusb_time_delay_ms_api(ENUM_RESET_ROOT_DELAY_MS); + hcd_port_reset_end(dev0_bus->rhport); + + if (!hcd_port_connect_status(dev0_bus->rhport)) { + // device unplugged while delaying + enum_full_complete(); + return true; + } + + dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport); + TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]); + + // fake transfer to kick-off the enumeration process + tuh_xfer_t xfer; + xfer.daddr = 0; + xfer.result = XFER_RESULT_SUCCESS; + xfer.user_data = ENUM_ADDR0_DEVICE_DESC; + process_enumeration(&xfer); + } + #if CFG_TUH_HUB + else { + // connected via hub + TU_VERIFY(dev0_bus->hub_port != 0); + TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, + process_enumeration, ENUM_HUB_RERSET)); + } + #endif // hub + + return true; +} // process device enumeration static void process_enumeration(tuh_xfer_t* xfer) { @@ -1431,6 +1478,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { uint8_t const daddr = xfer->daddr; uintptr_t const state = xfer->user_data; usbh_device_t* dev = get_device(daddr); + tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; if (daddr > 0) { TU_ASSERT(dev,); } @@ -1438,53 +1486,54 @@ static void process_enumeration(tuh_xfer_t* xfer) { switch (state) { #if CFG_TUH_HUB - //case ENUM_HUB_GET_STATUS_1: break; - case ENUM_HUB_CLEAR_RESET_1: { + case ENUM_HUB_RERSET: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); + hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); if (!port_status.status.connection) { - // device unplugged while delaying, nothing else to do + TU_LOG_USBH("Device unplugged from hub while debouncing\r\n"); enum_full_complete(); return; } - _usbh_data.dev0_bus.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : - (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; - - // Acknowledge Port Reset Change - if (port_status.change.reset) { - hub_port_clear_reset_change(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, - process_enumeration, ENUM_ADDR0_DEVICE_DESC); - } + TU_ASSERT(hub_port_reset(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_GET_STATUS_AFTER_RESET),); break; } - case ENUM_HUB_GET_STATUS_2: - tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - TU_ASSERT(hub_port_get_status(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, _usbh_epbuf.ctrl, - process_enumeration, ENUM_HUB_CLEAR_RESET_2),); + case ENUM_HUB_GET_STATUS_AFTER_RESET: { + tusb_time_delay_ms_api(ENUM_RESET_HUB_DELAY_MS); // wait for reset to take effect + + // get status to check for reset change + TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET),); break; + } - case ENUM_HUB_CLEAR_RESET_2: { + case ENUM_HUB_CLEAR_RESET: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); + hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); + dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : + (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; - // Acknowledge Port Reset Change if Reset Successful if (port_status.change.reset) { - TU_ASSERT(hub_port_clear_reset_change(_usbh_data.dev0_bus.hub_addr, _usbh_data.dev0_bus.hub_port, - process_enumeration, ENUM_SET_ADDR),); + // Acknowledge Port Reset Change + TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC),); + } else { + // maybe retry if reset change not set but we need timeout to prevent infinite loop + // TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET),); } + break; } #endif case ENUM_ADDR0_DEVICE_DESC: { + tusb_time_delay_ms_api(ENUM_RESET_RECOVERY_DELAY_MS); // reset recovery + // TODO probably doesn't need to open/close each enumeration uint8_t const addr0 = 0; TU_ASSERT(usbh_edpt_control_open(addr0, 8),); - // Get first 8 bytes of device descriptor for Control Endpoint size + // Get first 8 bytes of device descriptor for control endpoint size TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8, process_enumeration, ENUM_SET_ADDR),); @@ -1686,59 +1735,6 @@ static void process_enumeration(tuh_xfer_t* xfer) { } } -static bool enum_new_device(hcd_event_t* event) { - tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; - dev0_bus->rhport = event->rhport; - dev0_bus->hub_addr = event->connection.hub_addr; - dev0_bus->hub_port = event->connection.hub_port; - - // wait until device connection is stable TODO non blocking - tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); - - if (dev0_bus->hub_addr == 0) { - // connected directly to roothub - - if (!hcd_port_connect_status(dev0_bus->rhport)) { - TU_LOG_USBH("Device unplugged while debouncing\r\n"); - enum_full_complete(); - return true; - } - - hcd_port_reset(dev0_bus->rhport); // reset device - - // Since we are in middle of rhport reset, frame number is not available yet. - // need to depend on tusb_time_millis_api() TODO non blocking - tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - - hcd_port_reset_end(dev0_bus->rhport); - - // device unplugged while delaying - if (!hcd_port_connect_status(dev0_bus->rhport)) { - enum_full_complete(); - return true; - } - - dev0_bus->speed = hcd_port_speed_get(dev0_bus->rhport); - TU_LOG_USBH("%s Speed\r\n", tu_str_speed[dev0_bus->speed]); - - // fake transfer to kick-off the enumeration process - tuh_xfer_t xfer; - xfer.daddr = 0; - xfer.result = XFER_RESULT_SUCCESS; - xfer.user_data = ENUM_ADDR0_DEVICE_DESC; - process_enumeration(&xfer); - } -#if CFG_TUH_HUB - else { - // connected via external hub - TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, _usbh_epbuf.ctrl, - process_enumeration, ENUM_HUB_CLEAR_RESET_1)); - } -#endif // hub - - return true; -} - static uint8_t enum_get_new_address(bool is_hub) { uint8_t start; uint8_t end; -- cgit v1.3.1 From 093720f60b2b849f7129e532f8efef94c04d408b Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Apr 2025 18:08:00 +0700 Subject: fix build --- src/host/usbh.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 94a1fa247..25942315b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1546,7 +1546,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { TU_ASSERT(new_addr != 0,); usbh_device_t* new_dev = get_device(new_addr); - new_dev->bus_info = _usbh_data.dev0_bus; + new_dev->bus_info = *dev0_bus; new_dev->connected = 1; new_dev->ep0_size = desc_device->bMaxPacketSize0; @@ -1564,7 +1564,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { new_dev->addressed = 1; _usbh_data.enumerating_daddr = new_addr; - hcd_device_close(_usbh_data.dev0_bus.rhport, 0); // close dev0_bus + hcd_device_close(dev0_bus->rhport, 0); // close dev0 TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // open new control endpoint -- cgit v1.3.1 From b5b7a4be60428193a773c1177456f138c21e48ad Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 24 Apr 2025 21:53:57 +0700 Subject: hub check status before get 1st device descriptor --- .idea/cmake.xml | 4 ++-- src/host/usbh.c | 23 +++++++++++++++++++---- 2 files changed, 21 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 7365e13a8..b8383a5ff 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -6,9 +6,9 @@ - - + + diff --git a/src/host/usbh.c b/src/host/usbh.c index 25942315b..8469aee83 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1370,6 +1370,7 @@ enum { ENUM_HUB_RERSET, ENUM_HUB_GET_STATUS_AFTER_RESET, ENUM_HUB_CLEAR_RESET, + ENUM_HUB_CLEAR_RESET_COMPLETE, ENUM_ADDR0_DEVICE_DESC, ENUM_SET_ADDR, @@ -1511,19 +1512,33 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_CLEAR_RESET: { hub_port_status_response_t port_status; hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); - dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : - (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; if (port_status.change.reset) { // Acknowledge Port Reset Change - TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_ADDR0_DEVICE_DESC),); + TU_ASSERT(hub_port_clear_reset_change(dev0_bus->hub_addr, dev0_bus->hub_port, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),); } else { // maybe retry if reset change not set but we need timeout to prevent infinite loop - // TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET),); + // TU_ASSERT(hub_port_get_status(dev0_bus->hub_addr, dev0_bus->hub_port, NULL, process_enumeration, ENUM_HUB_CLEAR_RESET_COMPLETE),); } break; } + + case ENUM_HUB_CLEAR_RESET_COMPLETE: { + hub_port_status_response_t port_status; + hub_port_get_status_local(dev0_bus->hub_addr, dev0_bus->hub_port, &port_status); + + if (!port_status.status.connection) { + TU_LOG_USBH("Device unplugged from hub (not addressed yet)\r\n"); + enum_full_complete(); + return; + } + + dev0_bus->speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH : + (port_status.status.low_speed) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL; + + TU_ATTR_FALLTHROUGH; + } #endif case ENUM_ADDR0_DEVICE_DESC: { -- cgit v1.3.1 From 2c1414b4c18518a179560a097aada40609303693 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Apr 2025 12:59:59 +0700 Subject: usbh: add roothub debounncing flag to ignore attach/remove event on the roothub that is currently doing debouncing delay --- src/host/usbh.c | 22 ++++++++++++++++++---- src/portable/synopsys/dwc2/hcd_dwc2.c | 19 +++---------------- 2 files changed, 21 insertions(+), 20 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 8469aee83..8852bdda4 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -275,6 +275,7 @@ typedef struct { typedef struct { uint8_t controller_id; // controller ID uint8_t enumerating_daddr; // device address of the device being enumerated + uint8_t attach_debouncing_bm; // bitmask for roothub port attach debouncing tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer } usbh_data_t; @@ -349,7 +350,7 @@ bool tuh_rhport_is_active(uint8_t rhport) { bool tuh_rhport_reset_bus(uint8_t rhport, bool active) { TU_VERIFY(tuh_rhport_is_active(rhport)); - if ( active ) { + if (active) { hcd_port_reset(rhport); } else { hcd_port_reset_end(rhport); @@ -1021,10 +1022,18 @@ bool tuh_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info) { TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) { switch (event->event_id) { case HCD_EVENT_DEVICE_ATTACH: - - break; - case HCD_EVENT_DEVICE_REMOVE: + // Attach debouncing on roothub: skip attach/remove while debouncing delay + if (event->connection.hub_addr == 0) { + if (tu_bit_test(_usbh_data.attach_debouncing_bm, event->rhport)) { + return; + } + + if (event->event_id == HCD_EVENT_DEVICE_ATTACH) { + // No debouncing, set flag if attach event + _usbh_data.attach_debouncing_bm |= TU_BIT(event->rhport); + } + } break; default: break; @@ -1406,6 +1415,11 @@ static bool enum_new_device(hcd_event_t* event) { // wait until device connection is stable TODO non blocking tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); + // clear roothub debouncing delay + if (dev0_bus->hub_addr == 0) { + _usbh_data.attach_debouncing_bm &= (uint8_t) ~TU_BIT(dev0_bus->rhport); + } + if (dev0_bus->hub_addr == 0) { // connected directly to roothub // USB bus not active and frame number is not available yet. diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7c29a03cf..2de15068a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -107,7 +107,6 @@ typedef struct { typedef struct { hcd_xfer_t xfer[DWC2_CHANNEL_COUNT_MAX]; hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX]; - bool attach_debounce; // if true: wait for the debounce delay before issuing new attach events } hcd_data_t; hcd_data_t _hcd_data; @@ -423,11 +422,6 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { - // this is called from enum_new_device() - after the debouncing delays - if (_hcd_data.attach_debounce) { - _hcd_data.attach_debounce = false; // allow new attach events again - } - dwc2_regs_t* dwc2 = DWC2_REG(rhport); return dwc2->hprt & HPRT_CONN_STATUS; } @@ -1328,10 +1322,7 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { hprt |= HPRT_CONN_DETECT; if (hprt_bm.conn_status) { - if (!_hcd_data.attach_debounce) { - _hcd_data.attach_debounce = true; // block new attach events until the debounce delay is over - hcd_event_device_attach(rhport, in_isr); - } + hcd_event_device_attach(rhport, in_isr); } } @@ -1398,12 +1389,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // Device disconnected dwc2->gintsts = GINTSTS_DISCINT; - // ignore device removal if attach debounce is active - // it will evaluate the port status after the debounce delay - if (!_hcd_data.attach_debounce) { - if (!(dwc2->hprt & HPRT_CONN_STATUS)) { - hcd_event_device_remove(rhport, in_isr); - } + if (!(dwc2->hprt & HPRT_CONN_STATUS)) { + hcd_event_device_remove(rhport, in_isr); } } -- cgit v1.3.1 From 42d4f7c81e65a2d39b8e108b1ef8ed58945b7617 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Apr 2025 15:10:03 +0700 Subject: remove the old attach duplicated logic, debouncing skip should take care of it. --- src/host/usbh.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 8852bdda4..6f875c80b 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -513,28 +513,19 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { case HCD_EVENT_DEVICE_ATTACH: // due to the shared control buffer, we must fully complete enumerating one device first. // TODO better to have an separated queue for newly attached devices - if (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) { - if (event.rhport == _usbh_data.dev0_bus.rhport && - event.connection.hub_addr == _usbh_data.dev0_bus.hub_addr && event.connection.hub_port == _usbh_data.dev0_bus.hub_port) { - // Some device can cause multiple duplicated attach events - // drop current enumerating and start over for a proper port reset - // abort/cancel current enumeration and start new one - TU_LOG1("[%u:] USBH Device Attach (duplicated)\r\n", event.rhport); - tuh_edpt_abort_xfer(0, 0); - enum_new_device(&event); - } else { - TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); - bool is_empty = osal_queue_empty(_usbh_q); - queue_event(&event, in_isr); - - if (is_empty) { - // Exit if this is the only event in the queue, otherwise we may loop forever - return; - } - } - } else { + if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) { + // New device attached and we are ready TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport); + _usbh_data.enumerating_daddr = 0; // enumerate new device with address 0 enum_new_device(&event); + } else { + // currently enumerating another device + TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); + const bool is_empty = osal_queue_empty(_usbh_q); + queue_event(&event, in_isr); + if (is_empty) { + return; // Exit if this is the only event in the queue, otherwise we loop forever + } } break; @@ -1410,8 +1401,6 @@ static bool enum_new_device(hcd_event_t* event) { dev0_bus->hub_addr = event->connection.hub_addr; dev0_bus->hub_port = event->connection.hub_port; - _usbh_data.enumerating_daddr = 0; - // wait until device connection is stable TODO non blocking tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); -- cgit v1.3.1 From fc43eeddf2b3d045431d56cc50bb0e2d6fdf5b98 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Apr 2025 10:11:20 +0700 Subject: attach debouncing fixed issue with port1 highspeed on imxrt --- .idea/debugServers/rt1060.xml | 2 +- .idea/debugServers/rt1064.xml | 2 +- .idea/debugServers/sam21.xml | 2 +- .idea/debugServers/sam51.xml | 2 +- .idea/debugServers/stm32f769.xml | 4 ++-- .idea/debugServers/stm32h563.xml | 2 +- .idea/debugServers/stm32h743.xml | 2 +- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 6 ------ 8 files changed, 8 insertions(+), 14 deletions(-) (limited to 'src') diff --git a/.idea/debugServers/rt1060.xml b/.idea/debugServers/rt1060.xml index 3325cc81f..cbd295b4e 100644 --- a/.idea/debugServers/rt1060.xml +++ b/.idea/debugServers/rt1060.xml @@ -5,7 +5,7 @@ - + diff --git a/.idea/debugServers/rt1064.xml b/.idea/debugServers/rt1064.xml index 4dc38ef63..691066f9d 100644 --- a/.idea/debugServers/rt1064.xml +++ b/.idea/debugServers/rt1064.xml @@ -5,7 +5,7 @@ - + diff --git a/.idea/debugServers/sam21.xml b/.idea/debugServers/sam21.xml index d8763b33b..3f6735bd1 100644 --- a/.idea/debugServers/sam21.xml +++ b/.idea/debugServers/sam21.xml @@ -5,7 +5,7 @@ - + diff --git a/.idea/debugServers/sam51.xml b/.idea/debugServers/sam51.xml index 0d15ff856..99a92c174 100644 --- a/.idea/debugServers/sam51.xml +++ b/.idea/debugServers/sam51.xml @@ -5,7 +5,7 @@ - + diff --git a/.idea/debugServers/stm32f769.xml b/.idea/debugServers/stm32f769.xml index 2fb322a0f..22a452218 100644 --- a/.idea/debugServers/stm32f769.xml +++ b/.idea/debugServers/stm32f769.xml @@ -1,11 +1,11 @@ - + - + diff --git a/.idea/debugServers/stm32h563.xml b/.idea/debugServers/stm32h563.xml index 9bf6db6e9..637839314 100644 --- a/.idea/debugServers/stm32h563.xml +++ b/.idea/debugServers/stm32h563.xml @@ -5,7 +5,7 @@ - + diff --git a/.idea/debugServers/stm32h743.xml b/.idea/debugServers/stm32h743.xml index 63680b78c..b04e4a708 100644 --- a/.idea/debugServers/stm32h743.xml +++ b/.idea/debugServers/stm32h743.xml @@ -5,7 +5,7 @@ - + diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 22eb22690..b5324a754 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -93,12 +93,6 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { hcd_reg->USBMODE = USBMODE_CM_HOST; #endif - // FIXME force full speed, still have issue with Highspeed enumeration - // probably due to physical connection bouncing when plug/unplug - // 1. Have issue when plug/unplug devices, maybe the port is not reset properly - // 2. Also does not seems to detect disconnection - hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; - return ehci_init(rhport, (uint32_t) &hcd_reg->CAPLENGTH, (uint32_t) &hcd_reg->USBCMD); } -- cgit v1.3.1 From e7d4b5c9e718b1e72df8aadb884d2f36ab9d158c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Apr 2025 17:04:10 +0700 Subject: add enum for set addr recovery --- .idea/cmake.xml | 6 +++--- .idea/debugServers/rt1064.xml | 4 ++-- src/host/usbh.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index b8383a5ff..dd219bc77 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -12,7 +12,7 @@ - + @@ -94,7 +94,8 @@ - + + @@ -166,7 +167,6 @@ - \ No newline at end of file diff --git a/.idea/debugServers/rt1064.xml b/.idea/debugServers/rt1064.xml index 691066f9d..b908b59e2 100644 --- a/.idea/debugServers/rt1064.xml +++ b/.idea/debugServers/rt1064.xml @@ -1,11 +1,11 @@ - + - + diff --git a/src/host/usbh.c b/src/host/usbh.c index 6f875c80b..fbb61e10e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1363,6 +1363,7 @@ enum { // USB 2.0 specs 7.1.7 for timing ENUM_RESET_ROOT_DELAY_MS = 50, // T(DRSTr) minimum 50 ms for reset from root port ENUM_RESET_HUB_DELAY_MS = 20, // T(DRST) 10-20 ms for hub reset ENUM_RESET_RECOVERY_DELAY_MS = 10, // T(RSTRCY) minimum 10 ms for reset recovery + ENUM_SET_ADDRESS_RECOVERY_DELAY_MS = 2, // USB 2.0 Spec 9.2.6.3 min is 2 ms }; enum { @@ -1573,8 +1574,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_GET_DEVICE_DESC: { - // Allow 2ms for address recovery time, Ref USB Spec 9.2.6.3 - tusb_time_delay_ms_api(2); + tusb_time_delay_ms_api(ENUM_SET_ADDRESS_RECOVERY_DELAY_MS); // set address recovery const uint8_t new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue); usbh_device_t* new_dev = get_device(new_addr); -- cgit v1.3.1 From 2abd3c54c4141e5e6e0bd4fea38849cb150fb161 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Apr 2025 20:49:47 +0700 Subject: define hcd_devtree_info_t forr backward compatible --- src/host/usbh.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/host/usbh.h b/src/host/usbh.h index 6f09f0c80..6f34d8bb3 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -86,6 +86,9 @@ typedef struct { uint8_t speed; } tuh_bus_info_t; +// backward compatibility for hcd_devtree_info_t, maybe removed in the future +#define hcd_devtree_info_t tuh_bus_info_t +#define hcd_devtree_get_info(_daddr, _bus_info) tuh_bus_info_get(_daddr, _bus_info) // ConfigID for tuh_configure() enum { -- cgit v1.3.1 From 6a92b8efa442d0bfffa5bb43419d35d12c753910 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 4 May 2025 15:10:17 +0200 Subject: dcd/ci_hs: add vbus charge option. Signed-off-by: HiFiPhile --- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++++ src/tusb_option.h | 9 +++++++++ 2 files changed, 13 insertions(+) (limited to 'src') diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index a716dc24c..244f5a2d4 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -239,7 +239,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { usbmode |= USBMODE_CM_DEVICE; dcd_reg->USBMODE = usbmode; +#ifdef CFG_TUD_CI_HS_VBUS_CHARGE + dcd_reg->OTGSC = OTGSC_VBUS_CHARGE | OTGSC_OTG_TERMINATION; +#else dcd_reg->OTGSC = OTGSC_VBUS_DISCHARGE | OTGSC_OTG_TERMINATION; +#endif #if !TUD_OPT_HIGH_SPEED dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; diff --git a/src/tusb_option.h b/src/tusb_option.h index 98f1a91b5..679b80420 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -267,6 +267,15 @@ #define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT #endif +// Enable CI_HS VBUS Charge +#ifndef CFG_TUD_CI_HS_VBUS_CHARGE + #ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT + #define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0 + #endif + + #define CFG_TUD_CI_HS_VBUS_CHARGE CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT +#endif + // Enable DWC2 Slave mode for host #ifndef CFG_TUH_DWC2_SLAVE_ENABLE #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT -- cgit v1.3.1 From bc37ed6e3e9158a811ed07479638d3db8437344e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 6 May 2025 15:23:23 +0700 Subject: usbh: force removed device in the same bus info, before setting address. usbh: move code around hub: queue status endpoint for detach/remove event --- src/host/hub.c | 3 +- src/host/usbh.c | 231 +++++++++++++++++++++++++++----------------------------- 2 files changed, 114 insertions(+), 120 deletions(-) (limited to 'src') diff --git a/src/host/hub.c b/src/host/hub.c index c87289a14..0ed0e0c42 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -459,7 +459,8 @@ static void process_new_status(tuh_xfer_t* xfer) { } }; hcd_event_handler(&event, false); - processed = true; // usbh queue status after handled this in (de)enumeration + // skip status for attach event, usbh will do it after handled this enumeration + processed = (event.event_id == HCD_EVENT_DEVICE_ATTACH); break; } diff --git a/src/host/usbh.c b/src/host/usbh.c index fbb61e10e..92c254a9e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -34,7 +34,7 @@ #include "hub.h" //--------------------------------------------------------------------+ -// USBH Configuration +// Configuration //--------------------------------------------------------------------+ #ifndef CFG_TUH_TASK_QUEUE_SZ #define CFG_TUH_TASK_QUEUE_SZ 16 @@ -89,7 +89,7 @@ TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_si } //--------------------------------------------------------------------+ -// USBH-HCD common data structure +// Data Structure //--------------------------------------------------------------------+ typedef struct { tuh_bus_info_t bus_info; @@ -131,8 +131,60 @@ typedef struct { } usbh_device_t; +// sum of end device + hub +#define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) + +// all devices excluding zero-address +// hub address start from CFG_TUH_DEVICE_MAX+1 +// TODO: hub can has its own simpler struct to save memory +static usbh_device_t _usbh_devices[TOTAL_DEVICES]; + +// Mutex for claiming endpoint +#if OSAL_MUTEX_REQUIRED +static osal_mutex_def_t _usbh_mutexdef; +static osal_mutex_t _usbh_mutex; +#else +#define _usbh_mutex NULL +#endif + +// Event queue: usbh_int_set() is used as mutex in OS NONE config +OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); +static osal_queue_t _usbh_q; + +// Control transfers: since most controllers do not support multiple control transfers +// on multiple devices concurrently and control transfers are not used much except for +// enumeration, we will only execute control transfers one at a time. +typedef struct { + uint8_t* buffer; + tuh_xfer_cb_t complete_cb; + uintptr_t user_data; + + volatile uint8_t stage; + uint8_t daddr; + volatile uint16_t actual_len; + uint8_t failed_count; +} usbh_ctrl_xfer_info_t; + +typedef struct { + uint8_t controller_id; // controller ID + uint8_t enumerating_daddr; // device address of the device being enumerated + uint8_t attach_debouncing_bm; // bitmask for roothub port attach debouncing + tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration + usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer +} usbh_data_t; + +static usbh_data_t _usbh_data = { + .controller_id = TUSB_INDEX_INVALID_8, +}; + +typedef struct { + TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request); + TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); +} usbh_epbuf_t; +CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; + //--------------------------------------------------------------------+ -// MACRO CONSTANT TYPEDEF +// Class Driver //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUH_LOG_LEVEL #define DRIVER_NAME(_name) _name @@ -235,82 +287,58 @@ static inline usbh_class_driver_t const *get_driver(uint8_t drv_id) { } //--------------------------------------------------------------------+ -// INTERNAL OBJECT & FUNCTION DECLARATION +// Function Inline and Prototypes //--------------------------------------------------------------------+ +static bool enum_new_device(hcd_event_t* event); +static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); +static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); +static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); -// sum of end device + hub -#define TOTAL_DEVICES (CFG_TUH_DEVICE_MAX + CFG_TUH_HUB) - -// all devices excluding zero-address -// hub address start from CFG_TUH_DEVICE_MAX+1 -// TODO: hub can has its own simpler struct to save memory -static usbh_device_t _usbh_devices[TOTAL_DEVICES]; - -// Mutex for claiming endpoint -#if OSAL_MUTEX_REQUIRED - static osal_mutex_def_t _usbh_mutexdef; - static osal_mutex_t _usbh_mutex; -#else - #define _usbh_mutex NULL -#endif - -// Event queue: usbh_int_set() is used as mutex in OS NONE config -OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); -static osal_queue_t _usbh_q; - -// Control transfers: since most controllers do not support multiple control transfers -// on multiple devices concurrently and control transfers are not used much except for -// enumeration, we will only execute control transfers one at a time. -typedef struct { - uint8_t* buffer; - tuh_xfer_cb_t complete_cb; - uintptr_t user_data; - - volatile uint8_t stage; - uint8_t daddr; - volatile uint16_t actual_len; - uint8_t failed_count; -} usbh_ctrl_xfer_info_t; - -typedef struct { - uint8_t controller_id; // controller ID - uint8_t enumerating_daddr; // device address of the device being enumerated - uint8_t attach_debouncing_bm; // bitmask for roothub port attach debouncing - tuh_bus_info_t dev0_bus; // bus info for dev0 in enumeration - usbh_ctrl_xfer_info_t ctrl_xfer_info; // control transfer -} usbh_data_t; - -static usbh_data_t _usbh_data = { - .controller_id = TUSB_INDEX_INVALID_8, -}; - -typedef struct { - TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request); - TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); -} usbh_epbuf_t; -CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; - -//------------- Helper Function -------------// TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) { TU_VERIFY(dev_addr > 0 && dev_addr <= TOTAL_DEVICES, NULL); return &_usbh_devices[dev_addr-1]; } -static bool enum_new_device(hcd_event_t* event); -static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port); -static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); -static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); - TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) { TU_ASSERT(osal_queue_send(_usbh_q, event, in_isr)); tuh_event_hook_cb(event->rhport, event->event_id, in_isr); return true; } +TU_ATTR_ALWAYS_INLINE static inline void _control_set_xfer_stage(uint8_t stage) { + if (_usbh_data.ctrl_xfer_info.stage != stage) { + (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); + _usbh_data.ctrl_xfer_info.stage = stage; + (void) osal_mutex_unlock(_usbh_mutex); + } +} + +TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const uint8_t setup_packet[8]) { + const uint8_t rhport = usbh_get_rhport(daddr); + const bool ret = hcd_setup_send(rhport, daddr, setup_packet); + if (!ret) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } + return ret; +} + +TU_ATTR_ALWAYS_INLINE static inline void usbh_device_close(uint8_t rhport, uint8_t daddr) { + hcd_device_close(rhport, daddr); + + // abort any ongoing control transfer + if (daddr == _usbh_data.ctrl_xfer_info.daddr) { + _control_set_xfer_stage(CONTROL_STAGE_IDLE); + } + + // invalidate if enumerating + if (daddr == _usbh_data.enumerating_daddr) { + _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; + } +} + //--------------------------------------------------------------------+ // Device API //--------------------------------------------------------------------+ - bool tuh_mounted(uint8_t dev_addr) { usbh_device_t *dev = get_device(dev_addr); TU_VERIFY(dev); @@ -530,16 +558,16 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { break; case HCD_EVENT_DEVICE_REMOVE: - TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); - process_removed_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); - - #if CFG_TUH_HUB - // TODO remove - if (event.connection.hub_addr != 0 && event.connection.hub_port != 0) { - // done with hub, waiting for next data on status pipe - (void) hub_edpt_status_xfer(event.connection.hub_addr); + TU_LOG1("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); + if (_usbh_data.enumerating_daddr == 0 && + event.rhport == _usbh_data.dev0_bus.rhport && + event.connection.hub_addr == _usbh_data.dev0_bus.hub_addr && + event.connection.hub_port == _usbh_data.dev0_bus.hub_port) { + // dev0 is unplugged while enumerating (not yet assigned an address) + usbh_device_close(_usbh_data.dev0_bus.rhport, 0); + } else { + process_removed_device(event.rhport, event.connection.hub_addr, event.connection.hub_port); } - #endif break; case HCD_EVENT_XFER_COMPLETE: { @@ -623,23 +651,6 @@ static void _control_blocking_complete_cb(tuh_xfer_t* xfer) { *((xfer_result_t*) xfer->user_data) = xfer->result; } -TU_ATTR_ALWAYS_INLINE static inline void _control_set_xfer_stage(uint8_t stage) { - if (_usbh_data.ctrl_xfer_info.stage != stage) { - (void) osal_mutex_lock(_usbh_mutex, OSAL_TIMEOUT_WAIT_FOREVER); - _usbh_data.ctrl_xfer_info.stage = stage; - (void) osal_mutex_unlock(_usbh_mutex); - } -} - -TU_ATTR_ALWAYS_INLINE static inline bool usbh_setup_send(uint8_t daddr, const uint8_t setup_packet[8]) { - const uint8_t rhport = usbh_get_rhport(daddr); - const bool ret = hcd_setup_send(rhport, daddr, setup_packet); - if (!ret) { - _control_set_xfer_stage(CONTROL_STAGE_IDLE); - } - return ret; -} - // TODO timeout_ms is not supported yet bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); // EP0 with setup packet @@ -1270,21 +1281,8 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { // a device unplugged from rhport:hub_addr:hub_port static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { - // if dev0 is unplugged while enumerating (not yet assigned an address) - if (_usbh_data.enumerating_daddr == 0) { - const tuh_bus_info_t* dev0_bus = &_usbh_data.dev0_bus; - if ((rhport == dev0_bus->rhport) && (hub_addr == dev0_bus->hub_addr) && (hub_port == dev0_bus->hub_port)) { - hcd_device_close(dev0_bus->rhport, 0); - if (_usbh_data.ctrl_xfer_info.daddr == 0) { - _control_set_xfer_stage(CONTROL_STAGE_IDLE); - } - _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; - return; - } - } - - //------------- find the all devices (star-network) under port that is unplugged -------------// - uint32_t removing_hubs = 0; + // Find the all devices (star-network) under port that is unplugged + uint32_t removing_hubs_bm = 0; do { for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { usbh_device_t* dev = &_usbh_devices[dev_id]; @@ -1298,7 +1296,7 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub if (is_hub_addr(daddr)) { TU_LOG_USBH(" is a HUB device %u\r\n", daddr); - removing_hubs |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX); + removing_hubs_bm |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX); } else { // Invoke callback before closing driver (maybe call it later ?) if (tuh_umount_cb) { @@ -1314,30 +1312,21 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub } } - hcd_device_close(rhport, daddr); + usbh_device_close(rhport, daddr); clear_device(dev); - - // abort ongoing control xfer on this device if any - if (daddr == _usbh_data.ctrl_xfer_info.daddr) { - _control_set_xfer_stage(CONTROL_STAGE_IDLE); - } - - if (daddr == _usbh_data.enumerating_daddr) { - _usbh_data.enumerating_daddr = TUSB_INDEX_INVALID_8; - } } } // if removing a hub, we need to remove all of its downstream devices #if CFG_TUH_HUB - if (removing_hubs == 0) { + if (removing_hubs_bm == 0) { break; } // find a marked hub to process for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) { - if (tu_bit_test(removing_hubs, h_id)) { - removing_hubs &= ~TU_BIT(h_id); + if (tu_bit_test(removing_hubs_bm, h_id)) { + removing_hubs_bm &= ~TU_BIT(h_id); // update hub_addr and hub_port for next loop hub_addr = h_id + 1 + CFG_TUH_DEVICE_MAX; @@ -1560,6 +1549,10 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_SET_ADDR: { + // Due to physical debouncing, some devices can cause multiple attaches (actually reset) without detach event + // Force remove currently mounted with the same bus info (rhport, hub addr, hub port) if exists + process_removed_device(dev0_bus->rhport, dev0_bus->hub_addr, dev0_bus->hub_port); + const tusb_desc_device_t *desc_device = (const tusb_desc_device_t *) _usbh_epbuf.ctrl; const uint8_t new_addr = enum_get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); TU_ASSERT(new_addr != 0,); @@ -1582,7 +1575,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { new_dev->addressed = 1; _usbh_data.enumerating_daddr = new_addr; - hcd_device_close(dev0_bus->rhport, 0); // close dev0 + usbh_device_close(dev0_bus->rhport, 0); // close dev0 TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // open new control endpoint -- cgit v1.3.1 From 809af3e74ca37495d6c385acd33a488c2984a093 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 6 May 2025 15:44:00 +0700 Subject: chore(usbh): change removing_hubs to array instead of bitmask --- .idea/debugServers/rt1064.xml | 2 +- src/host/usbh.c | 37 +++++++++++++++++++++---------------- 2 files changed, 22 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/.idea/debugServers/rt1064.xml b/.idea/debugServers/rt1064.xml index b908b59e2..4fb2fdf6a 100644 --- a/.idea/debugServers/rt1064.xml +++ b/.idea/debugServers/rt1064.xml @@ -1,5 +1,5 @@ - + diff --git a/src/host/usbh.c b/src/host/usbh.c index 92c254a9e..a3d79a105 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -299,6 +299,10 @@ TU_ATTR_ALWAYS_INLINE static inline usbh_device_t* get_device(uint8_t dev_addr) return &_usbh_devices[dev_addr-1]; } +TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { + return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX); +} + TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) { TU_ASSERT(osal_queue_send(_usbh_q, event, in_isr)); tuh_event_hook_cb(event->rhport, event->event_id, in_isr); @@ -1274,15 +1278,13 @@ uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_i //--------------------------------------------------------------------+ // Detaching //--------------------------------------------------------------------+ - -TU_ATTR_ALWAYS_INLINE static inline bool is_hub_addr(uint8_t daddr) { - return (CFG_TUH_HUB > 0) && (daddr > CFG_TUH_DEVICE_MAX); -} - // a device unplugged from rhport:hub_addr:hub_port static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port) { // Find the all devices (star-network) under port that is unplugged - uint32_t removing_hubs_bm = 0; + #if CFG_TUH_HUB + uint8_t removing_hubs[CFG_TUH_HUB] = { 0 }; + #endif + do { for (uint8_t dev_id = 0; dev_id < TOTAL_DEVICES; dev_id++) { usbh_device_t* dev = &_usbh_devices[dev_id]; @@ -1294,10 +1296,13 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub (hub_port == 0 || dev->bus_info.hub_port == hub_port)) { TU_LOG_USBH("[%u:%u:%u] unplugged address = %u\r\n", rhport, hub_addr, hub_port, daddr); + #if CFG_TUH_HUB if (is_hub_addr(daddr)) { TU_LOG_USBH(" is a HUB device %u\r\n", daddr); - removing_hubs_bm |= TU_BIT(dev_id - CFG_TUH_DEVICE_MAX); - } else { + removing_hubs[dev_id - CFG_TUH_DEVICE_MAX] = 1; + } else + #endif + { // Invoke callback before closing driver (maybe call it later ?) if (tuh_umount_cb) { tuh_umount_cb(daddr); @@ -1317,16 +1322,16 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub } } - // if removing a hub, we need to remove all of its downstream devices - #if CFG_TUH_HUB - if (removing_hubs_bm == 0) { +#if CFG_TUH_HUB + // if a hub is removed, we need to remove all of its downstream devices + if (tu_mem_is_zero(removing_hubs, CFG_TUH_HUB)) { break; } // find a marked hub to process for (uint8_t h_id = 0; h_id < CFG_TUH_HUB; h_id++) { - if (tu_bit_test(removing_hubs_bm, h_id)) { - removing_hubs_bm &= ~TU_BIT(h_id); + if (removing_hubs[h_id]) { + removing_hubs[h_id] = 0; // update hub_addr and hub_port for next loop hub_addr = h_id + 1 + CFG_TUH_DEVICE_MAX; @@ -1334,10 +1339,10 @@ static void process_removed_device(uint8_t rhport, uint8_t hub_addr, uint8_t hub break; } } - #else - (void) removing_hubs; +#else break; - #endif +#endif + } while(1); } -- cgit v1.3.1 From 95be35b58727c28932dd0903c7d44fddd275df09 Mon Sep 17 00:00:00 2001 From: Moritz Scholjegerdes Date: Tue, 6 May 2025 16:06:10 +0200 Subject: add support for usbtmc vendor-spicific command messages --- src/class/usbtmc/usbtmc_device.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index abde9679f..d47da101f 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -45,7 +45,7 @@ */ //Limitations: -// "vendor-specific" commands are not handled. +// "vendor-specific" commands are handled similar to normal massages, except that the MsgID is changed to "vendor-specific". // Dealing with "termchar" must be handled by the application layer, // though additional error checking is does in this module. // talkOnly and listenOnly are NOT supported. They're not permitted @@ -171,6 +171,8 @@ tu_static uint8_t termChar; tu_static uint8_t termCharRequested = false; +tu_static uint8_t usbtmcVendorSpecificRequested = false; + #if OSAL_MUTEX_REQUIRED static OSAL_MUTEX_DEF(usbtmcLockBuffer); #endif @@ -226,7 +228,14 @@ bool tud_usbtmc_transmit_dev_msg_data( TU_VERIFY(usbtmc_state.state == STATE_TX_REQUESTED); usbtmc_msg_dev_dep_msg_in_header_t *hdr = (usbtmc_msg_dev_dep_msg_in_header_t*)usbtmc_epbuf.epin; tu_varclr(hdr); - hdr->header.MsgID = USBTMC_MSGID_DEV_DEP_MSG_IN; + if(usbtmcVendorSpecificRequested) + { + hdr->header.MsgID = USBTMC_MSGID_VENDOR_SPECIFIC_IN; + } + else + { + hdr->header.MsgID = USBTMC_MSGID_DEV_DEP_MSG_IN; + } hdr->header.bTag = usbtmc_state.lastBulkInTag; hdr->header.bTagInverse = (uint8_t)~(usbtmc_state.lastBulkInTag); hdr->TransferSize = len; @@ -512,6 +521,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint switch(msg->header.MsgID) { case USBTMC_MSGID_DEV_DEP_MSG_OUT: + usbtmcVendorSpecificRequested = false; if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) { usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); @@ -520,6 +530,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint break; case USBTMC_MSGID_DEV_DEP_MSG_IN: + usbtmcVendorSpecificRequested = false; TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); break; @@ -532,7 +543,19 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint break; #endif case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT: + usbtmcVendorSpecificRequested = true; + if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) + { + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + return false; + } + break; + case USBTMC_MSGID_VENDOR_SPECIFIC_IN: + usbtmcVendorSpecificRequested = true; + TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); + break; + default: usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); return false; -- cgit v1.3.1 From f5944d35b093f63a9bd66a1b4a7414b7db5dce44 Mon Sep 17 00:00:00 2001 From: ZakDanger Date: Fri, 9 May 2025 18:17:07 +1000 Subject: vendor device open fix for descriptor parsing --- src/class/vendor/vendor_device.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 2fc0ac944..d7cef20ff 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -196,8 +196,9 @@ void vendord_reset(uint8_t rhport) { uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - const uint8_t* p_desc = tu_desc_next(desc_itf); - const uint8_t* desc_end = (uint8_t const*)desc_itf + max_len; + const uint8_t* p_desc = (const uint8_t*)desc_itf; + const uint8_t* desc_end = p_desc + max_len; + p_desc = tu_desc_next(p_desc); // Find available interface vendord_interface_t* p_vendor = NULL; @@ -235,6 +236,11 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin p_desc = tu_desc_next(p_desc); } + // skip any other descriptors until the next interface descriptor, or end of all descriptors + while ( (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) && (p_desc < desc_end) ) { + p_desc = tu_desc_next(p_desc); + } + return (uint16_t) ((uintptr_t) p_desc - (uintptr_t) desc_itf); } -- cgit v1.3.1 From ae8c00f5d79629eddb22b9b442cd72f892b5eef6 Mon Sep 17 00:00:00 2001 From: ZakDanger Date: Fri, 9 May 2025 20:42:19 +1000 Subject: revert 'end fix' --- src/class/vendor/vendor_device.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index d7cef20ff..6f41a9f3b 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -196,9 +196,8 @@ void vendord_reset(uint8_t rhport) { uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - const uint8_t* p_desc = (const uint8_t*)desc_itf; - const uint8_t* desc_end = p_desc + max_len; - p_desc = tu_desc_next(p_desc); + const uint8_t* p_desc = tu_desc_next(p_desc); + const uint8_t* desc_end = (const uint8_t*)desc_itf + max_len; // Find available interface vendord_interface_t* p_vendor = NULL; -- cgit v1.3.1 From 6b30a61bdbeeccf2b9447971c17d75946881b64f Mon Sep 17 00:00:00 2001 From: ZakDanger Date: Fri, 9 May 2025 20:44:11 +1000 Subject: revert 'end fix' --- src/class/vendor/vendor_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 6f41a9f3b..8d6e980a2 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -196,7 +196,7 @@ void vendord_reset(uint8_t rhport) { uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - const uint8_t* p_desc = tu_desc_next(p_desc); + const uint8_t* p_desc = tu_desc_next(desc_itf); const uint8_t* desc_end = (const uint8_t*)desc_itf + max_len; // Find available interface -- cgit v1.3.1 From a2117d5d0fb0eea1f76fe7db25642df7a9c83324 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 9 May 2025 16:43:19 +0200 Subject: simplify vendord_open parsing loop Signed-off-by: HiFiPhile --- src/class/vendor/vendor_device.c | 37 ++++++++++++------------------------- 1 file changed, 12 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 8d6e980a2..0f0b0cbb2 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -210,33 +210,20 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin TU_VERIFY(p_vendor, 0); p_vendor->itf_num = desc_itf->bInterfaceNumber; - uint8_t found_ep = 0; - while (found_ep < desc_itf->bNumEndpoints) { - // skip non-endpoint descriptors - while ( (TUSB_DESC_ENDPOINT != tu_desc_type(p_desc)) && (p_desc < desc_end) ) { - p_desc = tu_desc_next(p_desc); + while (TUSB_DESC_INTERFACE != tu_desc_type(p_desc) && (desc_end - p_desc > 0)) { + if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { + const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; + TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); + tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); + } else { + tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep); + TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data + } } - if (p_desc >= desc_end) { - break; - } - - const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; - TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); - found_ep++; - - if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { - tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); - tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); - } else { - tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep); - TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data - } - - p_desc = tu_desc_next(p_desc); - } - // skip any other descriptors until the next interface descriptor, or end of all descriptors - while ( (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) && (p_desc < desc_end) ) { p_desc = tu_desc_next(p_desc); } -- cgit v1.3.1 From baf67539fc2d328a6274c35c18c90da27c37bc60 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 13 May 2025 10:28:42 +0700 Subject: fix warnings, minor clean up --- .github/actions/setup_toolchain/toolchain.json | 2 +- examples/host/cdc_msc_hid/src/hid_app.c | 100 ++++++++----------------- src/class/cdc/cdc_host.c | 2 +- src/class/hid/hid_host.c | 6 +- src/host/hub.c | 1 - src/host/usbh.c | 5 +- 6 files changed, 41 insertions(+), 75 deletions(-) (limited to 'src') diff --git a/.github/actions/setup_toolchain/toolchain.json b/.github/actions/setup_toolchain/toolchain.json index ea07ca344..f7123ef11 100644 --- a/.github/actions/setup_toolchain/toolchain.json +++ b/.github/actions/setup_toolchain/toolchain.json @@ -1,7 +1,7 @@ { "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz", "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz", - "arm-gcc": "https://github.com/xpack-dev-tools/gcc-xpack/releases/download/v14.2.0-1/xpack-gcc-14.2.0-1-linux-x64.tar.gz", + "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v14.2.1-1.1/xpack-arm-none-eabi-gcc-14.2.1-1.1-linux-x64.tar.gz", "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2", "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz", "rx-gcc": "https://github.com/hathach/rx_device/releases/download/0.0.1/gcc-8.3.0.202411-GNURX-ELF.run", diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c index a751c9c80..6f01d6f45 100644 --- a/examples/host/cdc_msc_hid/src/hid_app.c +++ b/examples/host/cdc_msc_hid/src/hid_app.c @@ -29,14 +29,9 @@ //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ +#define MAX_REPORT 4 -// If your host terminal support ansi escape code such as TeraTerm -// it can be use to simulate mouse cursor movement within terminal -#define USE_ANSI_ESCAPE 0 - -#define MAX_REPORT 4 - -static uint8_t const keycode2ascii[128][2] = { HID_KEYCODE_TO_ASCII }; +static uint8_t const keycode2ascii[128][2] = {HID_KEYCODE_TO_ASCII}; // Each HID instance can has multiple reports static struct { @@ -45,8 +40,8 @@ static struct { } hid_info[CFG_TUH_HID]; static void process_kbd_report(hid_keyboard_report_t const *report); -static void process_mouse_report(hid_mouse_report_t const * report); -static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const* report, uint16_t len); +static void process_mouse_report(hid_mouse_report_t const *report); +static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t const *report, uint16_t len); void hid_app_task(void) { // nothing to do @@ -70,7 +65,7 @@ void tuh_hid_mount_cb(uint8_t dev_addr, uint8_t instance, uint8_t const *desc_re printf("HID Interface Protocol = %s\r\n", protocol_str[itf_protocol]); - // By default host stack will use activate boot protocol on supported interface. + // By default, host stack will use boot protocol on supported interface. // Therefore for this simple example, we only need to parse generic report descriptor (with built-in parser) if (itf_protocol == HID_ITF_PROTOCOL_NONE) { hid_info[instance].report_count = tuh_hid_parse_report_descriptor(hid_info[instance].report_info, MAX_REPORT, desc_report, desc_len); @@ -121,7 +116,7 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons //--------------------------------------------------------------------+ // look up new key in previous keys -static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) { +static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) { for (uint8_t i = 0; i < 6; i++) { if (report->keycode[i] == keycode) { return true; @@ -130,28 +125,25 @@ static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8 return false; } -static void process_kbd_report(hid_keyboard_report_t const *report) -{ - static hid_keyboard_report_t prev_report = { 0, 0, {0} }; // previous report to check key released +static void process_kbd_report(hid_keyboard_report_t const *report) { + static hid_keyboard_report_t prev_report = {0, 0, {0}};// previous report to check key released //------------- example code ignore control (non-printable) key affects -------------// - for(uint8_t i=0; i<6; i++) - { - if ( report->keycode[i] ) - { - if ( find_key_in_report(&prev_report, report->keycode[i]) ) - { + for (uint8_t i = 0; i < 6; i++) { + if (report->keycode[i]) { + if (find_key_in_report(&prev_report, report->keycode[i])) { // exist in previous report means the current key is holding - }else - { + } else { // not existed in previous report means the current key is pressed bool const is_shift = report->modifier & (KEYBOARD_MODIFIER_LEFTSHIFT | KEYBOARD_MODIFIER_RIGHTSHIFT); uint8_t ch = keycode2ascii[report->keycode[i]][is_shift ? 1 : 0]; putchar(ch); - if ( ch == '\r' ) putchar('\n'); // added new line for enter key + if (ch == '\r') { + putchar('\n'); + } - #ifndef __ICCARM__ // TODO IAR doesn't support stream control ? - fflush(stdout); // flush right away, else nanolib will wait for newline + #ifndef __ICCARM__ // TODO IAR doesn't support stream control ? + fflush(stdout);// flush right away, else nanolib will wait for newline #endif } } @@ -166,55 +158,22 @@ static void process_kbd_report(hid_keyboard_report_t const *report) //--------------------------------------------------------------------+ static void cursor_movement(int8_t x, int8_t y, int8_t wheel) { -#if USE_ANSI_ESCAPE - // Move X using ansi escape - if ( x < 0) - { - printf(ANSI_CURSOR_BACKWARD(%d), (-x)); // move left - }else if ( x > 0) - { - printf(ANSI_CURSOR_FORWARD(%d), x); // move right - } - - // Move Y using ansi escape - if ( y < 0) - { - printf(ANSI_CURSOR_UP(%d), (-y)); // move up - }else if ( y > 0) - { - printf(ANSI_CURSOR_DOWN(%d), y); // move down - } - - // Scroll using ansi escape - if (wheel < 0) - { - printf(ANSI_SCROLL_UP(%d), (-wheel)); // scroll up - }else if (wheel > 0) - { - printf(ANSI_SCROLL_DOWN(%d), wheel); // scroll down - } - - printf("\r\n"); -#else printf("(%d %d %d)\r\n", x, y, wheel); -#endif } -static void process_mouse_report(hid_mouse_report_t const * report) -{ - static hid_mouse_report_t prev_report = { 0 }; +static void process_mouse_report(hid_mouse_report_t const *report) { + static hid_mouse_report_t prev_report = {0}; - //------------- button state -------------// + // button state uint8_t button_changed_mask = report->buttons ^ prev_report.buttons; - if ( button_changed_mask & report->buttons) - { + if (button_changed_mask & report->buttons) { printf(" %c%c%c ", - report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-', - report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-', - report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-'); + report->buttons & MOUSE_BUTTON_LEFT ? 'L' : '-', + report->buttons & MOUSE_BUTTON_MIDDLE ? 'M' : '-', + report->buttons & MOUSE_BUTTON_RIGHT ? 'R' : '-'); } - //------------- cursor movement -------------// + // cursor movement cursor_movement(report->x, report->y, report->wheel); } @@ -263,18 +222,23 @@ static void process_generic_report(uint8_t dev_addr, uint8_t instance, uint8_t c if (rpt_info->usage_page == HID_USAGE_PAGE_DESKTOP) { switch (rpt_info->usage) { case HID_USAGE_DESKTOP_KEYBOARD: - TU_LOG1("HID receive keyboard report\r\n"); + TU_LOG2("HID receive keyboard report\r\n"); // Assume keyboard follow boot report layout process_kbd_report((hid_keyboard_report_t const *) report); break; case HID_USAGE_DESKTOP_MOUSE: - TU_LOG1("HID receive mouse report\r\n"); + TU_LOG2("HID receive mouse report\r\n"); // Assume mouse follow boot report layout process_mouse_report((hid_mouse_report_t const *) report); break; default: + printf("report[%u] ", rpt_info->report_id); + for (uint8_t i = 0; i < len; i++) { + printf("%02X ", report[i]); + } + printf("\r\n"); break; } } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 4058857c5..bf245db3f 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -672,7 +672,7 @@ void cdch_close(uint8_t daddr) { bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) { // TODO handle stall response, retry failed transfer ... - TU_ASSERT(event == XFER_RESULT_SUCCESS); + TU_VERIFY(event == XFER_RESULT_SUCCESS); uint8_t const idx = get_idx_by_ep_addr(daddr, ep_addr); cdch_interface_t * p_cdc = get_itf(idx); diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index a3cc7d6d7..57e437196 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -444,7 +444,7 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t hidh_epbuf_t* epbuf = get_hid_epbuf(idx); if (dir == TUSB_DIR_IN) { - TU_LOG_DRV(" Get Report callback (%u, %u)\r\n", daddr, idx); + TU_LOG_DRV(" [idx=%u] Get Report callback\r\n", idx); TU_LOG3_MEM(epbuf->epin, xferred_bytes, 2); tuh_hid_report_received_cb(daddr, idx, epbuf->epin, (uint16_t) xferred_bytes); } else { @@ -461,7 +461,9 @@ void hidh_close(uint8_t daddr) { hidh_interface_t* p_hid = &_hidh_itf[i]; if (p_hid->daddr == daddr) { TU_LOG_DRV(" HIDh close addr = %u index = %u\r\n", daddr, i); - if (tuh_hid_umount_cb) tuh_hid_umount_cb(daddr, i); + if (tuh_hid_umount_cb) { + tuh_hid_umount_cb(daddr, i); + } tu_memclr(p_hid, sizeof(hidh_interface_t)); } } diff --git a/src/host/hub.c b/src/host/hub.c index 0ed0e0c42..0b172a596 100644 --- a/src/host/hub.c +++ b/src/host/hub.c @@ -201,7 +201,6 @@ bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, bool hub_port_get_status_local(uint8_t hub_addr, uint8_t hub_port, hub_port_status_response_t* resp) { (void) hub_port; - TU_VERIFY(hub_addr > CFG_TUH_DEVICE_MAX); hub_interface_t* p_hub = get_hub_itf(hub_addr); *resp = p_hub->port_status; return true; diff --git a/src/host/usbh.c b/src/host/usbh.c index a3d79a105..8ab1402dc 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -579,7 +579,8 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = (uint8_t) tu_edpt_dir(ep_addr); - TU_LOG_USBH("on EP %02X with %u bytes: %s\r\n", ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]); + TU_LOG_USBH("[:%u] on EP %02X with %u bytes: %s\r\n", + event.dev_addr, ep_addr, (unsigned int) event.xfer_complete.len, tu_str_xfer_result[event.xfer_complete.result]); if (event.dev_addr == 0) { // device 0 only has control endpoint @@ -618,7 +619,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { uint8_t drv_id = dev->ep2drv[epnum][ep_dir]; usbh_class_driver_t const* driver = get_driver(drv_id); if (driver) { - TU_LOG_USBH("%s xfer callback\r\n", driver->name); + TU_LOG_USBH(" %s xfer callback\r\n", driver->name); driver->xfer_cb(event.dev_addr, ep_addr, (xfer_result_t) event.xfer_complete.result, event.xfer_complete.len); } else { -- cgit v1.3.1 From fe4446090e5ab872faa973cae55839cf6929bf7e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 13 May 2025 16:27:26 +0700 Subject: fix dual example for rp2350 conflict printf and cdc_printf --- examples/dual/host_hid_to_device_cdc/src/main.c | 8 +++-- examples/dual/host_info_to_device_cdc/src/main.c | 44 +++++++++++++----------- src/host/usbh.c | 6 ++-- 3 files changed, 33 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 633f7a6ac..6f30ca381 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -190,7 +190,9 @@ void tuh_hid_umount_cb(uint8_t dev_addr, uint8_t instance) { // look up new key in previous keys static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) { for (uint8_t i = 0; i < 6; i++) { - if (report->keycode[i] == keycode) return true; + if (report->keycode[i] == keycode) { + return true; + } } return false; @@ -230,7 +232,9 @@ static void process_kbd_report(uint8_t dev_addr, hid_keyboard_report_t const* re // TODO example skips key released } - if (flush) tud_cdc_write_flush(); + if (flush) { + tud_cdc_write_flush(); + } prev_report = *report; } diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index 7e593f234..82a48fc61 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -78,6 +78,22 @@ static void print_device_info(uint8_t daddr, const tusb_desc_device_t* desc_devi void led_blinking_task(void); void cdc_task(void); +#define cdc_printf(...) \ + do { \ + char _tempbuf[256]; \ + char* _bufptr = _tempbuf; \ + uint32_t count = (uint32_t) sprintf(_tempbuf, __VA_ARGS__); \ + while (count > 0) { \ + uint32_t wr_count = tud_cdc_write(_bufptr, count); \ + count -= wr_count; \ + _bufptr += wr_count; \ + if (count > 0){ \ + tud_task(); \ + tud_cdc_write_flush(); \ + } \ + } \ + } while(0) + /*------------- MAIN -------------*/ int main(void) { board_init(); @@ -160,22 +176,6 @@ void cdc_task(void) { //--------------------------------------------------------------------+ // Host Get device information //--------------------------------------------------------------------+ -#define cdc_printf(...) \ - do { \ - char _tempbuf[256]; \ - char* _bufptr = _tempbuf; \ - uint32_t count = (uint32_t) sprintf(_tempbuf, __VA_ARGS__); \ - while (count > 0) { \ - uint32_t wr_count = tud_cdc_write(_bufptr, count); \ - count -= wr_count; \ - _bufptr += wr_count; \ - if (count > 0){ \ - tud_task();\ - tud_cdc_write_flush(); \ - } \ - } \ - } while(0) - static void print_device_info(uint8_t daddr, const tusb_desc_device_t* desc_device) { // Get String descriptor using Sync API uint16_t serial[64]; @@ -232,12 +232,12 @@ void tuh_enum_descriptor_device_cb(uint8_t daddr, tusb_desc_device_t const* desc } void tuh_mount_cb(uint8_t daddr) { - printf("mounted device %u\r\n", daddr); + cdc_printf("mounted device %u\r\n", daddr); is_print[daddr] = true; } void tuh_umount_cb(uint8_t daddr) { - printf("unmounted device %u\r\n", daddr); + cdc_printf("unmounted device %u\r\n", daddr); is_print[daddr] = false; } @@ -249,7 +249,9 @@ void led_blinking_task(void) { static bool led_state = false; // Blink every interval ms - if (board_millis() - start_ms < blink_interval_ms) return; // not enough time + if (board_millis() - start_ms < blink_interval_ms) { + return;// not enough time + } start_ms += blink_interval_ms; board_led_write(led_state); @@ -300,7 +302,9 @@ static int _count_utf8_bytes(const uint16_t *buf, size_t len) { } static void print_utf16(uint16_t *temp_buf, size_t buf_len) { - if ((temp_buf[0] & 0xff) == 0) return; // empty + if ((temp_buf[0] & 0xff) == 0) { + return;// empty + } size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); diff --git a/src/host/usbh.c b/src/host/usbh.c index 8ab1402dc..b7d5a05f2 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -547,7 +547,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // TODO better to have an separated queue for newly attached devices if (_usbh_data.enumerating_daddr == TUSB_INDEX_INVALID_8) { // New device attached and we are ready - TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport); + TU_LOG_USBH("[%u:] USBH Device Attach\r\n", event.rhport); _usbh_data.enumerating_daddr = 0; // enumerate new device with address 0 enum_new_device(&event); } else { @@ -562,7 +562,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { break; case HCD_EVENT_DEVICE_REMOVE: - TU_LOG1("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); + TU_LOG_USBH("[%u:%u:%u] USBH DEVICE REMOVED\r\n", event.rhport, event.connection.hub_addr, event.connection.hub_port); if (_usbh_data.enumerating_daddr == 0 && event.rhport == _usbh_data.dev0_bus.rhport && event.connection.hub_addr == _usbh_data.dev0_bus.hub_addr && @@ -1464,7 +1464,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { bool retry = (_usbh_data.enumerating_daddr != TUSB_INDEX_INVALID_8) && (failed_count < ATTEMPT_COUNT_MAX); if (retry) { tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit - TU_LOG1("Enumeration attempt %u/%u\r\n", failed_count+1, ATTEMPT_COUNT_MAX); + TU_LOG_USBH("Enumeration attempt %u/%u\r\n", failed_count+1, ATTEMPT_COUNT_MAX); retry = tuh_control_xfer(xfer); } -- cgit v1.3.1 From 67389f37f2a9dabc33b9f180d49c827e9616572c Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 May 2025 16:39:53 +0700 Subject: follow up to pr3118, interface also end with IAD. Add more checks --- src/class/vendor/vendor_device.c | 22 +++++++++++++++------- src/common/tusb_types.h | 6 ++++++ 2 files changed, 21 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 0f0b0cbb2..7f1fd8c41 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -196,8 +196,8 @@ void vendord_reset(uint8_t rhport) { uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == desc_itf->bInterfaceClass, 0); - const uint8_t* p_desc = tu_desc_next(desc_itf); const uint8_t* desc_end = (const uint8_t*)desc_itf + max_len; + const uint8_t* p_desc = tu_desc_next(desc_itf); // Find available interface vendord_interface_t* p_vendor = NULL; @@ -210,17 +210,25 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin TU_VERIFY(p_vendor, 0); p_vendor->itf_num = desc_itf->bInterfaceNumber; - while (TUSB_DESC_INTERFACE != tu_desc_type(p_desc) && (desc_end - p_desc > 0)) { - if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { + while (tu_desc_is_valid(p_desc, desc_end)) { + const uint8_t desc_type = tu_desc_type(p_desc); + if (desc_type == TUSB_DESC_INTERFACE || desc_type == TUSB_DESC_INTERFACE_ASSOCIATION) { + break; // end of this interface + } else if (desc_type == TUSB_DESC_ENDPOINT) { const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; TU_ASSERT(usbd_edpt_open(rhport, desc_ep)); + // open endpoint stream, skip if already opened if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { - tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); - tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); + if (p_vendor->tx.stream.ep_addr == 0) { + tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); + tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); + } } else { - tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep); - TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data + if (p_vendor->rx.stream.ep_addr == 0) { + tu_edpt_stream_open(&p_vendor->rx.stream, desc_ep); + TU_ASSERT(tu_edpt_stream_read_xfer(rhport, &p_vendor->rx.stream) > 0, 0); // prepare for incoming data + } } } diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index e000a4bd3..fd7f01b67 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -586,6 +586,12 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_subtype(void const* desc) { return ((uint8_t const*) desc)[DESC_OFFSET_SUBTYPE]; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_is_valid(void const* desc, uint8_t const* desc_end) { + const uint8_t* desc8 = (uint8_t const*) desc; + return (desc8 < desc_end) && (tu_desc_next(desc) <= desc_end); +} + + // find descriptor that match byte1 (type) uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1); -- cgit v1.3.1 From 4f4ba3b16d9bcb98a1cb51cb6030f0be4dfd7513 Mon Sep 17 00:00:00 2001 From: Niklas Hauser Date: Sat, 17 May 2025 17:35:45 +0200 Subject: [stm32] Wait until the PHYC PLL is stable --- src/portable/synopsys/dwc2/dwc2_stm32.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index c11c1eb05..0bbad55f5 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -222,6 +222,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // Enable PLL internal PHY USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + // Wait ~2ms until the PLL is ready (there's no RDY bit to query) + uint32_t count = (SystemCoreClock / 1000) * 2; + while (count--) __NOP(); #else #endif -- cgit v1.3.1 From c8baba10f9a7a6150348618aec74719522887c93 Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Wed, 9 Apr 2025 10:52:44 +0200 Subject: fix(dcd): Fixed race condition on device disconnect TinyUSB does not provide any locking means to protect the DCD variables. This can lead to race conditions when the user is trying to submit a transfer while the device is being disconnected. This can cause the device to be in an inconsistent state, leading to a crash or undefined behavior. This commit adds a spin-lock to protect the DCD variables during device disconnect. Closes https://github.com/espressif/esp-idf/issues/9691 Also reported in https://github.com/espressif/esp-usb/pull/131 --- src/portable/synopsys/dwc2/dcd_dwc2.c | 24 ++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_critical.h | 25 +++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 src/portable/synopsys/dwc2/dwc2_critical.h (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 52d675611..23273cb78 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -40,6 +40,7 @@ #include "device/dcd.h" #include "dwc2_common.h" +#include "dwc2_critical.h" //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM @@ -52,6 +53,9 @@ typedef struct { uint8_t interval; } xfer_ctl_t; +/* +This variable is modified from ISR context, so it must be protected by critical section +*/ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) @@ -321,6 +325,9 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } +// Since this function returns void, it is not possible to return a boolean success message +// We must make sure that this function is not called when the EP is disabled +// Must be called from critical section static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); @@ -531,6 +538,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + DCD_ENTER_CRITICAL(); _dcd_data.allocated_epin_count = 0; // Disable non-control interrupt @@ -550,6 +558,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_rx(dwc2); dfifo_device_init(rhport); // re-init dfifo + DCD_EXIT_CRITICAL(); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -568,7 +577,12 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + DCD_ENTER_CRITICAL(); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + if (xfer->max_size == 0) { + DCD_EXIT_CRITICAL(); + return false; // Endpoint is closed + } xfer->buffer = buffer; xfer->ff = NULL; xfer->total_len = total_bytes; @@ -580,6 +594,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir); + DCD_EXIT_CRITICAL(); return true; } @@ -595,7 +610,12 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + DCD_ENTER_CRITICAL(); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + if (xfer->max_size == 0) { + DCD_EXIT_CRITICAL(); + return false; // Endpoint is closed + } xfer->buffer = NULL; xfer->ff = ff; xfer->total_len = total_bytes; @@ -603,6 +623,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t // Schedule packets to be sent within interrupt // TODO xfer fifo may only available for slave mode edpt_schedule_packets(rhport, epnum, dir); + DCD_EXIT_CRITICAL(); return true; } @@ -631,6 +652,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { //-------------------------------------------------------------------- // 7.4.1 Initialization on USB Reset +// Must be called from critical section static void handle_bus_reset(uint8_t rhport) { dwc2_regs_t *dwc2 = DWC2_REG(rhport); const uint8_t ep_count = dwc2_ep_count(dwc2); @@ -989,8 +1011,10 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. + DCD_ENTER_CRITICAL(); dwc2->gintsts = GINTSTS_USBRST; handle_bus_reset(rhport); + DCD_EXIT_CRITICAL(); } if (gintsts & GINTSTS_ENUMDNE) { diff --git a/src/portable/synopsys/dwc2/dwc2_critical.h b/src/portable/synopsys/dwc2/dwc2_critical.h new file mode 100644 index 000000000..e2508c8fd --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_critical.h @@ -0,0 +1,25 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef TUSB_DWC2_CRITICAL_H_ +#define TUSB_DWC2_CRITICAL_H_ + +#include "common/tusb_mcu.h" + +#if defined(TUP_USBIP_DWC2_ESP32) + #include "freertos/FreeRTOS.h" + static portMUX_TYPE dcd_lock = portMUX_INITIALIZER_UNLOCKED; + #define DCD_ENTER_CRITICAL() portENTER_CRITICAL(&dcd_lock) + #define DCD_EXIT_CRITICAL() portEXIT_CRITICAL(&dcd_lock) + +#else + // Define critical section macros for DWC2 as no-op if not defined + // This is to avoid breaking existing code that does not use critical section + #define DCD_ENTER_CRITICAL() // no-op + #define DCD_EXIT_CRITICAL() // no-op +#endif + +#endif // TUSB_DWC2_CRITICAL_H_ -- cgit v1.3.1 From 72ee742761e5ed9cad29911ff19b8808972854ee Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 16 May 2025 20:09:02 +0700 Subject: add osal_critical API() for use with dwc2 --- src/osal/osal_freertos.h | 84 ++++++++++++++++++++++------------- src/osal/osal_none.h | 17 +++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 82 +++++++++++++++++++--------------- 3 files changed, 116 insertions(+), 67 deletions(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index a3a0f3a3f..ba998bfa1 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -42,20 +42,20 @@ extern "C" { //--------------------------------------------------------------------+ #if configSUPPORT_STATIC_ALLOCATION - typedef StaticSemaphore_t osal_semaphore_def_t; - typedef StaticSemaphore_t osal_mutex_def_t; +typedef StaticSemaphore_t osal_semaphore_def_t; +typedef StaticSemaphore_t osal_mutex_def_t; #else - // not used therefore defined to smallest possible type to save space - typedef uint8_t osal_semaphore_def_t; - typedef uint8_t osal_mutex_def_t; + +// not used therefore defined to the smallest possible type to save space +typedef uint8_t osal_semaphore_def_t; +typedef uint8_t osal_mutex_def_t; #endif typedef SemaphoreHandle_t osal_semaphore_t; typedef SemaphoreHandle_t osal_mutex_t; typedef QueueHandle_t osal_queue_t; -typedef struct -{ +typedef struct { uint16_t depth; uint16_t item_sz; void* buf; @@ -83,16 +83,14 @@ typedef struct //--------------------------------------------------------------------+ // TASK API //--------------------------------------------------------------------+ - TU_ATTR_ALWAYS_INLINE static inline uint32_t _osal_ms2tick(uint32_t msec) { - if ( msec == OSAL_TIMEOUT_WAIT_FOREVER ) return portMAX_DELAY; - if ( msec == 0 ) return 0; + if (msec == OSAL_TIMEOUT_WAIT_FOREVER) { return portMAX_DELAY; } + if (msec == 0) { return 0; } uint32_t ticks = pdMS_TO_TICKS(msec); - // configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms - // we still need to delay at least 1 tick - if ( ticks == 0 ) ticks = 1; + // If configTICK_RATE_HZ is less than 1000 and 1 tick > 1 ms, we still need to delay at least 1 tick + if (ticks == 0) { ticks = 1; } return ticks; } @@ -102,9 +100,47 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { } //--------------------------------------------------------------------+ -// Semaphore API +// Critical API //--------------------------------------------------------------------+ +#if TUSB_MCU_VENDOR_ESPRESSIF +// Espressif critical take spinlock as argument +typedef portMUX_TYPE osal_critical_t; + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { + spinlock_initialize(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { + portENTER_CRITICAL(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { + portEXIT_CRITICAL(ctx); +} +#else + +typedef uint8_t osal_critical_t; // not used + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { + (void) ctx; + portENTER_CRITICAL(); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { + (void) ctx; + portEXIT_CRITICAL(); +} + +#endif + +//--------------------------------------------------------------------+ +// Semaphore API +//--------------------------------------------------------------------+ TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t *semdef) { #if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateBinaryStatic(semdef); @@ -120,19 +156,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t } TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { - if ( !in_isr ) { + if (!in_isr) { return xSemaphoreGive(sem_hdl) != 0; } else { BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken); - -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 - // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 - if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); -#else portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#endif - return res != 0; } } @@ -148,7 +177,6 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t c //--------------------------------------------------------------------+ // MUTEX API (priority inheritance) //--------------------------------------------------------------------+ - TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) { #if configSUPPORT_STATIC_ALLOCATION return xSemaphoreCreateMutexStatic(mdef); @@ -174,7 +202,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd //--------------------------------------------------------------------+ // QUEUE API //--------------------------------------------------------------------+ - TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { osal_queue_t q; @@ -201,19 +228,12 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v } TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) { - if ( !in_isr ) { + if (!in_isr) { return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0; } else { BaseType_t xHigherPriorityTaskWoken = pdFALSE; BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken); - -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 - // not needed after https://github.com/espressif/esp-idf/commit/c5fd79547ac9b7bae06fa660e9f814d18d3390b7 (IDF v5) - if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR(); -#else portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#endif - return res != 0; } } diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 40e9bb83a..d9100cfdd 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -40,6 +40,23 @@ extern "C" { TU_ATTR_WEAK void osal_task_delay(uint32_t msec); #endif +//--------------------------------------------------------------------+ +// Critical API +//--------------------------------------------------------------------+ +typedef uint8_t osal_critical_t; // not used + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { + (void) ctx; +} + //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 23273cb78..5dd392409 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -40,7 +40,6 @@ #include "device/dcd.h" #include "dwc2_common.h" -#include "dwc2_critical.h" //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM @@ -53,12 +52,12 @@ typedef struct { uint8_t interval; } xfer_ctl_t; -/* -This variable is modified from ISR context, so it must be protected by critical section -*/ +// This variable is modified from ISR context, so it must be protected by critical section static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) +static osal_critical_t _dcd_critical; + typedef struct { // EP0 transfers are limited to 1 packet - larger sizes has to be split uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type @@ -394,6 +393,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); tu_memclr(&_dcd_data, sizeof(_dcd_data)); + osal_critical_init(&_dcd_critical); // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); @@ -538,7 +538,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - DCD_ENTER_CRITICAL(); + osal_critical_enter(&_dcd_critical); _dcd_data.allocated_epin_count = 0; // Disable non-control interrupt @@ -558,7 +558,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_rx(dwc2); dfifo_device_init(rhport); // re-init dfifo - DCD_EXIT_CRITICAL(); + osal_critical_exit(&_dcd_critical); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -576,27 +576,33 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpo bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - - DCD_ENTER_CRITICAL(); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + + bool ret; + + osal_critical_enter(&_dcd_critical); + if (xfer->max_size == 0) { - DCD_EXIT_CRITICAL(); - return false; // Endpoint is closed - } - xfer->buffer = buffer; - xfer->ff = NULL; - xfer->total_len = total_bytes; + ret = false; // Endpoint is closed + } else { + xfer->buffer = buffer; + xfer->ff = NULL; + xfer->total_len = total_bytes; - // EP0 can only handle one packet - if (epnum == 0) { - _dcd_data.ep0_pending[dir] = total_bytes; + // EP0 can only handle one packet + if (epnum == 0) { + _dcd_data.ep0_pending[dir] = total_bytes; + } + + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir); + + ret = true; } - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir); - DCD_EXIT_CRITICAL(); + osal_critical_exit(&_dcd_critical); - return true; + return ret; } // The number of bytes has to be given explicitly to allow more flexible control of how many @@ -609,23 +615,29 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - - DCD_ENTER_CRITICAL(); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); + + bool ret; + + osal_critical_enter(&_dcd_critical); + if (xfer->max_size == 0) { - DCD_EXIT_CRITICAL(); - return false; // Endpoint is closed + ret = false; // Endpoint is closed + } else { + xfer->buffer = NULL; + xfer->ff = ff; + xfer->total_len = total_bytes; + + // Schedule packets to be sent within interrupt + // TODO xfer fifo may only available for slave mode + edpt_schedule_packets(rhport, epnum, dir); + + ret = true; } - xfer->buffer = NULL; - xfer->ff = ff; - xfer->total_len = total_bytes; - // Schedule packets to be sent within interrupt - // TODO xfer fifo may only available for slave mode - edpt_schedule_packets(rhport, epnum, dir); - DCD_EXIT_CRITICAL(); + osal_critical_exit(&_dcd_critical); - return true; + return ret; } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { @@ -1011,10 +1023,10 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. - DCD_ENTER_CRITICAL(); + osal_critical_enter(&_dcd_critical); dwc2->gintsts = GINTSTS_USBRST; handle_bus_reset(rhport); - DCD_EXIT_CRITICAL(); + osal_critical_exit(&_dcd_critical); } if (gintsts & GINTSTS_ENUMDNE) { -- cgit v1.3.1 From 9aea7751f292f40684d4533196037c26e2239934 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 May 2025 18:57:39 +0700 Subject: dwc2 only enter critical in isr with multiple core CPUs --- src/common/tusb_mcu.h | 7 +++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 14 ++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a0175d664..6678265b5 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -369,6 +369,10 @@ #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ + #if CFG_TUSB_MCU == OPT_MCU_ESP32S3 + #define TUP_MCU_MULTIPLE_CORE 1 + #endif + // Disable slave if DMA is enabled #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE @@ -381,6 +385,8 @@ #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ + #define TUP_MCU_MULTIPLE_CORE 1 + // Disable slave if DMA is enabled #define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE @@ -410,6 +416,7 @@ #elif TU_CHECK_MCU(OPT_MCU_RP2040) #define TUP_DCD_EDPT_ISO_ALLOC #define TUP_DCD_ENDPOINT_MAX 16 + #define TUP_MCU_MULTIPLE_CORE 1 #define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb"))) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 5dd392409..dc00ba82b 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -539,6 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) { uint8_t const ep_count = _dwc2_controller[rhport].ep_count; osal_critical_enter(&_dcd_critical); + _dcd_data.allocated_epin_count = 0; // Disable non-control interrupt @@ -556,8 +557,8 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - dfifo_device_init(rhport); // re-init dfifo + osal_critical_exit(&_dcd_critical); } @@ -577,7 +578,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - bool ret; osal_critical_enter(&_dcd_critical); @@ -596,7 +596,6 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir); - ret = true; } @@ -616,7 +615,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); - bool ret; osal_critical_enter(&_dcd_critical); @@ -631,7 +629,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t // Schedule packets to be sent within interrupt // TODO xfer fifo may only available for slave mode edpt_schedule_packets(rhport, epnum, dir); - ret = true; } @@ -1017,16 +1014,21 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) { */ void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint32_t gintmask = dwc2->gintmsk; const uint32_t gintsts = dwc2->gintsts & gintmask; if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. + #if TUP_MCU_MULTIPLE_CORE osal_critical_enter(&_dcd_critical); + #endif + dwc2->gintsts = GINTSTS_USBRST; handle_bus_reset(rhport); + + #if TUP_MCU_MULTIPLE_CORE osal_critical_exit(&_dcd_critical); + #endif } if (gintsts & GINTSTS_ENUMDNE) { -- cgit v1.3.1 From bb1d348eb3908543f7bc80fc462d91bba62edace Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 May 2025 22:51:40 +0700 Subject: implement osal critical for none/freertos/pico-sdk --- src/device/usbd.c | 9 +++------ src/osal/osal_freertos.h | 30 +++++++++++++++++++++--------- src/osal/osal_none.h | 19 ++++++++++++++----- src/osal/osal_pico.h | 21 +++++++++++++++++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 19 ++++++++++--------- 5 files changed, 69 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 9c381d5e0..32de8740b 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1242,13 +1242,10 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) // USBD API For Class Driver //--------------------------------------------------------------------+ -void usbd_int_set(bool enabled) -{ - if (enabled) - { +void usbd_int_set(bool enabled) { + if (enabled) { dcd_int_enable(_usbd_rhport); - }else - { + } else { dcd_int_disable(_usbd_rhport); } } diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index ba998bfa1..5d6534709 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -102,38 +102,50 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { //--------------------------------------------------------------------+ // Critical API //--------------------------------------------------------------------+ +#define OSAL_CRITIAL_DEF(_name, _int_set) \ + osal_critical_t _name + #if TUSB_MCU_VENDOR_ESPRESSIF -// Espressif critical take spinlock as argument +// Espressif critical take spinlock as argument and does not use in_isr typedef portMUX_TYPE osal_critical_t; TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { spinlock_initialize(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { + (void) in_isr; portENTER_CRITICAL(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { + (void) in_isr; portEXIT_CRITICAL(ctx); } #else -typedef uint8_t osal_critical_t; // not used +typedef UBaseType_t osal_critical_t; TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { (void) ctx; } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { - (void) ctx; - portENTER_CRITICAL(); +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { + if (in_isr) { + *ctx = taskENTER_CRITICAL_FROM_ISR(); + } else { + taskENTER_CRITICAL(); + } } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { (void) ctx; - portEXIT_CRITICAL(); + if (in_isr) { + taskEXIT_CRITICAL_FROM_ISR(*ctx); + } else { + taskEXIT_CRITICAL(); + } } #endif diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index d9100cfdd..05a121ae6 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -43,18 +43,27 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec); //--------------------------------------------------------------------+ // Critical API //--------------------------------------------------------------------+ -typedef uint8_t osal_critical_t; // not used +typedef struct { + void (* interrupt_set)(bool); +} osal_critical_t; + +#define OSAL_CRITIAL_DEF(_name, _int_set) \ + osal_critical_t _name = { .interrupt_set = _int_set } TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { (void) ctx; } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx) { - (void) ctx; +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { + if (!in_isr) { + ctx->interrupt_set(false); + } } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx) { - (void) ctx; +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { + if (!in_isr) { + ctx->interrupt_set(true); + } } //--------------------------------------------------------------------+ diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h index 315de0950..be631ed18 100644 --- a/src/osal/osal_pico.h +++ b/src/osal/osal_pico.h @@ -43,6 +43,27 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { sleep_ms(msec); } +//--------------------------------------------------------------------+ +// Critical API +//--------------------------------------------------------------------+ +typedef critical_section_t osal_critical_t; +#define OSAL_CRITIAL_DEF(_name, _int_set) \ + osal_critical_t _name + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { + critical_section_init(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { + (void) in_isr; + critical_section_enter_blocking(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { + (void) in_isr; + critical_section_exit(ctx); +} + //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index dc00ba82b..4a2dad69e 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -39,6 +39,7 @@ #define DWC2_DEBUG 2 #include "device/dcd.h" +#include "device/usbd_pvt.h" #include "dwc2_common.h" //--------------------------------------------------------------------+ @@ -56,7 +57,7 @@ typedef struct { static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) -static osal_critical_t _dcd_critical; +static OSAL_CRITIAL_DEF(_dcd_critical, usbd_int_set); typedef struct { // EP0 transfers are limited to 1 packet - larger sizes has to be split @@ -538,7 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - osal_critical_enter(&_dcd_critical); + osal_critical_enter(&_dcd_critical, false); _dcd_data.allocated_epin_count = 0; @@ -559,7 +560,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_rx(dwc2); dfifo_device_init(rhport); // re-init dfifo - osal_critical_exit(&_dcd_critical); + osal_critical_exit(&_dcd_critical, false); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -580,7 +581,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_critical_enter(&_dcd_critical); + osal_critical_enter(&_dcd_critical, false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -599,7 +600,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to ret = true; } - osal_critical_exit(&_dcd_critical); + osal_critical_exit(&_dcd_critical, false); return ret; } @@ -617,7 +618,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_critical_enter(&_dcd_critical); + osal_critical_enter(&_dcd_critical, false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -632,7 +633,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t ret = true; } - osal_critical_exit(&_dcd_critical); + osal_critical_exit(&_dcd_critical, false); return ret; } @@ -1020,14 +1021,14 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. #if TUP_MCU_MULTIPLE_CORE - osal_critical_enter(&_dcd_critical); + osal_critical_enter(&_dcd_critical, true); #endif dwc2->gintsts = GINTSTS_USBRST; handle_bus_reset(rhport); #if TUP_MCU_MULTIPLE_CORE - osal_critical_exit(&_dcd_critical); + osal_critical_exit(&_dcd_critical, true); #endif } -- cgit v1.3.1 From a4875fefead1a2b27f13a588dea44eaca737f553 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 20 May 2025 16:18:00 +0700 Subject: rename osal_critcal to osal_spinlock add spinlock implementation for most rtos --- src/osal/osal.h | 4 ++++ src/osal/osal_freertos.h | 22 +++++++++++----------- src/osal/osal_mynewt.h | 22 ++++++++++++++++++++++ src/osal/osal_none.h | 15 ++++++++------- src/osal/osal_pico.h | 14 +++++++------- src/osal/osal_rtthread.h | 22 ++++++++++++++++++++++ src/osal/osal_rtx4.h | 19 +++++++++++++++++++ src/osal/osal_zephyr.h | 25 +++++++++++++++++++++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 20 ++++++++++---------- 9 files changed, 128 insertions(+), 35 deletions(-) (limited to 'src') diff --git a/src/osal/osal.h b/src/osal/osal.h index 38d45da44..a33280425 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -75,6 +75,10 @@ typedef void (*osal_task_func_t)( void * ); // OSAL Porting API // Should be implemented as static inline function in osal_port.h header /* + void osal_spin_init(osal_spinlock_t *ctx); + void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) + void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr); + osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef); bool osal_semaphore_delete(osal_semaphore_t semd_hdl); bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr); diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 5d6534709..09b6cb338 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -100,38 +100,38 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { } //--------------------------------------------------------------------+ -// Critical API +// Spinlock API //--------------------------------------------------------------------+ -#define OSAL_CRITIAL_DEF(_name, _int_set) \ - osal_critical_t _name +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name #if TUSB_MCU_VENDOR_ESPRESSIF // Espressif critical take spinlock as argument and does not use in_isr -typedef portMUX_TYPE osal_critical_t; +typedef portMUX_TYPE osal_spinlock_t; -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { spinlock_initialize(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { (void) in_isr; portENTER_CRITICAL(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { (void) in_isr; portEXIT_CRITICAL(ctx); } #else -typedef UBaseType_t osal_critical_t; +typedef UBaseType_t osal_spinlock_t; -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { (void) ctx; } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { if (in_isr) { *ctx = taskENTER_CRITICAL_FROM_ISR(); } else { @@ -139,7 +139,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ct } } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { (void) ctx; if (in_isr) { taskEXIT_CRITICAL_FROM_ISR(*ctx); diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h index 16def0d2a..58d226b10 100644 --- a/src/osal/osal_mynewt.h +++ b/src/osal/osal_mynewt.h @@ -40,6 +40,28 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { os_time_delay( os_time_ms_to_ticks32(msec) ); } +//--------------------------------------------------------------------+ +// Spinlock API +//--------------------------------------------------------------------+ +typedef os_sr_t osal_spinlock_t; + +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + OS_ENTER_CRITICAL(*ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + OS_ENTER_CRITICAL(*ctx); +} + //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 05a121ae6..2a0170ba4 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -41,26 +41,27 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec); #endif //--------------------------------------------------------------------+ -// Critical API +// Spinlock API //--------------------------------------------------------------------+ typedef struct { void (* interrupt_set)(bool); -} osal_critical_t; +} osal_spinlock_t; -#define OSAL_CRITIAL_DEF(_name, _int_set) \ - osal_critical_t _name = { .interrupt_set = _int_set } +// For SMP, spinlock must be locked by hardware, not use interrupt +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name = { .interrupt_set = _int_set } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { (void) ctx; } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { if (!in_isr) { ctx->interrupt_set(false); } } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { if (!in_isr) { ctx->interrupt_set(true); } diff --git a/src/osal/osal_pico.h b/src/osal/osal_pico.h index be631ed18..ace5907d7 100644 --- a/src/osal/osal_pico.h +++ b/src/osal/osal_pico.h @@ -44,22 +44,22 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { } //--------------------------------------------------------------------+ -// Critical API +// Spinlock API //--------------------------------------------------------------------+ -typedef critical_section_t osal_critical_t; -#define OSAL_CRITIAL_DEF(_name, _int_set) \ - osal_critical_t _name +typedef critical_section_t osal_spinlock_t; // pico implement critical section with spinlock +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_init(osal_critical_t *ctx) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { critical_section_init(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_enter(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { (void) in_isr; critical_section_enter_blocking(ctx); } -TU_ATTR_ALWAYS_INLINE static inline void osal_critical_exit(osal_critical_t *ctx, bool in_isr) { +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { (void) in_isr; critical_section_exit(ctx); } diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index c27814835..97f5dc69a 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -42,6 +42,28 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { rt_thread_mdelay(msec); } +//--------------------------------------------------------------------+ +// Spinlock API +//--------------------------------------------------------------------+ +typedef struct rt_spinlock osal_spinlock_t; + +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { + rt_spin_lock_init(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + rt_spin_lock(ctx); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + rt_spin_unlock(ctx); +} + //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_rtx4.h b/src/osal/osal_rtx4.h index 35909e4d6..35860ddd5 100644 --- a/src/osal/osal_rtx4.h +++ b/src/osal/osal_rtx4.h @@ -56,6 +56,25 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t msec2wait(uint32_t msec) { } } +//--------------------------------------------------------------------+ +// Spinlock API, stub not implemented +//--------------------------------------------------------------------+ +typedef uint8_t osal_spinlock_t; +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { + (void) ctx; (void) in_isr; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { + (void) ctx; (void) in_isr; +} + //--------------------------------------------------------------------+ // Semaphore API //--------------------------------------------------------------------+ diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h index 8ecb13c6d..7a43b8ec1 100644 --- a/src/osal/osal_zephyr.h +++ b/src/osal/osal_zephyr.h @@ -35,6 +35,31 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { k_msleep(msec); } +//--------------------------------------------------------------------+ +// Spinlock API +//--------------------------------------------------------------------+ +typedef struct { + struct k_spinlock lock; + k_spinlock_key_t key; +} osal_spinlock_t; + +#define OSAL_SPINLOCK_DEF(_name, _int_set) \ + osal_spinlock_t _name + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { + (void) ctx; +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + ctx->key = k_spin_lock(&ctx->lock); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { + (void) in_isr; + k_spin_unlock(&ctx->lock, ctx->key); +} + //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 4a2dad69e..67484c3df 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -57,7 +57,7 @@ typedef struct { static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) -static OSAL_CRITIAL_DEF(_dcd_critical, usbd_int_set); +static OSAL_SPINLOCK_DEF(_dcd_spinlock, usbd_int_set); typedef struct { // EP0 transfers are limited to 1 packet - larger sizes has to be split @@ -394,7 +394,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); tu_memclr(&_dcd_data, sizeof(_dcd_data)); - osal_critical_init(&_dcd_critical); + osal_spin_init(&_dcd_spinlock); // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); @@ -539,7 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - osal_critical_enter(&_dcd_critical, false); + osal_spin_lock(&_dcd_spinlock, false); _dcd_data.allocated_epin_count = 0; @@ -560,7 +560,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_rx(dwc2); dfifo_device_init(rhport); // re-init dfifo - osal_critical_exit(&_dcd_critical, false); + osal_spin_unlock(&_dcd_spinlock, false); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -581,7 +581,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_critical_enter(&_dcd_critical, false); + osal_spin_lock(&_dcd_spinlock, false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -600,7 +600,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to ret = true; } - osal_critical_exit(&_dcd_critical, false); + osal_spin_unlock(&_dcd_spinlock, false); return ret; } @@ -618,7 +618,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_critical_enter(&_dcd_critical, false); + osal_spin_lock(&_dcd_spinlock, false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -633,7 +633,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t ret = true; } - osal_critical_exit(&_dcd_critical, false); + osal_spin_unlock(&_dcd_spinlock, false); return ret; } @@ -1021,14 +1021,14 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. #if TUP_MCU_MULTIPLE_CORE - osal_critical_enter(&_dcd_critical, true); + osal_spin_lock(&_dcd_spinlock, true); #endif dwc2->gintsts = GINTSTS_USBRST; handle_bus_reset(rhport); #if TUP_MCU_MULTIPLE_CORE - osal_critical_exit(&_dcd_critical, true); + osal_spin_unlock(&_dcd_spinlock, true); #endif } -- cgit v1.3.1 From c1d23a0a92bef016e22be3ed8194230cfab1c358 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 May 2025 11:19:07 +0700 Subject: osal_spin skipping lock/unlock when executed in isr --- src/osal/osal_freertos.h | 17 ++++++++++++++--- src/osal/osal_mynewt.h | 8 ++++++-- src/osal/osal_none.h | 2 +- src/osal/osal_rtthread.h | 8 ++++++-- src/osal/osal_zephyr.h | 8 ++++++-- src/portable/synopsys/dwc2/dcd_dwc2.c | 9 ++------- src/portable/synopsys/dwc2/dwc2_esp32.h | 4 ++-- 7 files changed, 37 insertions(+), 19 deletions(-) (limited to 'src') diff --git a/src/osal/osal_freertos.h b/src/osal/osal_freertos.h index 09b6cb338..bde5ec010 100644 --- a/src/osal/osal_freertos.h +++ b/src/osal/osal_freertos.h @@ -114,12 +114,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } portENTER_CRITICAL(ctx); } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } portEXIT_CRITICAL(ctx); } @@ -133,6 +137,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { if (in_isr) { + if (!TUP_MCU_MULTIPLE_CORE) { + (void) ctx; + return; // single core MCU does not need to lock in ISR + } *ctx = taskENTER_CRITICAL_FROM_ISR(); } else { taskENTER_CRITICAL(); @@ -140,8 +148,11 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bo } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { - (void) ctx; if (in_isr) { + if (!TUP_MCU_MULTIPLE_CORE) { + (void) ctx; + return; // single core MCU does not need to lock in ISR + } taskEXIT_CRITICAL_FROM_ISR(*ctx); } else { taskEXIT_CRITICAL(); diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h index 58d226b10..ee95e684f 100644 --- a/src/osal/osal_mynewt.h +++ b/src/osal/osal_mynewt.h @@ -53,12 +53,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } OS_ENTER_CRITICAL(*ctx); } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } OS_ENTER_CRITICAL(*ctx); } diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 2a0170ba4..a8eb1042b 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -47,7 +47,7 @@ typedef struct { void (* interrupt_set)(bool); } osal_spinlock_t; -// For SMP, spinlock must be locked by hardware, not use interrupt +// For SMP, spinlock must be locked by hardware, cannot just use interrupt #define OSAL_SPINLOCK_DEF(_name, _int_set) \ osal_spinlock_t _name = { .interrupt_set = _int_set } diff --git a/src/osal/osal_rtthread.h b/src/osal/osal_rtthread.h index 97f5dc69a..a778f5425 100644 --- a/src/osal/osal_rtthread.h +++ b/src/osal/osal_rtthread.h @@ -55,12 +55,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } rt_spin_lock(ctx); } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } rt_spin_unlock(ctx); } diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h index 7a43b8ec1..91f225f79 100644 --- a/src/osal/osal_zephyr.h +++ b/src/osal/osal_zephyr.h @@ -51,12 +51,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) { } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } ctx->key = k_spin_lock(&ctx->lock); } TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) { - (void) in_isr; + if (!TUP_MCU_MULTIPLE_CORE && in_isr) { + return; // single core MCU does not need to lock in ISR + } k_spin_unlock(&ctx->lock, ctx->key); } diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 67484c3df..19eac6e15 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1020,16 +1020,11 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. - #if TUP_MCU_MULTIPLE_CORE - osal_spin_lock(&_dcd_spinlock, true); - #endif - dwc2->gintsts = GINTSTS_USBRST; - handle_bus_reset(rhport); - #if TUP_MCU_MULTIPLE_CORE + osal_spin_lock(&_dcd_spinlock, true); + handle_bus_reset(rhport); osal_spin_unlock(&_dcd_spinlock, true); - #endif } if (gintsts & GINTSTS_ENUMDNE) { diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 3309760ff..49b8c54cb 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -55,8 +55,8 @@ static const dwc2_controller_t _dwc2_controller[] = { // On ESP32 for consistency we associate // - Port0 to OTG_FS, and Port1 to OTG_HS static const dwc2_controller_t _dwc2_controller[] = { -{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }, -{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 } + { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }, + { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 } }; #endif -- cgit v1.3.1 From 5551a3e430c1a330ec2a09121abc79fbb7b3c7b0 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 May 2025 11:41:06 +0700 Subject: add usbd_spin_lock/unlock for driver usage --- src/device/usbd.c | 22 ++++++++++++++++------ src/device/usbd_pvt.h | 2 ++ src/portable/synopsys/dwc2/dcd_dwc2.c | 19 ++++++++----------- 3 files changed, 26 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 32de8740b..6e5fcf3b6 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -340,15 +340,16 @@ TU_ATTR_ALWAYS_INLINE static inline usbd_class_driver_t const * get_driver(uint8 enum { RHPORT_INVALID = 0xFFu }; tu_static uint8_t _usbd_rhport = RHPORT_INVALID; -// Event queue -// usbd_int_set() is used as mutex in OS NONE config +static OSAL_SPINLOCK_DEF(_usbd_spin, usbd_int_set); + +// Event queue: usbd_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbd_int_set, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t); -tu_static osal_queue_t _usbd_q; +static osal_queue_t _usbd_q; // Mutex for claiming endpoint #if OSAL_MUTEX_REQUIRED - tu_static osal_mutex_def_t _ubsd_mutexdef; - tu_static osal_mutex_t _usbd_mutex; + static osal_mutex_def_t _ubsd_mutexdef; + static osal_mutex_t _usbd_mutex; #else #define _usbd_mutex NULL #endif @@ -466,7 +467,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { TU_ASSERT(rh_init); TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport, - rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full"); + rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full"); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(tu_fifo_t)); @@ -475,6 +476,8 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { tu_varclr(&_usbd_dev); _usbd_queued_setup = 0; + osal_spin_init(&_usbd_spin); + #if OSAL_MUTEX_REQUIRED // Init device mutex _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef); @@ -1250,6 +1253,13 @@ void usbd_int_set(bool enabled) { } } +void usbd_spin_lock(bool in_isr) { + osal_spin_lock(&_usbd_spin, in_isr); +} +void usbd_spin_unlock(bool in_isr) { + osal_spin_unlock(&_usbd_spin, in_isr); +} + // Parse consecutive endpoint descriptors (IN & OUT) bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in) { diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 190d6fd7f..5c6f9dbee 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -68,6 +68,8 @@ usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); void usbd_int_set(bool enabled); +void usbd_spin_lock(bool in_isr); +void usbd_spin_unlock(bool in_isr); //--------------------------------------------------------------------+ // USBD Endpoint API diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 19eac6e15..865c51894 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -57,8 +57,6 @@ typedef struct { static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) -static OSAL_SPINLOCK_DEF(_dcd_spinlock, usbd_int_set); - typedef struct { // EP0 transfers are limited to 1 packet - larger sizes has to be split uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type @@ -394,7 +392,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); tu_memclr(&_dcd_data, sizeof(_dcd_data)); - osal_spin_init(&_dcd_spinlock); // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); @@ -539,7 +536,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - osal_spin_lock(&_dcd_spinlock, false); + usbd_spin_lock(false); _dcd_data.allocated_epin_count = 0; @@ -560,7 +557,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_rx(dwc2); dfifo_device_init(rhport); // re-init dfifo - osal_spin_unlock(&_dcd_spinlock, false); + usbd_spin_unlock(false); } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -581,7 +578,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_spin_lock(&_dcd_spinlock, false); + usbd_spin_lock(false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -600,7 +597,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to ret = true; } - osal_spin_unlock(&_dcd_spinlock, false); + usbd_spin_unlock(false); return ret; } @@ -618,7 +615,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); bool ret; - osal_spin_lock(&_dcd_spinlock, false); + usbd_spin_lock(false); if (xfer->max_size == 0) { ret = false; // Endpoint is closed @@ -633,7 +630,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t ret = true; } - osal_spin_unlock(&_dcd_spinlock, false); + usbd_spin_unlock(false); return ret; } @@ -1022,9 +1019,9 @@ void dcd_int_handler(uint8_t rhport) { // USBRST is start of reset. dwc2->gintsts = GINTSTS_USBRST; - osal_spin_lock(&_dcd_spinlock, true); + usbd_spin_lock(true); handle_bus_reset(rhport); - osal_spin_unlock(&_dcd_spinlock, true); + usbd_spin_unlock(true); } if (gintsts & GINTSTS_ENUMDNE) { -- cgit v1.3.1 From 58dfc126ac96d151bc6a9e9ee8bda564b52c350f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 May 2025 14:36:53 +0700 Subject: remove unused dwc2_critical.h --- src/portable/synopsys/dwc2/dwc2_critical.h | 25 ------------------------- 1 file changed, 25 deletions(-) delete mode 100644 src/portable/synopsys/dwc2/dwc2_critical.h (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_critical.h b/src/portable/synopsys/dwc2/dwc2_critical.h deleted file mode 100644 index e2508c8fd..000000000 --- a/src/portable/synopsys/dwc2/dwc2_critical.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef TUSB_DWC2_CRITICAL_H_ -#define TUSB_DWC2_CRITICAL_H_ - -#include "common/tusb_mcu.h" - -#if defined(TUP_USBIP_DWC2_ESP32) - #include "freertos/FreeRTOS.h" - static portMUX_TYPE dcd_lock = portMUX_INITIALIZER_UNLOCKED; - #define DCD_ENTER_CRITICAL() portENTER_CRITICAL(&dcd_lock) - #define DCD_EXIT_CRITICAL() portEXIT_CRITICAL(&dcd_lock) - -#else - // Define critical section macros for DWC2 as no-op if not defined - // This is to avoid breaking existing code that does not use critical section - #define DCD_ENTER_CRITICAL() // no-op - #define DCD_EXIT_CRITICAL() // no-op -#endif - -#endif // TUSB_DWC2_CRITICAL_H_ -- cgit v1.3.1 From e41a63c60dbebd9579698e6444bc62cfa518e15c Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 21 May 2025 15:27:18 +0700 Subject: add usbh_spin_lock/unlock() use spinlock instead of atomic flag for hcd max3421 --- .../boards/adafruit_feather_esp32c6/board.cmake | 3 + .../boards/adafruit_feather_esp32c6/board.h | 56 ++++++++++++++++++ hw/bsp/espressif/boards/family.c | 2 + src/host/usbh.c | 13 ++++ src/host/usbh_pvt.h | 3 + src/portable/analog/max3421/hcd_max3421.c | 69 ++++++++++++++++------ 6 files changed, 129 insertions(+), 17 deletions(-) create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h (limited to 'src') diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake new file mode 100644 index 000000000..9adaefb17 --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.cmake @@ -0,0 +1,3 @@ +# Apply board specific content here +set(IDF_TARGET "esp32c6") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h new file mode 100644 index 000000000..18b51410d --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32c6/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Adafruit Feather EPS32-C6 + url: https://www.adafruit.com/product/5933 +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define NEOPIXEL_PIN 15 + +#define BUTTON_PIN 9 +#define BUTTON_STATE_ACTIVE 0 + +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 21 +#define MAX3421_MOSI_PIN 22 +#define MAX3421_MISO_PIN 23 +#define MAX3421_CS_PIN 8 +#define MAX3421_INTR_PIN 7 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index cf11e2441..8f6c4bee2 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -49,7 +49,9 @@ static led_strip_handle_t led_strip; static void max3421_init(void); #endif +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) static bool usb_init(void); +#endif //--------------------------------------------------------------------+ // Implementation diff --git a/src/host/usbh.c b/src/host/usbh.c index b7d5a05f2..f2e5c1f0e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -147,6 +147,9 @@ static osal_mutex_t _usbh_mutex; #define _usbh_mutex NULL #endif +// Spinlock for interrupt handler +static OSAL_SPINLOCK_DEF(_usbh_spin, usbh_int_set); + // Event queue: usbh_int_set() is used as mutex in OS NONE config OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; @@ -424,6 +427,8 @@ bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { TU_LOG_INT_USBH(sizeof(tu_fifo_t)); TU_LOG_INT_USBH(sizeof(tu_edpt_stream_t)); + osal_spin_init(&_usbh_spin); + // Event queue _usbh_q = osal_queue_create(&_usbh_qdef); TU_ASSERT(_usbh_q != NULL); @@ -895,6 +900,14 @@ void usbh_int_set(bool enabled) { } } +void usbh_spin_lock(bool in_isr) { + osal_spin_lock(&_usbh_spin, in_isr); +} + +void usbh_spin_unlock(bool in_isr) { + osal_spin_unlock(&_usbh_spin, in_isr); +} + void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr) { hcd_event_t event = { 0 }; event.event_id = USBH_EVENT_FUNC_CALL; diff --git a/src/host/usbh_pvt.h b/src/host/usbh_pvt.h index 61b012493..cb092e5f3 100644 --- a/src/host/usbh_pvt.h +++ b/src/host/usbh_pvt.h @@ -71,6 +71,9 @@ void usbh_int_set(bool enabled); void usbh_defer_func(osal_task_func_t func, void *param, bool in_isr); +void usbh_spin_lock(bool in_isr); +void usbh_spin_unlock(bool in_isr); + //--------------------------------------------------------------------+ // USBH Endpoint API //--------------------------------------------------------------------+ diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index bb33200f2..971dbd62e 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -28,9 +28,9 @@ #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 -#include #include "host/hcd.h" #include "host/usbh.h" +#include "host/usbh_pvt.h" //--------------------------------------------------------------------+ // @@ -233,7 +233,7 @@ typedef struct { uint8_t hxfr; }sndfifo_owner; - atomic_flag busy; // busy transferring + bool busy_lock; // busy transferring #if OSAL_MUTEX_REQUIRED OSAL_MUTEX_DEF(spi_mutexdef); @@ -327,7 +327,9 @@ TU_ATTR_ALWAYS_INLINE static inline void mode_write(uint8_t rhport, uint8_t data } TU_ATTR_ALWAYS_INLINE static inline void peraddr_write(uint8_t rhport, uint8_t data, bool in_isr) { - if ( _hcd_data.peraddr == data ) return; // no need to change address + if (_hcd_data.peraddr == data) { + return; // no need to change address + } _hcd_data.peraddr = data; reg_write(rhport, PERADDR_ADDR, data, in_isr); @@ -373,7 +375,7 @@ TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { uint8_t hirq; - uint8_t const reg = RCVVFIFO_ADDR; + const uint8_t reg = RCVVFIFO_ADDR; max3421_spi_lock(rhport, in_isr); @@ -389,7 +391,7 @@ static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool //--------------------------------------------------------------------+ static max3421_ep_t* find_ep_not_addr0(uint8_t daddr, uint8_t ep_num, uint8_t ep_dir) { - uint8_t const is_out = 1-ep_dir; + const uint8_t is_out = 1-ep_dir; for(size_t i=1; ixferred_len = 0; ep->state = EP_STATE_ATTEMPT_1; + bool has_xfer = false; + + usbh_spin_lock(false); + if (!_hcd_data.busy_lock) { + _hcd_data.busy_lock = true; + has_xfer = true; + } + usbh_spin_unlock(false); + // carry out transfer if not busy - if (!atomic_flag_test_and_set(&_hcd_data.busy)) { + if (has_xfer) { xact_generic(rhport, ep, true, false); } @@ -781,8 +792,17 @@ bool hcd_setup_send(uint8_t rhport, uint8_t daddr, uint8_t const setup_packet[8] ep->xferred_len = 0; ep->state = EP_STATE_ATTEMPT_1; + bool has_xfer = false; + + usbh_spin_lock(false); + if (!_hcd_data.busy_lock) { + _hcd_data.busy_lock = true; + has_xfer = true; + } + usbh_spin_unlock(false); + // carry out transfer if not busy - if (!atomic_flag_test_and_set(&_hcd_data.busy)) { + if (has_xfer) { xact_setup(rhport, ep, false); } @@ -848,8 +868,8 @@ static void handle_connect_irq(uint8_t rhport, bool in_isr) { } static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t result, uint8_t hrsl, bool in_isr) { - uint8_t const ep_dir = 1-ep->hxfr_bm.is_out; - uint8_t const ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir); + const uint8_t ep_dir = 1 - ep->hxfr_bm.is_out; + const uint8_t ep_addr = tu_edpt_addr(ep->hxfr_bm.ep_num, ep_dir); // save data toggle if (ep_dir) { @@ -867,7 +887,9 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re xact_generic(rhport, next_ep, true, in_isr); }else { // no more pending - atomic_flag_clear(&_hcd_data.busy); + usbh_spin_lock(in_isr); + _hcd_data.busy_lock = false; + usbh_spin_unlock(in_isr); } } @@ -906,7 +928,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { xact_generic(rhport, next_ep, true, in_isr); } else { // no more pending in this frame -> clear busy - atomic_flag_clear(&_hcd_data.busy); + usbh_spin_lock(in_isr); + _hcd_data.busy_lock = false; + usbh_spin_unlock(in_isr); } return; @@ -997,8 +1021,8 @@ void print_hirq(uint8_t hirq) { // Interrupt handler void hcd_int_handler(uint8_t rhport, bool in_isr) { uint8_t hirq = reg_read(rhport, HIRQ_ADDR, in_isr) & _hcd_data.hien; - if (!hirq) return; -// print_hirq(hirq); + if (!hirq) { return; } + // print_hirq(hirq); if (hirq & HIRQ_FRAME_IRQ) { _hcd_data.frame_count++; @@ -1017,8 +1041,19 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } // start usb transfer if not busy - if (ep_retry != NULL && !atomic_flag_test_and_set(&_hcd_data.busy)) { - xact_generic(rhport, ep_retry, true, in_isr); + if (ep_retry != NULL) { + bool has_xfer = false; + + usbh_spin_lock(in_isr); + if (!_hcd_data.busy_lock) { + _hcd_data.busy_lock = true; + has_xfer = true; + } + usbh_spin_unlock(in_isr); + + if (has_xfer) { + xact_generic(rhport, ep_retry, true, in_isr); + } } } -- cgit v1.3.1 From 1a13bd8eba883aa9d1fda8f95823db8217c912f4 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 23 May 2025 13:27:27 +0200 Subject: Add comment about CFG_TUD_CI_HS_VBUS_CHARGE Signed-off-by: HiFiPhile --- src/tusb_option.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/tusb_option.h b/src/tusb_option.h index 679b80420..6d733a429 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -267,7 +267,7 @@ #define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT #endif -// Enable CI_HS VBUS Charge +// Enable CI_HS VBUS Charge. Set this to 1 if the USB_VBUS pin is not connected to 5V VBUS (note: 3.3V is insufficient). #ifndef CFG_TUD_CI_HS_VBUS_CHARGE #ifndef CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT #define CFG_TUD_CI_HS_VBUS_CHARGE_DEFAULT 0 -- cgit v1.3.1 From 132c55aca0aa9bb68b4ffb96ec89947e08e19b88 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 28 May 2025 08:38:26 +0700 Subject: add OPT_MCU_MAX32665 --- .github/workflows/codeql.yml | 2 +- src/CMakeLists.txt | 5 +---- src/tusb_option.h | 1 + tools/build.py | 4 ++-- 4 files changed, 5 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index a22c65c79..dfcca6315 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -124,7 +124,7 @@ jobs: output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - name: Upload SARIF - uses: github/codeql-action/upload-sarif@v2 + uses: github/codeql-action/upload-sarif@v3 with: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 55c52033c..99d3059fc 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,9 +1,6 @@ -# TODO more docs and example on how to use this file -# TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target - cmake_minimum_required(VERSION 3.20) -# Add tinyusb to a existing target +# Add tinyusb to a existing target, DCD and HCD drivers are not included function(tinyusb_target_add TARGET) target_sources(${TARGET} PRIVATE # common diff --git a/src/tusb_option.h b/src/tusb_option.h index 6d733a429..104f669c9 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -195,6 +195,7 @@ // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 +#define OPT_MCU_MAX32665 2401 ///< ADI MAX32666/5 #define OPT_MCU_MAX32666 2401 ///< ADI MAX32666/5 #define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 #define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 diff --git a/tools/build.py b/tools/build.py index f2f6e6228..6e73681fe 100755 --- a/tools/build.py +++ b/tools/build.py @@ -101,13 +101,13 @@ def cmake_board(board, toolchain, build_flags_on): if build_utils.skip_example(example, board): ret[2] += 1 else: - rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" ' + rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G Ninja ' f'-DBOARD={board} {build_flags}') if rcmd.returncode == 0: rcmd = run_cmd(f'cmake --build {build_dir}/{example}') ret[0 if rcmd.returncode == 0 else 1] += 1 else: - rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' + rcmd = run_cmd(f'cmake examples -B {build_dir} -G Ninja -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel ' f'-DTOOLCHAIN={toolchain} {build_flags}') if rcmd.returncode == 0: cmd = f"cmake --build {build_dir}" -- cgit v1.3.1 From 5de4a23abe315ecc5f9387ced910f54e29e0e69e Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 27 May 2025 15:06:05 +1000 Subject: Add USB NCM link state control support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the ability to dynamically control the network link state for NCM devices. The host OS will see the network interface as connected/disconnected based on the link state. New API: - tud_network_link_state(rhport, is_up): Set link up/down state Example updates: - Added button control to toggle link state - Fixed LWIP integration to properly handle link state changes - Added printf to show correct protocol (NCM vs RNDIS/ECM) 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- examples/device/net_lwip_webserver/src/lwipopts.h | 1 + examples/device/net_lwip_webserver/src/main.c | 73 +++++++++++++++++++--- .../device/net_lwip_webserver/src/tusb_config.h | 2 + src/class/net/ncm_device.c | 36 ++++++++++- src/class/net/net_device.h | 5 ++ 5 files changed, 107 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/examples/device/net_lwip_webserver/src/lwipopts.h b/examples/device/net_lwip_webserver/src/lwipopts.h index 41e8f0d67..04949cef9 100644 --- a/examples/device/net_lwip_webserver/src/lwipopts.h +++ b/examples/device/net_lwip_webserver/src/lwipopts.h @@ -58,6 +58,7 @@ #define LWIP_HTTPD_SSI_INCLUDE_TAG 0 #define LWIP_SINGLE_NETIF 1 +#define LWIP_NETIF_LINK_CALLBACK 1 #define PBUF_POOL_SIZE 4 diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 36f402332..41f02576f 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -31,6 +31,12 @@ this appears as either a RNDIS or CDC-ECM USB virtual network adapter; the OS pi RNDIS should be valid on Linux and Windows hosts, and CDC-ECM should be valid on Linux and macOS hosts The MCU appears to the host as IP address 192.168.7.1, and provides a DHCP server, DNS server, and web server. + +Link State Control: +- Press the user button to toggle the network link state (UP/DOWN) +- This simulates "ethernet cable unplugged/plugged" events +- The host OS will see the network interface as disconnected/connected accordingly +- Use this to test network error handling and recovery in host applications */ /* Some smartphones *may* work with this implementation as well, but likely have limited (broken) drivers, @@ -137,6 +143,12 @@ static err_t netif_init_cb(struct netif *netif) { return ERR_OK; } +/* notifies the USB host about the link state change. */ +static void usbnet_netif_link_callback(struct netif *netif) { + bool link_up = netif_is_link_up(netif); + tud_network_link_state(BOARD_TUD_RHPORT, link_up); +} + static void init_lwip(void) { struct netif *netif = &netif_data; @@ -147,11 +159,19 @@ static void init_lwip(void) { memcpy(netif->hwaddr, tud_network_mac_address, sizeof(tud_network_mac_address)); netif->hwaddr[5] ^= 0x01; - netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ip_input); + netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, netif_init_cb, ethernet_input); #if LWIP_IPV6 netif_create_ip6_linklocal_address(netif, 1); #endif netif_set_default(netif); + +#if LWIP_NETIF_LINK_CALLBACK + // Set the link callback to notify USB host about link state changes + netif_set_link_callback(netif, usbnet_netif_link_callback); + netif_set_link_up(netif); +#else + tud_network_link_state(BOARD_TUD_RHPORT, true); +#endif } /* handle any DNS requests from dns-server */ @@ -171,13 +191,16 @@ bool tud_network_recv_cb(const uint8_t *src, uint16_t size) { if (size) { struct pbuf *p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); - if (p) { - /* pbuf_alloc() has already initialized struct; all we need to do is copy the data */ - memcpy(p->payload, src, size); - - /* store away the pointer for service_traffic() to later handle */ - received_frame = p; + if (p == NULL) { + printf("ERROR: Failed to allocate pbuf of size %d\n", size); + return false; } + + /* Copy buf to pbuf */ + pbuf_take(p, src, size); + + /* store away the pointer for service_traffic() to later handle */ + received_frame = p; } return true; @@ -194,12 +217,14 @@ uint16_t tud_network_xmit_cb(uint8_t *dst, void *ref, uint16_t arg) { static void service_traffic(void) { /* handle any packet received by tud_network_recv_cb() */ if (received_frame) { + struct netif *netif = &netif_data; // Surrender ownership of our pbuf unless there was an error // Only call pbuf_free if not Ok else it will panic with "pbuf_free: p->ref > 0" // or steal it from whatever took ownership of it with undefined consequences. // See: https://savannah.nongnu.org/patch/index.php?10121 - if (ethernet_input(received_frame, &netif_data)!=ERR_OK) { - pbuf_free(received_frame); + if (netif->input(received_frame, netif) != ERR_OK) { + printf("ERROR: netif input failed\n"); + pbuf_free(received_frame); } received_frame = NULL; tud_network_recv_renew(); @@ -216,6 +241,28 @@ void tud_network_init_cb(void) { } } +static void handle_link_state_switch(void) { + /* Check for button press to toggle link state */ + static bool last_link_state = true; + static bool last_button_state = false; + bool current_button_state = board_button_read(); + + if (current_button_state && !last_button_state) { + /* Button pressed - toggle link state */ + last_link_state = !last_link_state; + if (last_link_state) { + printf("Link state: UP\n"); + netif_set_link_up(&netif_data); + } else { + printf("Link state: DOWN\n"); + netif_set_link_down(&netif_data); + } + /* LWIP callback will notify USB host about the change */ + } + last_button_state = current_button_state; + +} + int main(void) { /* initialize TinyUSB */ board_init(); @@ -243,15 +290,23 @@ int main(void) { lwiperf_start_tcp_server_default(NULL, NULL); #endif +#if CFG_TUD_NCM + printf("USB NCM network interface initialized\n"); +#elif CFG_TUD_ECM_RNDIS + printf("USB RNDIS/ECM network interface initialized\n"); +#endif + while (1) { tud_task(); service_traffic(); + handle_link_state_switch(); } return 0; } /* lwip has provision for using a mutex, when applicable */ +/* This implementation is for single-threaded use only */ sys_prot_t sys_arch_protect(void) { return 0; } diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index 22082fc81..c774f59ff 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -85,6 +85,7 @@ extern "C" { #endif // Use different configurations to test all net devices (also due to resource limitations) +#ifndef USE_ECM #if TU_CHECK_MCU(OPT_MCU_LPC15XX, OPT_MCU_LPC40XX, OPT_MCU_LPC51UXX, OPT_MCU_LPC54) #define USE_ECM 1 #elif TU_CHECK_MCU(OPT_MCU_SAMD21, OPT_MCU_SAML21, OPT_MCU_SAML22) @@ -97,6 +98,7 @@ extern "C" { #define USE_ECM 0 #define INCLUDE_IPERF #endif +#endif //-------------------------------------------------------------------- // NCM CLASS CONFIGURATION, SEE "ncm.h" FOR PERFORMANCE TUNING diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index f9fda0698..02833c5f1 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -110,6 +110,7 @@ typedef struct { NOTIFICATION_DONE } notification_xmit_state; // state of notification transmission bool notification_xmit_is_running; // notification is currently transmitted + bool link_is_up; // current link state // misc bool tud_network_recv_renew_active; // tud_network_recv_renew() is active (avoid recursive invocations) @@ -218,7 +219,7 @@ static void notification_xmit(uint8_t rhport, bool force_next) { .direction = TUSB_DIR_IN }, .bRequest = CDC_NOTIF_NETWORK_CONNECTION, - .wValue = 1 /* Connected */, + .wValue = ncm_interface.link_is_up ? 1 : 0, /* Dynamic link state */ .wIndex = ncm_interface.itf_num, .wLength = 0, }, @@ -232,6 +233,7 @@ static void notification_xmit(uint8_t rhport, bool force_next) { ncm_interface.notification_xmit_is_running = true; } else { TU_LOG_DRV(" NOTIFICATION_FINISHED\n"); + ncm_interface.notification_xmit_is_running = false; } } // notification_xmit @@ -755,6 +757,32 @@ static void tud_network_recv_renew_r(uint8_t rhport) { tud_network_recv_renew(); } // tud_network_recv_renew +/** + * Set the link state and send notification to host + */ +void tud_network_link_state(uint8_t rhport, bool is_up) { + TU_LOG_DRV("tud_network_link_state(%d, %d)\n", rhport, is_up); + + if (ncm_interface.link_is_up == is_up) { + // No change in link state + return; + } + + ncm_interface.link_is_up = is_up; + + // Only send notification if we have an active data interface + if (ncm_interface.itf_data_alt != 1) { + TU_LOG_DRV(" link state notification skipped (interface not active)\n"); + return; + } + + // Reset notification state to send link state update + ncm_interface.notification_xmit_state = NOTIFICATION_CONNECTED; + + // Trigger notification transmission + notification_xmit(rhport, false); +} + //----------------------------------------------------------------------------- // // all the netd_*() stuff (interface TinyUSB -> driver) @@ -774,6 +802,12 @@ void netd_init(void) { for (int i = 0; i < RECV_NTB_N; ++i) { ncm_interface.recv_free_ntb[i] = &ncm_epbuf.recv[i].ntb; } + // Default link state - can be configured via CFG_TUD_NCM_DEFAULT_LINK_UP + #ifdef CFG_TUD_NCM_DEFAULT_LINK_UP + ncm_interface.link_is_up = CFG_TUD_NCM_DEFAULT_LINK_UP; + #else + ncm_interface.link_is_up = true; // Default to link up if not set. + #endif } // netd_init /** diff --git a/src/class/net/net_device.h b/src/class/net/net_device.h index 4c9a92f2d..fff2623b7 100644 --- a/src/class/net/net_device.h +++ b/src/class/net/net_device.h @@ -87,6 +87,11 @@ void tud_network_init_cb(void); // TODO removed later since it is not part of tinyusb stack extern uint8_t tud_network_mac_address[6]; +//------------- NCM -------------// + +// Set the network link state (up/down) and notify the host +void tud_network_link_state(uint8_t rhport, bool is_up); + //--------------------------------------------------------------------+ // INTERNAL USBD-CLASS DRIVER API //--------------------------------------------------------------------+ -- cgit v1.3.1 From 9021efcacb9d7380bce9d5c9e075b41cb8f28da5 Mon Sep 17 00:00:00 2001 From: Andrew Leech Date: Tue, 27 May 2025 15:06:27 +1000 Subject: Add link state control support for ECM mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extends the link state control feature to CDC-ECM mode. RNDIS mode prints state changes but doesn't send notifications to the host yet (would require RNDIS_INDICATE_STATUS_MSG). For ECM: - Tracks link state and sends proper CDC notifications - Handles notification endpoint busy conditions - Only sends connection notification when link is actually up 🤖 Generated with [Claude Code](https://claude.ai/code) Co-Authored-By: Claude --- src/class/net/ecm_rndis_device.c | 48 ++++++++++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 7 deletions(-) (limited to 'src') diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index a54e6d662..f1a88b3c0 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -81,6 +81,7 @@ typedef struct { static netd_interface_t _netd_itf; CFG_TUD_MEM_SECTION static netd_epbuf_t _netd_epbuf; static bool can_xmit; +static bool ecm_link_is_up = true; // Store link state for ECM mode void tud_network_recv_renew(void) { usbd_edpt_xfer(0, _netd_itf.ep_out, _netd_epbuf.rx, NETD_PACKET_SIZE); @@ -95,7 +96,11 @@ void netd_report(uint8_t *buf, uint16_t len) { const uint8_t rhport = 0; len = tu_min16(len, sizeof(ecm_notify_t)); - TU_VERIFY(usbd_edpt_claim(rhport, _netd_itf.ep_notif), ); + if (!usbd_edpt_claim(rhport, _netd_itf.ep_notif)) { + TU_LOG1("ECM: Failed to claim notification endpoint\n"); + return; + } + memcpy(_netd_epbuf.notify, buf, len); usbd_edpt_xfer(rhport, _netd_itf.ep_notif, _netd_epbuf.notify, len); } @@ -196,11 +201,11 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 } static void ecm_report(bool nc) { - const ecm_notify_t ecm_notify_nc = { + ecm_notify_t ecm_notify_nc = { .header = { .bmRequestType = 0xA1, .bRequest = 0, /* NETWORK_CONNECTION aka NetworkConnection */ - .wValue = 1, /* Connected */ + .wValue = ecm_link_is_up ? 1 : 0, /* Use current link state */ .wLength = 0, }, }; @@ -286,7 +291,10 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t /* the only required CDC-ECM Management Element Request is SetEthernetPacketFilter */ if (0x43 /* SET_ETHERNET_PACKET_FILTER */ == request->bRequest) { tud_control_xfer(rhport, request, NULL, 0); - ecm_report(true); + // Only send connection notification if link is up + if (ecm_link_is_up) { + ecm_report(true); + } } } else { if (request->bmRequestType_bit.direction == TUSB_DIR_IN) { @@ -363,9 +371,8 @@ bool netd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ } if (_netd_itf.ecm_mode && (ep_addr == _netd_itf.ep_notif)) { - if (sizeof(tusb_control_request_t) == xferred_bytes) { - ecm_report(false); - } + // Notification transfer complete - endpoint is now free + // Don't automatically send speed change notification after link state changes } return true; @@ -398,4 +405,31 @@ void tud_network_xmit(void *ref, uint16_t arg) { do_in_xfer(_netd_epbuf.tx, len); } +// Set the network link state (up/down) and notify the host +void tud_network_link_state(uint8_t rhport, bool is_up) { + (void)rhport; + + if (_netd_itf.ecm_mode) { + ecm_link_is_up = is_up; + + // For ECM mode, send network connection notification only + // Don't trigger speed change notification for link state changes + ecm_notify_t notify = { + .header = { + .bmRequestType = 0xA1, + .bRequest = 0, /* NETWORK_CONNECTION */ + .wValue = is_up ? 1 : 0, /* 0 = disconnected, 1 = connected */ + .wLength = 0, + }, + }; + notify.header.wIndex = _netd_itf.itf_num; + netd_report((uint8_t *)¬ify, sizeof(notify.header)); + } else { + // For RNDIS mode, we would need to implement RNDIS status indication + // This is more complex and requires RNDIS_INDICATE_STATUS_MSG + // For now, RNDIS doesn't support dynamic link state changes + (void)is_up; + } +} + #endif -- cgit v1.3.1 From dc0038f6147584dce64323bb4895a3632c312bc1 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 29 May 2025 13:50:05 +0200 Subject: uac2: remove support fifo Signed-off-by: HiFiPhile --- examples/device/audio_4_channel_mic/src/main.c | 35 - .../device/audio_4_channel_mic/src/tusb_config.h | 15 - .../device/audio_4_channel_mic_freertos/src/main.c | 35 - .../audio_4_channel_mic_freertos/src/tusb_config.h | 15 - src/class/audio/audio_device.c | 872 ++------------------- src/class/audio/audio_device.h | 236 +----- 6 files changed, 74 insertions(+), 1134 deletions(-) (limited to 'src') diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index e8c40309e..f78e48f0c 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -69,13 +69,8 @@ uint8_t clkValid; audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state -#if CFG_TUD_AUDIO_ENABLE_ENCODING -// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2 -uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; -#else // Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000]; -#endif void led_blinking_task(void); void audio_task(void); @@ -106,27 +101,6 @@ int main(void) sampleFreqRng.subrange[0].bRes = 0; // Generate dummy data -#if CFG_TUD_AUDIO_ENABLE_ENCODING - uint16_t * p_buff = i2s_dummy_buffer[0]; - uint16_t dataVal = 0; - for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) - { - // CH0 saw wave - *p_buff++ = dataVal; - // CH1 inverted saw wave - *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal; - dataVal+= 32; - } - p_buff = i2s_dummy_buffer[1]; - for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) - { - // CH3 square wave - *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000; - // CH4 sinus wave - float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); - *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000); - } -#else uint16_t * p_buff = i2s_dummy_buffer; uint16_t dataVal = 0; for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) @@ -142,7 +116,6 @@ int main(void) float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000); } -#endif while (1) { @@ -195,15 +168,7 @@ void audio_task(void) uint32_t curr_ms = board_millis(); if ( start_ms == curr_ms ) return; // not enough time start_ms = curr_ms; -#if CFG_TUD_AUDIO_ENABLE_ENCODING - // Write I2S buffer into FIFO - for (uint8_t cnt=0; cnt < 2; cnt++) - { - tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX); - } -#else tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX); -#endif } //--------------------------------------------------------------------+ diff --git a/examples/device/audio_4_channel_mic/src/tusb_config.h b/examples/device/audio_4_channel_mic/src/tusb_config.h index 46484f847..446a7a32a 100644 --- a/examples/device/audio_4_channel_mic/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic/src/tusb_config.h @@ -115,26 +115,11 @@ extern "C" { #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup #define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) -#define CFG_TUD_AUDIO_ENABLE_ENCODING 1 #define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1 -#if CFG_TUD_AUDIO_ENABLE_ENCODING - -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN - -#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1 -#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value -#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX) -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device - -#else - #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device -#endif - #ifdef __cplusplus } #endif diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index c9de4029a..99278b5cc 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -105,13 +105,8 @@ uint8_t clkValid; audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state -#if CFG_TUD_AUDIO_ENABLE_ENCODING -// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2 -uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; -#else // Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3 uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000]; -#endif void led_blinking_task(void* param); void usb_device_task(void* param); @@ -132,27 +127,6 @@ int main(void) sampleFreqRng.subrange[0].bRes = 0; // Generate dummy data -#if CFG_TUD_AUDIO_ENABLE_ENCODING - uint16_t * p_buff = i2s_dummy_buffer[0]; - uint16_t dataVal = 0; - for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) - { - // CH0 saw wave - *p_buff++ = dataVal; - // CH1 inverted saw wave - *p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal; - dataVal+= 32; - } - p_buff = i2s_dummy_buffer[1]; - for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) - { - // CH3 square wave - *p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000; - // CH4 sinus wave - float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); - *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000); - } -#else uint16_t * p_buff = i2s_dummy_buffer; uint16_t dataVal = 0; for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++) @@ -168,7 +142,6 @@ int main(void) float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000); *p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000); } -#endif #if configSUPPORT_STATIC_ALLOCATION // blinky task @@ -269,15 +242,7 @@ void audio_task(void* param) // Here we simulate a I2S receive callback every 1ms. while (1) { vTaskDelay(1); -#if CFG_TUD_AUDIO_ENABLE_ENCODING - // Write I2S buffer into FIFO - for (uint8_t cnt=0; cnt < 2; cnt++) - { - tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX); - } -#else tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX); -#endif } } diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h index 5cd93b0d6..5ac51b153 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h @@ -121,26 +121,11 @@ extern "C" { #define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup #define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX) -#define CFG_TUD_AUDIO_ENABLE_ENCODING 1 #define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1 -#if CFG_TUD_AUDIO_ENABLE_ENCODING - -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN -#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN - -#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1 -#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value -#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX) -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device - -#else - #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN #define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device -#endif - #ifdef __cplusplus } #endif diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 7a6fd453f..11a3d4a73 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -108,19 +108,19 @@ #endif // Put swap buffer in USB section only if necessary -#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING +#if USE_LINEAR_BUFFER #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4) #else #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN #endif -#if USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING +#if USE_LINEAR_BUFFER #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4) #else #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN #endif // EP IN software buffers and mutexes -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN tu_static IN_SW_BUF_MEM_ATTR struct { #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ); @@ -144,12 +144,11 @@ tu_static IN_SW_BUF_MEM_ATTR struct { tu_static osal_mutex_def_t ep_in_ff_mutex_wr_3; #endif #endif -#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#endif// CFG_TUD_AUDIO_ENABLE_EP_IN // Linear buffer TX in case: // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR -// - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into -#if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING) +#if CFG_TUD_AUDIO_ENABLE_EP_IN && USE_LINEAR_BUFFER tu_static CFG_TUD_MEM_SECTION struct { #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX > 0 TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX); @@ -161,10 +160,10 @@ tu_static CFG_TUD_MEM_SECTION struct { TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SZ_MAX); #endif } lin_buf_in; -#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) +#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && USE_LINEAR_BUFFER // EP OUT software buffers and mutexes -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT tu_static OUT_SW_BUF_MEM_ATTR struct { #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ); @@ -188,12 +187,11 @@ tu_static OUT_SW_BUF_MEM_ATTR struct { tu_static osal_mutex_def_t ep_out_ff_mutex_rd_3; #endif #endif -#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT // Linear buffer RX in case: // - target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR -// - the software encoding is used - in this case the linear buffers serve as a target memory where logical channels are encoded into -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) +#if CFG_TUD_AUDIO_ENABLE_EP_OUT && USE_LINEAR_BUFFER tu_static CFG_TUD_MEM_SECTION struct { #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0 TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX); @@ -205,7 +203,7 @@ tu_static CFG_TUD_MEM_SECTION struct { TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX); #endif } lin_buf_out; -#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) +#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && USE_LINEAR_BUFFER // Control buffers tu_static CFG_TUD_MEM_SECTION struct { @@ -229,59 +227,6 @@ tu_static uint8_t alt_setting_2[CFG_TUD_AUDIO_FUNC_2_N_AS_INT]; tu_static uint8_t alt_setting_3[CFG_TUD_AUDIO_FUNC_3_N_AS_INT]; #endif -// Software encoding/decoding support FIFOs -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t tx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_1[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO - #endif - #endif - - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t tx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_2[CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO - #endif - #endif - - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t tx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t tx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t tx_supp_ff_mutex_wr_3[CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO];// No need for read mutex as only USB driver reads from FIFO - #endif - #endif -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t rx_supp_ff_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_1[CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO - #endif - #endif - - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t rx_supp_ff_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_2[CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO - #endif - #endif - - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 - tu_static TU_ATTR_ALIGNED(4) uint8_t rx_supp_ff_buf_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ]; - tu_static tu_fifo_t rx_supp_ff_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO]; - #if CFG_FIFO_MUTEX - tu_static osal_mutex_def_t rx_supp_ff_mutex_rd_3[CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO];// No need for write mutex as only USB driver writes into FIFO - #endif - #endif -#endif - // Aligned buffer for feedback EP #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP tu_static CFG_TUD_MEM_SECTION struct { @@ -363,19 +308,6 @@ typedef struct } feedback; #endif// CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP -// Decoding parameters - parameters are set when alternate AS interface is set by host -// Coding is currently only supported for EP. Software coding corresponding to AS interfaces without EPs are not supported currently. -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - audio_format_type_t format_type_rx; - uint8_t n_channels_rx; - - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING - audio_data_format_type_I_t format_type_I_rx; - uint8_t n_bytes_per_sample_rx; - uint8_t n_ff_used_rx; - #endif -#endif - #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL uint32_t sample_rate_tx; uint16_t packet_sz_tx[3]; @@ -384,15 +316,10 @@ typedef struct #endif // Encoding parameters - parameters are set when alternate AS interface is set by host -#if CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL) +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL audio_format_type_t format_type_tx; uint8_t n_channels_tx; uint8_t n_bytes_per_sample_tx; - - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - audio_data_format_type_I_t format_type_I_tx; - uint8_t n_ff_used_tx; - #endif #endif /*------------- From this point, data is not cleared by bus reset -------------*/ @@ -405,40 +332,21 @@ typedef struct uint8_t *alt_setting;// We need to save the current alternate setting this way, because it is possible that there are AS interfaces which do not have an EP! // EP Transfer buffers and FIFOs -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT tu_fifo_t ep_out_ff; #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN tu_fifo_t ep_in_ff; #endif -// Support FIFOs for software encoding and decoding -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - tu_fifo_t *rx_supp_ff; - uint8_t n_rx_supp_ff; - uint16_t rx_supp_ff_sz_max; - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING - uint8_t n_channels_per_ff_rx; - #endif -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - tu_fifo_t *tx_supp_ff; - uint8_t n_tx_supp_ff; - uint16_t tx_supp_ff_sz_max; - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - uint8_t n_channels_per_ff_tx; - #endif -#endif - -// Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically OR the support FIFOs are used -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_DECODING) +// Linear buffer in case target MCU is not capable of handling a ring buffer FIFO e.g. no hardware buffer is available or driver is would need to be changed dramatically +#if CFG_TUD_AUDIO_ENABLE_EP_OUT && USE_LINEAR_BUFFER uint8_t *lin_buf_out; #define USE_LINEAR_BUFFER_RX 1 #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && (USE_LINEAR_BUFFER || CFG_TUD_AUDIO_ENABLE_ENCODING) +#if CFG_TUD_AUDIO_ENABLE_EP_IN && USE_LINEAR_BUFFER uint8_t *lin_buf_in; #define USE_LINEAR_BUFFER_TX 1 #endif @@ -604,18 +512,10 @@ tu_static CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO]; static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received); #endif -#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT -static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received); -#endif - #if CFG_TUD_AUDIO_ENABLE_EP_IN static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio); #endif -#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN -static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t *audio); -#endif - static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const *p_request); static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p_request); @@ -626,11 +526,8 @@ static bool audiod_verify_itf_exists(uint8_t itf, uint8_t *func_id); static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id); static uint8_t audiod_get_audio_fct_idx(audiod_function_t *audio); -#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) -static void audiod_parse_for_AS_params(audiod_function_t *audio, uint8_t const *p_desc, uint8_t const *p_desc_end, uint8_t const as_itf); -#endif - #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +static void audiod_parse_flow_control_params(audiod_function_t *audio, uint8_t const *p_desc); static bool audiod_calc_tx_packet_sz(audiod_function_t *audio); static uint16_t audiod_tx_packet_size(const uint16_t *norminal_size, uint16_t data_count, uint16_t fifo_depth, uint16_t max_size); #endif @@ -651,7 +548,7 @@ bool tud_audio_n_mounted(uint8_t func_id) { // READ API //--------------------------------------------------------------------+ -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT uint16_t tud_audio_n_available(uint8_t func_id) { TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); @@ -673,36 +570,7 @@ tu_fifo_t *tud_audio_n_get_ep_out_ff(uint8_t func_id) { return NULL; } -#endif - -#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT -// Delete all content in the support RX FIFOs -bool tud_audio_n_clear_rx_support_ff(uint8_t func_id, uint8_t ff_idx) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff); - return tu_fifo_clear(&_audiod_fct[func_id].rx_supp_ff[ff_idx]); -} - -uint16_t tud_audio_n_available_support_ff(uint8_t func_id, uint8_t ff_idx) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff); - return tu_fifo_count(&_audiod_fct[func_id].rx_supp_ff[ff_idx]); -} - -uint16_t tud_audio_n_read_support_ff(uint8_t func_id, uint8_t ff_idx, void *buffer, uint16_t bufsize) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff); - return tu_fifo_read_n(&_audiod_fct[func_id].rx_supp_ff[ff_idx], buffer, bufsize); -} - -tu_fifo_t *tud_audio_n_get_rx_support_ff(uint8_t func_id, uint8_t ff_idx) { - if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_rx_supp_ff) return &_audiod_fct[func_id].rx_supp_ff[ff_idx]; - return NULL; -} -#endif - -// This function is called once an audio packet is received by the USB and is responsible for putting data from USB memory into EP_OUT_FIFO (or support FIFOs + decoding of received stream into audio channels). -// If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_DECODING = 0. - -#if CFG_TUD_AUDIO_ENABLE_EP_OUT - +// This function is called once an audio packet is received by the USB and is responsible for putting data from USB memory into EP_OUT_FIFO. static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received) { uint8_t idxItf = 0; uint8_t const *dummy2; @@ -711,62 +579,24 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t idx_audio_fct = audiod_get_audio_fct_idx(audio); TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2)); - // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO (or decoded into support RX software FIFO) + // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf])); - #if CFG_TUD_AUDIO_ENABLE_DECODING - - switch (audio->format_type_rx) { - case AUDIO_FORMAT_TYPE_UNDEFINED: - // INDIVIDUAL DECODING PROCEDURE REQUIRED HERE! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT encoding not implemented!\r\n"); - TU_BREAKPOINT(); - break; - - case AUDIO_FORMAT_TYPE_I: - - switch (audio->format_type_I_rx) { - case AUDIO_DATA_FORMAT_TYPE_I_PCM: - TU_VERIFY(audiod_decode_type_I_pcm(rhport, audio, n_bytes_received)); - break; - - default: - // DESIRED CFG_TUD_AUDIO_FORMAT_TYPE_I_RX NOT IMPLEMENTED! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT_TYPE_I_RX encoding not implemented!\r\n"); - TU_BREAKPOINT(); - break; - } - break; - - default: - // Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT_TYPE_RX not implemented!\r\n"); - TU_BREAKPOINT(); - break; - } - - // Prepare for next transmission - TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false); - - #else - - #if USE_LINEAR_BUFFER_RX + #if USE_LINEAR_BUFFER_RX // Data currently is in linear buffer, copy into EP OUT FIFO TU_VERIFY(tu_fifo_write_n(&audio->ep_out_ff, audio->lin_buf_out, n_bytes_received)); // Schedule for next receive TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false); - #else + #else // Data is already placed in EP FIFO, schedule for next receive TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_out, &audio->ep_out_ff, audio->ep_out_sz), false); - #endif + #endif - #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP + #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP if (audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT) { audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->ep_out_ff)); } - #endif - #endif // Call a weak callback here - a possibility for user to get informed decoding was completed @@ -777,103 +607,11 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t #endif//CFG_TUD_AUDIO_ENABLE_EP_OUT -// The following functions are used in case CFG_TUD_AUDIO_ENABLE_DECODING != 0 -#if CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_EP_OUT - -// Decoding according to 2.3.1.5 Audio Streams - -// Helper function -static inline void *audiod_interleaved_copy_bytes_fast_decode(uint16_t const nBytesPerSample, void *dst, const void *dst_end, void *src, uint8_t const n_ff_used) { - // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2) - uint16_t *dst16 = dst; - uint16_t *src16 = src; - const uint16_t *dst_end16 = dst_end; - uint32_t *dst32 = dst; - uint32_t *src32 = src; - const uint32_t *dst_end32 = dst_end; - - if (nBytesPerSample == 1) { - while (dst16 < dst_end16) { - *dst16++ = *src16++; - src16 += n_ff_used - 1; - } - return src16; - } else if (nBytesPerSample == 2) { - while (dst32 < dst_end32) { - *dst32++ = *src32++; - src32 += n_ff_used - 1; - } - return src32; - } else if (nBytesPerSample == 3) { - while (dst16 < dst_end16) { - *dst16++ = *src16++; - *dst16++ = *src16++; - *dst16++ = *src16++; - src16 += 3 * (n_ff_used - 1); - } - return src16; - } else// nBytesPerSample == 4 - { - while (dst32 < dst_end32) { - *dst32++ = *src32++; - *dst32++ = *src32++; - src32 += 2 * (n_ff_used - 1); - } - return src32; - } -} - -static bool audiod_decode_type_I_pcm(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received) { - (void) rhport; - - // Determine amount of samples - uint8_t const n_ff_used = audio->n_ff_used_rx; - uint16_t const nBytesPerFFToRead = n_bytes_received / n_ff_used; - uint8_t cnt_ff; - - // Decode - uint8_t *src; - uint8_t *dst_end; - - tu_fifo_buffer_info_t info; - - for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++) { - tu_fifo_get_write_info(&audio->rx_supp_ff[cnt_ff], &info); - - if (info.len_lin != 0) { - info.len_lin = tu_min16(nBytesPerFFToRead, info.len_lin); - src = &audio->lin_buf_out[cnt_ff * audio->n_channels_per_ff_rx * audio->n_bytes_per_sample_rx]; - dst_end = info.ptr_lin + info.len_lin; - src = audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_lin, dst_end, src, n_ff_used); - - // Handle wrapped part of FIFO - info.len_wrap = tu_min16(nBytesPerFFToRead - info.len_lin, info.len_wrap); - if (info.len_wrap != 0) { - dst_end = info.ptr_wrap + info.len_wrap; - audiod_interleaved_copy_bytes_fast_decode(audio->n_bytes_per_sample_rx, info.ptr_wrap, dst_end, src, n_ff_used); - } - tu_fifo_advance_write_pointer(&audio->rx_supp_ff[cnt_ff], info.len_lin + info.len_wrap); - } - } - - // Number of bytes should be a multiple of CFG_TUD_AUDIO_N_BYTES_PER_SAMPLE_RX * CFG_TUD_AUDIO_N_CHANNELS_RX but checking makes no sense - no way to correct it - // TU_VERIFY(cnt != n_bytes); - - #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - if (audio->feedback.compute_method == AUDIO_FEEDBACK_METHOD_FIFO_COUNT) { - audiod_fb_fifo_count_update(audio, tu_fifo_count(&audio->rx_supp_ff[0])); - } - #endif - - return true; -} -#endif//CFG_TUD_AUDIO_ENABLE_DECODING - //--------------------------------------------------------------------+ // WRITE API //--------------------------------------------------------------------+ -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN /** * \brief Write data to EP in buffer @@ -902,71 +640,8 @@ tu_fifo_t *tud_audio_n_get_ep_in_ff(uint8_t func_id) { return NULL; } -#endif - -#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN - -uint16_t tud_audio_n_flush_tx_support_ff(uint8_t func_id)// Force all content in the support TX FIFOs to be written into linear buffer and schedule a transmit -{ - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); - audiod_function_t *audio = &_audiod_fct[func_id]; - - uint16_t n_bytes_copied = tu_fifo_count(&audio->tx_supp_ff[0]); - - TU_VERIFY(audiod_tx_done_cb(audio->rhport, audio)); - - n_bytes_copied -= tu_fifo_count(&audio->tx_supp_ff[0]); - n_bytes_copied = n_bytes_copied * audio->tx_supp_ff[0].item_size; - - return n_bytes_copied; -} - -bool tud_audio_n_clear_tx_support_ff(uint8_t func_id, uint8_t ff_idx) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff); - return tu_fifo_clear(&_audiod_fct[func_id].tx_supp_ff[ff_idx]); -} - -uint16_t tud_audio_n_write_support_ff(uint8_t func_id, uint8_t ff_idx, const void *data, uint16_t len) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff); - return tu_fifo_write_n(&_audiod_fct[func_id].tx_supp_ff[ff_idx], data, len); -} - -tu_fifo_t *tud_audio_n_get_tx_support_ff(uint8_t func_id, uint8_t ff_idx) { - if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL && ff_idx < _audiod_fct[func_id].n_tx_supp_ff) return &_audiod_fct[func_id].tx_supp_ff[ff_idx]; - return NULL; -} - -#endif - - -#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP -// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_done_cb() is called in inform user -bool tud_audio_int_n_write(uint8_t func_id, const audio_interrupt_data_t *data) { - TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); - - TU_VERIFY(_audiod_fct[func_id].ep_int != 0); - - // We write directly into the EP's buffer - abort if previous transfer not complete - TU_VERIFY(usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int)); - - // Check length - if (tu_memcpy_s(int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf), data, sizeof(audio_interrupt_data_t)) == 0) { - // Schedule transmit - TU_ASSERT(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf)), 0); - } else { - // Release endpoint since we don't make any transfer - usbd_edpt_release(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int); - } - - return true; -} -#endif - // This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission. -// If you prefer your own (more efficient) implementation suiting your purpose set CFG_TUD_AUDIO_ENABLE_ENCODING = 0 and use tud_audio_n_write. - // n_bytes_copied - Informs caller how many bytes were loaded. In case n_bytes_copied = 0, a ZLP is scheduled to inform host no data is available for current frame. -#if CFG_TUD_AUDIO_ENABLE_EP_IN static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { uint8_t idxItf; uint8_t const *dummy2; @@ -984,59 +659,18 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { // Send everything in ISO EP FIFO uint16_t n_bytes_tx; - // If support FIFOs are used, encode and schedule transmit - #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN - switch (audio->format_type_tx) { - case AUDIO_FORMAT_TYPE_UNDEFINED: - // INDIVIDUAL ENCODING PROCEDURE REQUIRED HERE! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT encoding not implemented!\r\n"); - TU_BREAKPOINT(); - n_bytes_tx = 0; - break; - - case AUDIO_FORMAT_TYPE_I: - - switch (audio->format_type_I_tx) { - case AUDIO_DATA_FORMAT_TYPE_I_PCM: - - n_bytes_tx = audiod_encode_type_I_pcm(rhport, audio); - break; - - default: - // YOUR ENCODING IS REQUIRED HERE! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT_TYPE_I_TX encoding not implemented!\r\n"); - TU_BREAKPOINT(); - n_bytes_tx = 0; - break; - } - break; - - default: - // Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented! - TU_LOG2(" Desired CFG_TUD_AUDIO_FORMAT_TYPE_TX not implemented!\r\n"); - TU_BREAKPOINT(); - n_bytes_tx = 0; - break; - } - - TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx)); - - #else - // No support FIFOs, if no linear buffer required schedule transmit, else put data into linear buffer and schedule - #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - // packet_sz_tx is based on total packet size, here we want size for each support buffer. + #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + // packet_sz_tx is based on total packet size n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz); - #else + #else n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);// Limit up to max packet size, more can not be done for ISO - #endif - #if USE_LINEAR_BUFFER_TX + #endif + #if USE_LINEAR_BUFFER_TX tu_fifo_read_n(&audio->ep_in_ff, audio->lin_buf_in, n_bytes_tx); TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, n_bytes_tx)); - #else + #else // Send everything in ISO EP FIFO TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_in, &audio->ep_in_ff, n_bytes_tx)); - #endif - #endif // Call a weak callback here - a possibility for user to get informed former TX was completed and how many bytes were loaded for the next frame @@ -1045,140 +679,33 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { return true; } -#endif//CFG_TUD_AUDIO_ENABLE_EP_IN - -#if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_EP_IN -// Take samples from the support buffer and encode them into the IN EP software FIFO -// Returns number of bytes written into linear buffer - -/* 2.3.1.7.1 PCM Format -The PCM (Pulse Coded Modulation) format is the most commonly used audio format to represent audio -data streams. The audio data is not compressed and uses a signed two’s-complement fixed point format. It -is left-justified (the sign bit is the Msb) and data is padded with trailing zeros to fill the remaining unused -bits of the subslot. The binary point is located to the right of the sign bit so that all values lie within the -range [-1, +1) - */ - -/* - * This function encodes channels saved within the support FIFOs into one stream by interleaving the PCM samples - * in the support FIFOs according to 2.3.1.5 Audio Streams. It does not control justification (left or right) and - * does not change the number of bytes per sample. - * */ - -// Helper function -static inline void *audiod_interleaved_copy_bytes_fast_encode(uint16_t const nBytesPerSample, void *src, const void *src_end, void *dst, uint8_t const n_ff_used) { - // Due to one FIFO contains 2 channels, data always aligned to (nBytesPerSample * 2) - uint16_t *dst16 = dst; - uint16_t *src16 = src; - const uint16_t *src_end16 = src_end; - uint32_t *dst32 = dst; - uint32_t *src32 = src; - const uint32_t *src_end32 = src_end; - - if (nBytesPerSample == 1) { - while (src16 < src_end16) { - *dst16++ = *src16++; - dst16 += n_ff_used - 1; - } - return dst16; - } else if (nBytesPerSample == 2) { - while (src32 < src_end32) { - *dst32++ = *src32++; - dst32 += n_ff_used - 1; - } - return dst32; - } else if (nBytesPerSample == 3) { - while (src16 < src_end16) { - *dst16++ = *src16++; - *dst16++ = *src16++; - *dst16++ = *src16++; - dst16 += 3 * (n_ff_used - 1); - } - return dst16; - } else// nBytesPerSample == 4 - { - while (src32 < src_end32) { - *dst32++ = *src32++; - *dst32++ = *src32++; - dst32 += 2 * (n_ff_used - 1); - } - return dst32; - } -} - -static uint16_t audiod_encode_type_I_pcm(uint8_t rhport, audiod_function_t *audio) { - // This function relies on the fact that the length of the support FIFOs was configured to be a multiple of the active sample size in bytes s.t. no sample is split within a wrap - // This is ensured within set_interface, where the FIFOs are reconfigured according to this size - - // We encode directly into IN EP's linear buffer - abort if previous transfer not complete - TU_VERIFY(!usbd_edpt_busy(rhport, audio->ep_in)); - - // Determine amount of samples - uint8_t const n_ff_used = audio->n_ff_used_tx; - uint16_t nBytesPerFFToSend = tu_fifo_count(&audio->tx_supp_ff[0]); - uint8_t cnt_ff; - - for (cnt_ff = 1; cnt_ff < n_ff_used; cnt_ff++) { - uint16_t const count = tu_fifo_count(&audio->tx_supp_ff[cnt_ff]); - if (count < nBytesPerFFToSend) { - nBytesPerFFToSend = count; - } - } - - #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - const uint16_t norm_packet_sz_tx[3] = {audio->packet_sz_tx[0] / n_ff_used, - audio->packet_sz_tx[1] / n_ff_used, - audio->packet_sz_tx[2] / n_ff_used}; - // packet_sz_tx is based on total packet size, here we want size for each support buffer. - nBytesPerFFToSend = audiod_tx_packet_size(norm_packet_sz_tx, nBytesPerFFToSend, audio->tx_supp_ff[0].depth, audio->ep_in_sz / n_ff_used); - // Check if there is enough data - if (nBytesPerFFToSend == 0) return 0; - #else - // Check if there is enough data - if (nBytesPerFFToSend == 0) return 0; - // Limit to maximum sample number - THIS IS A POSSIBLE ERROR SOURCE IF TOO MANY SAMPLE WOULD NEED TO BE SENT BUT CAN NOT! - nBytesPerFFToSend = tu_min16(nBytesPerFFToSend, audio->ep_in_sz / n_ff_used); - // Round to full number of samples (flooring) - uint16_t const nSlotSize = audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx; - nBytesPerFFToSend = (nBytesPerFFToSend / nSlotSize) * nSlotSize; - #endif - - // Encode - uint8_t *dst; - uint8_t *src_end; - - tu_fifo_buffer_info_t info; - - for (cnt_ff = 0; cnt_ff < n_ff_used; cnt_ff++) { - dst = &audio->lin_buf_in[cnt_ff * audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx]; - - tu_fifo_get_read_info(&audio->tx_supp_ff[cnt_ff], &info); +#endif - if (info.len_lin != 0) { - info.len_lin = tu_min16(nBytesPerFFToSend, info.len_lin);// Limit up to desired length - src_end = (uint8_t *) info.ptr_lin + info.len_lin; - dst = audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_lin, src_end, dst, n_ff_used); +#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP +// If no interrupt transmit is pending bytes get written into buffer and a transmit is scheduled - once transmit completed tud_audio_int_done_cb() is called in inform user +bool tud_audio_int_n_write(uint8_t func_id, const audio_interrupt_data_t *data) { + TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); - // Limit up to desired length - info.len_wrap = tu_min16(nBytesPerFFToSend - info.len_lin, info.len_wrap); + TU_VERIFY(_audiod_fct[func_id].ep_int != 0); - // Handle wrapped part of FIFO - if (info.len_wrap != 0) { - src_end = (uint8_t *) info.ptr_wrap + info.len_wrap; - audiod_interleaved_copy_bytes_fast_encode(audio->n_bytes_per_sample_tx, info.ptr_wrap, src_end, dst, n_ff_used); - } + // We write directly into the EP's buffer - abort if previous transfer not complete + TU_VERIFY(usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int)); - tu_fifo_advance_read_pointer(&audio->tx_supp_ff[cnt_ff], info.len_lin + info.len_wrap); - } + // Check length + if (tu_memcpy_s(int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf), data, sizeof(audio_interrupt_data_t)) == 0) { + // Schedule transmit + TU_ASSERT(usbd_edpt_xfer(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int, int_ep_buf[func_id].buf, sizeof(int_ep_buf[func_id].buf)), 0); + } else { + // Release endpoint since we don't make any transfer + usbd_edpt_release(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_int); } - return nBytesPerFFToSend * n_ff_used; + return true; } -#endif//CFG_TUD_AUDIO_ENABLE_ENCODING - -// This function is called once a transmit of a feedback packet was successfully completed. Here, we get the next feedback value to be sent +#endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP +// This function is called once a transmit of a feedback packet was successfully completed. Here, we get the next feedback value to be sent static inline bool audiod_fb_send(audiod_function_t *audio) { bool apply_correction = (TUSB_SPEED_FULL == tud_speed_get()) && audio->feedback.format_correction; // Format the feedback value @@ -1260,7 +787,7 @@ void audiod_init(void) { } // Initialize IN EP FIFO if required -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN switch (i) { #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 @@ -1288,7 +815,7 @@ void audiod_init(void) { break; #endif } -#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#endif// CFG_TUD_AUDIO_ENABLE_EP_IN // Initialize linear buffers #if USE_LINEAR_BUFFER_TX @@ -1312,7 +839,7 @@ void audiod_init(void) { #endif// USE_LINEAR_BUFFER_TX // Initialize OUT EP FIFO if required -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT switch (i) { #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 @@ -1340,7 +867,7 @@ void audiod_init(void) { break; #endif } -#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#endif// CFG_TUD_AUDIO_ENABLE_EP_OUT // Initialize linear buffers #if USE_LINEAR_BUFFER_RX @@ -1382,150 +909,6 @@ void audiod_init(void) { #endif } #endif// CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - - // Initialize TX support FIFOs if required -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - - switch (i) { - #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - case 0: - audio->tx_supp_ff = tx_supp_ff_1; - audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; - audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&tx_supp_ff_1[cnt], tx_supp_ff_buf_1[cnt], CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&tx_supp_ff_1[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_1[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - case 1: - audio->tx_supp_ff = tx_supp_ff_2; - audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO; - audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&tx_supp_ff_2[cnt], tx_supp_ff_buf_2[cnt], CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&tx_supp_ff_2[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_2[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 - case 2: - audio->tx_supp_ff = tx_supp_ff_3; - audio->n_tx_supp_ff = CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO; - audio->tx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&tx_supp_ff_3[cnt], tx_supp_ff_buf_3[cnt], CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&tx_supp_ff_3[cnt], osal_mutex_create(&tx_supp_ff_mutex_wr_3[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - } -#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - - // Set encoding parameters for Type_I formats -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - switch (i) { - #if CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ > 0 - case 0: - audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX; - break; - #endif - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ > 0 - case 1: - audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_TX; - break; - #endif - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ > 0 - case 2: - audio->n_channels_per_ff_tx = CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_TX; - break; - #endif - } -#endif// CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - - // Initialize RX support FIFOs if required -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - - switch (i) { - #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - case 0: - audio->rx_supp_ff = rx_supp_ff_1; - audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO; - audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&rx_supp_ff_1[cnt], rx_supp_ff_buf_1[cnt], CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&rx_supp_ff_1[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_1[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - case 1: - audio->rx_supp_ff = rx_supp_ff_2; - audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO; - audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&rx_supp_ff_2[cnt], rx_supp_ff_buf_2[cnt], CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&rx_supp_ff_2[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_2[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 - case 2: - audio->rx_supp_ff = rx_supp_ff_3; - audio->n_rx_supp_ff = CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO; - audio->rx_supp_ff_sz_max = CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ; - for (uint8_t cnt = 0; cnt < CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO; cnt++) { - tu_fifo_config(&rx_supp_ff_3[cnt], rx_supp_ff_buf_3[cnt], CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&rx_supp_ff_3[cnt], osal_mutex_create(&rx_supp_ff_mutex_rd_3[cnt]), NULL); - #endif - } - - break; - #endif// CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - } -#endif// CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - - // Set encoding parameters for Type_I formats -#if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING - switch (i) { - #if CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ > 0 - case 0: - audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_RX; - break; - #endif - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ > 0 - case 1: - audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_RX; - break; - #endif - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ > 0 - case 2: - audio->n_channels_per_ff_rx = CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_RX; - break; - #endif - } -#endif// CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING } } @@ -1540,25 +923,13 @@ void audiod_reset(uint8_t rhport) { audiod_function_t *audio = &_audiod_fct[i]; tu_memclr(audio, ITF_MEM_RESET_SIZE); -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN tu_fifo_clear(&audio->ep_in_ff); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT tu_fifo_clear(&audio->ep_out_ff); #endif - -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { - tu_fifo_clear(&audio->tx_supp_ff[cnt]); - } -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) { - tu_fifo_clear(&audio->rx_supp_ff[cnt]); - } -#endif } } @@ -1783,13 +1154,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p #endif // Clear FIFOs, since data is no longer valid - #if !CFG_TUD_AUDIO_ENABLE_ENCODING tu_fifo_clear(&audio->ep_in_ff); - #else - for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { - tu_fifo_clear(&audio->tx_supp_ff[cnt]); - } - #endif // Invoke callback - can be used to stop data sampling TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); @@ -1812,13 +1177,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p #endif // Clear FIFOs, since data is no longer valid - #if !CFG_TUD_AUDIO_ENABLE_DECODING tu_fifo_clear(&audio->ep_out_ff); - #else - for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) { - tu_fifo_clear(&audio->rx_supp_ff[cnt]); - } - #endif // Invoke callback - can be used to stop data sampling TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); @@ -1848,7 +1207,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p while (p_desc_end - p_desc > 0) { // Find correct interface if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE && ((tusb_desc_interface_t const *) p_desc)->bInterfaceNumber == itf && ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == alt) { -#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL uint8_t const *p_desc_parse_for_params = p_desc; #endif // From this point forward follow the EP descriptors associated to the current alternate setting interface - Open EPs if necessary @@ -1875,21 +1234,10 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p audio->ep_in_as_intf_num = itf; audio->ep_in_sz = tu_edpt_packet_size(desc_ep); - // If software encoding is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters - #if CFG_TUD_AUDIO_ENABLE_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); - - // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap - #if CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - const uint16_t active_fifo_depth = (uint16_t) ((audio->tx_supp_ff_sz_max / (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx)) * (audio->n_channels_per_ff_tx * audio->n_bytes_per_sample_tx)); - for (uint8_t cnt = 0; cnt < audio->n_tx_supp_ff; cnt++) { - tu_fifo_config(&audio->tx_supp_ff[cnt], audio->tx_supp_ff[cnt].buffer, active_fifo_depth, 1, true); - } - audio->n_ff_used_tx = audio->n_channels_tx / audio->n_channels_per_ff_tx; - TU_ASSERT(audio->n_ff_used_tx <= audio->n_tx_supp_ff); - #endif + // If flow control is enabled, parse for the corresponding parameters - doing this here means only AS interfaces with EPs get scanned for parameters + #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL + audiod_parse_flow_control_params(audio, p_desc_parse_for_params); #endif - // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there TU_VERIFY(audiod_tx_done_cb(rhport, &_audiod_fct[func_id])); @@ -1897,7 +1245,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p #endif// CFG_TUD_AUDIO_ENABLE_EP_IN #if CFG_TUD_AUDIO_ENABLE_EP_OUT - if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT)// Checking usage not necessary { // Save address @@ -1905,20 +1252,6 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p audio->ep_out_as_intf_num = itf; audio->ep_out_sz = tu_edpt_packet_size(desc_ep); - #if CFG_TUD_AUDIO_ENABLE_DECODING - audiod_parse_for_AS_params(audio, p_desc_parse_for_params, p_desc_end, itf); - - // Reconfigure size of support FIFOs - this is necessary to avoid samples to get split in case of a wrap - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING - const uint16_t active_fifo_depth = (audio->rx_supp_ff_sz_max / audio->n_bytes_per_sample_rx) * audio->n_bytes_per_sample_rx; - for (uint8_t cnt = 0; cnt < audio->n_rx_supp_ff; cnt++) { - tu_fifo_config(&audio->rx_supp_ff[cnt], audio->rx_supp_ff[cnt].buffer, active_fifo_depth, 1, true); - } - audio->n_ff_used_rx = audio->n_channels_rx / audio->n_channels_per_ff_rx; - TU_ASSERT(audio->n_ff_used_rx <= audio->n_rx_supp_ff); - #endif - #endif - // Prepare for incoming data #if USE_LINEAR_BUFFER_RX TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_out, audio->lin_buf_out, audio->ep_out_sz), false); @@ -1971,12 +1304,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p case AUDIO_FEEDBACK_METHOD_FIFO_COUNT: { // Initialize the threshold level to half filled - uint16_t fifo_lvl_thr; - #if CFG_TUD_AUDIO_ENABLE_DECODING - fifo_lvl_thr = tu_fifo_depth(&audio->rx_supp_ff[0]) / 2; - #else - fifo_lvl_thr = tu_fifo_depth(&audio->ep_out_ff) / 2; - #endif + uint16_t fifo_lvl_thr = tu_fifo_depth(&audio->ep_out_ff) / 2; audio->feedback.compute.fifo_count.fifo_lvl_thr = fifo_lvl_thr; audio->feedback.compute.fifo_count.fifo_lvl_avg = ((uint32_t) fifo_lvl_thr) << 16; // Avoid 64bit division @@ -2555,86 +1883,22 @@ static bool audiod_verify_ep_exists(uint8_t ep, uint8_t *func_id) { return false; } -#if (CFG_TUD_AUDIO_ENABLE_EP_IN && (CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_ENCODING)) || (CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING) -// p_desc points to the AS interface of alternate setting zero -// itf is the interface number of the corresponding interface - we check if the interface belongs to EP in or EP out to see if it is a TX or RX parameter -// Currently, only AS interfaces with an EP (in or out) are supposed to be parsed for! -static void audiod_parse_for_AS_params(audiod_function_t *audio, uint8_t const *p_desc, uint8_t const *p_desc_end, uint8_t const as_itf) { - #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) return;// Abort, this interface has no EP, this driver does not support this currently - #endif - #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_in_as_intf_num) return; - #endif - #if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_out_as_intf_num) return; - #endif +#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL +static void audiod_parse_flow_control_params(audiod_function_t *audio, uint8_t const *p_desc) { p_desc = tu_desc_next(p_desc);// Exclude standard AS interface descriptor of current alternate interface descriptor - // Condition modified from p_desc < p_desc_end to prevent gcc>=12 strict-overflow warning - while (p_desc_end - p_desc > 0) { - // Abort if follow up descriptor is a new standard interface descriptor - indicates the last AS descriptor was already finished - if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) break; - - // Look for a Class-Specific AS Interface Descriptor(4.9.2) to verify format type and format and also to get number of physical channels - if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_AS_GENERAL) { - #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (as_itf == audio->ep_in_as_intf_num) { - audio->n_channels_tx = ((audio_desc_cs_as_interface_t const *) p_desc)->bNrChannels; - audio->format_type_tx = (audio_format_type_t) (((audio_desc_cs_as_interface_t const *) p_desc)->bFormatType); - - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING - audio->format_type_I_tx = (audio_data_format_type_I_t) (((audio_desc_cs_as_interface_t const *) p_desc)->bmFormats); - #endif - } - #endif - - #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - if (as_itf == audio->ep_out_as_intf_num) { - audio->n_channels_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bNrChannels; - audio->format_type_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bFormatType; - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING - audio->format_type_I_rx = ((audio_desc_cs_as_interface_t const *) p_desc)->bmFormats; - #endif - } - #endif - } + // Look for a Class-Specific AS Interface Descriptor(4.9.2) to verify format type and format and also to get number of physical channels + if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_AS_GENERAL) { + audio->n_channels_tx = ((audio_desc_cs_as_interface_t const *) p_desc)->bNrChannels; + audio->format_type_tx = (audio_format_type_t) (((audio_desc_cs_as_interface_t const *) p_desc)->bFormatType); // Look for a Type I Format Type Descriptor(2.3.1.6 - Audio Formats) - #if CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING || CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL || CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING + p_desc = tu_desc_next(p_desc); if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AS_INTERFACE_FORMAT_TYPE && ((audio_desc_type_I_format_t const *) p_desc)->bFormatType == AUDIO_FORMAT_TYPE_I) { - #if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_in_as_intf_num && as_itf != audio->ep_out_as_intf_num) break;// Abort loop, this interface has no EP, this driver does not support this currently - #endif - #if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_in_as_intf_num) break; - #endif - #if !CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_EP_OUT - if (as_itf != audio->ep_out_as_intf_num) break; - #endif - - #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (as_itf == audio->ep_in_as_intf_num) { - audio->n_bytes_per_sample_tx = ((audio_desc_type_I_format_t const *) p_desc)->bSubslotSize; - } - #endif - - #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - if (as_itf == audio->ep_out_as_intf_num) { - audio->n_bytes_per_sample_rx = ((audio_desc_type_I_format_t const *) p_desc)->bSubslotSize; - } - #endif + audio->n_bytes_per_sample_tx = ((audio_desc_type_I_format_t const *) p_desc)->bSubslotSize; } - #endif - - // Other format types are not supported yet - - p_desc = tu_desc_next(p_desc); } } -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL static bool audiod_calc_tx_packet_sz(audiod_function_t *audio) { TU_VERIFY(audio->format_type_tx == AUDIO_FORMAT_TYPE_I); diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 0a7bff212..603535b2a 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -206,153 +206,6 @@ // Audio control interrupt EP - 6 Bytes according to UAC 2 specification (p. 74) #define CFG_TUD_AUDIO_INTERRUPT_EP_SZ 6 -// Use software encoding/decoding - -// The software coding feature of the driver is not mandatory. It is useful if, for instance, you have two I2S streams which need to be interleaved -// into a single PCM stream as SAMPLE_1 | SAMPLE_2 | SAMPLE_3 | SAMPLE_4. -// -// Currently, only PCM type I encoding/decoding is supported! -// -// If the coding feature is to be used, support FIFOs need to be configured. Their sizes and numbers are defined below. - -// Encoding/decoding is done in software and thus time consuming. If you can encode/decode your stream more efficiently do not use the -// support FIFOs but write/read directly into/from the EP_X_SW_BUFFER_FIFOs using -// - tud_audio_n_write() or -// - tud_audio_n_read(). -// To write/read to/from the support FIFOs use -// - tud_audio_n_write_support_ff() or -// - tud_audio_n_read_support_ff(). -// -// The encoding/decoding format type done is defined below. -// -// The encoding/decoding starts when the private callback functions -// - audio_tx_done_cb() -// - audio_rx_done_cb() -// are invoked. If support FIFOs are used, the corresponding encoding/decoding functions are called from there. -// Once encoding/decoding is done the result is put directly into the EP_X_SW_BUFFER_FIFOs. You can use the public callback functions -// - tud_audio_tx_done_pre_load_cb() or tud_audio_tx_done_post_load_cb() -// - tud_audio_rx_done_pre_read_cb() or tud_audio_rx_done_post_read_cb() -// if you want to get informed what happened. -// -// If you don't use the support FIFOs you may use the public callback functions -// - tud_audio_tx_done_pre_load_cb() or tud_audio_tx_done_post_load_cb() -// - tud_audio_rx_done_pre_read_cb() or tud_audio_rx_done_post_read_cb() -// to write/read from/into the EP_X_SW_BUFFER_FIFOs at the right time. -// -// If you need a different encoding which is not support so far implement it in the -// - audio_tx_done_cb() -// - audio_rx_done_cb() -// functions. - -// Enable encoding/decodings - for these to work, support FIFOs need to be setup in appropriate numbers and size -// The actual coding parameters of active AS alternate interface is parsed from the descriptors - -// The item size of the FIFO is always fixed to one i.e. bytes! Furthermore, the actively used FIFO depth is reconfigured such that the depth is a multiple -// of the current sample size in order to avoid samples to get split up in case of a wrap in the FIFO ring buffer (depth = (max_depth / sample_sz) * sample_sz)! -// This is important to remind in case you use DMAs! If the sample sizes changes, the DMA MUST BE RECONFIGURED just like the FIFOs for a different depth!!! - -// For PCM encoding/decoding - -#ifndef CFG_TUD_AUDIO_ENABLE_ENCODING -#define CFG_TUD_AUDIO_ENABLE_ENCODING 0 -#endif - -#ifndef CFG_TUD_AUDIO_ENABLE_DECODING -#define CFG_TUD_AUDIO_ENABLE_DECODING 0 -#endif - -// This enabling allows to save the current coding parameters e.g. # of bytes per sample etc. - TYPE_I includes common PCM encoding -#ifndef CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING -#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 0 -#endif - -#ifndef CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING -#define CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING 0 -#endif - -// Type I Coding parameters not given within UAC2 descriptors -// It would be possible to allow for a more flexible setting and not fix this parameter as done below. However, this is most often not needed and kept for later if really necessary. The more flexible setting could be implemented within set_interface(), however, how the values are saved per alternate setting is to be determined! -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING -#ifndef CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#if CFG_TUD_AUDIO > 1 -#ifndef CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_TX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 2 -#ifndef CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_TX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#endif -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING && CFG_TUD_AUDIO_ENABLE_TYPE_I_DECODING -#ifndef CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_RX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#if CFG_TUD_AUDIO > 1 -#ifndef CFG_TUD_AUDIO_FUNC_2_CHANNEL_PER_FIFO_RX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#endif -#if CFG_TUD_AUDIO > 2 -#ifndef CFG_TUD_AUDIO_FUNC_3_CHANNEL_PER_FIFO_RX -#error You must tell the driver the number of channels per FIFO for the interleaved encoding! E.g. for an I2S interface having two channels, CHANNEL_PER_FIFO = 2 as the I2S stream having two channels is usually saved within one FIFO -#endif -#endif -#endif - -// Remaining types not support so far - -// Number of support FIFOs to set up - multiple channels can be handled by one FIFO - very common is two channels per FIFO stemming from one I2S interface -#ifndef CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_2_N_TX_SUPP_SW_FIFO 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_3_N_TX_SUPP_SW_FIFO 0 -#endif - -#ifndef CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_1_N_RX_SUPP_SW_FIFO 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_2_N_RX_SUPP_SW_FIFO 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO -#define CFG_TUD_AUDIO_FUNC_3_N_RX_SUPP_SW_FIFO 0 -#endif - -// Size of support FIFOs IN BYTES - if size > 0 there are as many FIFOs set up as CFG_TUD_AUDIO_FUNC_X_N_TX_SUPP_SW_FIFO and CFG_TUD_AUDIO_FUNC_X_N_RX_SUPP_SW_FIFO -#ifndef CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ 0 // FIFO size - minimum size: ceil(f_s/1000) * max(# of TX channels) / (# of TX support FIFOs) * max(# of bytes per sample) -#endif -#ifndef CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_2_TX_SUPP_SW_FIFO_SZ 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_3_TX_SUPP_SW_FIFO_SZ 0 -#endif - -#ifndef CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_1_RX_SUPP_SW_FIFO_SZ 0 // FIFO size - minimum size: ceil(f_s/1000) * max(# of RX channels) / (# of RX support FIFOs) * max(# of bytes per sample) -#endif -#ifndef CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_2_RX_SUPP_SW_FIFO_SZ 0 -#endif -#ifndef CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ -#define CFG_TUD_AUDIO_FUNC_3_RX_SUPP_SW_FIFO_SZ 0 -#endif - -//static_assert(sizeof(tud_audio_desc_lengths) != CFG_TUD_AUDIO, "Supply audio function descriptor pack length!"); - -// Supported types of this driver: -// AUDIO_DATA_FORMAT_TYPE_I_PCM - Required definitions: CFG_TUD_AUDIO_N_CHANNELS and CFG_TUD_AUDIO_BYTES_PER_CHANNEL - #ifdef __cplusplus extern "C" { #endif @@ -368,38 +221,23 @@ extern "C" { //--------------------------------------------------------------------+ bool tud_audio_n_mounted (uint8_t func_id); -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT uint16_t tud_audio_n_available (uint8_t func_id); uint16_t tud_audio_n_read (uint8_t func_id, void* buffer, uint16_t bufsize); bool tud_audio_n_clear_ep_out_ff (uint8_t func_id); // Delete all content in the EP OUT FIFO tu_fifo_t* tud_audio_n_get_ep_out_ff (uint8_t func_id); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING -bool tud_audio_n_clear_rx_support_ff (uint8_t func_id, uint8_t ff_idx); // Delete all content in the support RX FIFOs -uint16_t tud_audio_n_available_support_ff (uint8_t func_id, uint8_t ff_idx); -uint16_t tud_audio_n_read_support_ff (uint8_t func_id, uint8_t ff_idx, void* buffer, uint16_t bufsize); -tu_fifo_t* tud_audio_n_get_rx_support_ff (uint8_t func_id, uint8_t ff_idx); -#endif - -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN uint16_t tud_audio_n_write (uint8_t func_id, const void * data, uint16_t len); bool tud_audio_n_clear_ep_in_ff (uint8_t func_id); // Delete all content in the EP IN FIFO tu_fifo_t* tud_audio_n_get_ep_in_ff (uint8_t func_id); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING -uint16_t tud_audio_n_flush_tx_support_ff (uint8_t func_id); // Force all content in the support TX FIFOs to be written into EP SW FIFO -bool tud_audio_n_clear_tx_support_ff (uint8_t func_id, uint8_t ff_idx); -uint16_t tud_audio_n_write_support_ff (uint8_t func_id, uint8_t ff_idx, const void * data, uint16_t len); -tu_fifo_t* tud_audio_n_get_tx_support_ff (uint8_t func_id, uint8_t ff_idx); -#endif - #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP bool tud_audio_int_n_write (uint8_t func_id, const audio_interrupt_data_t * data); #endif - //--------------------------------------------------------------------+ // Application API (Interface0) //--------------------------------------------------------------------+ @@ -408,35 +246,21 @@ static inline bool tud_audio_mounted (void); // RX API -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT static inline uint16_t tud_audio_available (void); static inline bool tud_audio_clear_ep_out_ff (void); // Delete all content in the EP OUT FIFO static inline uint16_t tud_audio_read (void* buffer, uint16_t bufsize); static inline tu_fifo_t* tud_audio_get_ep_out_ff (void); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING -static inline bool tud_audio_clear_rx_support_ff (uint8_t ff_idx); -static inline uint16_t tud_audio_available_support_ff (uint8_t ff_idx); -static inline uint16_t tud_audio_read_support_ff (uint8_t ff_idx, void* buffer, uint16_t bufsize); -static inline tu_fifo_t* tud_audio_get_rx_support_ff (uint8_t ff_idx); -#endif - // TX API -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN static inline uint16_t tud_audio_write (const void * data, uint16_t len); static inline bool tud_audio_clear_ep_in_ff (void); static inline tu_fifo_t* tud_audio_get_ep_in_ff (void); #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING -static inline uint16_t tud_audio_flush_tx_support_ff (void); -static inline uint16_t tud_audio_clear_tx_support_ff (uint8_t ff_idx); -static inline uint16_t tud_audio_write_support_ff (uint8_t ff_idx, const void * data, uint16_t len); -static inline tu_fifo_t* tud_audio_get_tx_support_ff (uint8_t ff_idx); -#endif - // INT CTR API #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP @@ -593,7 +417,7 @@ static inline bool tud_audio_mounted(void) // RX API -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING +#if CFG_TUD_AUDIO_ENABLE_EP_OUT static inline uint16_t tud_audio_available(void) { @@ -617,33 +441,9 @@ static inline tu_fifo_t* tud_audio_get_ep_out_ff(void) #endif -#if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_DECODING - -static inline bool tud_audio_clear_rx_support_ff(uint8_t ff_idx) -{ - return tud_audio_n_clear_rx_support_ff(0, ff_idx); -} - -static inline uint16_t tud_audio_available_support_ff(uint8_t ff_idx) -{ - return tud_audio_n_available_support_ff(0, ff_idx); -} - -static inline uint16_t tud_audio_read_support_ff(uint8_t ff_idx, void* buffer, uint16_t bufsize) -{ - return tud_audio_n_read_support_ff(0, ff_idx, buffer, bufsize); -} - -static inline tu_fifo_t* tud_audio_get_rx_support_ff(uint8_t ff_idx) -{ - return tud_audio_n_get_rx_support_ff(0, ff_idx); -} - -#endif - // TX API -#if CFG_TUD_AUDIO_ENABLE_EP_IN && !CFG_TUD_AUDIO_ENABLE_ENCODING +#if CFG_TUD_AUDIO_ENABLE_EP_IN static inline uint16_t tud_audio_write(const void * data, uint16_t len) { @@ -662,30 +462,6 @@ static inline tu_fifo_t* tud_audio_get_ep_in_ff(void) #endif -#if CFG_TUD_AUDIO_ENABLE_EP_IN && CFG_TUD_AUDIO_ENABLE_ENCODING - -static inline uint16_t tud_audio_flush_tx_support_ff(void) -{ - return tud_audio_n_flush_tx_support_ff(0); -} - -static inline uint16_t tud_audio_clear_tx_support_ff(uint8_t ff_idx) -{ - return tud_audio_n_clear_tx_support_ff(0, ff_idx); -} - -static inline uint16_t tud_audio_write_support_ff(uint8_t ff_idx, const void * data, uint16_t len) -{ - return tud_audio_n_write_support_ff(0, ff_idx, data, len); -} - -static inline tu_fifo_t* tud_audio_get_tx_support_ff(uint8_t ff_idx) -{ - return tud_audio_n_get_tx_support_ff(0, ff_idx); -} - -#endif - #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP static inline bool tud_audio_int_write(const audio_interrupt_data_t * data) { -- cgit v1.3.1 From 56c9521abdef663b455a345c99a4f6b22591aa56 Mon Sep 17 00:00:00 2001 From: James Sandison Date: Wed, 4 Jun 2025 11:21:27 +1000 Subject: chore: squash previous commits from other branches --- docs/reference/boards.rst | 2 + docs/reference/dependencies.rst | 1 + examples/build_system/cmake/cpu/cortex-m55.cmake | 26 + examples/build_system/make/cpu/cortex-m55.mk | 28 + examples/device/net_lwip_webserver/skip.txt | 1 + examples/host/bare_api/only.txt | 1 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/cdc_msc_hid_freertos/only.txt | 1 + examples/host/device_info/only.txt | 1 + examples/host/hid_controller/only.txt | 1 + examples/host/midi_rx/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++ .../stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld | 203 +++ hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake | 25 + hw/bsp/stm32n6/boards/stm32n657nucleo/board.h | 283 ++++ hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk | 23 + .../boards/stm32n657nucleo/tcpp0203/LICENSE.txt | 6 + .../stm32n657nucleo/tcpp0203/Release_Notes.html | 205 +++ .../stm32n657nucleo/tcpp0203/_htmresc/favicon.png | Bin 0 -> 4126 bytes .../tcpp0203/_htmresc/mini-st_2020.css | 1703 ++++++++++++++++++++ .../tcpp0203/_htmresc/st_logo_2020.png | Bin 0 -> 7520 bytes .../boards/stm32n657nucleo/tcpp0203/tcpp0203.c | 886 ++++++++++ .../boards/stm32n657nucleo/tcpp0203/tcpp0203.h | 353 ++++ .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c | 73 + .../boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h | 98 ++ hw/bsp/stm32n6/family.c | 276 ++++ hw/bsp/stm32n6/family.cmake | 147 ++ hw/bsp/stm32n6/family.mk | 101 ++ hw/bsp/stm32n6/partition_stm32n657xx.h | 792 +++++++++ hw/bsp/stm32n6/stm32n6xx_hal_conf.h | 504 ++++++ hw/bsp/zephyr_board_aliases.cmake | 1 + src/common/tusb_mcu.h | 9 + src/portable/synopsys/dwc2/dcd_dwc2.c | 5 + src/portable/synopsys/dwc2/dwc2_info.py | 1 + src/portable/synopsys/dwc2/dwc2_stm32.h | 11 + src/portable/synopsys/dwc2/hcd_dwc2.c | 4 + src/tusb_option.h | 1 + tools/get_deps.py | 8 +- 39 files changed, 5931 insertions(+), 1 deletion(-) create mode 100644 examples/build_system/cmake/cpu/cortex-m55.cmake create mode 100644 examples/build_system/make/cpu/cortex-m55.mk create mode 100644 hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/STM32N657XX_AXISRAM2_fsbl.ld create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c create mode 100644 hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h create mode 100644 hw/bsp/stm32n6/family.c create mode 100644 hw/bsp/stm32n6/family.cmake create mode 100644 hw/bsp/stm32n6/family.mk create mode 100644 hw/bsp/stm32n6/partition_stm32n657xx.h create mode 100644 hw/bsp/stm32n6/stm32n6xx_hal_conf.h (limited to 'src') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 5786b2182..317a40c9c 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -269,6 +269,8 @@ stm32l412nucleo STM32 L412 Nucleo stm32l4 https://www.st stm32l476disco STM32 L476 Disco stm32l4 https://www.st.com/en/evaluation-tools/32l476gdiscovery.html stm32l4p5nucleo STM32 L4P5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html stm32l4r5nucleo STM32 L4R5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html +stm32n657_dk STM32 N657 Discovery Kit stm32n6 https://www.st.com/en/evaluation-tools/stm32n6570-dk.html +stm32n657nucleo STM32 N657 Nucleo stm32n6 https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html b_u585i_iot2a STM32 B-U585i IOT2A Discovery kit stm32u5 https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html stm32u545nucleo STM32 U545 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html stm32u575eval STM32 U575 Eval stm32u5 https://www.st.com/en/evaluation-tools/stm32u575i-ev.html diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst index e124466da..98545b4cf 100644 --- a/docs/reference/dependencies.rst +++ b/docs/reference/dependencies.rst @@ -57,6 +57,7 @@ hw/mcu/st/stm32l0xx_hal_driver https://github.com/STMicroelectronics/ hw/mcu/st/stm32l1xx_hal_driver https://github.com/STMicroelectronics/stm32l1xx_hal_driver.git 44efc446fa69ed8344e7fd966e68ed11043b35d9 stm32l1 hw/mcu/st/stm32l4xx_hal_driver https://github.com/STMicroelectronics/stm32l4xx_hal_driver.git aee3d5bf283ae5df87532b781bdd01b7caf256fc stm32l4 hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git 675c32a75df37f39d50d61f51cb0dcf53f07e1cb stm32l5 +hw/mcu/st/stm32n6xx_hal_driver https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git 49f9989d10cf6817d4b07ac01848956b46bd0fd6 stm32n6 hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5 hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c diff --git a/examples/build_system/cmake/cpu/cortex-m55.cmake b/examples/build_system/cmake/cpu/cortex-m55.cmake new file mode 100644 index 000000000..a7a57957c --- /dev/null +++ b/examples/build_system/cmake/cpu/cortex-m55.cmake @@ -0,0 +1,26 @@ +if (TOOLCHAIN STREQUAL "gcc") + set(TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m55 + -mfloat-abi=hard + -mfpu=fpv5-d16 + -mcmse + ) + set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "clang") + set(TOOLCHAIN_COMMON_FLAGS + --target=arm-none-eabi + -mcpu=cortex-m55 + -mfpu=fpv5-d16 + ) + set(FREERTOS_PORT GCC_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "iar") + set(TOOLCHAIN_COMMON_FLAGS + --cpu cortex-m55 + --fpu VFPv5_D16 + ) + set(FREERTOS_PORT IAR_ARM_CM55_NTZ_NONSECURE CACHE INTERNAL "") + +endif () diff --git a/examples/build_system/make/cpu/cortex-m55.mk b/examples/build_system/make/cpu/cortex-m55.mk new file mode 100644 index 000000000..de627caed --- /dev/null +++ b/examples/build_system/make/cpu/cortex-m55.mk @@ -0,0 +1,28 @@ +ifeq ($(TOOLCHAIN),gcc) + CFLAGS += \ + -mthumb \ + -mcpu=cortex-m55 \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + -mcmse + +else ifeq ($(TOOLCHAIN),clang) + CFLAGS += \ + --target=arm-none-eabi \ + -mcpu=cortex-m55 \ + -mfpu=fpv5-d16 \ + +else ifeq ($(TOOLCHAIN),iar) + CFLAGS += \ + --cpu cortex-m55 \ + --fpu VFPv5_D16 \ + + ASFLAGS += \ + --cpu cortex-m55 \ + --fpu VFPv5_D16 \ + +else + $(error "TOOLCHAIN is not supported") +endif + +FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM55_NTZ/non_secure diff --git a/examples/device/net_lwip_webserver/skip.txt b/examples/device/net_lwip_webserver/skip.txt index 5ebe71612..c2e0d54ec 100644 --- a/examples/device/net_lwip_webserver/skip.txt +++ b/examples/device/net_lwip_webserver/skip.txt @@ -10,6 +10,7 @@ mcu:SAMD11 mcu:STM32L0 mcu:STM32F0 mcu:KINETIS_KL +mcu:STM32N6 family:broadcom_64bit family:broadcom_32bit family:espressif diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index e3ae25260..4ff3841a4 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -13,3 +13,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index b6f87f423..6e6e2184f 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -18,3 +18,4 @@ mcu:RAXXX mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt index b6f87f423..6e6e2184f 100644 --- a/examples/host/midi_rx/only.txt +++ b/examples/host/midi_rx/only.txt @@ -18,3 +18,4 @@ mcu:RAXXX mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 95f9f1d82..9b8d535e6 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -15,3 +15,4 @@ mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 +mcu:STM32N6 diff --git a/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..9fd3f6c50 --- /dev/null +++ b/hw/bsp/stm32n6/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32h7rsxx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*8*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 4 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<ROM + + /* The program code and other data into "RAM" Ram type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >ROM + + /* Constant data into "RAM" Ram type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >ROM + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >ROM + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >ROM + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >ROM + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >ROM + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >ROM + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> ROM + + .noncacheable : + { + . = ALIGN(8); + __snoncacheable = .;/* create symbol for start of section */ + KEEP(*(.noncacheable)) + . = ALIGN(8); + __enoncacheable = .; /* create symbol for end of section */ + } > RAM + + + .gnu.sgstubs : + { + . = ALIGN(4); + *(.gnu.sgstubs*) /* Secure Gateway stubs */ + . = ALIGN(4); + } >ROM + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake new file mode 100644 index 000000000..197b5108f --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.cmake @@ -0,0 +1,25 @@ +set(MCU_VARIANT stm32n657xx) +set(JLINK_DEVICE stm32n6xx) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32N657XX_LRUN.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + +function(update_board TARGET) + + target_compile_definitions(${TARGET} PUBLIC + STM32N6xx + SEGGER_RTT_SECTION="noncacheable_buffer" + BUFFER_SIZE_UP=0x3000 + ) + + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203/tcpp0203_reg.c + ) + target_include_directories(${TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tcpp0203 + ) +endfunction() diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h new file mode 100644 index 000000000..d3781c6d0 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.h @@ -0,0 +1,283 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: STM32 H723 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stm32n657xx.h" +#include "stm32n6xx_ll_exti.h" +#include "stm32n6xx_ll_system.h" +#include "tcpp0203.h" + +#define UART_DEV USART1 +#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE + +#define BOARD_TUD_RHPORT 1 + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 1 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_TCPP0203_EN 4 + +static board_pindef_t board_pindef[] = { + {// LED + .port = GPIOG, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// Button + .port = GPIOC, + .pin_init = {.Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 1}, + {// UART TX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_5, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// UART RX + .port = GPIOE, + .pin_init = {.Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF7_USART1}, + .active_state = 0}, + {// VBUS input pin used for TCPP0203 EN + .port = GPIOA, + .pin_init = {.Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + .active_state = 0}, + { + // I2C SCL for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // I2C SDA for TCPP0203 + .port = GPIOB, + .pin_init = {.Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_FREQ_LOW, .Alternate = GPIO_AF4_I2C2}, + }, + { + // INT for TCPP0203 + .port = GPIOD, + .pin_init = {.Pin = GPIO_PIN_2, .Mode = GPIO_MODE_IT_FALLING, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_FREQ_HIGH, .Alternate = 0}, + }, +}; + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + /* Configure the power domain */ + if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY) != HAL_OK) { + Error_Handler(); + } + + /* Get current CPU/System buses clocks configuration */ + /* and if necessary switch to intermediate HSI clock */ + /* to ensure target clock can be set */ + HAL_RCC_GetClockConfig(&RCC_ClkInitStruct); + if ((RCC_ClkInitStruct.CPUCLKSource == RCC_CPUCLKSOURCE_IC1) || + (RCC_ClkInitStruct.SYSCLKSource == RCC_SYSCLKSOURCE_IC2_IC6_IC11)) { + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_HSI; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + Error_Handler(); + } + } + + /* HSE selected as source (stable clock on Level 0 samples */ + /* PLL1 output = ((HSE/PLLM)*PLLN)/PLLP1/PLLP2 */ + /* = ((48000000/3)*75)/1/1 */ + /* = (16000000*75)/1/1 */ + /* = 1200000000 (1200 MHz) */ + /* PLL2 off */ + /* PLL3 off */ + /* PLL4 off */ + + /* Enable HSE && HSI */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* 48 MHz */ + + RCC_OscInitStruct.PLL1.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL1.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL1.PLLM = 3; + RCC_OscInitStruct.PLL1.PLLN = 75; /* PLL1 VCO = 48/3 * 75 = 1200MHz */ + RCC_OscInitStruct.PLL1.PLLP1 = 1; /* PLL output = PLL VCO frequency / (PLLP1 * PLLP2) */ + RCC_OscInitStruct.PLL1.PLLP2 = 1; /* PLL output = 1200 MHz */ + RCC_OscInitStruct.PLL1.PLLFractional = 0; + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + /* Initialization error */ + Error_Handler(); + } + + /* Select PLL1 outputs as CPU and System bus clock source */ + /* CPUCLK = ic1_ck = PLL1 output/ic1_divider = 600 MHz */ + /* SYSCLK = ic2_ck = PLL1 output/ic2_divider = 400 MHz */ + /* Configure the HCLK clock divider */ + /* HCLK = PLL1 SYSCLK/HCLK divider = 200 MHz */ + /* PCLKx = HCLK / PCLKx divider = 200 MHz */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_CPUCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK4 | RCC_CLOCKTYPE_PCLK5); + RCC_ClkInitStruct.CPUCLKSource = RCC_CPUCLKSOURCE_IC1; + RCC_ClkInitStruct.IC1Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC1Selection.ClockDivider = 2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_IC2_IC6_IC11; + RCC_ClkInitStruct.IC2Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC2Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC6Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC6Selection.ClockDivider = 3; + RCC_ClkInitStruct.IC11Selection.ClockSelection = RCC_ICCLKSOURCE_PLL1; + RCC_ClkInitStruct.IC11Selection.ClockDivider = 3; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + RCC_ClkInitStruct.APB5CLKDivider = RCC_APB5_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Initializes the peripherals clock + */ + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBOTGHS1; + PeriphClkInitStruct.UsbOtgHs1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } + + /** Set USB OTG HS PHY1 Reference Clock Source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USBPHY1; + PeriphClkInitStruct.UsbPhy1ClockSelection = RCC_USBPHY1REFCLKSOURCE_HSE_DIRECT; + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + /* Initialization Error */ + Error_Handler(); + } +} + +//--------------------------------------------------------------------+ +// USB PD +//--------------------------------------------------------------------+ +static I2C_HandleTypeDef i2c_handle = { + .Instance = I2C2, + .Init = { + .Timing = 0x20C0EDFF, + .OwnAddress1 = 0, + .AddressingMode = I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = I2C_DUALADDRESS_DISABLE, + .OwnAddress2 = 0, + .OwnAddress2Masks = I2C_OA2_NOMASK, + .GeneralCallMode = I2C_GENERALCALL_DISABLE, + .NoStretchMode = I2C_NOSTRETCH_DISABLE, + }}; +static TCPP0203_Object_t tcpp0203_obj = {0}; + +int32_t board_tcpp0203_init(void) { + board_pindef_t *pindef = &board_pindef[PINID_TCPP0203_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, GPIO_PIN_SET); + + __HAL_RCC_I2C2_CLK_ENABLE(); + __HAL_RCC_I2C2_FORCE_RESET(); + __HAL_RCC_I2C2_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { + return HAL_ERROR; + } + + NVIC_SetPriority(EXTI8_IRQn, 12); + NVIC_EnableIRQ(EXTI8_IRQn); + + return 0; +} + +int32_t board_tcpp0203_deinit(void) { + return 0; +} + +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); + return 0; +} + +static inline void board_init2(void) { + TCPP0203_IO_t io_ctx; + + io_ctx.Address = TCPP0203_I2C_ADDRESS_X68; + io_ctx.Init = board_tcpp0203_init; + io_ctx.DeInit = board_tcpp0203_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + + TU_ASSERT(TCPP0203_RegisterBusIO(&tcpp0203_obj, &io_ctx) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_Init(&tcpp0203_obj) == TCPP0203_OK, ); + + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); +} + +void board_vbus_set(uint8_t rhport, bool state) { + (void) state; + if (rhport == 1) { + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +void EXTI8_IRQHandler(void) { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_PIN_8); + if (tcpp0203_obj.IsInitialized) { + TU_ASSERT(TCPP0203_SetPowerMode(&tcpp0203_obj, TCPP0203_POWER_MODE_NORMAL) == TCPP0203_OK, ); + TU_ASSERT(TCPP0203_SetGateDriverProvider(&tcpp0203_obj, TCPP0203_GD_PROVIDER_SWITCH_CLOSED) == TCPP0203_OK, ); + } +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk new file mode 100644 index 000000000..b851da0ca --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/board.mk @@ -0,0 +1,23 @@ +MCU_VARIANT = stm32n6xx +CFLAGS += -DSTM32N6xx + +# For flash-jlink target +JLINK_DEVICE = stm32n6xx + +# flash target using on-board stlink +flash: flash-stlink + +PORT = 1 + + +SRC_C += \ + $(BOARD_PATH)/tcpp0203/tcpp0203.c \ + $(BOARD_PATH)/tcpp0203/tcpp0203_reg.c \ + +INC += \ + $(TOP)/$(BOARD_PATH)/tcpp0203 \ + +CFLAGS += \ + -DSEGGER_RTT_SECTION=\"noncacheable_buffer\" \ + -DSTM32N657xx + -DBUFFER_SIZE_UP=0x3000 \ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt new file mode 100644 index 000000000..1cbbc544a --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the BSD-3-Clause license shall apply. +You may obtain a copy of the BSD-3-Clause at: +https://opensource.org/licenses/BSD-3-Clause diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html new file mode 100644 index 000000000..6bbba86a4 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/Release_Notes.html @@ -0,0 +1,205 @@ + + + + + + + Release Notes for TCPP0203 Component Driver + + + + + + +
+
+
+

Release Notes for TCPP0203 Component Driver

+

Copyright © 2020 STMicroelectronics
+

+ +
+

Purpose

+

This driver provides a set of functions needed to drive TCPP0203 Type-C Port Protection component

+
+
+

Update History

+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + +
Headline
MISRA Rule-81.13 correction on TCPP0203 component driver files
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MISRA corrections on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.8.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
License updates
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.6.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
CodeSpell correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+ + + + + + + + + + + + +
Fixed bugs list
Headline
MCUAstyle correction on TCPP0203 component driver files
+

Known Limitations

+

Outstanding bugs list : None

+

Requirements not met or planned in a forthcoming release : None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V8.32.3
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.27.1
    • +
  • STM32CubeIDE toolchain V1.5.0
    • +
+

Backward compatibility

+

No compatibility break with previous version

+

Dependencies

+
+
+
+ +
+

Main Changes

+
    +
  • First official release of TCPP0203 Type-C port Protection Component drivers
    • +
+
+
+
+
+
+

For complete documentation on STM32,visit: [www.st.com/stm32]

+This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge. +
+ + diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png new file mode 100644 index 000000000..06713eec4 Binary files /dev/null and b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/favicon.png differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css new file mode 100644 index 000000000..dd19969d1 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/mini-st_2020.css @@ -0,0 +1,1703 @@ +@charset "UTF-8"; +/* + Flavor name: Custom (mini-custom) + Generated online - https://minicss.org/flavors + mini.css version: v3.0.1 +*/ +/* + Browsers resets and base typography. +*/ +/* Core module CSS variable definitions */ +:root { + --fore-color: #03234b; + --secondary-fore-color: #03234b; + --back-color: #ffffff; + --secondary-back-color: #ffffff; + --blockquote-color: #e6007e; + --pre-color: #e6007e; + --border-color: #3cb4e6; + --secondary-border-color: #3cb4e6; + --heading-ratio: 1.2; + --universal-margin: 0.5rem; + --universal-padding: 0.25rem; + --universal-border-radius: 0.075rem; + --background-margin: 1.5%; + --a-link-color: #3cb4e6; + --a-visited-color: #8c0078; } + +html { + font-size: 13.5px; } + +a, b, del, em, i, ins, q, span, strong, u { + font-size: 1em; } + +html, * { + font-family: -apple-system, BlinkMacSystemFont, Helvetica, arial, sans-serif; + line-height: 1.25; + -webkit-text-size-adjust: 100%; } + +* { + font-size: 1rem; } + +body { + margin: 0; + color: var(--fore-color); + @background: var(--back-color); + background: var(--back-color) linear-gradient(#ffd200, #ffd200) repeat-y left top; + background-size: var(--background-margin); + } + +details { + display: block; } + +summary { + display: list-item; } + +abbr[title] { + border-bottom: none; + text-decoration: underline dotted; } + +input { + overflow: visible; } + +img { + max-width: 100%; + height: auto; } + +h1, h2, h3, h4, h5, h6 { + line-height: 1.25; + margin: calc(1.5 * var(--universal-margin)) var(--universal-margin); + font-weight: 400; } + h1 small, h2 small, h3 small, h4 small, h5 small, h6 small { + color: var(--secondary-fore-color); + display: block; + margin-top: -0.25rem; } + +h1 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) * var(--heading-ratio)); } + +h2 { + font-size: calc(1rem * var(--heading-ratio) * var(--heading-ratio) ); + border-style: none none solid none ; + border-width: thin; + border-color: var(--border-color); } +h3 { + font-size: calc(1rem * var(--heading-ratio) ); } + +h4 { + font-size: calc(1rem * var(--heading-ratio)); } + +h5 { + font-size: 1rem; } + +h6 { + font-size: calc(1rem / var(--heading-ratio)); } + +p { + margin: var(--universal-margin); } + +ol, ul { + margin: var(--universal-margin); + padding-left: calc(3 * var(--universal-margin)); } + +b, strong { + font-weight: 700; } + +hr { + box-sizing: content-box; + border: 0; + line-height: 1.25em; + margin: var(--universal-margin); + height: 0.0714285714rem; + background: linear-gradient(to right, transparent, var(--border-color) 20%, var(--border-color) 80%, transparent); } + +blockquote { + display: block; + position: relative; + font-style: italic; + color: var(--secondary-fore-color); + margin: var(--universal-margin); + padding: calc(3 * var(--universal-padding)); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.3rem solid var(--blockquote-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + blockquote:before { + position: absolute; + top: calc(0rem - var(--universal-padding)); + left: 0; + font-family: sans-serif; + font-size: 2rem; + font-weight: 800; + content: "\201c"; + color: var(--blockquote-color); } + blockquote[cite]:after { + font-style: normal; + font-size: 0.75em; + font-weight: 700; + content: "\a— " attr(cite); + white-space: pre; } + +code, kbd, pre, samp { + font-family: Menlo, Consolas, monospace; + font-size: 0.85em; } + +code { + background: var(--secondary-back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +kbd { + background: var(--fore-color); + color: var(--back-color); + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) calc(var(--universal-padding) / 2); } + +pre { + overflow: auto; + background: var(--secondary-back-color); + padding: calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + border: 0.0714285714rem solid var(--secondary-border-color); + border-left: 0.2857142857rem solid var(--pre-color); + border-radius: 0 var(--universal-border-radius) var(--universal-border-radius) 0; } + +sup, sub, code, kbd { + line-height: 0; + position: relative; + vertical-align: baseline; } + +small, sup, sub, figcaption { + font-size: 0.75em; } + +sup { + top: -0.5em; } + +sub { + bottom: -0.25em; } + +figure { + margin: var(--universal-margin); } + +figcaption { + color: var(--secondary-fore-color); } + +a { + text-decoration: none; } + a:link { + color: var(--a-link-color); } + a:visited { + color: var(--a-visited-color); } + a:hover, a:focus { + text-decoration: underline; } + +/* + Definitions for the grid system, cards and containers. +*/ +.container { + margin: 0 auto; + padding: 0 calc(1.5 * var(--universal-padding)); } + +.row { + box-sizing: border-box; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + margin: 0 0 0 var(--background-margin); } + +.col-sm, +[class^='col-sm-'], +[class^='col-sm-offset-'], +.row[class*='cols-sm-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + +.col-sm, +.row.cols-sm > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + +.col-sm-1, +.row.cols-sm-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + +.col-sm-offset-0 { + margin-left: 0; } + +.col-sm-2, +.row.cols-sm-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + +.col-sm-offset-1 { + margin-left: 8.3333333333%; } + +.col-sm-3, +.row.cols-sm-3 > * { + max-width: 25%; + flex-basis: 25%; } + +.col-sm-offset-2 { + margin-left: 16.6666666667%; } + +.col-sm-4, +.row.cols-sm-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + +.col-sm-offset-3 { + margin-left: 25%; } + +.col-sm-5, +.row.cols-sm-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + +.col-sm-offset-4 { + margin-left: 33.3333333333%; } + +.col-sm-6, +.row.cols-sm-6 > * { + max-width: 50%; + flex-basis: 50%; } + +.col-sm-offset-5 { + margin-left: 41.6666666667%; } + +.col-sm-7, +.row.cols-sm-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + +.col-sm-offset-6 { + margin-left: 50%; } + +.col-sm-8, +.row.cols-sm-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + +.col-sm-offset-7 { + margin-left: 58.3333333333%; } + +.col-sm-9, +.row.cols-sm-9 > * { + max-width: 75%; + flex-basis: 75%; } + +.col-sm-offset-8 { + margin-left: 66.6666666667%; } + +.col-sm-10, +.row.cols-sm-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + +.col-sm-offset-9 { + margin-left: 75%; } + +.col-sm-11, +.row.cols-sm-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + +.col-sm-offset-10 { + margin-left: 83.3333333333%; } + +.col-sm-12, +.row.cols-sm-12 > * { + max-width: 100%; + flex-basis: 100%; } + +.col-sm-offset-11 { + margin-left: 91.6666666667%; } + +.col-sm-normal { + order: initial; } + +.col-sm-first { + order: -999; } + +.col-sm-last { + order: 999; } + +@media screen and (min-width: 500px) { + .col-md, + [class^='col-md-'], + [class^='col-md-offset-'], + .row[class*='cols-md-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-md, + .row.cols-md > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-md-1, + .row.cols-md-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-md-offset-0 { + margin-left: 0; } + + .col-md-2, + .row.cols-md-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-md-offset-1 { + margin-left: 8.3333333333%; } + + .col-md-3, + .row.cols-md-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-md-offset-2 { + margin-left: 16.6666666667%; } + + .col-md-4, + .row.cols-md-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-md-offset-3 { + margin-left: 25%; } + + .col-md-5, + .row.cols-md-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-md-offset-4 { + margin-left: 33.3333333333%; } + + .col-md-6, + .row.cols-md-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-md-offset-5 { + margin-left: 41.6666666667%; } + + .col-md-7, + .row.cols-md-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-md-offset-6 { + margin-left: 50%; } + + .col-md-8, + .row.cols-md-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-md-offset-7 { + margin-left: 58.3333333333%; } + + .col-md-9, + .row.cols-md-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-md-offset-8 { + margin-left: 66.6666666667%; } + + .col-md-10, + .row.cols-md-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-md-offset-9 { + margin-left: 75%; } + + .col-md-11, + .row.cols-md-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-md-offset-10 { + margin-left: 83.3333333333%; } + + .col-md-12, + .row.cols-md-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-md-offset-11 { + margin-left: 91.6666666667%; } + + .col-md-normal { + order: initial; } + + .col-md-first { + order: -999; } + + .col-md-last { + order: 999; } } +@media screen and (min-width: 1280px) { + .col-lg, + [class^='col-lg-'], + [class^='col-lg-offset-'], + .row[class*='cols-lg-'] > * { + box-sizing: border-box; + flex: 0 0 auto; + padding: 0 calc(var(--universal-padding) / 2); } + + .col-lg, + .row.cols-lg > * { + max-width: 100%; + flex-grow: 1; + flex-basis: 0; } + + .col-lg-1, + .row.cols-lg-1 > * { + max-width: 8.3333333333%; + flex-basis: 8.3333333333%; } + + .col-lg-offset-0 { + margin-left: 0; } + + .col-lg-2, + .row.cols-lg-2 > * { + max-width: 16.6666666667%; + flex-basis: 16.6666666667%; } + + .col-lg-offset-1 { + margin-left: 8.3333333333%; } + + .col-lg-3, + .row.cols-lg-3 > * { + max-width: 25%; + flex-basis: 25%; } + + .col-lg-offset-2 { + margin-left: 16.6666666667%; } + + .col-lg-4, + .row.cols-lg-4 > * { + max-width: 33.3333333333%; + flex-basis: 33.3333333333%; } + + .col-lg-offset-3 { + margin-left: 25%; } + + .col-lg-5, + .row.cols-lg-5 > * { + max-width: 41.6666666667%; + flex-basis: 41.6666666667%; } + + .col-lg-offset-4 { + margin-left: 33.3333333333%; } + + .col-lg-6, + .row.cols-lg-6 > * { + max-width: 50%; + flex-basis: 50%; } + + .col-lg-offset-5 { + margin-left: 41.6666666667%; } + + .col-lg-7, + .row.cols-lg-7 > * { + max-width: 58.3333333333%; + flex-basis: 58.3333333333%; } + + .col-lg-offset-6 { + margin-left: 50%; } + + .col-lg-8, + .row.cols-lg-8 > * { + max-width: 66.6666666667%; + flex-basis: 66.6666666667%; } + + .col-lg-offset-7 { + margin-left: 58.3333333333%; } + + .col-lg-9, + .row.cols-lg-9 > * { + max-width: 75%; + flex-basis: 75%; } + + .col-lg-offset-8 { + margin-left: 66.6666666667%; } + + .col-lg-10, + .row.cols-lg-10 > * { + max-width: 83.3333333333%; + flex-basis: 83.3333333333%; } + + .col-lg-offset-9 { + margin-left: 75%; } + + .col-lg-11, + .row.cols-lg-11 > * { + max-width: 91.6666666667%; + flex-basis: 91.6666666667%; } + + .col-lg-offset-10 { + margin-left: 83.3333333333%; } + + .col-lg-12, + .row.cols-lg-12 > * { + max-width: 100%; + flex-basis: 100%; } + + .col-lg-offset-11 { + margin-left: 91.6666666667%; } + + .col-lg-normal { + order: initial; } + + .col-lg-first { + order: -999; } + + .col-lg-last { + order: 999; } } +/* Card component CSS variable definitions */ +:root { + --card-back-color: #3cb4e6; + --card-fore-color: #03234b; + --card-border-color: #03234b; } + +.card { + display: flex; + flex-direction: column; + justify-content: space-between; + align-self: center; + position: relative; + width: 100%; + background: var(--card-back-color); + color: var(--card-fore-color); + border: 0.0714285714rem solid var(--card-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + overflow: hidden; } + @media screen and (min-width: 320px) { + .card { + max-width: 320px; } } + .card > .sectione { + background: var(--card-back-color); + color: var(--card-fore-color); + box-sizing: border-box; + margin: 0; + border: 0; + border-radius: 0; + border-bottom: 0.0714285714rem solid var(--card-border-color); + padding: var(--universal-padding); + width: 100%; } + .card > .sectione.media { + height: 200px; + padding: 0; + -o-object-fit: cover; + object-fit: cover; } + .card > .sectione:last-child { + border-bottom: 0; } + +/* + Custom elements for card elements. +*/ +@media screen and (min-width: 240px) { + .card.small { + max-width: 240px; } } +@media screen and (min-width: 480px) { + .card.large { + max-width: 480px; } } +.card.fluid { + max-width: 100%; + width: auto; } + +.card.warning { + --card-back-color: #e5b8b7; + --card-fore-color: #3b234b; + --card-border-color: #8c0078; } + +.card.error { + --card-back-color: #464650; + --card-fore-color: #ffffff; + --card-border-color: #8c0078; } + +.card > .sectione.dark { + --card-back-color: #3b234b; + --card-fore-color: #ffffff; } + +.card > .sectione.double-padded { + padding: calc(1.5 * var(--universal-padding)); } + +/* + Definitions for forms and input elements. +*/ +/* Input_control module CSS variable definitions */ +:root { + --form-back-color: #ffe97f; + --form-fore-color: #03234b; + --form-border-color: #3cb4e6; + --input-back-color: #ffffff; + --input-fore-color: #03234b; + --input-border-color: #3cb4e6; + --input-focus-color: #0288d1; + --input-invalid-color: #d32f2f; + --button-back-color: #e2e2e2; + --button-hover-back-color: #dcdcdc; + --button-fore-color: #212121; + --button-border-color: transparent; + --button-hover-border-color: transparent; + --button-group-border-color: rgba(124, 124, 124, 0.54); } + +form { + background: var(--form-back-color); + color: var(--form-fore-color); + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); } + +fieldset { + border: 0.0714285714rem solid var(--form-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 4); + padding: var(--universal-padding); } + +legend { + box-sizing: border-box; + display: table; + max-width: 100%; + white-space: normal; + font-weight: 500; + padding: calc(var(--universal-padding) / 2); } + +label { + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +.input-group { + display: inline-block; } + .input-group.fluid { + display: flex; + align-items: center; + justify-content: center; } + .input-group.fluid > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + @media screen and (max-width: 499px) { + .input-group.fluid { + align-items: stretch; + flex-direction: column; } } + .input-group.vertical { + display: flex; + align-items: stretch; + flex-direction: column; } + .input-group.vertical > input { + max-width: 100%; + flex-grow: 1; + flex-basis: 0px; } + +[type="number"]::-webkit-inner-spin-button, [type="number"]::-webkit-outer-spin-button { + height: auto; } + +[type="search"] { + -webkit-appearance: textfield; + outline-offset: -2px; } + +[type="search"]::-webkit-search-cancel-button, +[type="search"]::-webkit-search-decoration { + -webkit-appearance: none; } + +input:not([type]), [type="text"], [type="email"], [type="number"], [type="search"], +[type="password"], [type="url"], [type="tel"], [type="checkbox"], [type="radio"], textarea, select { + box-sizing: border-box; + background: var(--input-back-color); + color: var(--input-fore-color); + border: 0.0714285714rem solid var(--input-border-color); + border-radius: var(--universal-border-radius); + margin: calc(var(--universal-margin) / 2); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + +input:not([type="button"]):not([type="submit"]):not([type="reset"]):hover, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus, textarea:hover, textarea:focus, select:hover, select:focus { + border-color: var(--input-focus-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"]):invalid, input:not([type="button"]):not([type="submit"]):not([type="reset"]):focus:invalid, textarea:invalid, textarea:focus:invalid, select:invalid, select:focus:invalid { + border-color: var(--input-invalid-color); + box-shadow: none; } +input:not([type="button"]):not([type="submit"]):not([type="reset"])[readonly], textarea[readonly], select[readonly] { + background: var(--secondary-back-color); } + +select { + max-width: 100%; } + +option { + overflow: hidden; + text-overflow: ellipsis; } + +[type="checkbox"], [type="radio"] { + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + position: relative; + height: calc(1rem + var(--universal-padding) / 2); + width: calc(1rem + var(--universal-padding) / 2); + vertical-align: text-bottom; + padding: 0; + flex-basis: calc(1rem + var(--universal-padding) / 2) !important; + flex-grow: 0 !important; } + [type="checkbox"]:checked:before, [type="radio"]:checked:before { + position: absolute; } + +[type="checkbox"]:checked:before { + content: '\2713'; + font-family: sans-serif; + font-size: calc(1rem + var(--universal-padding) / 2); + top: calc(0rem - var(--universal-padding)); + left: calc(var(--universal-padding) / 4); } + +[type="radio"] { + border-radius: 100%; } + [type="radio"]:checked:before { + border-radius: 100%; + content: ''; + top: calc(0.0714285714rem + var(--universal-padding) / 2); + left: calc(0.0714285714rem + var(--universal-padding) / 2); + background: var(--input-fore-color); + width: 0.5rem; + height: 0.5rem; } + +:placeholder-shown { + color: var(--input-fore-color); } + +::-ms-placeholder { + color: var(--input-fore-color); + opacity: 0.54; } + +button::-moz-focus-inner, [type="button"]::-moz-focus-inner, [type="reset"]::-moz-focus-inner, [type="submit"]::-moz-focus-inner { + border-style: none; + padding: 0; } + +button, html [type="button"], [type="reset"], [type="submit"] { + -webkit-appearance: button; } + +button { + overflow: visible; + text-transform: none; } + +button, [type="button"], [type="submit"], [type="reset"], +a.button, label.button, .button, +a[role="button"], label[role="button"], [role="button"] { + display: inline-block; + background: var(--button-back-color); + color: var(--button-fore-color); + border: 0.0714285714rem solid var(--button-border-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); + margin: var(--universal-margin); + text-decoration: none; + cursor: pointer; + transition: background 0.3s; } + button:hover, button:focus, [type="button"]:hover, [type="button"]:focus, [type="submit"]:hover, [type="submit"]:focus, [type="reset"]:hover, [type="reset"]:focus, + a.button:hover, + a.button:focus, label.button:hover, label.button:focus, .button:hover, .button:focus, + a[role="button"]:hover, + a[role="button"]:focus, label[role="button"]:hover, label[role="button"]:focus, [role="button"]:hover, [role="button"]:focus { + background: var(--button-hover-back-color); + border-color: var(--button-hover-border-color); } + +input:disabled, input[disabled], textarea:disabled, textarea[disabled], select:disabled, select[disabled], button:disabled, button[disabled], .button:disabled, .button[disabled], [role="button"]:disabled, [role="button"][disabled] { + cursor: not-allowed; + opacity: 0.75; } + +.button-group { + display: flex; + border: 0.0714285714rem solid var(--button-group-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + .button-group > button, .button-group [type="button"], .button-group > [type="submit"], .button-group > [type="reset"], .button-group > .button, .button-group > [role="button"] { + margin: 0; + max-width: 100%; + flex: 1 1 auto; + text-align: center; + border: 0; + border-radius: 0; + box-shadow: none; } + .button-group > :not(:first-child) { + border-left: 0.0714285714rem solid var(--button-group-border-color); } + @media screen and (max-width: 499px) { + .button-group { + flex-direction: column; } + .button-group > :not(:first-child) { + border: 0; + border-top: 0.0714285714rem solid var(--button-group-border-color); } } + +/* + Custom elements for forms and input elements. +*/ +button.primary, [type="button"].primary, [type="submit"].primary, [type="reset"].primary, .button.primary, [role="button"].primary { + --button-back-color: #1976d2; + --button-fore-color: #f8f8f8; } + button.primary:hover, button.primary:focus, [type="button"].primary:hover, [type="button"].primary:focus, [type="submit"].primary:hover, [type="submit"].primary:focus, [type="reset"].primary:hover, [type="reset"].primary:focus, .button.primary:hover, .button.primary:focus, [role="button"].primary:hover, [role="button"].primary:focus { + --button-hover-back-color: #1565c0; } + +button.secondary, [type="button"].secondary, [type="submit"].secondary, [type="reset"].secondary, .button.secondary, [role="button"].secondary { + --button-back-color: #d32f2f; + --button-fore-color: #f8f8f8; } + button.secondary:hover, button.secondary:focus, [type="button"].secondary:hover, [type="button"].secondary:focus, [type="submit"].secondary:hover, [type="submit"].secondary:focus, [type="reset"].secondary:hover, [type="reset"].secondary:focus, .button.secondary:hover, .button.secondary:focus, [role="button"].secondary:hover, [role="button"].secondary:focus { + --button-hover-back-color: #c62828; } + +button.tertiary, [type="button"].tertiary, [type="submit"].tertiary, [type="reset"].tertiary, .button.tertiary, [role="button"].tertiary { + --button-back-color: #308732; + --button-fore-color: #f8f8f8; } + button.tertiary:hover, button.tertiary:focus, [type="button"].tertiary:hover, [type="button"].tertiary:focus, [type="submit"].tertiary:hover, [type="submit"].tertiary:focus, [type="reset"].tertiary:hover, [type="reset"].tertiary:focus, .button.tertiary:hover, .button.tertiary:focus, [role="button"].tertiary:hover, [role="button"].tertiary:focus { + --button-hover-back-color: #277529; } + +button.inverse, [type="button"].inverse, [type="submit"].inverse, [type="reset"].inverse, .button.inverse, [role="button"].inverse { + --button-back-color: #212121; + --button-fore-color: #f8f8f8; } + button.inverse:hover, button.inverse:focus, [type="button"].inverse:hover, [type="button"].inverse:focus, [type="submit"].inverse:hover, [type="submit"].inverse:focus, [type="reset"].inverse:hover, [type="reset"].inverse:focus, .button.inverse:hover, .button.inverse:focus, [role="button"].inverse:hover, [role="button"].inverse:focus { + --button-hover-back-color: #111; } + +button.small, [type="button"].small, [type="submit"].small, [type="reset"].small, .button.small, [role="button"].small { + padding: calc(0.5 * var(--universal-padding)) calc(0.75 * var(--universal-padding)); + margin: var(--universal-margin); } + +button.large, [type="button"].large, [type="submit"].large, [type="reset"].large, .button.large, [role="button"].large { + padding: calc(1.5 * var(--universal-padding)) calc(2 * var(--universal-padding)); + margin: var(--universal-margin); } + +/* + Definitions for navigation elements. +*/ +/* Navigation module CSS variable definitions */ +:root { + --header-back-color: #03234b; + --header-hover-back-color: #ffd200; + --header-fore-color: #ffffff; + --header-border-color: #3cb4e6; + --nav-back-color: #ffffff; + --nav-hover-back-color: #ffe97f; + --nav-fore-color: #e6007e; + --nav-border-color: #3cb4e6; + --nav-link-color: #3cb4e6; + --footer-fore-color: #ffffff; + --footer-back-color: #03234b; + --footer-border-color: #3cb4e6; + --footer-link-color: #3cb4e6; + --drawer-back-color: #ffffff; + --drawer-hover-back-color: #ffe97f; + --drawer-border-color: #3cb4e6; + --drawer-close-color: #e6007e; } + +header { + height: 2.75rem; + background: var(--header-back-color); + color: var(--header-fore-color); + border-bottom: 0.0714285714rem solid var(--header-border-color); + padding: calc(var(--universal-padding) / 4) 0; + white-space: nowrap; + overflow-x: auto; + overflow-y: hidden; } + header.row { + box-sizing: content-box; } + header .logo { + color: var(--header-fore-color); + font-size: 1.75rem; + padding: var(--universal-padding) calc(2 * var(--universal-padding)); + text-decoration: none; } + header button, header [type="button"], header .button, header [role="button"] { + box-sizing: border-box; + position: relative; + top: calc(0rem - var(--universal-padding) / 4); + height: calc(3.1875rem + var(--universal-padding) / 2); + background: var(--header-back-color); + line-height: calc(3.1875rem - var(--universal-padding) * 1.5); + text-align: center; + color: var(--header-fore-color); + border: 0; + border-radius: 0; + margin: 0; + text-transform: uppercase; } + header button:hover, header button:focus, header [type="button"]:hover, header [type="button"]:focus, header .button:hover, header .button:focus, header [role="button"]:hover, header [role="button"]:focus { + background: var(--header-hover-back-color); } + +nav { + background: var(--nav-back-color); + color: var(--nav-fore-color); + border: 0.0714285714rem solid var(--nav-border-color); + border-radius: var(--universal-border-radius); + margin: var(--universal-margin); } + nav * { + padding: var(--universal-padding) calc(1.5 * var(--universal-padding)); } + nav a, nav a:visited { + display: block; + color: var(--nav-link-color); + border-radius: var(--universal-border-radius); + transition: background 0.3s; } + nav a:hover, nav a:focus, nav a:visited:hover, nav a:visited:focus { + text-decoration: none; + background: var(--nav-hover-back-color); } + nav .sublink-1 { + position: relative; + margin-left: calc(2 * var(--universal-padding)); } + nav .sublink-1:before { + position: absolute; + left: calc(var(--universal-padding) - 1 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + nav .sublink-2 { + position: relative; + margin-left: calc(4 * var(--universal-padding)); } + nav .sublink-2:before { + position: absolute; + left: calc(var(--universal-padding) - 3 * var(--universal-padding)); + top: -0.0714285714rem; + content: ''; + height: 100%; + border: 0.0714285714rem solid var(--nav-border-color); + border-left: 0; } + +footer { + background: var(--footer-back-color); + color: var(--footer-fore-color); + border-top: 0.0714285714rem solid var(--footer-border-color); + padding: calc(2 * var(--universal-padding)) var(--universal-padding); + font-size: 0.875rem; } + footer a, footer a:visited { + color: var(--footer-link-color); } + +header.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + top: 0; } + +footer.sticky { + position: -webkit-sticky; + position: sticky; + z-index: 1101; + bottom: 0; } + +.drawer-toggle:before { + display: inline-block; + position: relative; + vertical-align: bottom; + content: '\00a0\2261\00a0'; + font-family: sans-serif; + font-size: 1.5em; } +@media screen and (min-width: 500px) { + .drawer-toggle:not(.persistent) { + display: none; } } + +[type="checkbox"].drawer { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].drawer + * { + display: block; + box-sizing: border-box; + position: fixed; + top: 0; + width: 320px; + height: 100vh; + overflow-y: auto; + background: var(--drawer-back-color); + border: 0.0714285714rem solid var(--drawer-border-color); + border-radius: 0; + margin: 0; + z-index: 1110; + right: -320px; + transition: right 0.3s; } + [type="checkbox"].drawer + * .drawer-close { + position: absolute; + top: var(--universal-margin); + right: var(--universal-margin); + z-index: 1111; + width: 2rem; + height: 2rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].drawer + * .drawer-close:before { + display: block; + content: '\00D7'; + color: var(--drawer-close-color); + position: relative; + font-family: sans-serif; + font-size: 2rem; + line-height: 1; + text-align: center; } + [type="checkbox"].drawer + * .drawer-close:hover, [type="checkbox"].drawer + * .drawer-close:focus { + background: var(--drawer-hover-back-color); } + @media screen and (max-width: 320px) { + [type="checkbox"].drawer + * { + width: 100%; } } + [type="checkbox"].drawer:checked + * { + right: 0; } + @media screen and (min-width: 500px) { + [type="checkbox"].drawer:not(.persistent) + * { + position: static; + height: 100%; + z-index: 1100; } + [type="checkbox"].drawer:not(.persistent) + * .drawer-close { + display: none; } } + +/* + Definitions for the responsive table component. +*/ +/* Table module CSS variable definitions. */ +:root { + --table-border-color: #03234b; + --table-border-separator-color: #03234b; + --table-head-back-color: #03234b; + --table-head-fore-color: #ffffff; + --table-body-back-color: #ffffff; + --table-body-fore-color: #03234b; + --table-body-alt-back-color: #f4f4f4; } + +table { + border-collapse: separate; + border-spacing: 0; + margin: 0; + display: flex; + flex: 0 1 auto; + flex-flow: row wrap; + padding: var(--universal-padding); + padding-top: 0; } + table caption { + font-size: 1rem; + margin: calc(2 * var(--universal-margin)) 0; + max-width: 100%; + flex: 0 0 100%; } + table thead, table tbody { + display: flex; + flex-flow: row wrap; + border: 0.0714285714rem solid var(--table-border-color); } + table thead { + z-index: 999; + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; + border-bottom: 0.0714285714rem solid var(--table-border-separator-color); } + table tbody { + border-top: 0; + margin-top: calc(0 - var(--universal-margin)); + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + table tr { + display: flex; + padding: 0; } + table th, table td { + padding: calc(0.5 * var(--universal-padding)); + font-size: 0.9rem; } + table th { + text-align: left; + background: var(--table-head-back-color); + color: var(--table-head-fore-color); } + table td { + background: var(--table-body-back-color); + color: var(--table-body-fore-color); + border-top: 0.0714285714rem solid var(--table-border-color); } + +table:not(.horizontal) { + overflow: auto; + max-height: 100%; } + table:not(.horizontal) thead, table:not(.horizontal) tbody { + max-width: 100%; + flex: 0 0 100%; } + table:not(.horizontal) tr { + flex-flow: row wrap; + flex: 0 0 100%; } + table:not(.horizontal) th, table:not(.horizontal) td { + flex: 1 0 0%; + overflow: hidden; + text-overflow: ellipsis; } + table:not(.horizontal) thead { + position: sticky; + top: 0; } + table:not(.horizontal) tbody tr:first-child td { + border-top: 0; } + +table.horizontal { + border: 0; } + table.horizontal thead, table.horizontal tbody { + border: 0; + flex: .2 0 0; + flex-flow: row nowrap; } + table.horizontal tbody { + overflow: auto; + justify-content: space-between; + flex: .8 0 0; + margin-left: 0; + padding-bottom: calc(var(--universal-padding) / 4); } + table.horizontal tr { + flex-direction: column; + flex: 1 0 auto; } + table.horizontal th, table.horizontal td { + width: auto; + border: 0; + border-bottom: 0.0714285714rem solid var(--table-border-color); } + table.horizontal th:not(:first-child), table.horizontal td:not(:first-child) { + border-top: 0; } + table.horizontal th { + text-align: right; + border-left: 0.0714285714rem solid var(--table-border-color); + border-right: 0.0714285714rem solid var(--table-border-separator-color); } + table.horizontal thead tr:first-child { + padding-left: 0; } + table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td { + border-right: 0.0714285714rem solid var(--table-border-color); } + table.horizontal tbody tr:last-child td:first-child { + border-top-right-radius: 0.25rem; } + table.horizontal tbody tr:last-child td:last-child { + border-bottom-right-radius: 0.25rem; } + table.horizontal thead tr:first-child th:first-child { + border-top-left-radius: 0.25rem; } + table.horizontal thead tr:first-child th:last-child { + border-bottom-left-radius: 0.25rem; } + +@media screen and (max-width: 499px) { + table, table.horizontal { + border-collapse: collapse; + border: 0; + width: 100%; + display: table; } + table thead, table th, table.horizontal thead, table.horizontal th { + border: 0; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + padding: 0; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + table tbody, table.horizontal tbody { + border: 0; + display: table-row-group; } + table tr, table.horizontal tr { + display: block; + border: 0.0714285714rem solid var(--table-border-color); + border-radius: var(--universal-border-radius); + background: #ffffff; + padding: var(--universal-padding); + margin: var(--universal-margin); + margin-bottom: calc(1 * var(--universal-margin)); } + table th, table td, table.horizontal th, table.horizontal td { + width: auto; } + table td, table.horizontal td { + display: block; + border: 0; + text-align: right; } + table td:before, table.horizontal td:before { + content: attr(data-label); + float: left; + font-weight: 600; } + table th:first-child, table td:first-child, table.horizontal th:first-child, table.horizontal td:first-child { + border-top: 0; } + table tbody tr:last-child td, table.horizontal tbody tr:last-child td { + border-right: 0; } } +table tr:nth-of-type(2n) > td { + background: var(--table-body-alt-back-color); } + +@media screen and (max-width: 500px) { + table tr:nth-of-type(2n) { + background: var(--table-body-alt-back-color); } } +:root { + --table-body-hover-back-color: #90caf9; } + +table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } + +@media screen and (max-width: 500px) { + table.hoverable tr:hover, table.hoverable tr:hover > td, table.hoverable tr:focus, table.hoverable tr:focus > td { + background: var(--table-body-hover-back-color); } } +/* + Definitions for contextual background elements, toasts and tooltips. +*/ +/* Contextual module CSS variable definitions */ +:root { + --mark-back-color: #3cb4e6; + --mark-fore-color: #ffffff; } + +mark { + background: var(--mark-back-color); + color: var(--mark-fore-color); + font-size: 0.95em; + line-height: 1em; + border-radius: var(--universal-border-radius); + padding: calc(var(--universal-padding) / 4) var(--universal-padding); } + mark.inline-block { + display: inline-block; + font-size: 1em; + line-height: 1.4; + padding: calc(var(--universal-padding) / 2) var(--universal-padding); } + +:root { + --toast-back-color: #424242; + --toast-fore-color: #fafafa; } + +.toast { + position: fixed; + bottom: calc(var(--universal-margin) * 3); + left: 50%; + transform: translate(-50%, -50%); + z-index: 1111; + color: var(--toast-fore-color); + background: var(--toast-back-color); + border-radius: calc(var(--universal-border-radius) * 16); + padding: var(--universal-padding) calc(var(--universal-padding) * 3); } + +:root { + --tooltip-back-color: #212121; + --tooltip-fore-color: #fafafa; } + +.tooltip { + position: relative; + display: inline-block; } + .tooltip:before, .tooltip:after { + position: absolute; + opacity: 0; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: all 0.3s; + z-index: 1010; + left: 50%; } + .tooltip:not(.bottom):before, .tooltip:not(.bottom):after { + bottom: 75%; } + .tooltip.bottom:before, .tooltip.bottom:after { + top: 75%; } + .tooltip:hover:before, .tooltip:hover:after, .tooltip:focus:before, .tooltip:focus:after { + opacity: 1; + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); } + .tooltip:before { + content: ''; + background: transparent; + border: var(--universal-margin) solid transparent; + left: calc(50% - var(--universal-margin)); } + .tooltip:not(.bottom):before { + border-top-color: #212121; } + .tooltip.bottom:before { + border-bottom-color: #212121; } + .tooltip:after { + content: attr(aria-label); + color: var(--tooltip-fore-color); + background: var(--tooltip-back-color); + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + white-space: nowrap; + transform: translateX(-50%); } + .tooltip:not(.bottom):after { + margin-bottom: calc(2 * var(--universal-margin)); } + .tooltip.bottom:after { + margin-top: calc(2 * var(--universal-margin)); } + +:root { + --modal-overlay-color: rgba(0, 0, 0, 0.45); + --modal-close-color: #e6007e; + --modal-close-hover-color: #ffe97f; } + +[type="checkbox"].modal { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + [type="checkbox"].modal + div { + position: fixed; + top: 0; + left: 0; + display: none; + width: 100vw; + height: 100vh; + background: var(--modal-overlay-color); } + [type="checkbox"].modal + div .card { + margin: 0 auto; + max-height: 50vh; + overflow: auto; } + [type="checkbox"].modal + div .card .modal-close { + position: absolute; + top: 0; + right: 0; + width: 1.75rem; + height: 1.75rem; + border-radius: var(--universal-border-radius); + padding: var(--universal-padding); + margin: 0; + cursor: pointer; + transition: background 0.3s; } + [type="checkbox"].modal + div .card .modal-close:before { + display: block; + content: '\00D7'; + color: var(--modal-close-color); + position: relative; + font-family: sans-serif; + font-size: 1.75rem; + line-height: 1; + text-align: center; } + [type="checkbox"].modal + div .card .modal-close:hover, [type="checkbox"].modal + div .card .modal-close:focus { + background: var(--modal-close-hover-color); } + [type="checkbox"].modal:checked + div { + display: flex; + flex: 0 1 auto; + z-index: 1200; } + [type="checkbox"].modal:checked + div .card .modal-close { + z-index: 1211; } + +:root { + --collapse-label-back-color: #03234b; + --collapse-label-fore-color: #ffffff; + --collapse-label-hover-back-color: #3cb4e6; + --collapse-selected-label-back-color: #3cb4e6; + --collapse-border-color: var(--collapse-label-back-color); + --collapse-selected-border-color: #ceecf8; + --collapse-content-back-color: #ffffff; + --collapse-selected-label-border-color: #3cb4e6; } + +.collapse { + width: calc(100% - 2 * var(--universal-margin)); + opacity: 1; + display: flex; + flex-direction: column; + margin: var(--universal-margin); + border-radius: var(--universal-border-radius); } + .collapse > [type="radio"], .collapse > [type="checkbox"] { + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); } + .collapse > label { + flex-grow: 1; + display: inline-block; + height: 1.25rem; + cursor: pointer; + transition: background 0.2s; + color: var(--collapse-label-fore-color); + background: var(--collapse-label-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + padding: calc(1.25 * var(--universal-padding)); } + .collapse > label:hover, .collapse > label:focus { + background: var(--collapse-label-hover-back-color); } + .collapse > label + div { + flex-basis: auto; + height: 1px; + width: 1px; + margin: -1px; + overflow: hidden; + position: absolute; + clip: rect(0 0 0 0); + -webkit-clip-path: inset(100%); + clip-path: inset(100%); + transition: max-height 0.3s; + max-height: 1px; } + .collapse > :checked + label { + background: var(--collapse-selected-label-back-color); + border-color: var(--collapse-selected-label-border-color); } + .collapse > :checked + label + div { + box-sizing: border-box; + position: relative; + width: 100%; + height: auto; + overflow: auto; + margin: 0; + background: var(--collapse-content-back-color); + border: 0.0714285714rem solid var(--collapse-selected-border-color); + border-top: 0; + padding: var(--universal-padding); + clip: auto; + -webkit-clip-path: inset(0%); + clip-path: inset(0%); + max-height: 100%; } + .collapse > label:not(:first-of-type) { + border-top: 0; } + .collapse > label:first-of-type { + border-radius: var(--universal-border-radius) var(--universal-border-radius) 0 0; } + .collapse > label:last-of-type:not(:first-of-type) { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + .collapse > label:last-of-type:first-of-type { + border-radius: var(--universal-border-radius); } + .collapse > :checked:last-of-type:not(:first-of-type) + label { + border-radius: 0; } + .collapse > :checked:last-of-type + label + div { + border-radius: 0 0 var(--universal-border-radius) var(--universal-border-radius); } + +/* + Custom elements for contextual background elements, toasts and tooltips. +*/ +mark.tertiary { + --mark-back-color: #3cb4e6; } + +mark.tag { + padding: calc(var(--universal-padding)/2) var(--universal-padding); + border-radius: 1em; } + +/* + Definitions for progress elements and spinners. +*/ +/* Progress module CSS variable definitions */ +:root { + --progress-back-color: #3cb4e6; + --progress-fore-color: #555; } + +progress { + display: block; + vertical-align: baseline; + -webkit-appearance: none; + -moz-appearance: none; + appearance: none; + height: 0.75rem; + width: calc(100% - 2 * var(--universal-margin)); + margin: var(--universal-margin); + border: 0; + border-radius: calc(2 * var(--universal-border-radius)); + background: var(--progress-back-color); + color: var(--progress-fore-color); } + progress::-webkit-progress-value { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress::-webkit-progress-bar { + background: var(--progress-back-color); } + progress::-moz-progress-bar { + background: var(--progress-fore-color); + border-top-left-radius: calc(2 * var(--universal-border-radius)); + border-bottom-left-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-webkit-progress-value { + border-radius: calc(2 * var(--universal-border-radius)); } + progress[value="1000"]::-moz-progress-bar { + border-radius: calc(2 * var(--universal-border-radius)); } + progress.inline { + display: inline-block; + vertical-align: middle; + width: 60%; } + +:root { + --spinner-back-color: #ddd; + --spinner-fore-color: #555; } + +@keyframes spinner-donut-anim { + 0% { + transform: rotate(0deg); } + 100% { + transform: rotate(360deg); } } +.spinner { + display: inline-block; + margin: var(--universal-margin); + border: 0.25rem solid var(--spinner-back-color); + border-left: 0.25rem solid var(--spinner-fore-color); + border-radius: 50%; + width: 1.25rem; + height: 1.25rem; + animation: spinner-donut-anim 1.2s linear infinite; } + +/* + Custom elements for progress bars and spinners. +*/ +progress.primary { + --progress-fore-color: #1976d2; } + +progress.secondary { + --progress-fore-color: #d32f2f; } + +progress.tertiary { + --progress-fore-color: #308732; } + +.spinner.primary { + --spinner-fore-color: #1976d2; } + +.spinner.secondary { + --spinner-fore-color: #d32f2f; } + +.spinner.tertiary { + --spinner-fore-color: #308732; } + +/* + Definitions for icons - powered by Feather (https://feathericons.com/). +*/ +span[class^='icon-'] { + display: inline-block; + height: 1em; + width: 1em; + vertical-align: -0.125em; + background-size: contain; + margin: 0 calc(var(--universal-margin) / 4); } + span[class^='icon-'].secondary { + -webkit-filter: invert(25%); + filter: invert(25%); } + span[class^='icon-'].inverse { + -webkit-filter: invert(100%); + filter: invert(100%); } + +span.icon-alert { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='8' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='16' x2='12' y2='16'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-bookmark { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M19 21l-7-5-7 5V5a2 2 0 0 1 2-2h10a2 2 0 0 1 2 2z'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-calendar { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='4' width='18' height='18' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='16' y1='2' x2='16' y2='6'%3E%3C/line%3E%3Cline x1='8' y1='2' x2='8' y2='6'%3E%3C/line%3E%3Cline x1='3' y1='10' x2='21' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-credit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='1' y='4' width='22' height='16' rx='2' ry='2'%3E%3C/rect%3E%3Cline x1='1' y1='10' x2='23' y2='10'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-edit { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M20 14.66V20a2 2 0 0 1-2 2H4a2 2 0 0 1-2-2V6a2 2 0 0 1 2-2h5.34'%3E%3C/path%3E%3Cpolygon points='18 2 22 6 12 16 8 16 8 12 18 2'%3E%3C/polygon%3E%3C/svg%3E"); } +span.icon-link { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M18 13v6a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2V8a2 2 0 0 1 2-2h6'%3E%3C/path%3E%3Cpolyline points='15 3 21 3 21 9'%3E%3C/polyline%3E%3Cline x1='10' y1='14' x2='21' y2='3'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-help { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M9.09 9a3 3 0 0 1 5.83 1c0 2-3 3-3 3'%3E%3C/path%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='17' x2='12' y2='17'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-home { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M3 9l9-7 9 7v11a2 2 0 0 1-2 2H5a2 2 0 0 1-2-2z'%3E%3C/path%3E%3Cpolyline points='9 22 9 12 15 12 15 22'%3E%3C/polyline%3E%3C/svg%3E"); } +span.icon-info { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Ccircle cx='12' cy='12' r='10'%3E%3C/circle%3E%3Cline x1='12' y1='16' x2='12' y2='12'%3E%3C/line%3E%3Cline x1='12' y1='8' x2='12' y2='8'%3E%3C/line%3E%3C/svg%3E"); } +span.icon-lock { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Crect x='3' y='11' width='18' height='11' rx='2' ry='2'%3E%3C/rect%3E%3Cpath d='M7 11V7a5 5 0 0 1 10 0v4'%3E%3C/path%3E%3C/svg%3E"); } +span.icon-mail { + background-image: url("data:image/svg+xml,%3Csvg xmlns='http://www.w3.org/2000/svg' width='24' height='24' viewBox='0 0 24 24' fill='none' stroke='%2303234b' stroke-width='2' stroke-linecap='round' stroke-linejoin='round'%3E%3Cpath d='M4 4h16c1.1 0 2 .9 2 2v12c0 1.1-.9 2-2 2H4c-1.1 0-2-.9-2-2V6c0-1.1.9-2 2-2z'%3E%3C/path%3E%3Cpolyline points='22,6 12,13 2,6'%3E%3C/polyline%3E%3C/svg%3E"); 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+ overflow: hidden !important; } + +.bordered { + border: 0.0714285714rem solid var(--generic-border-color) !important; } + +.rounded { + border-radius: var(--universal-border-radius) !important; } + +.circular { + border-radius: 50% !important; } + +.shadowed { + box-shadow: var(--generic-box-shadow) !important; } + +.responsive-margin { + margin: calc(var(--universal-margin) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-margin { + margin: calc(var(--universal-margin) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-margin { + margin: var(--universal-margin) !important; } } + +.responsive-padding { + padding: calc(var(--universal-padding) / 4) !important; } + @media screen and (min-width: 500px) { + .responsive-padding { + padding: calc(var(--universal-padding) / 2) !important; } } + @media screen and (min-width: 1280px) { + .responsive-padding { + padding: var(--universal-padding) !important; } } + +@media screen and (max-width: 499px) { + .hidden-sm { + display: none !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .hidden-md { + display: none !important; } } +@media screen and (min-width: 1280px) { + .hidden-lg { + display: none !important; } } +@media screen and (max-width: 499px) { + .visually-hidden-sm { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 500px) and (max-width: 1279px) { + .visually-hidden-md { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } +@media screen and (min-width: 1280px) { + .visually-hidden-lg { + position: absolute !important; + width: 1px !important; + height: 1px !important; + margin: -1px !important; + border: 0 !important; + padding: 0 !important; + clip: rect(0 0 0 0) !important; + -webkit-clip-path: inset(100%) !important; + clip-path: inset(100%) !important; + overflow: hidden !important; } } + +/*# sourceMappingURL=mini-custom.css.map */ + +img[alt="ST logo"] { display: block; margin: auto; width: 75%; max-width: 250px; min-width: 71px; } +img[alt="Cube logo"] { float: right; width: 30%; max-width: 10rem; min-width: 8rem; padding-right: 1rem;} + +.figure { + display: block; + margin-left: auto; + margin-right: auto; + text-align: center; +} diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png new file mode 100644 index 000000000..d6cebb5ac Binary files /dev/null and b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/_htmresc/st_logo_2020.png differ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c new file mode 100644 index 000000000..952ff16c9 --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.c @@ -0,0 +1,886 @@ +/** + ****************************************************************************** + * @file tcpp0203.c + * @author MCD Application Team + * @brief This file provides the TCPP02/03 Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203.h" + +#if defined(_TRACE) +#include "usbpd_core.h" +#include "usbpd_trace.h" +#include "string.h" +#include "stdio.h" +#endif /* _TRACE */ + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection. + * @{ + */ + +/** @defgroup TCPP0203_Private_Constants Private Constants + * @{ + */ + +/* Compilation option in order to enable/disable a concistency check performed + after each I2C access into TCPP0203 registers : goal is to check that written value in Reg0 + is properly reflected into reg1 register content. + To enable register consistency check, please uncomment below definition. + To disable it, comment below line */ +/* #define TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** @defgroup TCPP0203_Private_Types Private Types + * @{ + */ +/* TCPP02/03 Type-C port protection driver structure initialization */ +TCPP0203_Drv_t TCPP0203_Driver = +{ + TCPP0203_Init, + TCPP0203_DeInit, + TCPP0203_Reset, + TCPP0203_SetVConnSwitch, + TCPP0203_SetGateDriverProvider, + TCPP0203_SetGateDriverConsumer, + TCPP0203_SetPowerMode, + TCPP0203_SetVBusDischarge, + TCPP0203_SetVConnDischarge, + TCPP0203_GetVConnSwitchAck, + TCPP0203_GetGateDriverProviderAck, + TCPP0203_GetGateDriverConsumerAck, + TCPP0203_GetPowerModeAck, + TCPP0203_GetVBusDischargeAck, + TCPP0203_GetVConnDischargeAck, + TCPP0203_GetOCPVConnFlag, + TCPP0203_GetOCPVBusFlag, + TCPP0203_GetOVPVBusFlag, + TCPP0203_GetOVPCCFlag, + TCPP0203_GetOTPFlag, + TCPP0203_GetVBusOkFlag, + TCPP0203_ReadTCPPType, + TCPP0203_ReadVCONNPower, + TCPP0203_WriteCtrlRegister, + TCPP0203_ReadAckRegister, + TCPP0203_ReadFlagRegister, +}; + +/** + * @} + */ + +/** @defgroup TCPP0203_Private_Variables Private Variables + * @{ + */ +static uint8_t TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_03; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static uint8_t Reg0_Expected_Value = 0x00; +static uint8_t Reg1_LastRead_Value = 0x00; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup TCPP0203_Private_Function_Prototypes TCPP0203 Private Function Prototypes + * @{ + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *Data, uint8_t Length); + +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/** + * @brief Register Bus Io to component + * @param Component object pointer + * @retval Status of execution + */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO) +{ + int32_t ret; + + if (pObj == NULL) + { + ret = TCPP0203_ERROR; + } + else + { + pObj->IO.Init = pIO->Init; + pObj->IO.DeInit = pIO->DeInit; + pObj->IO.Address = pIO->Address; + pObj->IO.WriteReg = pIO->WriteReg; + pObj->IO.ReadReg = pIO->ReadReg; + pObj->IO.GetTick = pIO->GetTick; + + pObj->Ctx.ReadReg = TCPP0203_ReadRegWrap; + pObj->Ctx.WriteReg = TCPP0203_WriteRegWrap; + pObj->Ctx.handle = pObj; + + if (pObj->IO.Init != NULL) + { + ret = pObj->IO.Init(); + } + else + { + ret = TCPP0203_ERROR; + } + } + + return ret; +} + +/** + * @brief Initializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj) +{ + int32_t ret = 0; + uint8_t tmp; + + if (pObj->IsInitialized == 0U) + { + /* Read TCPP Device type */ + ret += tcpp0203_read_reg(&pObj->Ctx, TCPP0203_READ_REG2, &tmp, 1); + + if (ret == TCPP0203_OK) + { + TCPP0203_DeviceType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + } + else + { + TCPP0203_DeviceType = TCPP0203_DEVICE_TYPE_02; + } + pObj->IsInitialized = 1U; + } + + if (ret != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + + return ret; +} + +/** + * @brief Deinitializes the TCPP0203 interface + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj) +{ + if (pObj->IsInitialized == 1U) + { + /* De-Initialize IO BUS layer */ + pObj->IO.DeInit(); + + pObj->IsInitialized = 0U; + } + + return TCPP0203_OK; +} + +/** + * @brief Resets TCPP0203 register (Reg0) + * @param pObj Pointer to component object + * @retval Component status (TCPP0203_OK / TCPP0203_ERROR) + */ +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj) +{ + int32_t ret = TCPP0203_OK; + uint8_t tmp = TCPP0203_REG0_RST_VALUE; + + /* Write reset values in Reg0 register */ + if (tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1) != TCPP0203_OK) + { + ret = TCPP0203_ERROR; + } + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = TCPP0203_REG0_RST_VALUE; + Reg1_LastRead_Value = TCPP0203_REG0_RST_VALUE; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Configure TCPP0203 VConn Switch + * @param pObj Pointer to component object + * @param VConnSwitch VConn Switch requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 + * @retval Component status + */ +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnSwitch != TCPP0203_VCONN_SWITCH_OPEN) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC1) + && (VConnSwitch != TCPP0203_VCONN_SWITCH_CC2)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn switch setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnSwitch, TCPP0203_VCONN_SWITCH_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param GateDriverProvider GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_OPEN GDP Switch Load Open + * @arg TCPP0203_GD_PROVIDER_SWITCH_CLOSED GDP Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider) +{ + int32_t ret = TCPP0203_OK; + + if ((GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_OPEN) + && (GateDriverProvider != TCPP0203_GD_PROVIDER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDP Switch Load setting in Writing register Reg0 */ + if (GateDriverProvider == TCPP0203_GD_PROVIDER_SWITCH_CLOSED) + { + /* If Gate Driver Provider is to be closed, Gate Driver Consumer should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverProvider | TCPP0203_GD_CONSUMER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverProvider, TCPP0203_GD_PROVIDER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Consumer path + * @param pObj Pointer to component object + * @param GateDriverConsumer GDC switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_OPEN GDC Switch Load Open + * @arg TCPP0203_GD_CONSUMER_SWITCH_CLOSED GDC Switch Load closed + * @retval Component status + */ +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer) +{ + int32_t ret = TCPP0203_OK; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + if ((GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_OPEN) + && (GateDriverConsumer != TCPP0203_GD_CONSUMER_SWITCH_CLOSED)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update GDC Switch Load setting in Writing register Reg0 */ + if (GateDriverConsumer == TCPP0203_GD_CONSUMER_SWITCH_CLOSED) + { + /* If Gate Driver Consumer is to be closed, Gate Driver Provider should be open */ + ret += TCPP0203_ModifyReg0(pObj, (GateDriverConsumer | TCPP0203_GD_PROVIDER_SWITCH_OPEN), + (TCPP0203_GD_PROVIDER_SWITCH_MSK | TCPP0203_GD_CONSUMER_SWITCH_MSK)); + } + else + { + ret += TCPP0203_ModifyReg0(pObj, GateDriverConsumer, TCPP0203_GD_CONSUMER_SWITCH_MSK); + } + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Power Mode + * @param pObj Pointer to component object + * @param PowerMode Power mode requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_HIBERNATE Hibernate + * @arg TCPP0203_POWER_MODE_LOWPOWER Low Power + * @arg TCPP0203_POWER_MODE_NORMAL Normal + * @retval Component status + */ +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode) +{ + int32_t ret = TCPP0203_OK; + + if ((PowerMode != TCPP0203_POWER_MODE_HIBERNATE) + && (PowerMode != TCPP0203_POWER_MODE_LOWPOWER) + && (PowerMode != TCPP0203_POWER_MODE_NORMAL)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update Power Mode setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, PowerMode, TCPP0203_POWER_MODE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VBusDischarge VBUS Discharge requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_OFF VBUS Discharge Off + * @arg TCPP0203_VBUS_DISCHARGE_ON VBUS Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VBusDischarge != TCPP0203_VBUS_DISCHARGE_OFF) + && (VBusDischarge != TCPP0203_VBUS_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VBUS Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VBusDischarge, TCPP0203_VBUS_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Configure TCPP0203 Gate Driver for Provider path + * @param pObj Pointer to component object + * @param VConnDischarge GDP switch load requested setting + * This parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_OFF VConn Discharge Off + * @arg TCPP0203_VCONN_DISCHARGE_ON VConn Discharge On + * @retval Component status + */ +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge) +{ + int32_t ret = TCPP0203_OK; + + if ((VConnDischarge != TCPP0203_VCONN_DISCHARGE_OFF) + && (VConnDischarge != TCPP0203_VCONN_DISCHARGE_ON)) + { + ret = TCPP0203_ERROR; + } + else + { + /* Update VConn Discharge setting in Writing register Reg0 */ + ret += TCPP0203_ModifyReg0(pObj, VConnDischarge, TCPP0203_VCONN_DISCHARGE_MSK); + } + + return ret; +} + +/** + * @brief Get VConn switch Ack value + * @param pObj Pointer to component object + * @param pVConnSwitchAck Pointer on VConn switch Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_SWITCH_OPEN VConn switch open Ack + * @arg TCPP0203_VCONN_SWITCH_CC1 VConn closed on CC1 Ack + * @arg TCPP0203_VCONN_SWITCH_CC2 VConn closed on CC2 Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnSwitchAck = (tmp & TCPP0203_VCONN_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Provider Ack value + * @param pObj Pointer to component object + * @param pGateDriverProviderAck Pointer on Gate Driver Provider Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN Gate Driver Provider Open Ack + * @arg TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED Gate Driver Provider Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverProviderAck = (tmp & TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Gate Driver Consumer Ack value + * @param pObj Pointer to component object + * @param pGateDriverConsumerAck Pointer on Gate Driver Consumer Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN Gate Driver Consumer Open Ack + * @arg TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED Gate Driver Consumer Closed Ack + * @retval Component status + */ +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck) +{ + int32_t ret; + uint8_t tmp; + + /* Check if TCPP type is TCPP03. Otherwise, return error */ + if (TCPP0203_DeviceType != TCPP0203_DEVICE_TYPE_03) + { + return (TCPP0203_ERROR); + } + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pGateDriverConsumerAck = (tmp & TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK); + + return ret; +} + +/** + * @brief Get Power Mode Ack value + * @param pObj Pointer to component object + * @param pPowerModeAck Pointer on Power Mode Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_POWER_MODE_ACK_HIBERNATE Power Mode Hibernate Ack + * @arg TCPP0203_POWER_MODE_ACK_LOWPOWER Power Mode Low Power Ack + * @arg TCPP0203_POWER_MODE_ACK_NORMAL Power Mode Normal Ack + * @retval Component status + */ +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pPowerModeAck = (tmp & TCPP0203_POWER_MODE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VBUS Discharge Ack value + * @param pObj Pointer to component object + * @param pVBusDischargeAck Pointer on VBUS Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VBUS_DISCHARGE_ACK_OFF VBUS Discharge Off Ack + * @arg TCPP0203_VBUS_DISCHARGE_ACK_ON VBUS Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVBusDischargeAck = (tmp & TCPP0203_VBUS_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get VConn Discharge Ack value + * @param pObj Pointer to component object + * @param pVConnDischargeAck Pointer on VConn Discharge Ack value + * This output parameter can be one of the following values: + * @arg TCPP0203_VCONN_DISCHARGE_ACK_OFF VConn Discharge Off Ack + * @arg TCPP0203_VCONN_DISCHARGE_ACK_ON VConn Discharge On Ack + * @retval Component status + */ +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + *pVConnDischargeAck = (tmp & TCPP0203_VCONN_DISCHARGE_ACK_MSK); + + return ret; +} + +/** + * @brief Get OCP VConn Flag value + * @param pObj Pointer to component object + * @param pOCPVConnFlag Pointer on OCP VConn Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VCONN_RESET OCP VConn flag not set + * @arg TCPP0203_FLAG_OCP_VCONN_SET OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOCPVConnFlag = (tmp & TCPP0203_FLAG_OCP_VCONN_MSK); + + return ret; +} + +/** + * @brief Get OCP VBUS Flag value + * @param pObj Pointer to component object + * @param pGetOCPVBusFlag Pointer on OCP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OCP_VBUS_RESET OCP VBUS flag not set + * @arg TCPP0203_FLAG_OCP_VBUS_SET OCP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pGetOCPVBusFlag = (tmp & TCPP0203_FLAG_OCP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP VBUS Flag value + * @param pObj Pointer to component object + * @param pOVPVBusFlag Pointer on OVP VBUS Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_VBUS_RESET OVP VBUS flag not set + * @arg TCPP0203_FLAG_OVP_VBUS_SET OVP VBUS flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPVBusFlag = (tmp & TCPP0203_FLAG_OVP_VBUS_MSK); + + return ret; +} + +/** + * @brief Get OVP CC Flag value + * @param pObj Pointer to component object + * @param pOVPCCFlag Pointer on OVP CC Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OVP_CC_RESET OVP CC flag not set + * @arg TCPP0203_FLAG_OVP_CC_SET OVP CC flag set + * @retval Component status + */ +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOVPCCFlag = (tmp & TCPP0203_FLAG_OVP_CC_MSK); + + return ret; +} + +/** + * @brief Get Over Temperature Flag value + * @param pObj Pointer to component object + * @param pOTPFlag Pointer on Over Temperature Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_OTP_RESET Over Temperature flag not set + * @arg TCPP0203_FLAG_OTP_SET Over Temperature flag set + * @retval Component status + */ +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pOTPFlag = (tmp & TCPP0203_FLAG_OTP_MSK); + + return ret; +} + +/** + * @brief Get VBUS OK Flag value + * @param pObj Pointer to component object + * @param pVBusOkFlag Pointer on VBUS OK Flag value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VBUS_OK_RESET VBUS OK flag not set + * @arg TCPP0203_FLAG_VBUS_OK_SET VBUS OK flag set + * @retval Component status + */ +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVBusOkFlag = (tmp & TCPP0203_FLAG_VBUS_OK_MSK); + + return ret; +} + +/** + * @brief Get TCPP0203 Device Type value + * @param pObj Pointer to component object + * @param pTCPPType Pointer on TCPP0203 Device Type value + * This output parameter can be one of the following values: + * @arg TCPP0203_DEVICE_TYPE_02 TCPP02 Type + * @arg TCPP0203_DEVICE_TYPE_03 TCPP03 Type + * @retval Component status + */ +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pTCPPType = (tmp & TCPP0203_DEVICE_TYPE_MSK); + + return ret; +} + +/** + * @brief Get VConn Power value + * @param pObj Pointer to component object + * @param pVCONNPower Pointer on VConn Power value + * This output parameter can be one of the following values: + * @arg TCPP0203_FLAG_VCONN_PWR_1W OCP VConn flag not set + * @arg TCPP0203_FLAG_VCONN_PWR_0_1W OCP VConn flag set + * @retval Component status + */ +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower) +{ + int32_t ret; + uint8_t tmp; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, &tmp, 1); + *pVCONNPower = (tmp & TCPP0203_FLAG_VCONN_PWR_MSK); + + return ret; +} + +/** + * @brief Set complete Ctrl register value (Reg 0) + * @param pObj Pointer to component object + * @param pCtrlRegister Pointer on Ctrl register value + * @retval Component status + */ +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister) +{ + int32_t ret; + + /* Update value in writing register (reg0) */ + ret = tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, pCtrlRegister, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pCtrlRegister; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +/** + * @brief Get complete Ack register value + * @param pObj Pointer to component object + * @param pAckRegister Pointer on Ack register value + * @retval Component status + */ +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, pAckRegister, 1); + + return ret; +} + +/** + * @brief Get complete Flag register value + * @param pObj Pointer to component object + * @param pFlagRegister Pointer on Flag register value + * @retval Component status + */ +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister) +{ + int32_t ret; + + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_FLAG_REG, pFlagRegister, 1); + + return ret; +} + +/******************** Static functions ****************************************/ +/** + * @brief Wrap TCPP0203 read function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to read + * @param pData Buffer where Target register value should be stored + * @param Length buffer size to be read + * @retval error status + */ +static int32_t TCPP0203_ReadRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + + return pObj->IO.ReadReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief Wrap TCPP0203 write function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_WriteRegWrap(const void *handle, uint8_t Reg, uint8_t *pData, uint8_t Length) +{ + const TCPP0203_Object_t *pObj = (const TCPP0203_Object_t *)handle; + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = *pData; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return pObj->IO.WriteReg(pObj->IO.Address, Reg, pData, Length); +} + +/** + * @brief TCPP0203 register update function to Bus IO function + * @param handle Component object handle + * @param Reg Target register address to write + * @param pData Target register value to be written + * @param Length Buffer size to be written + * @retval error status + */ +static int32_t TCPP0203_ModifyReg0(TCPP0203_Object_t *pObj, uint8_t Value, uint8_t Mask) +{ + int32_t ret; + uint8_t tmp; + + /* Read current content of ACK register (reflects content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &tmp, 1); + + /* Update only the area dedicated to Mask */ + tmp &= ~(Mask); + tmp |= (Value & Mask); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + Reg0_Expected_Value = tmp; +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + /* Update value in writing register (reg0) */ + ret += tcpp0203_write_reg(&pObj->Ctx, TCPP0203_PROG_CTRL, &tmp, 1); + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) + ret += TCPP0203_CheckReg0Reg1(pObj, Reg0_Expected_Value); +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + + return ret; +} + +#if defined(TCPP0203_REGISTER_CONSISTENCY_CHECK) +/** + * @brief TCPP0203 register control function between Reg0 and Reg1 value + * @param handle Component object handle + * @param Reg0ExpectedValue Value expected in Reg0 (built after all calls to write functions) + * @retval error status + */ +static int32_t TCPP0203_CheckReg0Reg1(TCPP0203_Object_t *pObj, uint8_t Reg0ExpectedValue) +{ + int32_t ret; + + /* Read current content of ACK register (expected to reflect content of bits set to 1 in Writing register Reg0) */ + ret = tcpp0203_read_reg(&pObj->Ctx, TCPP0203_ACK_REG, &Reg1_LastRead_Value, 1); + +#ifdef _TRACE + char str[12]; + sprintf(str, "Exp0_0x%02x", Reg0ExpectedValue); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); + sprintf(str, "Reg1_0x%02x", Reg1_LastRead_Value); + USBPD_TRACE_Add(USBPD_TRACE_DEBUG, 0U, 0U, (uint8_t *)str, sizeof(str) - 1U); +#endif /* _TRACE */ + + /* Control if Reg1 value is same as Reg0 expected one */ + if (Reg1_LastRead_Value != Reg0ExpectedValue) + { + while (1); + } + + return ret; +} +#endif /* TCPP0203_REGISTER_CONSISTENCY_CHECK */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h new file mode 100644 index 000000000..271b534fc --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203.h @@ -0,0 +1,353 @@ +/** + ****************************************************************************** + * @file tcpp0203.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the + * tcpp0203.c driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_H +#define TCPP0203_H + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" +#include + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup TCPP0203_Exported_Types TCPP0203 Exported Types + * @{ + */ +typedef int32_t (*TCPP0203_Init_Func)(void); +typedef int32_t (*TCPP0203_DeInit_Func)(void); +typedef int32_t (*TCPP0203_GetTick_Func)(void); +typedef int32_t (*TCPP0203_WriteReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); +typedef int32_t (*TCPP0203_ReadReg_Func)(uint16_t, uint16_t, uint8_t *, uint16_t); + +typedef struct +{ + TCPP0203_Init_Func Init; + TCPP0203_DeInit_Func DeInit; + uint16_t Address; + TCPP0203_WriteReg_Func WriteReg; + TCPP0203_ReadReg_Func ReadReg; + TCPP0203_GetTick_Func GetTick; +} TCPP0203_IO_t; + + +typedef struct +{ + TCPP0203_IO_t IO; + TCPP0203_ctx_t Ctx; + uint8_t IsInitialized; +} TCPP0203_Object_t; + +typedef struct +{ + int32_t (*Init)(TCPP0203_Object_t *); + int32_t (*DeInit)(TCPP0203_Object_t *); + int32_t (*Reset)(TCPP0203_Object_t *); + int32_t (*SetVConnSwitch)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverProvider)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetGateDriverConsumer)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetPowerMode)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVBusDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*SetVConnDischarge)(TCPP0203_Object_t *, uint8_t); + int32_t (*GetVConnSwitchAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverProviderAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetGateDriverConsumerAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetPowerModeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVConnDischargeAck)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVConnFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOCPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPVBusFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOVPCCFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetOTPFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*GetVBusOkFlag)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadTCPPType)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadVCONNPower)(TCPP0203_Object_t *, uint8_t *); + int32_t (*WriteCtrlRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadAckRegister)(TCPP0203_Object_t *, uint8_t *); + int32_t (*ReadFlagRegister)(TCPP0203_Object_t *, uint8_t *); +} TCPP0203_Drv_t; + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/** + * @brief TCPP0203 Driver Response codes + */ +#define TCPP0203_OK (0) +#define TCPP0203_ERROR (-1) + +/** + * @brief TCPP0203 possible I2C Addresses + */ +#define TCPP0203_I2C_ADDRESS_X68 (0x68U) +#define TCPP0203_I2C_ADDRESS_X6A (0x6AU) + +/** + * @brief TCPP0203 Reg0 Reset Value + */ +#define TCPP0203_REG0_RST_VALUE TCPP0203_GD_CONSUMER_SWITCH_CLOSED + +/** + * @brief TCPP0203 VCONN Switch + */ +#define TCPP0203_VCONN_SWITCH_POS (0U) +#define TCPP0203_VCONN_SWITCH_MSK (0x03U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_CC1 (0x01U << TCPP0203_VCONN_SWITCH_POS) +#define TCPP0203_VCONN_SWITCH_CC2 (0x02U << TCPP0203_VCONN_SWITCH_POS) + +/** + * @brief TCPP0203 Gate Driver Provider values + */ +#define TCPP0203_GD_PROVIDER_SWITCH_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer values + */ +#define TCPP0203_GD_CONSUMER_SWITCH_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_OPEN (TCPP0203_GD_CONSUMER_SWITCH_MSK) + +/** + * @brief TCPP0203 Power Mode values + */ +#define TCPP0203_POWER_MODE_POS (4U) +#define TCPP0203_POWER_MODE_MSK (0x03U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_LOWPOWER (0x02U << TCPP0203_POWER_MODE_POS) +#define TCPP0203_POWER_MODE_NORMAL (0x01U << TCPP0203_POWER_MODE_POS) + +/** + * @brief TCPP0203 VBUS Discharge management + */ +#define TCPP0203_VBUS_DISCHARGE_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_POS) +#define TCPP0203_VBUS_DISCHARGE_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ON (TCPP0203_VBUS_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VConn Discharge management + */ +#define TCPP0203_VCONN_DISCHARGE_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_POS) +#define TCPP0203_VCONN_DISCHARGE_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ON (TCPP0203_VCONN_DISCHARGE_MSK) + +/** + * @brief TCPP0203 VCONN Switch Acknowledge + */ +#define TCPP0203_VCONN_SWITCH_ACK_POS (0U) +#define TCPP0203_VCONN_SWITCH_ACK_MSK (0x03U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_VCONN_SWITCH_ACK_CC1 (0x02U << TCPP0203_VCONN_SWITCH_ACK_POS) +#define TCPP0203_VCONN_SWITCH_ACK_CC2 (0x01U << TCPP0203_VCONN_SWITCH_ACK_POS) + +/** + * @brief TCPP0203 Gate Driver Provider Acknowledge + */ +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_POS (2U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_PROVIDER_SWITCH_ACK_POS) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_OPEN (0x00U) +#define TCPP0203_GD_PROVIDER_SWITCH_ACK_CLOSED (TCPP0203_GD_PROVIDER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Gate Driver Consumer Acknowledge + */ +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_POS (3U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK (0x01U << TCPP0203_GD_CONSUMER_SWITCH_ACK_POS) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_CLOSED (0x00U) +#define TCPP0203_GD_CONSUMER_SWITCH_ACK_OPEN (TCPP0203_GD_CONSUMER_SWITCH_ACK_MSK) + +/** + * @brief TCPP0203 Power Mode Acknowledge + */ +#define TCPP0203_POWER_MODE_ACK_POS (4U) +#define TCPP0203_POWER_MODE_ACK_MSK (0x03U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_HIBERNATE (0x00U) +#define TCPP0203_POWER_MODE_ACK_LOWPOWER (0x01U << TCPP0203_POWER_MODE_ACK_POS) +#define TCPP0203_POWER_MODE_ACK_NORMAL (0x02U << TCPP0203_POWER_MODE_ACK_POS) + +/** + * @brief TCPP0203 VBUS Discharge Acknowledge + */ +#define TCPP0203_VBUS_DISCHARGE_ACK_POS (6U) +#define TCPP0203_VBUS_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VBUS_DISCHARGE_ACK_POS) +#define TCPP0203_VBUS_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VBUS_DISCHARGE_ACK_ON (TCPP0203_VBUS_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 VConn Discharge Acknowledge + */ +#define TCPP0203_VCONN_DISCHARGE_ACK_POS (7U) +#define TCPP0203_VCONN_DISCHARGE_ACK_MSK (0x01U << TCPP0203_VCONN_DISCHARGE_ACK_POS) +#define TCPP0203_VCONN_DISCHARGE_ACK_OFF (0x00U) +#define TCPP0203_VCONN_DISCHARGE_ACK_ON (TCPP0203_VCONN_DISCHARGE_ACK_MSK) + +/** + * @brief TCPP0203 OCP Vconn Flag management + */ +#define TCPP0203_FLAG_OCP_VCONN_POS (0U) +#define TCPP0203_FLAG_OCP_VCONN_MSK (0x01U << TCPP0203_FLAG_OCP_VCONN_POS) +#define TCPP0203_FLAG_OCP_VCONN_SET (TCPP0203_FLAG_OCP_VCONN_MSK) +#define TCPP0203_FLAG_OCP_VCONN_RESET (0x00U) + +/** + * @brief TCPP0203 OCP VBUS Flag management + */ +#define TCPP0203_FLAG_OCP_VBUS_POS (1U) +#define TCPP0203_FLAG_OCP_VBUS_MSK (0x01U << TCPP0203_FLAG_OCP_VBUS_POS) +#define TCPP0203_FLAG_OCP_VBUS_SET (TCPP0203_FLAG_OCP_VBUS_MSK) +#define TCPP0203_FLAG_OCP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP VBUS Flag management + */ +#define TCPP0203_FLAG_OVP_VBUS_POS (2U) +#define TCPP0203_FLAG_OVP_VBUS_MSK (0x01U << TCPP0203_FLAG_OVP_VBUS_POS) +#define TCPP0203_FLAG_OVP_VBUS_SET (TCPP0203_FLAG_OVP_VBUS_MSK) +#define TCPP0203_FLAG_OVP_VBUS_RESET (0x00U) + +/** + * @brief TCPP0203 OVP CC Flag management + */ +#define TCPP0203_FLAG_OVP_CC_POS (3U) +#define TCPP0203_FLAG_OVP_CC_MSK (0x01U << TCPP0203_FLAG_OVP_CC_POS) +#define TCPP0203_FLAG_OVP_CC_SET (TCPP0203_FLAG_OVP_CC_MSK) +#define TCPP0203_FLAG_OVP_CC_RESET (0x00U) + +/** + * @brief TCPP0203 OTP Flag management + */ +#define TCPP0203_FLAG_OTP_POS (4U) +#define TCPP0203_FLAG_OTP_MSK (0x01U << TCPP0203_FLAG_OTP_POS) +#define TCPP0203_FLAG_OTP_SET (TCPP0203_FLAG_OTP_MSK) +#define TCPP0203_FLAG_OTP_RESET (0x00U) + +/** + * @brief TCPP0203 VBUS OK Flag management + */ +#define TCPP0203_FLAG_VBUS_OK_POS (5U) +#define TCPP0203_FLAG_VBUS_OK_MSK (0x01U << TCPP0203_FLAG_VBUS_OK_POS) +#define TCPP0203_FLAG_VBUS_OK_SET (TCPP0203_FLAG_VBUS_OK_MSK) +#define TCPP0203_FLAG_VBUS_OK_RESET (0x00U) + +/** + * @brief TCPP0203 VConn Power + */ +#define TCPP0203_FLAG_VCONN_PWR_POS (6U) +#define TCPP0203_FLAG_VCONN_PWR_MSK (0x01U << TCPP0203_FLAG_VCONN_PWR_POS) +#define TCPP0203_FLAG_VCONN_PWR_1W (TCPP0203_FLAG_VCONN_PWR_MSK) +#define TCPP0203_FLAG_VCONN_PWR_0_1W (0x00U) + +/** + * @brief TCPP0203 Device Type + */ +#define TCPP0203_DEVICE_TYPE_POS (7U) +#define TCPP0203_DEVICE_TYPE_MSK (0x01U << TCPP0203_DEVICE_TYPE_POS) +#define TCPP0203_DEVICE_TYPE_02 (TCPP0203_DEVICE_TYPE_MSK) +#define TCPP0203_DEVICE_TYPE_03 (0x00U) + +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Macros TCPP0203 Exported Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup TCPP0203_Exported_Functions TCPP0203 Exported Functions + * @{ + */ + +/*------------------------------------------------------------------------------ + TCPP02/03 Type-C port protection functions +------------------------------------------------------------------------------*/ +/* High Layer codec functions */ +int32_t TCPP0203_RegisterBusIO(TCPP0203_Object_t *pObj, TCPP0203_IO_t *pIO); +int32_t TCPP0203_Init(TCPP0203_Object_t *pObj); +int32_t TCPP0203_DeInit(TCPP0203_Object_t *pObj); +int32_t TCPP0203_Reset(TCPP0203_Object_t *pObj); +int32_t TCPP0203_SetVConnSwitch(TCPP0203_Object_t *pObj, uint8_t VConnSwitch); +int32_t TCPP0203_SetGateDriverProvider(TCPP0203_Object_t *pObj, uint8_t GateDriverProvider); +int32_t TCPP0203_SetGateDriverConsumer(TCPP0203_Object_t *pObj, uint8_t GateDriverConsumer); +int32_t TCPP0203_SetPowerMode(TCPP0203_Object_t *pObj, uint8_t PowerMode); +int32_t TCPP0203_SetVBusDischarge(TCPP0203_Object_t *pObj, uint8_t VBusDischarge); +int32_t TCPP0203_SetVConnDischarge(TCPP0203_Object_t *pObj, uint8_t VConnDischarge); +int32_t TCPP0203_GetVConnSwitchAck(TCPP0203_Object_t *pObj, uint8_t *pVConnSwitchAck); +int32_t TCPP0203_GetGateDriverProviderAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverProviderAck); +int32_t TCPP0203_GetGateDriverConsumerAck(TCPP0203_Object_t *pObj, uint8_t *pGateDriverConsumerAck); +int32_t TCPP0203_GetPowerModeAck(TCPP0203_Object_t *pObj, uint8_t *pPowerModeAck); +int32_t TCPP0203_GetVBusDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVBusDischargeAck); +int32_t TCPP0203_GetVConnDischargeAck(TCPP0203_Object_t *pObj, uint8_t *pVConnDischargeAck); +int32_t TCPP0203_GetOCPVConnFlag(TCPP0203_Object_t *pObj, uint8_t *pOCPVConnFlag); +int32_t TCPP0203_GetOCPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pGetOCPVBusFlag); +int32_t TCPP0203_GetOVPVBusFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPVBusFlag); +int32_t TCPP0203_GetOVPCCFlag(TCPP0203_Object_t *pObj, uint8_t *pOVPCCFlag); +int32_t TCPP0203_GetOTPFlag(TCPP0203_Object_t *pObj, uint8_t *pOTPFlag); +int32_t TCPP0203_GetVBusOkFlag(TCPP0203_Object_t *pObj, uint8_t *pVBusOkFlag); +int32_t TCPP0203_ReadTCPPType(TCPP0203_Object_t *pObj, uint8_t *pTCPPType); +int32_t TCPP0203_ReadVCONNPower(TCPP0203_Object_t *pObj, uint8_t *pVCONNPower); +int32_t TCPP0203_WriteCtrlRegister(TCPP0203_Object_t *pObj, uint8_t *pCtrlRegister); +int32_t TCPP0203_ReadAckRegister(TCPP0203_Object_t *pObj, uint8_t *pAckRegister); +int32_t TCPP0203_ReadFlagRegister(TCPP0203_Object_t *pObj, uint8_t *pFlagRegister); + +/** + * @} + */ + +/* TCPP02/03 Type-C port protection driver structure */ +extern TCPP0203_Drv_t TCPP0203_Driver; + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TCPP0203_H */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c new file mode 100644 index 000000000..8025fa85e --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.c @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.c + * @author MCD Application Team + * @brief This file provides unitary register function to control the TCPP02-03 + * Type-C port protection driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "tcpp0203_reg.h" + +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Components + * @{ + */ + +/** @addtogroup TCPP0203 + * @brief This file provides a set of functions needed to drive the + * TCPP02/03 Type-C port protection codec. + * @{ + */ + +/************** Generic Function *******************/ +/******************************************************************************* + * Function Name : tcpp0203_read_reg + * Description : Generic Reading function. It must be fulfilled with either + * I2C or SPI reading functions + * Input : Register Address, length of buffer + * Output : data Read + *******************************************************************************/ +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->ReadReg(ctx->handle, reg, data, length); +} + +/******************************************************************************* + * Function Name : tcpp0203_write_reg + * Description : Generic Writing function. It must be fulfilled with either + * I2C or SPI writing function + * Input : Register Address, data to be written, length of buffer + * Output : None + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length) +{ + return ctx->WriteReg(ctx->handle, reg, data, length); +} + +/******************************************************************************/ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h new file mode 100644 index 000000000..92420e1fe --- /dev/null +++ b/hw/bsp/stm32n6/boards/stm32n657nucleo/tcpp0203/tcpp0203_reg.h @@ -0,0 +1,98 @@ +/** + ****************************************************************************** + * @file tcpp0203_reg.h + * @author MCD Application Team + * @brief Header of tcpp0203_reg.c + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef TCPP0203_REG_H +#define TCPP0203_REG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/** @addtogroup BSP + * @{ + */ + +/** @addtogroup Component + * @{ + */ + +/** @addtogroup TCPP0203 + * @{ + */ + + +/** @defgroup TCPP0203_Exported_Constants TCPP0203 Exported Constants + * @{ + */ +/******************************************************************************/ +/****************************** REGISTER MAPPING ******************************/ +/******************************************************************************/ +#define TCPP0203_WRITE_REG 0x00U +#define TCPP0203_PROG_CTRL TCPP0203_WRITE_REG +#define TCPP0203_READ_REG1 0x01U +#define TCPP0203_ACK_REG TCPP0203_READ_REG1 +#define TCPP0203_READ_REG2 0x02U +#define TCPP0203_FLAG_REG TCPP0203_READ_REG2 + +/** + * @} + */ + +/************** Generic Function *******************/ + +typedef int32_t (*TCPP0203_Write_Func)(const void *, uint8_t, uint8_t *, uint8_t); +typedef int32_t (*TCPP0203_Read_Func)(const void *, uint8_t, uint8_t *, uint8_t); + +typedef struct +{ + TCPP0203_Write_Func WriteReg; + TCPP0203_Read_Func ReadReg; + void *handle; +} TCPP0203_ctx_t; + +/******************************************************************************* + * Register : Generic - All + * Address : Generic - All + * Bit Group Name: None + * Permission : W + *******************************************************************************/ +int32_t tcpp0203_write_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); +int32_t tcpp0203_read_reg(const TCPP0203_ctx_t *ctx, uint8_t reg, uint8_t *data, uint8_t length); + +#ifdef __cplusplus +} +#endif + +#endif /* TCPP0203_REG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/hw/bsp/stm32n6/family.c b/hw/bsp/stm32n6/family.c new file mode 100644 index 000000000..0ec1875ac --- /dev/null +++ b/hw/bsp/stm32n6/family.c @@ -0,0 +1,276 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 + * William D. Jones (thor0505@comcast.net), + * Ha Thach (tinyusb.org) + * Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + manufacturer: STMicroelectronics +*/ + +// Suppress warning caused by mcu driver +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wcast-align" +#endif + +#include "stm32n6xx_hal.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "bsp/board_api.h" + +TU_ATTR_UNUSED static void Error_Handler(void) { } + +void HardFault_Handler(void); + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + +#include "board.h" + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + +#ifndef SWO_FREQ +#define SWO_FREQ 4000000 +#endif + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ + +// Despite being call USB2_OTG_FS on some MCUs +// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port +void USB2_OTG_HS_IRQHandler(void) { + tusb_int_handler(0, true); +} + +// Despite being call USB1_OTG_HS on some MCUs +// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port +void USB1_OTG_HS_IRQHandler(void) { + tusb_int_handler(1, true); +} + +void board_init(void) { + + /* Enable BusFault and SecureFault handlers (HardFault is default) */ + SCB->SHCSR |= (SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk); + + HAL_PWREx_EnableVddA(); + HAL_PWREx_EnableVddIO2(); + HAL_PWREx_EnableVddIO3(); + HAL_PWREx_EnableVddIO4(); + HAL_PWREx_EnableVddIO5(); + + HAL_Init(); + + // Implemented in board.h + SystemClock_Config(); + + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPION_CLK_ENABLE(); + __HAL_RCC_GPIOO_CLK_ENABLE(); + __HAL_RCC_GPIOP_CLK_ENABLE(); + __HAL_RCC_GPIOQ_CLK_ENABLE(); + + // HAL_ICACHE_Enable(); + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + + NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0)); + NVIC_EnableIRQ(UCPD1_IRQn); + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); + +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); +#endif + + + +#ifdef UART_DEV + UART_CLK_EN(); + HAL_UART_Init(&UartHandle); +#endif + + + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); + HAL_PWREx_EnableVddUSBVMEN(); + while(__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY)); + HAL_PWREx_EnableVddUSB(); + + LL_AHB5_GRP1_ForceReset(0x00800000); + __HAL_RCC_USB1_OTG_HS_FORCE_RESET(); + __HAL_RCC_USB1_OTG_HS_PHY_FORCE_RESET(); + + LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock(); + LL_AHB5_GRP1_ReleaseReset(0x00800000); + + /* Peripheral clock enable */ + __HAL_RCC_USB1_OTG_HS_CLK_ENABLE(); + + /* Required few clock cycles before accessing USB PHY Controller Registers */ + HAL_Delay(1); + + USB1_HS_PHYC->USBPHYC_CR &= ~(0x7 << 0x4); + + USB1_HS_PHYC->USBPHYC_CR |= (0x1 << 16) | + (0x2 << 4) | + (0x1 << 2) | + 0x1U; + + __HAL_RCC_USB1_OTG_HS_PHY_RELEASE_RESET(); + + /* Required few clock cycles before Releasing Reset */ + HAL_Delay(1); + + __HAL_RCC_USB1_OTG_HS_RELEASE_RESET(); + + /* Peripheral PHY clock enable */ + __HAL_RCC_USB1_OTG_HS_PHY_CLK_ENABLE(); + + board_init2(); + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif +} + +uint32_t board_button_read(void) { +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) + buf, len, 0xffff); + return len; +#else + (void) buf; (void) len; + return -1; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} + +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/stm32n6/family.cmake b/hw/bsp/stm32n6/family.cmake new file mode 100644 index 000000000..600af7cdb --- /dev/null +++ b/hw/bsp/stm32n6/family.cmake @@ -0,0 +1,147 @@ +include_guard() + +set(ST_FAMILY n6) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m55 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32N6 CACHE INTERNAL "") + +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif() + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + if(NOT DEFINED LD_FILE_GNU) + set(LD_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/linker/${MCU_VARIANT}_flash.ld) + endif() + set(LD_FILE_Clang ${LD_FILE_GNU}) + if(NOT DEFINED LD_FILE_IAR) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + endif() + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}_ns.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32N6 ${RTOS}) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_stlink(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32n6/family.mk b/hw/bsp/stm32n6/family.mk new file mode 100644 index 000000000..97930e189 --- /dev/null +++ b/hw/bsp/stm32n6/family.mk @@ -0,0 +1,101 @@ +ST_FAMILY = n6 +ST_PREFIX = stm32${ST_FAMILY}xx +ST_PREFIX_LONG = stm32${ST_FAMILY}57xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver + +UF2_FAMILY_ID = 0x6db66083 + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m55 + +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32N6 \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += \ + -Wno-error=cast-align \ + -Wno-error=unused-parameter \ + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}_fsbl.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_hcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_i2c.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rif.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \ + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Linker +LD_FILE_GCC = $(BOARD_PATH)/STM32N657XX_AXISRAM2_fsbl.ld + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(ST_PREFIX_LONG)_fsbl.s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= $(ST_CMSIS)/Source/Templates/gcc/linker/$(ST_PREFIX_LONG)_flash.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32n6/partition_stm32n657xx.h b/hw/bsp/stm32n6/partition_stm32n657xx.h new file mode 100644 index 000000000..713068609 --- /dev/null +++ b/hw/bsp/stm32n6/partition_stm32n657xx.h @@ -0,0 +1,792 @@ +/** + ****************************************************************************** + * @file partition_stm32n657xx.h + * @author MCD Application Team + * @brief CMSIS STM32N657xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM55 based on CMSIS CORE V5.3.1 partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * Portions Copyright (c) 2023 STMicroelectronics, all rights reserved + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PARTITION_STM32N657XX_H +#define PARTITION_STM32N657XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 0 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x00000000 /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// PVD_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// LOCKUP_IRQn <0=> Secure state <1=> Non-Secure state +// CACHE_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// TCM_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// BKP_ECC_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RIFSC_TAMPER_IRQn <0=> Secure state <1=> Non-Secure state +// IAC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// CRYP_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// MCE1_IRQn <0=> Secure state <1=> Non-Secure state +// MCE2_IRQn <0=> Secure state <1=> Non-Secure state +// MCE3_IRQn <0=> Secure state <1=> Non-Secure state +// MCE4_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_2_IRQn <0=> Secure state <1=> Non-Secure state +// CSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCMIPP_IRQn <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// Reserved <0=> Secure state <1=> Non-Secure state +// PAHB_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// NPU0_IRQn <0=> Secure state <1=> Non-Secure state +// NPU1_IRQn <0=> Secure state <1=> Non-Secure state +// NPU2_IRQn <0=> Secure state <1=> Non-Secure state +// NPU3_IRQn <0=> Secure state <1=> Non-Secure state +// CACHEAXI_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_LO_ERR_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +// VENC_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// HPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM9_IRQn <0=> Secure state <1=> Non-Secure state +// TIM10_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..159 +// TIM11_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// TIM18_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_B_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_A_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_B_IRQn <0=> Secure state <1=> Non-Secure state +// SPDIFRX1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 1 + +/* +// Interrupts 160..191 +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// XSPI3_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// USB1_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// USB2_OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// ETH1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN3_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN_CU_IRQn <0=> Secure state <1=> Non-Secure state +// MDIOS_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// WAKEUP_PIN_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT0_IRQn <0=> Secure state <1=> Non-Secure state +// CTI_INT1_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 1 + +/* +// Interrupts 192..223 +// Reserved <0=> Secure state <1=> Non-Secure state +// LTDC_UP_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_UP_ERR_IRQn <0=> Secure state <1=> Non-Secure state + +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + +} + +#endif /* PARTITION_STM32N657XX_H */ diff --git a/hw/bsp/stm32n6/stm32n6xx_hal_conf.h b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h new file mode 100644 index 000000000..d98d365a3 --- /dev/null +++ b/hw/bsp/stm32n6/stm32n6xx_hal_conf.h @@ -0,0 +1,504 @@ +/** + ****************************************************************************** + * @file stm32n6xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32n6xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32N6xx_HAL_CONF_H +#define STM32N6xx_HAL_CONF_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/*#define HAL_ADC_MODULE_ENABLED */ +/*#define HAL_BSEC_MODULE_ENABLED */ +/*#define HAL_CRC_MODULE_ENABLED */ +/*#define HAL_CRYP_MODULE_ENABLED */ +/*#define HAL_DCMI_MODULE_ENABLED */ +/*#define HAL_DCMIPP_MODULE_ENABLED */ +/*#define HAL_DMA2D_MODULE_ENABLED */ +/*#define HAL_DTS_MODULE_ENABLED */ +/*#define HAL_ETH_MODULE_ENABLED */ +/*#define HAL_EXTI_MODULE_ENABLED */ +/*#define HAL_FDCAN_MODULE_ENABLED */ +/*#define HAL_GFXMMU_MODULE_ENABLED */ +/*#define HAL_GFXTIM_MODULE_ENABLED */ +/*#define HAL_HASH_MODULE_ENABLED */ +#define HAL_HCD_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +/*#define HAL_I2S_MODULE_ENABLED */ +/*#define HAL_I3C_MODULE_ENABLED */ +/*#define HAL_ICACHE_MODULE_ENABLED */ +/*#define HAL_IRDA_MODULE_ENABLED */ +/*#define HAL_IWDG_MODULE_ENABLED */ +/*#define HAL_JPEG_MODULE_ENABLED */ +/*#define HAL_LPTIM_MODULE_ENABLED */ +/*#define HAL_LTDC_MODULE_ENABLED */ +/*#define HAL_MCE_MODULE_ENABLED */ +/*#define HAL_MDF_MODULE_ENABLED */ +/*#define HAL_MMC_MODULE_ENABLED */ +/*#define HAL_NAND_MODULE_ENABLED */ +/*#define HAL_NOR_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED +/*#define HAL_PKA_MODULE_ENABLED */ +/*#define HAL_PSSI_MODULE_ENABLED */ +/*#define HAL_RAMCFG_MODULE_ENABLED */ +#define HAL_RIF_MODULE_ENABLED +/*#define HAL_RNG_MODULE_ENABLED */ +/*#define HAL_RTC_MODULE_ENABLED */ +/*#define HAL_SAI_MODULE_ENABLED */ +/*#define HAL_SD_MODULE_ENABLED */ +/*#define HAL_SDIO_MODULE_ENABLED */ +/*#define HAL_SDRAM_MODULE_ENABLED */ +/*#define HAL_SMARTCARD_MODULE_ENABLED*/ +/*#define HAL_SMBUS_MODULE_ENABLED */ +/*#define HAL_SPDIFRX_MODULE_ENABLED */ +/*#define HAL_SPI_MODULE_ENABLED */ +/*#define HAL_SRAM_MODULE_ENABLED */ +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +/*#define HAL_WWDG_MODULE_ENABLED */ +/*#define HAL_XSPI_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +/*#define HAL_MDIOS_MODULE_ENABLED */ +/*#define HAL_GPU2D_MODULE_ENABLED */ +/*#define HAL_CACHEAXI_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 48000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Multiple Speed oscillator (MSI) default value. + * This value is the default MSI range value after Reset. + */ +#if !defined (MSI_VALUE) +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* MSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz */ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz */ +/* The real value may vary depending on the variations in voltage and temperature.*/ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 15U /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32n6xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CACHEAXI_REGISTER_CALLBACKS 0U /* CACHEAXI register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMIPP_REGISTER_CALLBACKS 0U /* DCMIPP register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MCE_REGISTER_CALLBACKS 0U /* MCE register callback disabled */ +#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U /* PSSI register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDIO_REGISTER_CALLBACKS 0U /* SDIO register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 0U + +/* ################## SDMMC peripheral configuration ######################### */ + +#define USE_SD_TRANSCEIVER 0U + +/* ################## SDIO peripheral configuration ########################## */ +#define USE_SDIO_TRANSCEIVER 1U +#define SDIO_MAX_IO_NUMBER 7U /*!< SDIO device support maximum IO number */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32n6xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_RIF_MODULE_ENABLED +#include "stm32n6xx_hal_rif.h" +#endif /* HAL_RIF_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32n6xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CACHEAXI_MODULE_ENABLED +#include "stm32n6xx_hal_cacheaxi.h" +#endif /* HAL_CACHEAXI_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32n6xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32n6xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_BSEC_MODULE_ENABLED +#include "stm32n6xx_hal_bsec.h" +#endif /* HAL_BSEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32n6xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32n6xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32n6xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_DCMIPP_MODULE_ENABLED +#include "stm32n6xx_hal_dcmipp.h" +#endif /* HAL_DCMIPP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED +#include "stm32n6xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32n6xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32n6xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32n6xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32n6xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_GFXMMU_MODULE_ENABLED +#include "stm32n6xx_hal_gfxmmu.h" +#endif /* HAL_GFXMMU_MODULE_ENABLED */ + +#ifdef HAL_GFXTIM_MODULE_ENABLED +#include "stm32n6xx_hal_gfxtim.h" +#endif /* HAL_GFXTIM_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32n6xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GPU2D_MODULE_ENABLED +#include "stm32n6xx_hal_gpu2d.h" +#endif /* HAL_GPU2D_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32n6xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32n6xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32n6xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32n6xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32n6xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32n6xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32n6xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32n6xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED +#include "stm32n6xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32n6xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED +#include "stm32n6xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_MCE_MODULE_ENABLED +#include "stm32n6xx_hal_mce.h" +#endif /* HAL_MCE_MODULE_ENABLED */ + +#ifdef HAL_MDF_MODULE_ENABLED +#include "stm32n6xx_hal_mdf.h" +#endif /* HAL_MDF_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED +#include "stm32n6xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32n6xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32n6xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32n6xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32n6xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32n6xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32n6xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32n6xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32n6xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32n6xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32n6xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32n6xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32n6xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SDIO_MODULE_ENABLED +#include "stm32n6xx_hal_sdio.h" +#endif /* HAL_SDIO_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32n6xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32n6xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED +#include "stm32n6xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32n6xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32n6xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32n6xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32n6xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32n6xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32n6xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32n6xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macros -----------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32N6xx_HAL_CONF_H */ diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake index 91ffc3a39..b85ecec81 100644 --- a/hw/bsp/zephyr_board_aliases.cmake +++ b/hw/bsp/zephyr_board_aliases.cmake @@ -1 +1,2 @@ set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) +set(stm32n657nucleo_BOARD_ALIAS nucleo_n657x0_q) \ No newline at end of file diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 6678265b5..027446a85 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -322,6 +322,15 @@ // MCU with on-chip HS Phy #define TUP_RHPORT_HIGHSPEED 1 +#elif TU_CHECK_MCU(OPT_MCU_STM32N6) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_STM32 + + #define TUP_DCD_ENDPOINT_MAX 9 + + // MCU with on-chip HS Phy + #define TUP_RHPORT_HIGHSPEED 2 + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 865c51894..5f86d6b76 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -425,6 +425,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Clear A override, force B Valid dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; +#if CFG_TUSB_MCU == OPT_MCU_STM32N6 + // No hardware detection of Vbus B-session is available on the STM32N6 + dwc2->stm32_gccfg |= STM32_GCCFG_VBVALOVAL; +#endif + // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 25edcf22d..38aa5656a 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -22,6 +22,7 @@ dwc2_reg_value = { 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'ST N6xx HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index c11c1eb05..0c1f835a9 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -77,6 +77,17 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 +#elif CFG_TUSB_MCU == OPT_MCU_STM32N6 + #include "stm32n6xx.h" + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + + #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_BASE + #define OTG_HS_IRQn USB1_OTG_HS_IRQn + #elif CFG_TUSB_MCU == OPT_MCU_STM32F7 #include "stm32f7xx.h" #define EP_MAX_FS 6 diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 2de15068a..257fa2833 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -381,6 +381,10 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; +#if CFG_TUSB_MCU == OPT_MCU_STM32N6 + // No hardware detection of Vbus B-session is available on the STM32N6 + dwc2->stm32_gccfg &= ~STM32_GCCFG_VBVALOVAL; +#endif while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} // configure fixed-allocated fifo scheme diff --git a/src/tusb_option.h b/src/tusb_option.h index 104f669c9..cca6096c6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -94,6 +94,7 @@ #define OPT_MCU_STM32U0 316 ///< ST U0 #define OPT_MCU_STM32H7RS 317 ///< ST F7RS #define OPT_MCU_STM32C0 318 ///< ST C0 +#define OPT_MCU_STM32N6 319 ///< ST N6 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 1ce8be6c7..ab9d50585 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -118,6 +118,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_l5': ['https://github.com/STMicroelectronics/cmsis_device_l5.git', 'd922865fc0326a102c26211c44b8e42f52c1e53d', 'stm32l5'], + 'hw/mcu/st/cmsis_device_n6': ['https://github.com/STMicroelectronics/cmsis-device-n6.git', + 'f818b00f775444e8d19ef6cad822534c345e054f', + 'stm32n6'], 'hw/mcu/st/cmsis_device_u5': ['https://github.com/STMicroelectronics/cmsis_device_u5.git', '5ad9797c54ec3e55eff770fc9b3cd4a1aefc1309', 'stm32u5'], @@ -172,6 +175,9 @@ deps_optional = { 'hw/mcu/st/stm32l5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32l5xx_hal_driver.git', '675c32a75df37f39d50d61f51cb0dcf53f07e1cb', 'stm32l5'], + 'hw/mcu/st/stm32n6xx_hal_driver': ['https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git', + '49f9989d10cf6817d4b07ac01848956b46bd0fd6', + 'stm32n6'], 'hw/mcu/st/stm32u5xx_hal_driver': ['https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git', '4d93097a67928e9377e655ddd14622adc31b9770', 'stm32u5'], @@ -198,7 +204,7 @@ deps_optional = { 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' - 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' + 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32n6 stm32u5 stm32wb ' 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' 'tm4c '], 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', -- cgit v1.3.1 From 5c4b2c75d214fe9a7189dbcb91783d5b7841aa49 Mon Sep 17 00:00:00 2001 From: James Sandison Date: Wed, 4 Jun 2025 13:21:34 +1000 Subject: docs: update dwc2_info.md --- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++++++++---------------- 1 file changed, 58 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index dec021f59..230ab6b6f 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | XMC4500 | GD32VF103 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | ST N6xx HS | XMC4500 | GD32VF103 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:-------------|:------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | hub | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | -- cgit v1.3.1 From 1ccb10e3f1418e51c03898f7ea2067208fd642b5 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 8 Jun 2025 13:53:23 +0200 Subject: Fix ECM compile Signed-off-by: HiFiPhile --- src/class/net/ecm_rndis_device.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'src') diff --git a/src/class/net/ecm_rndis_device.c b/src/class/net/ecm_rndis_device.c index f1a88b3c0..299eb97c8 100644 --- a/src/class/net/ecm_rndis_device.c +++ b/src/class/net/ecm_rndis_device.c @@ -186,8 +186,6 @@ uint16_t netd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint1 // Open endpoint pair for RNDIS TU_ASSERT(usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &_netd_itf.ep_out, &_netd_itf.ep_in), 0); - tud_network_init_cb(); - // we are ready to transmit a packet can_xmit = true; @@ -264,7 +262,6 @@ bool netd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t // TODO should be merge with RNDIS's after endpoint opened // Also should have opposite callback for application to disable network !! - tud_network_init_cb(); can_xmit = true; // we are ready to transmit a packet tud_network_recv_renew(); // prepare for incoming packets } -- cgit v1.3.1 From 69f6b57772ad4f2923dcf48aabaaba044085c4b0 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 8 Jun 2025 14:27:57 +0200 Subject: Code reformat Signed-off-by: HiFiPhile --- src/class/usbtmc/usbtmc_device.c | 763 +++++++++++++++++---------------------- 1 file changed, 336 insertions(+), 427 deletions(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index d47da101f..b79c3369c 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -76,11 +76,6 @@ #include "usbtmc_device.h" -#ifdef xDEBUG -#include "uart_util.h" -tu_static char logMsg[150]; -#endif - // Buffer size must be an exact multiple of the max packet size for both // bulk (up to 64 bytes for FS, 512 bytes for HS). In addation, this driver // imposes a minimum buffer size of 32 bytes. @@ -88,7 +83,7 @@ tu_static char logMsg[150]; // Interrupt endpoint buffer size, default to 2 bytes as USB488 specification. #ifndef CFG_TUD_USBTMC_INT_EP_SIZE -#define CFG_TUD_USBTMC_INT_EP_SIZE 2 + #define CFG_TUD_USBTMC_INT_EP_SIZE 2 #endif /* @@ -96,27 +91,26 @@ tu_static char logMsg[150]; * consistent with USBTMC. */ -typedef enum -{ - STATE_CLOSED, // Endpoints have not yet been opened since USB reset - STATE_NAK, // Bulk-out endpoint is in NAK state. - STATE_IDLE, // Bulk-out endpoint is waiting for CMD. - STATE_RCV, // Bulk-out is receiving DEV_DEP message +typedef enum { + STATE_CLOSED,// Endpoints have not yet been opened since USB reset + STATE_NAK, // Bulk-out endpoint is in NAK state. + STATE_IDLE, // Bulk-out endpoint is waiting for CMD. + STATE_RCV, // Bulk-out is receiving DEV_DEP message STATE_TX_REQUESTED, STATE_TX_INITIATED, STATE_TX_SHORTED, STATE_CLEARING, STATE_ABORTING_BULK_IN, - STATE_ABORTING_BULK_IN_SHORTED, // aborting, and short packet has been queued for transmission - STATE_ABORTING_BULK_IN_ABORTED, // aborting, and short packet has been transmitted + STATE_ABORTING_BULK_IN_SHORTED,// aborting, and short packet has been queued for transmission + STATE_ABORTING_BULK_IN_ABORTED,// aborting, and short packet has been transmitted STATE_ABORTING_BULK_OUT, STATE_NUM_STATES } usbtmcd_state_enum; #if (CFG_TUD_USBTMC_ENABLE_488) - typedef usbtmc_response_capabilities_488_t usbtmc_capabilities_specific_t; +typedef usbtmc_response_capabilities_488_t usbtmc_capabilities_specific_t; #else - typedef usbtmc_response_capabilities_t usbtmc_capabilities_specific_t; +typedef usbtmc_response_capabilities_t usbtmc_capabilities_specific_t; #endif @@ -131,15 +125,15 @@ typedef struct uint8_t ep_int_in; uint32_t ep_bulk_in_wMaxPacketSize; uint32_t ep_bulk_out_wMaxPacketSize; - uint32_t transfer_size_remaining; // also used for requested length for bulk IN. - uint32_t transfer_size_sent; // To keep track of data bytes that have been queued in FIFO (not header bytes) + uint32_t transfer_size_remaining;// also used for requested length for bulk IN. + uint32_t transfer_size_sent; // To keep track of data bytes that have been queued in FIFO (not header bytes) - uint8_t lastBulkOutTag; // used for aborts (mostly) + uint8_t lastBulkOutTag;// used for aborts (mostly) uint8_t lastBulkInTag; // used for aborts (mostly) - uint8_t const * devInBuffer; // pointer to application-layer used for transmissions + uint8_t const *devInBuffer;// pointer to application-layer used for transmissions - usbtmc_capabilities_specific_t const * capabilities; + usbtmc_capabilities_specific_t const *capabilities; } usbtmc_interface_state_t; typedef struct { @@ -154,13 +148,13 @@ typedef struct { } usbtmc_epbuf_t; static usbtmc_interface_state_t usbtmc_state = { - .itf_id = 0xFF, + .itf_id = 0xFF, }; CFG_TUD_MEM_SECTION static usbtmc_epbuf_t usbtmc_epbuf; // We need all headers to fit in a single packet in this implementation, 32 bytes will fit all standard USBTMC headers -TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u,"USBTMC dev buffer size too small"); +TU_VERIFY_STATIC(USBTMCD_BUFFER_SIZE >= 32u, "USBTMC dev buffer size too small"); static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len); static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen); @@ -179,20 +173,18 @@ static OSAL_MUTEX_DEF(usbtmcLockBuffer); osal_mutex_t usbtmcLock; // Our own private lock, mostly for the state variable. -#define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) -#define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0) +#define criticalEnter() \ + do { (void) osal_mutex_lock(usbtmcLock, OSAL_TIMEOUT_WAIT_FOREVER); } while (0) +#define criticalLeave() \ + do { (void) osal_mutex_unlock(usbtmcLock); } while (0) -static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) -{ +static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) { bool ret = true; criticalEnter(); usbtmcd_state_enum oldState = usbtmc_state.state; - if (oldState == expectedState) - { + if (oldState == expectedState) { usbtmc_state.state = newState; - } - else - { + } else { ret = false; } criticalLeave(); @@ -207,61 +199,54 @@ static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_en // We can't just send the whole thing at once because we need to concatanate the // header with the data. bool tud_usbtmc_transmit_dev_msg_data( - const void * data, size_t len, + const void *data, size_t len, bool endOfMessage, - bool usingTermChar) -{ + bool usingTermChar) { const unsigned int txBufLen = USBTMCD_BUFFER_SIZE; #ifndef NDEBUG TU_ASSERT(len > 0u); TU_ASSERT(len <= usbtmc_state.transfer_size_remaining); TU_ASSERT(usbtmc_state.transfer_size_sent == 0u); - if(usingTermChar) - { + if (usingTermChar) { TU_ASSERT(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar); TU_ASSERT(termCharRequested); - TU_ASSERT(((uint8_t const*)data)[len-1u] == termChar); + TU_ASSERT(((uint8_t const *) data)[len - 1u] == termChar); } #endif TU_VERIFY(usbtmc_state.state == STATE_TX_REQUESTED); - usbtmc_msg_dev_dep_msg_in_header_t *hdr = (usbtmc_msg_dev_dep_msg_in_header_t*)usbtmc_epbuf.epin; + usbtmc_msg_dev_dep_msg_in_header_t *hdr = (usbtmc_msg_dev_dep_msg_in_header_t *) usbtmc_epbuf.epin; tu_varclr(hdr); - if(usbtmcVendorSpecificRequested) - { + if (usbtmcVendorSpecificRequested) { hdr->header.MsgID = USBTMC_MSGID_VENDOR_SPECIFIC_IN; - } - else - { + } else { hdr->header.MsgID = USBTMC_MSGID_DEV_DEP_MSG_IN; } hdr->header.bTag = usbtmc_state.lastBulkInTag; - hdr->header.bTagInverse = (uint8_t)~(usbtmc_state.lastBulkInTag); + hdr->header.bTagInverse = (uint8_t) ~(usbtmc_state.lastBulkInTag); hdr->TransferSize = len; hdr->bmTransferAttributes.EOM = endOfMessage; hdr->bmTransferAttributes.UsingTermChar = usingTermChar; // Copy in the header const size_t headerLen = sizeof(*hdr); - const size_t dataLen = ((headerLen + hdr->TransferSize) <= txBufLen) ? - len : (txBufLen - headerLen); + const size_t dataLen = ((headerLen + hdr->TransferSize) <= txBufLen) ? len : (txBufLen - headerLen); const size_t packetLen = headerLen + dataLen; - memcpy((uint8_t*)(usbtmc_epbuf.epin) + headerLen, data, dataLen); + memcpy((uint8_t *) (usbtmc_epbuf.epin) + headerLen, data, dataLen); usbtmc_state.transfer_size_remaining = len - dataLen; usbtmc_state.transfer_size_sent = dataLen; - usbtmc_state.devInBuffer = (uint8_t const*) data + (dataLen); + usbtmc_state.devInBuffer = (uint8_t const *) data + (dataLen); bool stateChanged = atomicChangeState(STATE_TX_REQUESTED, (packetLen >= txBufLen) ? STATE_TX_INITIATED : STATE_TX_SHORTED); TU_VERIFY(stateChanged); - TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t)packetLen)); + TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t) packetLen)); return true; } -bool tud_usbtmc_transmit_notification_data(const void * data, size_t len) -{ +bool tud_usbtmc_transmit_notification_data(const void *data, size_t len) { #ifndef NDEBUG TU_ASSERT(len > 0); TU_ASSERT(usbtmc_state.ep_int_in != 0); @@ -269,24 +254,23 @@ bool tud_usbtmc_transmit_notification_data(const void * data, size_t len) TU_VERIFY(usbd_edpt_busy(usbtmc_state.rhport, usbtmc_state.ep_int_in)); TU_VERIFY(tu_memcpy_s(usbtmc_epbuf.epnotif, CFG_TUD_USBTMC_INT_EP_SIZE, data, len) == 0); - TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_epbuf.epnotif, (uint16_t)len)); + TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_int_in, usbtmc_epbuf.epnotif, (uint16_t) len)); return true; } -void usbtmcd_init_cb(void) -{ +void usbtmcd_init_cb(void) { usbtmc_state.capabilities = tud_usbtmc_get_capabilities_cb(); #ifndef NDEBUG -# if CFG_TUD_USBTMC_ENABLE_488 + #if CFG_TUD_USBTMC_ENABLE_488 if (usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger) { - TU_ASSERT(&tud_usbtmc_msg_trigger_cb != NULL,); + TU_ASSERT(&tud_usbtmc_msg_trigger_cb != NULL, ); } // Per USB488 spec: table 8 - TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.listenOnly,); - TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.talkOnly,); -# endif + TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.listenOnly, ); + TU_ASSERT(!usbtmc_state.capabilities->bmIntfcCapabilities.talkOnly, ); + #endif if (usbtmc_state.capabilities->bmIntfcCapabilities.supportsIndicatorPulse) { - TU_ASSERT(&tud_usbtmc_indicator_pulse_cb != NULL,); + TU_ASSERT(&tud_usbtmc_indicator_pulse_cb != NULL, ); } #endif @@ -294,26 +278,25 @@ void usbtmcd_init_cb(void) } bool usbtmcd_deinit(void) { - #if OSAL_MUTEX_REQUIRED +#if OSAL_MUTEX_REQUIRED osal_mutex_delete(usbtmcLock); - #endif +#endif return true; } -uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) -{ - (void)rhport; +uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + (void) rhport; uint16_t drv_len; - uint8_t const * p_desc; + uint8_t const *p_desc; uint8_t found_endpoints = 0; - TU_VERIFY(itf_desc->bInterfaceClass == TUD_USBTMC_APP_CLASS , 0); + TU_VERIFY(itf_desc->bInterfaceClass == TUD_USBTMC_APP_CLASS, 0); TU_VERIFY(itf_desc->bInterfaceSubClass == TUD_USBTMC_APP_SUBCLASS, 0); #ifndef NDEBUG // Only 2 or 3 endpoints are allowed for USBTMC. - TU_ASSERT((itf_desc->bNumEndpoints == 2) || (itf_desc->bNumEndpoints ==3), 0); + TU_ASSERT((itf_desc->bNumEndpoints == 2) || (itf_desc->bNumEndpoints == 3), 0); #endif TU_ASSERT(usbtmc_state.state == STATE_CLOSED, 0); @@ -325,17 +308,14 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, usbtmc_state.itf_id = itf_desc->bInterfaceNumber; usbtmc_state.rhport = rhport; - while (found_endpoints < itf_desc->bNumEndpoints && drv_len <= max_len) - { - if ( TUSB_DESC_ENDPOINT == p_desc[DESC_OFFSET_TYPE]) - { - tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *)p_desc; - switch(ep_desc->bmAttributes.xfer) { + while (found_endpoints < itf_desc->bNumEndpoints && drv_len <= max_len) { + if (TUSB_DESC_ENDPOINT == p_desc[DESC_OFFSET_TYPE]) { + tusb_desc_endpoint_t const *ep_desc = (tusb_desc_endpoint_t const *) p_desc; + switch (ep_desc->bmAttributes.xfer) { case TUSB_XFER_BULK: // Ensure buffer is an exact multiple of the maxPacketSize TU_ASSERT((USBTMCD_BUFFER_SIZE % tu_edpt_packet_size(ep_desc)) == 0, 0); - if (tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN) - { + if (tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN) { usbtmc_state.ep_bulk_in = ep_desc->bEndpointAddress; usbtmc_state.ep_bulk_in_wMaxPacketSize = tu_edpt_packet_size(ep_desc); } else { @@ -354,33 +334,29 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, default: TU_ASSERT(false, 0); } - TU_ASSERT( usbd_edpt_open(rhport, ep_desc), 0); + TU_ASSERT(usbd_edpt_open(rhport, ep_desc), 0); found_endpoints++; } drv_len += tu_desc_len(p_desc); - p_desc = tu_desc_next(p_desc); + p_desc = tu_desc_next(p_desc); } - // bulk endpoints are required, but interrupt IN is optional +// bulk endpoints are required, but interrupt IN is optional #ifndef NDEBUG - TU_ASSERT(usbtmc_state.ep_bulk_in != 0, 0); + TU_ASSERT(usbtmc_state.ep_bulk_in != 0, 0); TU_ASSERT(usbtmc_state.ep_bulk_out != 0, 0); - if (itf_desc->bNumEndpoints == 2) - { + if (itf_desc->bNumEndpoints == 2) { TU_ASSERT(usbtmc_state.ep_int_in == 0, 0); - } - else if (itf_desc->bNumEndpoints == 3) - { + } else if (itf_desc->bNumEndpoints == 3) { TU_ASSERT(usbtmc_state.ep_int_in != 0, 0); } -#if (CFG_TUD_USBTMC_ENABLE_488) - if(usbtmc_state.capabilities->bmIntfcCapabilities488.is488_2 || - usbtmc_state.capabilities->bmDevCapabilities488.SR1) - { + #if (CFG_TUD_USBTMC_ENABLE_488) + if (usbtmc_state.capabilities->bmIntfcCapabilities488.is488_2 || + usbtmc_state.capabilities->bmDevCapabilities488.SR1) { TU_ASSERT(usbtmc_state.ep_int_in != 0, 0); } -#endif + #endif #endif atomicChangeState(STATE_CLOSED, STATE_NAK); tud_usbtmc_open_cb(itf_desc->iInterface); @@ -393,30 +369,27 @@ uint16_t usbtmcd_open_cb(uint8_t rhport, tusb_desc_interface_t const * itf_desc, // processing a command (such as a clear). Returns true if it was // in the NAK state and successfully transitioned to the ACK wait // state. -bool tud_usbtmc_start_bus_read(void) -{ +bool tud_usbtmc_start_bus_read(void) { usbtmcd_state_enum oldState = usbtmc_state.state; - switch(oldState) - { - // These may transition to IDLE - case STATE_NAK: - case STATE_ABORTING_BULK_IN_ABORTED: - TU_VERIFY(atomicChangeState(oldState, STATE_IDLE)); - break; - // When receiving, let it remain receiving - case STATE_RCV: - break; - default: - return false; + switch (oldState) { + // These may transition to IDLE + case STATE_NAK: + case STATE_ABORTING_BULK_IN_ABORTED: + TU_VERIFY(atomicChangeState(oldState, STATE_IDLE)); + break; + // When receiving, let it remain receiving + case STATE_RCV: + break; + default: + return false; } - TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_epbuf.epout, (uint16_t)usbtmc_state.ep_bulk_out_wMaxPacketSize)); + TU_VERIFY(usbd_edpt_xfer(usbtmc_state.rhport, usbtmc_state.ep_bulk_out, usbtmc_epbuf.epout, (uint16_t) usbtmc_state.ep_bulk_out_wMaxPacketSize)); return true; } -void usbtmcd_reset_cb(uint8_t rhport) -{ - (void)rhport; - usbtmc_capabilities_specific_t const * capabilities = tud_usbtmc_get_capabilities_cb(); +void usbtmcd_reset_cb(uint8_t rhport) { + (void) rhport; + usbtmc_capabilities_specific_t const *capabilities = tud_usbtmc_get_capabilities_cb(); criticalEnter(); tu_varclr(&usbtmc_state); @@ -425,35 +398,32 @@ void usbtmcd_reset_cb(uint8_t rhport) criticalLeave(); } -static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len) -{ - (void)rhport; +static bool handle_devMsgOutStart(uint8_t rhport, void *data, size_t len) { + (void) rhport; // return true upon failure, as we can assume error is being handled elsewhere. TU_VERIFY(atomicChangeState(STATE_IDLE, STATE_RCV), true); usbtmc_state.transfer_size_sent = 0u; // must be a header, should have been confirmed before calling here. - usbtmc_msg_request_dev_dep_out *msg = (usbtmc_msg_request_dev_dep_out*)data; + usbtmc_msg_request_dev_dep_out *msg = (usbtmc_msg_request_dev_dep_out *) data; usbtmc_state.transfer_size_remaining = msg->TransferSize; TU_VERIFY(tud_usbtmc_msgBulkOut_start_cb(msg)); - TU_VERIFY(handle_devMsgOut(rhport, (uint8_t*)data + sizeof(*msg), len - sizeof(*msg), len)); + TU_VERIFY(handle_devMsgOut(rhport, (uint8_t *) data + sizeof(*msg), len - sizeof(*msg), len)); usbtmc_state.lastBulkOutTag = msg->header.bTag; return true; } -static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen) -{ - (void)rhport; +static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t packetLen) { + (void) rhport; // return true upon failure, as we can assume error is being handled elsewhere. - TU_VERIFY(usbtmc_state.state == STATE_RCV,true); + TU_VERIFY(usbtmc_state.state == STATE_RCV, true); bool shortPacket = (packetLen < usbtmc_state.ep_bulk_out_wMaxPacketSize); // Packet is to be considered complete when we get enough data or at a short packet. bool atEnd = false; - if(len >= usbtmc_state.transfer_size_remaining || shortPacket) - { + if (len >= usbtmc_state.transfer_size_remaining || shortPacket) { atEnd = true; TU_VERIFY(atomicChangeState(STATE_RCV, STATE_NAK)); } @@ -464,8 +434,7 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack usbtmc_state.transfer_size_sent += len; // App may (should?) call the wait_for_bus() command at this point - if(!tud_usbtmc_msg_data_cb(data, len, atEnd)) - { + if (!tud_usbtmc_msg_data_cb(data, len, atEnd)) { // TODO: Go to an error state upon failure other than just stalling the EP? return false; } @@ -474,10 +443,9 @@ static bool handle_devMsgOut(uint8_t rhport, void *data, size_t len, size_t pack return true; } -static bool handle_devMsgIn(void *data, size_t len) -{ +static bool handle_devMsgIn(void *data, size_t len) { TU_VERIFY(len == sizeof(usbtmc_msg_request_dev_dep_in)); - usbtmc_msg_request_dev_dep_in *msg = (usbtmc_msg_request_dev_dep_in*)data; + usbtmc_msg_request_dev_dep_in *msg = (usbtmc_msg_request_dev_dep_in *) data; bool stateChanged = atomicChangeState(STATE_IDLE, STATE_TX_REQUESTED); TU_VERIFY(stateChanged); usbtmc_state.lastBulkInTag = msg->header.bTag; @@ -490,148 +458,135 @@ static bool handle_devMsgIn(void *data, size_t len) termChar = msg->TermChar; #endif - if(termCharRequested) + if (termCharRequested) TU_VERIFY(usbtmc_state.capabilities->bmDevCapabilities.canEndBulkInOnTermChar); TU_VERIFY(tud_usbtmc_msgBulkIn_request_cb(msg)); return true; } -bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { TU_VERIFY(result == XFER_RESULT_SUCCESS); //uart_tx_str_sync("TMC XFER CB\r\n"); - if(usbtmc_state.state == STATE_CLEARING) { + if (usbtmc_state.state == STATE_CLEARING) { return true; /* I think we can ignore everything here */ } - if(ep_addr == usbtmc_state.ep_bulk_out) - { + if (ep_addr == usbtmc_state.ep_bulk_out) { usbtmc_msg_generic_t *msg = NULL; - switch(usbtmc_state.state) - { - case STATE_IDLE: - { + switch (usbtmc_state.state) { + case STATE_IDLE: { TU_VERIFY(xferred_bytes >= sizeof(usbtmc_msg_generic_t)); - msg = (usbtmc_msg_generic_t*)(usbtmc_epbuf.epout); - uint8_t invInvTag = (uint8_t)~(msg->header.bTagInverse); + msg = (usbtmc_msg_generic_t *) (usbtmc_epbuf.epout); + uint8_t invInvTag = (uint8_t) ~(msg->header.bTagInverse); TU_VERIFY(msg->header.bTag == invInvTag); TU_VERIFY(msg->header.bTag != 0x00); - switch(msg->header.MsgID) { - case USBTMC_MSGID_DEV_DEP_MSG_OUT: - usbtmcVendorSpecificRequested = false; - if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) - { - usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); - return false; - } - break; + switch (msg->header.MsgID) { + case USBTMC_MSGID_DEV_DEP_MSG_OUT: + usbtmcVendorSpecificRequested = false; + if (!handle_devMsgOutStart(rhport, msg, xferred_bytes)) { + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + return false; + } + break; - case USBTMC_MSGID_DEV_DEP_MSG_IN: - usbtmcVendorSpecificRequested = false; - TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); - break; + case USBTMC_MSGID_DEV_DEP_MSG_IN: + usbtmcVendorSpecificRequested = false; + TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); + break; #if (CFG_TUD_USBTMC_ENABLE_488) - case USBTMC_MSGID_USB488_TRIGGER: - // Spec says we halt the EP if we didn't declare we support it. - TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger); - TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg)); + case USBTMC_MSGID_USB488_TRIGGER: + // Spec says we halt the EP if we didn't declare we support it. + TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities488.supportsTrigger); + TU_VERIFY(tud_usbtmc_msg_trigger_cb(msg)); - break; + break; #endif - case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT: - usbtmcVendorSpecificRequested = true; - if(!handle_devMsgOutStart(rhport, msg, xferred_bytes)) - { + case USBTMC_MSGID_VENDOR_SPECIFIC_MSG_OUT: + usbtmcVendorSpecificRequested = true; + if (!handle_devMsgOutStart(rhport, msg, xferred_bytes)) { + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + return false; + } + break; + + case USBTMC_MSGID_VENDOR_SPECIFIC_IN: + usbtmcVendorSpecificRequested = true; + TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); + break; + + default: usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); return false; - } - break; - - case USBTMC_MSGID_VENDOR_SPECIFIC_IN: - usbtmcVendorSpecificRequested = true; - TU_VERIFY(handle_devMsgIn(msg, xferred_bytes)); - break; - - default: + } + return true; + } + case STATE_RCV: + if (!handle_devMsgOut(rhport, usbtmc_epbuf.epout, xferred_bytes, xferred_bytes)) { usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); return false; } return true; - } - case STATE_RCV: - if(!handle_devMsgOut(rhport, usbtmc_epbuf.epout, xferred_bytes, xferred_bytes)) - { - usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); - return false; - } - return true; - case STATE_ABORTING_BULK_OUT: - // Should be stalled by now, shouldn't have received a packet. - return false; + case STATE_ABORTING_BULK_OUT: + // Should be stalled by now, shouldn't have received a packet. + return false; - case STATE_TX_REQUESTED: - case STATE_TX_INITIATED: - case STATE_ABORTING_BULK_IN: - case STATE_ABORTING_BULK_IN_SHORTED: - case STATE_ABORTING_BULK_IN_ABORTED: - default: - return false; + case STATE_TX_REQUESTED: + case STATE_TX_INITIATED: + case STATE_ABORTING_BULK_IN: + case STATE_ABORTING_BULK_IN_SHORTED: + case STATE_ABORTING_BULK_IN_ABORTED: + default: + return false; } - } - else if(ep_addr == usbtmc_state.ep_bulk_in) - { - switch(usbtmc_state.state) { - case STATE_TX_SHORTED: - TU_VERIFY(atomicChangeState(STATE_TX_SHORTED, STATE_NAK)); - TU_VERIFY(tud_usbtmc_msgBulkIn_complete_cb()); - break; - - case STATE_TX_INITIATED: - if(usbtmc_state.transfer_size_remaining >= USBTMCD_BUFFER_SIZE) - { - // Copy buffer to ensure alignment correctness - memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, USBTMCD_BUFFER_SIZE); - TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, USBTMCD_BUFFER_SIZE)); - usbtmc_state.devInBuffer += USBTMCD_BUFFER_SIZE; - usbtmc_state.transfer_size_remaining -= USBTMCD_BUFFER_SIZE; - usbtmc_state.transfer_size_sent += USBTMCD_BUFFER_SIZE; - } - else // last packet - { - size_t packetLen = usbtmc_state.transfer_size_remaining; - memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); - usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); - usbtmc_state.transfer_size_remaining = 0; - usbtmc_state.devInBuffer = NULL; - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t)packetLen) ); - if(((packetLen % usbtmc_state.ep_bulk_in_wMaxPacketSize) != 0) || (packetLen == 0 )) + } else if (ep_addr == usbtmc_state.ep_bulk_in) { + switch (usbtmc_state.state) { + case STATE_TX_SHORTED: + TU_VERIFY(atomicChangeState(STATE_TX_SHORTED, STATE_NAK)); + TU_VERIFY(tud_usbtmc_msgBulkIn_complete_cb()); + break; + + case STATE_TX_INITIATED: + if (usbtmc_state.transfer_size_remaining >= USBTMCD_BUFFER_SIZE) { + // Copy buffer to ensure alignment correctness + memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, USBTMCD_BUFFER_SIZE); + TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, USBTMCD_BUFFER_SIZE)); + usbtmc_state.devInBuffer += USBTMCD_BUFFER_SIZE; + usbtmc_state.transfer_size_remaining -= USBTMCD_BUFFER_SIZE; + usbtmc_state.transfer_size_sent += USBTMCD_BUFFER_SIZE; + } else// last packet { - usbtmc_state.state = STATE_TX_SHORTED; + size_t packetLen = usbtmc_state.transfer_size_remaining; + memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); + usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); + usbtmc_state.transfer_size_remaining = 0; + usbtmc_state.devInBuffer = NULL; + TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t) packetLen)); + if (((packetLen % usbtmc_state.ep_bulk_in_wMaxPacketSize) != 0) || (packetLen == 0)) { + usbtmc_state.state = STATE_TX_SHORTED; + } } - } - return true; + return true; - case STATE_ABORTING_BULK_IN: - // need to send short packet (ZLP?) - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin,(uint16_t)0u)); - usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED; - return true; + case STATE_ABORTING_BULK_IN: + // need to send short packet (ZLP?) + TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t) 0u)); + usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED; + return true; - case STATE_ABORTING_BULK_IN_SHORTED: - /* Done. :)*/ - usbtmc_state.state = STATE_ABORTING_BULK_IN_ABORTED; - return true; + case STATE_ABORTING_BULK_IN_SHORTED: + /* Done. :)*/ + usbtmc_state.state = STATE_ABORTING_BULK_IN_ABORTED; + return true; - default: - TU_ASSERT(false); + default: + TU_ASSERT(false); } - } - else if (ep_addr == usbtmc_state.ep_int_in) { + } else if (ep_addr == usbtmc_state.ep_int_in) { if (tud_usbtmc_notification_complete_cb) { TU_VERIFY(tud_usbtmc_notification_complete_cb()); } @@ -643,188 +598,157 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) -bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ +bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const *request) { // nothing to do with DATA and ACK stage - if ( stage != CONTROL_STAGE_SETUP ) return true; + if (stage != CONTROL_STAGE_SETUP) return true; uint8_t tmcStatusCode = USBTMC_STATUS_FAILED; #if (CFG_TUD_USBTMC_ENABLE_488) uint8_t bTag; #endif - if((request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) && + if ((request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD) && (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_ENDPOINT) && (request->bRequest == TUSB_REQ_CLEAR_FEATURE) && - (request->wValue == TUSB_REQ_FEATURE_EDPT_HALT)) - { + (request->wValue == TUSB_REQ_FEATURE_EDPT_HALT)) { uint32_t ep_addr = (request->wIndex); // At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT, // the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if // the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP. - if(ep_addr == usbtmc_state.ep_bulk_out) - { + if (ep_addr == usbtmc_state.ep_bulk_out) { criticalEnter(); - usbd_edpt_stall(rhport, (uint8_t)ep_addr); - usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr); - usbtmc_state.state = STATE_NAK; // USBD core has placed EP in NAK state for us + usbd_edpt_stall(rhport, (uint8_t) ep_addr); + usbd_edpt_clear_stall(rhport, (uint8_t) ep_addr); + usbtmc_state.state = STATE_NAK;// USBD core has placed EP in NAK state for us criticalLeave(); tud_usbtmc_bulkOut_clearFeature_cb(); - } - else if (ep_addr == usbtmc_state.ep_bulk_in) - { - usbd_edpt_stall(rhport, (uint8_t)ep_addr); - usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr); + } else if (ep_addr == usbtmc_state.ep_bulk_in) { + usbd_edpt_stall(rhport, (uint8_t) ep_addr); + usbd_edpt_clear_stall(rhport, (uint8_t) ep_addr); tud_usbtmc_bulkIn_clearFeature_cb(); - } - else if ((usbtmc_state.ep_int_in != 0) && (ep_addr == usbtmc_state.ep_int_in)) - { + } else if ((usbtmc_state.ep_int_in != 0) && (ep_addr == usbtmc_state.ep_int_in)) { // Clearing interrupt in EP - usbd_edpt_stall(rhport, (uint8_t)ep_addr); - usbd_edpt_clear_stall(rhport, (uint8_t)ep_addr); - } - else - { + usbd_edpt_stall(rhport, (uint8_t) ep_addr); + usbd_edpt_clear_stall(rhport, (uint8_t) ep_addr); + } else { return false; } return true; } // Otherwise, we only handle class requests. - if(request->bmRequestType_bit.type != TUSB_REQ_TYPE_CLASS) - { + if (request->bmRequestType_bit.type != TUSB_REQ_TYPE_CLASS) { return false; } // Verification that we own the interface is unneeded since it's been routed to us specifically. - switch(request->bRequest) - { - // USBTMC required requests - case USBTMC_bREQUEST_INITIATE_ABORT_BULK_OUT: - { - usbtmc_initiate_abort_rsp_t rsp = { - .bTag = usbtmc_state.lastBulkOutTag, - }; - TU_VERIFY(request->bmRequestType == 0xA2); // in,class,interface - TU_VERIFY(request->wLength == sizeof(rsp)); - TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_out); - - // wValue is the requested bTag to abort - if(usbtmc_state.state != STATE_RCV) - { - rsp.USBTMC_status = USBTMC_STATUS_FAILED; + switch (request->bRequest) { + // USBTMC required requests + case USBTMC_bREQUEST_INITIATE_ABORT_BULK_OUT: { + usbtmc_initiate_abort_rsp_t rsp = { + .bTag = usbtmc_state.lastBulkOutTag, + }; + TU_VERIFY(request->bmRequestType == 0xA2);// in,class,interface + TU_VERIFY(request->wLength == sizeof(rsp)); + TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_out); + + // wValue is the requested bTag to abort + if (usbtmc_state.state != STATE_RCV) { + rsp.USBTMC_status = USBTMC_STATUS_FAILED; + } else if (usbtmc_state.lastBulkOutTag == (request->wValue & 0x7Fu)) { + rsp.USBTMC_status = USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS; + } else { + rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; + // Check if we've queued a short packet + criticalEnter(); + usbtmc_state.state = STATE_ABORTING_BULK_OUT; + criticalLeave(); + TU_VERIFY(tud_usbtmc_initiate_abort_bulk_out_cb(&(rsp.USBTMC_status))); + usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + } + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &rsp, sizeof(rsp))); + return true; } - else if(usbtmc_state.lastBulkOutTag == (request->wValue & 0x7Fu)) - { - rsp.USBTMC_status = USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS; + + case USBTMC_bREQUEST_CHECK_ABORT_BULK_OUT_STATUS: { + usbtmc_check_abort_bulk_rsp_t rsp = { + .USBTMC_status = USBTMC_STATUS_SUCCESS, + .NBYTES_RXD_TXD = usbtmc_state.transfer_size_sent}; + TU_VERIFY(request->bmRequestType == 0xA2);// in,class,EP + TU_VERIFY(request->wLength == sizeof(rsp)); + TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_out); + TU_VERIFY(tud_usbtmc_check_abort_bulk_out_cb(&rsp)); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &rsp, sizeof(rsp))); + return true; } - else - { - rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; - // Check if we've queued a short packet - criticalEnter(); - usbtmc_state.state = STATE_ABORTING_BULK_OUT; - criticalLeave(); - TU_VERIFY(tud_usbtmc_initiate_abort_bulk_out_cb(&(rsp.USBTMC_status))); - usbd_edpt_stall(rhport, usbtmc_state.ep_bulk_out); + + case USBTMC_bREQUEST_INITIATE_ABORT_BULK_IN: { + usbtmc_initiate_abort_rsp_t rsp = { + .bTag = usbtmc_state.lastBulkInTag, + }; + TU_VERIFY(request->bmRequestType == 0xA2);// in,class,interface + TU_VERIFY(request->wLength == sizeof(rsp)); + TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_in); + // wValue is the requested bTag to abort + if ((usbtmc_state.state == STATE_TX_REQUESTED || usbtmc_state.state == STATE_TX_INITIATED) && + usbtmc_state.lastBulkInTag == (request->wValue & 0x7Fu)) { + rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; + usbtmc_state.transfer_size_remaining = 0u; + // Check if we've queued a short packet + criticalEnter(); + usbtmc_state.state = ((usbtmc_state.transfer_size_sent % usbtmc_state.ep_bulk_in_wMaxPacketSize) == 0) ? STATE_ABORTING_BULK_IN : STATE_ABORTING_BULK_IN_SHORTED; + criticalLeave(); + if (usbtmc_state.transfer_size_sent == 0) { + // Send short packet, nothing is in the buffer yet + TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t) 0u)); + usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED; + } + TU_VERIFY(tud_usbtmc_initiate_abort_bulk_in_cb(&(rsp.USBTMC_status))); + } else if ((usbtmc_state.state == STATE_TX_REQUESTED || usbtmc_state.state == STATE_TX_INITIATED)) {// FIXME: Unsure how to check if the OUT endpoint fifo is non-empty.... + rsp.USBTMC_status = USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS; + } else { + rsp.USBTMC_status = USBTMC_STATUS_FAILED; + } + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &rsp, sizeof(rsp))); + return true; } - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&rsp,sizeof(rsp))); - return true; - } - case USBTMC_bREQUEST_CHECK_ABORT_BULK_OUT_STATUS: - { - usbtmc_check_abort_bulk_rsp_t rsp = { - .USBTMC_status = USBTMC_STATUS_SUCCESS, - .NBYTES_RXD_TXD = usbtmc_state.transfer_size_sent - }; - TU_VERIFY(request->bmRequestType == 0xA2); // in,class,EP - TU_VERIFY(request->wLength == sizeof(rsp)); - TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_out); - TU_VERIFY(tud_usbtmc_check_abort_bulk_out_cb(&rsp)); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&rsp,sizeof(rsp))); - return true; - } + case USBTMC_bREQUEST_CHECK_ABORT_BULK_IN_STATUS: { + TU_VERIFY(request->bmRequestType == 0xA2);// in,class,EP + TU_VERIFY(request->wLength == 8u); - case USBTMC_bREQUEST_INITIATE_ABORT_BULK_IN: - { - usbtmc_initiate_abort_rsp_t rsp = { - .bTag = usbtmc_state.lastBulkInTag, - }; - TU_VERIFY(request->bmRequestType == 0xA2); // in,class,interface - TU_VERIFY(request->wLength == sizeof(rsp)); - TU_VERIFY(request->wIndex == usbtmc_state.ep_bulk_in); - // wValue is the requested bTag to abort - if((usbtmc_state.state == STATE_TX_REQUESTED || usbtmc_state.state == STATE_TX_INITIATED) && - usbtmc_state.lastBulkInTag == (request->wValue & 0x7Fu)) - { - rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; - usbtmc_state.transfer_size_remaining = 0u; - // Check if we've queued a short packet + usbtmc_check_abort_bulk_rsp_t rsp = + { + .USBTMC_status = USBTMC_STATUS_FAILED, + .bmAbortBulkIn = + { + .BulkInFifoBytes = (usbtmc_state.state != STATE_ABORTING_BULK_IN_ABORTED)}, + .NBYTES_RXD_TXD = usbtmc_state.transfer_size_sent, + }; + TU_VERIFY(tud_usbtmc_check_abort_bulk_in_cb(&rsp)); criticalEnter(); - usbtmc_state.state = ((usbtmc_state.transfer_size_sent % usbtmc_state.ep_bulk_in_wMaxPacketSize) == 0) ? - STATE_ABORTING_BULK_IN : STATE_ABORTING_BULK_IN_SHORTED; - criticalLeave(); - if(usbtmc_state.transfer_size_sent == 0) - { - // Send short packet, nothing is in the buffer yet - TU_VERIFY( usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin,(uint16_t)0u)); - usbtmc_state.state = STATE_ABORTING_BULK_IN_SHORTED; + switch (usbtmc_state.state) { + case STATE_ABORTING_BULK_IN_ABORTED: + rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; + usbtmc_state.state = STATE_IDLE; + break; + case STATE_ABORTING_BULK_IN: + case STATE_ABORTING_BULK_OUT: + rsp.USBTMC_status = USBTMC_STATUS_PENDING; + break; + default: + break; } - TU_VERIFY(tud_usbtmc_initiate_abort_bulk_in_cb(&(rsp.USBTMC_status))); - } - else if((usbtmc_state.state == STATE_TX_REQUESTED || usbtmc_state.state == STATE_TX_INITIATED)) - { // FIXME: Unsure how to check if the OUT endpoint fifo is non-empty.... - rsp.USBTMC_status = USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS; - } - else - { - rsp.USBTMC_status = USBTMC_STATUS_FAILED; - } - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&rsp,sizeof(rsp))); - return true; - } - - case USBTMC_bREQUEST_CHECK_ABORT_BULK_IN_STATUS: - { - TU_VERIFY(request->bmRequestType == 0xA2); // in,class,EP - TU_VERIFY(request->wLength == 8u); + criticalLeave(); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &rsp, sizeof(rsp))); - usbtmc_check_abort_bulk_rsp_t rsp = - { - .USBTMC_status = USBTMC_STATUS_FAILED, - .bmAbortBulkIn = - { - .BulkInFifoBytes = (usbtmc_state.state != STATE_ABORTING_BULK_IN_ABORTED) - }, - .NBYTES_RXD_TXD = usbtmc_state.transfer_size_sent, - }; - TU_VERIFY(tud_usbtmc_check_abort_bulk_in_cb(&rsp)); - criticalEnter(); - switch(usbtmc_state.state) - { - case STATE_ABORTING_BULK_IN_ABORTED: - rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; - usbtmc_state.state = STATE_IDLE; - break; - case STATE_ABORTING_BULK_IN: - case STATE_ABORTING_BULK_OUT: - rsp.USBTMC_status = USBTMC_STATUS_PENDING; - break; - default: - break; + return true; } - criticalLeave(); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&rsp,sizeof(rsp))); - - return true; - } - case USBTMC_bREQUEST_INITIATE_CLEAR: - { - TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface + case USBTMC_bREQUEST_INITIATE_CLEAR: { + TU_VERIFY(request->bmRequestType == 0xA1);// in,class,interface TU_VERIFY(request->wLength == sizeof(tmcStatusCode)); // After receiving an INITIATE_CLEAR request, the device must Halt the Bulk-OUT endpoint, queue the // control endpoint response shown in Table 31, and clear all input buffers and output buffers. @@ -834,112 +758,97 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request usbtmc_state.state = STATE_CLEARING; criticalLeave(); TU_VERIFY(tud_usbtmc_initiate_clear_cb(&tmcStatusCode)); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&tmcStatusCode,sizeof(tmcStatusCode))); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &tmcStatusCode, sizeof(tmcStatusCode))); return true; } - case USBTMC_bREQUEST_CHECK_CLEAR_STATUS: - { - TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface + case USBTMC_bREQUEST_CHECK_CLEAR_STATUS: { + TU_VERIFY(request->bmRequestType == 0xA1);// in,class,interface usbtmc_get_clear_status_rsp_t clearStatusRsp = {0}; TU_VERIFY(request->wLength == sizeof(clearStatusRsp)); - if(usbd_edpt_busy(rhport, usbtmc_state.ep_bulk_in)) - { + if (usbd_edpt_busy(rhport, usbtmc_state.ep_bulk_in)) { // Stuff stuck in TX buffer? clearStatusRsp.bmClear.BulkInFifoBytes = 1; clearStatusRsp.USBTMC_status = USBTMC_STATUS_PENDING; - } - else - { + } else { // Let app check if it's clear TU_VERIFY(tud_usbtmc_check_clear_cb(&clearStatusRsp)); } - if(clearStatusRsp.USBTMC_status == USBTMC_STATUS_SUCCESS) - { + if (clearStatusRsp.USBTMC_status == USBTMC_STATUS_SUCCESS) { criticalEnter(); usbtmc_state.state = STATE_IDLE; criticalLeave(); } - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&clearStatusRsp,sizeof(clearStatusRsp))); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &clearStatusRsp, sizeof(clearStatusRsp))); return true; } - case USBTMC_bREQUEST_GET_CAPABILITIES: - { - TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface + case USBTMC_bREQUEST_GET_CAPABILITIES: { + TU_VERIFY(request->bmRequestType == 0xA1);// in,class,interface TU_VERIFY(request->wLength == sizeof(*(usbtmc_state.capabilities))); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)(uintptr_t) usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities))); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) (uintptr_t) usbtmc_state.capabilities, sizeof(*usbtmc_state.capabilities))); return true; } - // USBTMC Optional Requests + // USBTMC Optional Requests - case USBTMC_bREQUEST_INDICATOR_PULSE: // Optional + case USBTMC_bREQUEST_INDICATOR_PULSE:// Optional { - TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface + TU_VERIFY(request->bmRequestType == 0xA1);// in,class,interface TU_VERIFY(request->wLength == sizeof(tmcStatusCode)); TU_VERIFY(usbtmc_state.capabilities->bmIntfcCapabilities.supportsIndicatorPulse); TU_VERIFY(tud_usbtmc_indicator_pulse_cb(request, &tmcStatusCode)); - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&tmcStatusCode, sizeof(tmcStatusCode))); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &tmcStatusCode, sizeof(tmcStatusCode))); return true; } #if (CFG_TUD_USBTMC_ENABLE_488) - // USB488 required requests - case USB488_bREQUEST_READ_STATUS_BYTE: - { + // USB488 required requests + case USB488_bREQUEST_READ_STATUS_BYTE: { usbtmc_read_stb_rsp_488_t rsp; TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface - TU_VERIFY(request->wLength == sizeof(rsp)); // in,class,interface + TU_VERIFY(request->wLength == sizeof(rsp));// in,class,interface bTag = request->wValue & 0x7F; TU_VERIFY(request->bmRequestType == 0xA1); - TU_VERIFY((request->wValue & (~0x7F)) == 0u); // Other bits are required to be zero (USB488v1.0 Table 11) + TU_VERIFY((request->wValue & (~0x7F)) == 0u);// Other bits are required to be zero (USB488v1.0 Table 11) TU_VERIFY(bTag >= 0x02 && bTag <= 127); TU_VERIFY(request->wIndex == usbtmc_state.itf_id); TU_VERIFY(request->wLength == 0x0003); - rsp.bTag = (uint8_t)bTag; - if(usbtmc_state.ep_int_in != 0) - { - rsp.statusByte = 0x00; // Use interrupt endpoint, instead. Must be 0x00 (USB488v1.0 4.3.1.2) - if(usbd_edpt_busy(rhport, usbtmc_state.ep_int_in)) - { + rsp.bTag = (uint8_t) bTag; + if (usbtmc_state.ep_int_in != 0) { + rsp.statusByte = 0x00;// Use interrupt endpoint, instead. Must be 0x00 (USB488v1.0 4.3.1.2) + if (usbd_edpt_busy(rhport, usbtmc_state.ep_int_in)) { rsp.USBTMC_status = USB488_STATUS_INTERRUPT_IN_BUSY; - } - else - { + } else { rsp.USBTMC_status = USBTMC_STATUS_SUCCESS; usbtmc_read_stb_interrupt_488_t intMsg = - { - .bNotify1 = { - .one = 1, - .bTag = bTag & 0x7Fu, - }, - .StatusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status)) - }; + { + .bNotify1 = { + .one = 1, + .bTag = bTag & 0x7Fu, + }, + .StatusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status))}; // Must be queued before control request response sent (USB488v1.0 4.3.1.2) - usbd_edpt_xfer(rhport, usbtmc_state.ep_int_in, (void*)&intMsg, sizeof(intMsg)); + usbd_edpt_xfer(rhport, usbtmc_state.ep_int_in, (void *) &intMsg, sizeof(intMsg)); } - } - else - { + } else { rsp.statusByte = tud_usbtmc_get_stb_cb(&(rsp.USBTMC_status)); } - TU_VERIFY(tud_control_xfer(rhport, request, (void*)&rsp, sizeof(rsp))); + TU_VERIFY(tud_control_xfer(rhport, request, (void *) &rsp, sizeof(rsp))); return true; } - // USB488 optional requests - case USB488_bREQUEST_REN_CONTROL: - case USB488_bREQUEST_GO_TO_LOCAL: - case USB488_bREQUEST_LOCAL_LOCKOUT: - { - TU_VERIFY(request->bmRequestType == 0xA1); // in,class,interface + // USB488 optional requests + case USB488_bREQUEST_REN_CONTROL: + case USB488_bREQUEST_GO_TO_LOCAL: + case USB488_bREQUEST_LOCAL_LOCKOUT: { + TU_VERIFY(request->bmRequestType == 0xA1);// in,class,interface return false; } #endif - default: - return false; + default: + return false; } } -- cgit v1.3.1 From d533650105c3d41e77a063869175cc56f5ef0461 Mon Sep 17 00:00:00 2001 From: Cédric Berger Date: Mon, 9 Jun 2025 16:56:02 +0200 Subject: Fix TUH_EPSIZE_BULK_MPS macro TUH_EPSIZE_BULK_MPS should be set based on TUH_OPT_HIGH_SPEED, not TUD_OPT_HIGH_SPEED --- src/host/usbh.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/host/usbh.h b/src/host/usbh.h index 6f34d8bb3..13eede869 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -42,7 +42,7 @@ //--------------------------------------------------------------------+ // Endpoint Bulk size depending on host mx speed -#define TUH_EPSIZE_BULK_MPS (TUD_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) +#define TUH_EPSIZE_BULK_MPS (TUH_OPT_HIGH_SPEED ? TUSB_EPSIZE_BULK_HS : TUSB_EPSIZE_BULK_FS) // forward declaration struct tuh_xfer_s; -- cgit v1.3.1 From 14124c1735507cdb40252f04a3580f80dd9952e9 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 11 Jun 2025 19:35:20 +0700 Subject: add h7rs to ci matrix --- .github/workflows/ci_set_matrix.py | 2 +- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 3 +- 3 files changed, 60 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index bccb07e3e..961e27a8f 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -40,7 +40,7 @@ family_list = { "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"], "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"], "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"], - "stm32h7": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32h7 stm32h7rs": ["arm-gcc", "arm-clang", "arm-iar"], "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"], "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"], "xmc4000": ["arm-gcc"], diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 76bd251c7..54b3cae7c 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | ST H7S3 HS | XMC4500 | GD32VF103 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:-------------|:------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | hub | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS HS | XMC4500 | GD32VF103 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:------------------|:-------------|:------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 6ab4e0641..3d7d16dcc 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -21,8 +21,7 @@ dwc2_reg_value = { 'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], - 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], - 'ST H7S3 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'ST U5A5/H7RS HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], } -- cgit v1.3.1 From 7d66a3e7758665138f495b5d9174c1874332ce1a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Jun 2025 21:20:49 +0700 Subject: merge n6 and h7rs (same config) --- src/common/tusb_mcu.h | 11 +---------- src/portable/synopsys/dwc2/dwc2_stm32.h | 4 ++-- 2 files changed, 3 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 027446a85..2ee2132bf 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -312,7 +312,7 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 -#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS) +#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS, OPT_MCU_STM32N6) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 @@ -322,15 +322,6 @@ // MCU with on-chip HS Phy #define TUP_RHPORT_HIGHSPEED 1 -#elif TU_CHECK_MCU(OPT_MCU_STM32N6) - #define TUP_USBIP_DWC2 - #define TUP_USBIP_DWC2_STM32 - - #define TUP_DCD_ENDPOINT_MAX 9 - - // MCU with on-chip HS Phy - #define TUP_RHPORT_HIGHSPEED 2 - //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 0c1f835a9..dc4251c29 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -79,8 +79,8 @@ extern "C" { #elif CFG_TUSB_MCU == OPT_MCU_STM32N6 #include "stm32n6xx.h" - #define EP_MAX_FS 6 - #define EP_FIFO_SIZE_FS 1280 + #define EP_MAX_FS 9 + #define EP_FIFO_SIZE_FS 4096 #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 -- cgit v1.3.1 From e84efd2771858b9f00d78824ccf8b1fade5f103c Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 25 Jan 2025 13:00:41 +0100 Subject: Add STM32 DWC2 cache support Signed-off-by: HiFiPhile --- src/common/tusb_mcu.h | 15 +++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 73 +++++++++++++++++++++++++++++++++ src/portable/synopsys/dwc2/hcd_dwc2.c | 2 +- 4 files changed, 90 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 2ee2132bf..8b30c98cd 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -220,12 +220,23 @@ #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS #endif + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #elif TU_CHECK_MCU(OPT_MCU_STM32H7) + #include "stm32h7xx.h" #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 #define TUP_DCD_ENDPOINT_MAX 9 + #if __CORTEX_M == 7 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #endif + #elif TU_CHECK_MCU(OPT_MCU_STM32H5) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 @@ -322,6 +333,10 @@ // MCU with on-chip HS Phy #define TUP_RHPORT_HIGHSPEED 1 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 5f86d6b76..f7e9aacfe 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- -#if CFG_TUD_MEM_DCACHE_ENABLE +#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE bool dcd_dcache_clean(const void* addr, uint32_t data_size) { TU_VERIFY(addr && data_size); return dwc2_dcache_clean(addr, data_size); diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index dc4251c29..f01d11fe8 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -279,6 +279,79 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { } } +//------------- DCache -------------// +#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE) + +typedef struct +{ + uintptr_t start; + uintptr_t end; +} mem_region_t; + +// Can be used to define additional uncached regions +#ifndef CFG_DWC2_MEM_UNCACHED_REGIONS +#define CFG_DWC2_MEM_UNCACHED_REGIONS +#endif + +static mem_region_t uncached_regions[] = { + // DTCM (although USB DMA can't transfer to/from DTCM) +#if CFG_TUSB_MCU == OPT_MCU_STM32H7 + {.start = 0x20000000, .end = 0x2001FFFF}, +#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS + // DTCM (although USB DMA can't transfer to/from DTCM) + {.start = 0x20000000, .end = 0x2002FFFF}, +#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 + // DTCM + {.start = 0x20000000, .end = 0x2000FFFF}, +#else +#error "Cache maintenance is not supported yet" +#endif + CFG_DWC2_MEM_UNCACHED_REGIONS +}; + +TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { + if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) { + size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE; + } + return size; +} + +TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) { + for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) { + if (addr >= uncached_regions[i].start && addr <= uncached_regions[i].end) + return false; + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); + } + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (is_cache_mem(addr32)) { + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} +#endif + #ifdef __cplusplus } #endif diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 257fa2833..6b48c2346 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; } -#if CFG_TUH_MEM_DCACHE_ENABLE +#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE bool hcd_dcache_clean(const void* addr, uint32_t data_size) { TU_VERIFY(addr && data_size); return dwc2_dcache_clean(addr, data_size); -- cgit v1.3.1 From e19ff3ecae3b5a04756749a3d8496e6284f37d85 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 13 Jun 2025 13:17:41 +0200 Subject: Add cache line size alignment to buffer macro Signed-off-by: HiFiPhile --- src/common/tusb_types.h | 12 ++++++------ src/tusb_option.h | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index fd7f01b67..2099e1af8 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -36,39 +36,39 @@ #endif //------------- Device DCache declaration -------------// -#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \ +#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \ (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) // Declare an endpoint buffer with uint8_t[size] #define TUD_EPBUF_DEF(_name, _size) \ union { \ CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ - uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ + TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ } // Declare an endpoint buffer with a type #define TUD_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUD_MEM_ALIGN _type _name; \ - uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ + TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ } //------------- Host DCache declaration -------------// -#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \ +#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \ (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size)) // Declare an endpoint buffer with uint8_t[size] #define TUH_EPBUF_DEF(_name, _size) \ union { \ CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \ - uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ + TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ } // Declare an endpoint buffer with a type #define TUH_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUH_MEM_ALIGN _type _name; \ - uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ + TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ } diff --git a/src/tusb_option.h b/src/tusb_option.h index cca6096c6..42c2e650f 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -465,6 +465,13 @@ #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif +#if CFG_TUD_MEM_DCACHE_ENABLE && \ + (CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS)) + #define TUD_EPBUF_DCACHE_ALIGNED 1 +#else + #define TUD_EPBUF_DCACHE_ALIGNED 0 +#endif + #ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 #endif @@ -584,6 +591,13 @@ #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif +#if CFG_TUH_MEM_DCACHE_ENABLE && \ + (CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS)) + #define TUH_EPBUF_DCACHE_ALIGNED 1 +#else + #define TUH_EPBUF_DCACHE_ALIGNED 0 +#endif + //------------- CLASS -------------// #ifndef CFG_TUH_HUB -- cgit v1.3.1 From ea02e929b4daafb28be30b08609a6f68f64e2a0d Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 13 Jun 2025 18:44:05 +0200 Subject: audio: buffer macro update Signed-off-by: HiFiPhile --- src/class/audio/audio_device.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 11a3d4a73..dc45a72bc 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -109,14 +109,14 @@ // Put swap buffer in USB section only if necessary #if USE_LINEAR_BUFFER - #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4) + #define IN_SW_BUF_MEM_ATTR #else - #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN + #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION #endif #if USE_LINEAR_BUFFER - #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4) + #define OUT_SW_BUF_MEM_ATTR #else - #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN + #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION #endif // EP IN software buffers and mutexes -- cgit v1.3.1 From 76a6834659e50f50bfff39febb62ec67be25d581 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 2 Jun 2024 14:04:54 +0200 Subject: USBD: introduce xfer_isr. --- src/device/usbd.c | 35 ++++++++++++++++++++++++++++++++++- src/device/usbd_pvt.h | 1 + 2 files changed, 35 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index 6e5fcf3b6..ae18792c5 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -163,6 +163,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = cdcd_open, .control_xfer_cb = cdcd_control_xfer_cb, .xfer_cb = cdcd_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -176,6 +177,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = mscd_open, .control_xfer_cb = mscd_control_xfer_cb, .xfer_cb = mscd_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -189,6 +191,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = hidd_open, .control_xfer_cb = hidd_control_xfer_cb, .xfer_cb = hidd_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -202,6 +205,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = audiod_open, .control_xfer_cb = audiod_control_xfer_cb, .xfer_cb = audiod_xfer_cb, + .xfer_isr = NULL, .sof = audiod_sof_isr }, #endif @@ -215,6 +219,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = videod_open, .control_xfer_cb = videod_control_xfer_cb, .xfer_cb = videod_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -228,6 +233,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .reset = midid_reset, .control_xfer_cb = midid_control_xfer_cb, .xfer_cb = midid_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -241,6 +247,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = vendord_open, .control_xfer_cb = tud_vendor_control_xfer_cb, .xfer_cb = vendord_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -254,6 +261,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = usbtmcd_open_cb, .control_xfer_cb = usbtmcd_control_xfer_cb, .xfer_cb = usbtmcd_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -267,6 +275,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = dfu_rtd_open, .control_xfer_cb = dfu_rtd_control_xfer_cb, .xfer_cb = NULL, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -280,6 +289,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = dfu_moded_open, .control_xfer_cb = dfu_moded_control_xfer_cb, .xfer_cb = NULL, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -293,7 +303,8 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = netd_open, .control_xfer_cb = netd_control_xfer_cb, .xfer_cb = netd_xfer_cb, - .sof = NULL, + .xfer_isr = NULL, + .sof = NULL, }, #endif @@ -306,6 +317,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = btd_open, .control_xfer_cb = btd_control_xfer_cb, .xfer_cb = btd_xfer_cb, + .xfer_isr = NULL, .sof = NULL }, #endif @@ -1231,6 +1243,27 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) send = true; break; + case DCD_EVENT_XFER_COMPLETE: + { + send = true; + // Invoke the class callback associated with the endpoint address + uint8_t const ep_addr = event->xfer_complete.ep_addr; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const ep_dir = tu_edpt_dir(ep_addr); + + if(epnum > 0) { + usbd_class_driver_t const* driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]); + + if (driver && driver->xfer_isr) { + _usbd_dev.ep_status[epnum][ep_dir].busy = 0; + _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; + + send = !driver->xfer_isr(event->rhport, ep_addr, (xfer_result_t) event->xfer_complete.result, event->xfer_complete.len); + } + } + break; + } + default: send = true; break; diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 5c6f9dbee..40622be66 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -57,6 +57,7 @@ typedef struct { uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len); bool (* control_xfer_cb ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); + bool (* xfer_isr ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); // optional void (* sof ) (uint8_t rhport, uint32_t frame_count); // optional } usbd_class_driver_t; -- cgit v1.3.1 From eed294fbb58257f56b0fb59284624e50f43fa8a4 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 14 Jun 2025 19:39:02 +0200 Subject: audio: move ISO transfers into xfer_isr Signed-off-by: HiFiPhile --- src/class/audio/audio_device.c | 154 ++++++++++++++++------------------------- src/class/audio/audio_device.h | 13 ++-- src/device/usbd.c | 2 +- 3 files changed, 67 insertions(+), 102 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 11a3d4a73..4c8a69ee1 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -371,35 +371,19 @@ typedef struct //--------------------------------------------------------------------+ #if CFG_TUD_AUDIO_ENABLE_EP_IN -TU_ATTR_WEAK bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) { +TU_ATTR_WEAK bool tud_audio_tx_done_isr(uint8_t rhport, uint16_t n_bytes_sent, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) { (void) rhport; + (void) n_bytes_sent; (void) func_id; (void) ep_in; (void) cur_alt_setting; return true; } -TU_ATTR_WEAK bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting) { - (void) rhport; - (void) n_bytes_copied; - (void) func_id; - (void) ep_in; - (void) cur_alt_setting; - return true; -} #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT -TU_ATTR_WEAK bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) { - (void) rhport; - (void) n_bytes_received; - (void) func_id; - (void) ep_out; - (void) cur_alt_setting; - return true; -} - -TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) { +TU_ATTR_WEAK bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting) { (void) rhport; (void) n_bytes_received; (void) func_id; @@ -410,10 +394,6 @@ TU_ATTR_WEAK bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_byte #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP -TU_ATTR_WEAK void tud_audio_fb_done_cb(uint8_t func_id) { - (void) func_id; -} - TU_ATTR_WEAK void tud_audio_feedback_params_cb(uint8_t func_id, uint8_t alt_itf, audio_feedback_params_t *feedback_param) { (void) func_id; (void) alt_itf; @@ -433,7 +413,7 @@ TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func #endif #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP -TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport) { +TU_ATTR_WEAK void tud_audio_int_xfer_cb(uint8_t rhport) { (void) rhport; } #endif @@ -509,11 +489,11 @@ TU_ATTR_WEAK bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_reque tu_static CFG_TUD_MEM_SECTION audiod_function_t _audiod_fct[CFG_TUD_AUDIO]; #if CFG_TUD_AUDIO_ENABLE_EP_OUT -static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received); +static bool audiod_rx_xfer_isr(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received); #endif #if CFG_TUD_AUDIO_ENABLE_EP_IN -static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio); +static bool audiod_tx_xfer_isr(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_sent); #endif static bool audiod_get_interface(uint8_t rhport, tusb_control_request_t const *p_request); @@ -570,18 +550,13 @@ tu_fifo_t *tud_audio_n_get_ep_out_ff(uint8_t func_id) { return NULL; } -// This function is called once an audio packet is received by the USB and is responsible for putting data from USB memory into EP_OUT_FIFO. -static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t n_bytes_received) { - uint8_t idxItf = 0; +static bool audiod_rx_xfer_isr(uint8_t rhport, audiod_function_t* audio, uint16_t n_bytes_received) { + uint8_t idxItf; uint8_t const *dummy2; - uint8_t idx_audio_fct = 0; - idx_audio_fct = audiod_get_audio_fct_idx(audio); + uint8_t idx_audio_fct = audiod_get_audio_fct_idx(audio); TU_VERIFY(audiod_get_AS_interface_index(audio->ep_out_as_intf_num, audio, &idxItf, &dummy2)); - // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO - TU_VERIFY(tud_audio_rx_done_pre_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf])); - #if USE_LINEAR_BUFFER_RX // Data currently is in linear buffer, copy into EP OUT FIFO TU_VERIFY(tu_fifo_write_n(&audio->ep_out_ff, audio->lin_buf_out, n_bytes_received)); @@ -599,8 +574,8 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t } #endif - // Call a weak callback here - a possibility for user to get informed decoding was completed - TU_VERIFY(tud_audio_rx_done_post_read_cb(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf])); + // Call a weak callback here - a possibility for user to get informed an audio packet was received and data gets now loaded into EP FIFO + TU_VERIFY(tud_audio_rx_done_isr(rhport, n_bytes_received, idx_audio_fct, audio->ep_out, audio->alt_setting[idxItf])); return true; } @@ -613,17 +588,6 @@ static bool audiod_rx_done_cb(uint8_t rhport, audiod_function_t *audio, uint16_t #if CFG_TUD_AUDIO_ENABLE_EP_IN -/** - * \brief Write data to EP in buffer - * - * Write data to buffer. If it is full, new data can be inserted once a transmit was scheduled. See audiod_tx_done_cb(). - * If TX FIFOs are used, this function is not available in order to not let the user mess up the encoding process. - * - * \param[in] func_id: Index of audio function interface - * \param[in] data: Pointer to data array to be copied from - * \param[in] len: # of array elements to copy - * \return Number of bytes actually written - */ uint16_t tud_audio_n_write(uint8_t func_id, const void *data, uint16_t len) { TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); return tu_fifo_write_n(&_audiod_fct[func_id].ep_in_ff, data, len); @@ -640,9 +604,7 @@ tu_fifo_t *tud_audio_n_get_ep_in_ff(uint8_t func_id) { return NULL; } -// This function is called once a transmit of an audio packet was successfully completed. Here, we encode samples and place it in IN EP's buffer for next transmission. -// n_bytes_copied - Informs caller how many bytes were loaded. In case n_bytes_copied = 0, a ZLP is scheduled to inform host no data is available for current frame. -static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { +static bool audiod_tx_xfer_isr(uint8_t rhport, audiod_function_t * audio, uint16_t n_bytes_sent) { uint8_t idxItf; uint8_t const *dummy2; @@ -652,15 +614,11 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { // Only send something if current alternate interface is not 0 as in this case nothing is to be sent due to UAC2 specifications if (audio->alt_setting[idxItf] == 0) return false; - // Call a weak callback here - a possibility for user to get informed former TX was completed and data gets now loaded into EP in buffer (in case FIFOs are used) or - // if no FIFOs are used the user may use this call back to load its data into the EP IN buffer by use of tud_audio_n_write_ep_in_buffer(). - TU_VERIFY(tud_audio_tx_done_pre_load_cb(rhport, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf])); - // Send everything in ISO EP FIFO uint16_t n_bytes_tx; #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL - // packet_sz_tx is based on total packet size + // packet_sz_tx is based on total packet size, here we want size for each support buffer. n_bytes_tx = audiod_tx_packet_size(audio->packet_sz_tx, tu_fifo_count(&audio->ep_in_ff), audio->ep_in_ff.depth, audio->ep_in_sz); #else n_bytes_tx = tu_min16(tu_fifo_count(&audio->ep_in_ff), audio->ep_in_sz);// Limit up to max packet size, more can not be done for ISO @@ -673,8 +631,8 @@ static bool audiod_tx_done_cb(uint8_t rhport, audiod_function_t *audio) { TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_in, &audio->ep_in_ff, n_bytes_tx)); #endif - // Call a weak callback here - a possibility for user to get informed former TX was completed and how many bytes were loaded for the next frame - TU_VERIFY(tud_audio_tx_done_post_load_cb(rhport, n_bytes_tx, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf])); + // Call a weak callback here - a possibility for user to get informed former TX was completed and data gets now loaded into EP in buffer + TU_VERIFY(tud_audio_tx_done_isr(rhport, n_bytes_sent, idx_audio_fct, audio->ep_in, audio->alt_setting[idxItf])); return true; } @@ -1227,8 +1185,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p usbd_edpt_clear_stall(rhport, ep_addr); #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00)// Check if usage is data EP - { + // Check if usage is data EP + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00) { // Save address audio->ep_in = ep_addr; audio->ep_in_as_intf_num = itf; @@ -1238,15 +1196,19 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p #if CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL audiod_parse_flow_control_params(audio, p_desc_parse_for_params); #endif - // Schedule first transmit if alternate interface is not zero i.e. streaming is disabled - in case no sample data is available a ZLP is loaded - // It is necessary to trigger this here since the refill is done with an RX FIFO empty interrupt which can only trigger if something was in there - TU_VERIFY(audiod_tx_done_cb(rhport, &_audiod_fct[func_id])); + // Schedule first transmit if alternate interface is not zero, as sample data is available a ZLP is loaded + #if USE_LINEAR_BUFFER_TX + TU_VERIFY(usbd_edpt_xfer(rhport, audio->ep_in, audio->lin_buf_in, 0)); + #else + // Send everything in ISO EP FIFO + TU_VERIFY(usbd_edpt_xfer_fifo(rhport, audio->ep_in, &audio->ep_in_ff, 0)); + #endif } #endif// CFG_TUD_AUDIO_ENABLE_EP_IN #if CFG_TUD_AUDIO_ENABLE_EP_OUT - if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT)// Checking usage not necessary - { + // Checking usage not necessary + if (tu_edpt_dir(ep_addr) == TUSB_DIR_OUT) { // Save address audio->ep_out = ep_addr; audio->ep_out_as_intf_num = itf; @@ -1261,10 +1223,12 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p } #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1)// Check if usage is explicit data feedback - { + // Check if usage is explicit data feedback + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 1) { audio->ep_fb = ep_addr; audio->feedback.frame_shift = desc_ep->bInterval - 1; + // Schedule first feedback transmit + audiod_fb_send(audio); } #endif #endif// CFG_TUD_AUDIO_ENABLE_EP_OUT @@ -1507,12 +1471,11 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 (void) result; (void) xferred_bytes; + #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP // Search for interface belonging to given end point address and proceed as required for (uint8_t func_id = 0; func_id < CFG_TUD_AUDIO; func_id++) { audiod_function_t *audio = &_audiod_fct[func_id]; -#if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP - // Data transmission of control interrupt finished if (audio->ep_int == ep_addr) { // According to USB2 specification, maximum payload of interrupt EP is 8 bytes on low speed, 64 bytes on full speed, and 1024 bytes on high speed (but only if an alternate interface other than 0 is used - see specification p. 49) @@ -1522,16 +1485,34 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 // I assume here, that things above are handled by PHY // All transmission is done - what remains to do is to inform job was completed - tud_audio_int_done_cb(rhport); + tud_audio_int_xfer_cb(rhport); return true; } -#endif + } + #else + (void) rhport; + (void) ep_addr; + #endif + + return false; +} + +bool audiod_xfer_isr(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) +{ + (void) result; + (void) xferred_bytes; + + // Search for interface belonging to given end point address and proceed as required + for (uint8_t func_id = 0; func_id < CFG_TUD_AUDIO; func_id++) + { + audiod_function_t* audio = &_audiod_fct[func_id]; #if CFG_TUD_AUDIO_ENABLE_EP_IN // Data transmission of audio packet finished - if (audio->ep_in == ep_addr && audio->alt_setting != 0) { + if (audio->ep_in == ep_addr && audio->alt_setting != 0) + { // USB 2.0, section 5.6.4, third paragraph, states "An isochronous endpoint must specify its required bus access period. However, an isochronous endpoint must be prepared to handle poll rates faster than the one specified." // That paragraph goes on to say "An isochronous IN endpoint must return a zero-length packet whenever data is requested at a faster interval than the specified interval and data is not available." // This can only be solved reliably if we load a ZLP after every IN transmission since we can not say if the host requests samples earlier than we declared! Once all samples are collected we overwrite the loaded ZLP. @@ -1541,32 +1522,25 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 // This is the only place where we can fill something into the EPs buffer! // Load new data - TU_VERIFY(audiod_tx_done_cb(rhport, audio)); - - // Transmission of ZLP is done by audiod_tx_done_cb() + audiod_tx_xfer_isr(rhport, audio, (uint16_t) xferred_bytes); return true; } #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT - // New audio packet received - if (audio->ep_out == ep_addr) { - TU_VERIFY(audiod_rx_done_cb(rhport, audio, (uint16_t) xferred_bytes)); + if (audio->ep_out == ep_addr) + { + audiod_rx_xfer_isr(rhport, audio, (uint16_t) xferred_bytes); return true; } - - #if CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP // Transmission of feedback EP finished if (audio->ep_fb == ep_addr) { - tud_audio_fb_done_cb(func_id); - // Schedule a transmit with the new value if EP is not busy - if (usbd_edpt_claim(rhport, audio->ep_fb)) { - // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent - return audiod_fb_send(audio); - } + // Schedule next transmission - value is changed bytud_audio_n_fb_set() in the meantime or the old value gets sent + audiod_fb_send(audio); + return true; } #endif #endif @@ -1627,11 +1601,6 @@ static void audiod_fb_fifo_count_update(audiod_function_t *audio, uint16_t lvl_n if (feedback > audio->feedback.max_value) feedback = audio->feedback.max_value; if (feedback < audio->feedback.min_value) feedback = audio->feedback.min_value; audio->feedback.value = feedback; - - // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value - if (usbd_edpt_claim(audio->rhport, audio->ep_fb)) { - audiod_fb_send(audio); - } } uint32_t tud_audio_feedback_update(uint8_t func_id, uint32_t cycles) { @@ -1673,11 +1642,6 @@ bool tud_audio_n_fb_set(uint8_t func_id, uint32_t feedback) { _audiod_fct[func_id].feedback.value = feedback; - // Schedule a transmit with the new value if EP is not busy - this triggers repetitive scheduling of the feedback value - if (usbd_edpt_claim(_audiod_fct[func_id].rhport, _audiod_fct[func_id].ep_fb)) { - return audiod_fb_send(&_audiod_fct[func_id]); - } - return true; } #endif diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 603535b2a..e5724fc6a 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -280,18 +280,18 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req //--------------------------------------------------------------------+ #if CFG_TUD_AUDIO_ENABLE_EP_IN -bool tud_audio_tx_done_pre_load_cb(uint8_t rhport, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting); -bool tud_audio_tx_done_post_load_cb(uint8_t rhport, uint16_t n_bytes_copied, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting); +// Callback in ISR context, this function is called once a transmit of an audio packet was successfully completed. +// Normally this function is not needed, since the data transfer should be driven by audio clock (i.e. I2S clock), call tud_audio_write() in I2S receive callback. +bool tud_audio_tx_done_isr(uint8_t rhport, uint16_t n_bytes_sent, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting); #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT -bool tud_audio_rx_done_pre_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting); -bool tud_audio_rx_done_post_read_cb(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting); +// Callback in ISR context, this function is called once a receive of an audio packet was successfully completed. +// Normally this function is not needed, since the data transfer should be driven by audio clock (i.e. I2S clock), call tud_audio_read() in I2S transmit callback. +bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting); #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP -void tud_audio_fb_done_cb(uint8_t func_id); - // Note about feedback calculation // @@ -487,6 +487,7 @@ void audiod_reset (uint8_t rhport); uint16_t audiod_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len); bool audiod_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); bool audiod_xfer_cb (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes); +bool audiod_xfer_isr (uint8_t rhport, uint8_t edpt_addr, xfer_result_t result, uint32_t xferred_bytes); void audiod_sof_isr (uint8_t rhport, uint32_t frame_count); #ifdef __cplusplus diff --git a/src/device/usbd.c b/src/device/usbd.c index ae18792c5..63519dcfd 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -205,7 +205,7 @@ tu_static usbd_class_driver_t const _usbd_driver[] = { .open = audiod_open, .control_xfer_cb = audiod_control_xfer_cb, .xfer_cb = audiod_xfer_cb, - .xfer_isr = NULL, + .xfer_isr = audiod_xfer_isr, .sof = audiod_sof_isr }, #endif -- cgit v1.3.1 From 1a36a1c1afefdf7e7d2def73d5fc64703aabe728 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 14 Jun 2025 16:53:18 +0200 Subject: audio: remove FIFO mutex, as audio streaming is always single producer single consumer Signed-off-by: HiFiPhile --- src/class/audio/audio_device.c | 46 ++---------------------------------------- 1 file changed, 2 insertions(+), 44 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 4c8a69ee1..290561a27 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -119,7 +119,7 @@ #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN #endif -// EP IN software buffers and mutexes +// EP IN software buffers #if CFG_TUD_AUDIO_ENABLE_EP_IN tu_static IN_SW_BUF_MEM_ATTR struct { #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 @@ -132,18 +132,6 @@ tu_static IN_SW_BUF_MEM_ATTR struct { TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ); #endif } ep_in_sw_buf; - - #if CFG_FIFO_MUTEX - #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_in_ff_mutex_wr_1; - #endif - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_in_ff_mutex_wr_2; - #endif - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_in_ff_mutex_wr_3; - #endif - #endif #endif// CFG_TUD_AUDIO_ENABLE_EP_IN // Linear buffer TX in case: @@ -162,7 +150,7 @@ tu_static CFG_TUD_MEM_SECTION struct { } lin_buf_in; #endif// CFG_TUD_AUDIO_ENABLE_EP_IN && USE_LINEAR_BUFFER -// EP OUT software buffers and mutexes +// EP OUT software buffers #if CFG_TUD_AUDIO_ENABLE_EP_OUT tu_static OUT_SW_BUF_MEM_ATTR struct { #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 @@ -175,18 +163,6 @@ tu_static OUT_SW_BUF_MEM_ATTR struct { TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ); #endif } ep_out_sw_buf; - - #if CFG_FIFO_MUTEX - #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_rd_1; - #endif - #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_rd_2; - #endif - #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_rd_3; - #endif - #endif #endif// CFG_TUD_AUDIO_ENABLE_EP_OUT // Linear buffer RX in case: @@ -751,25 +727,16 @@ void audiod_init(void) { #if CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ > 0 case 0: tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_1, CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_1), NULL); - #endif break; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ > 0 case 1: tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_2, CFG_TUD_AUDIO_FUNC_2_EP_IN_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_2), NULL); - #endif break; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ > 0 case 2: tu_fifo_config(&audio->ep_in_ff, ep_in_sw_buf.buf_3, CFG_TUD_AUDIO_FUNC_3_EP_IN_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_in_ff, osal_mutex_create(&ep_in_ff_mutex_wr_3), NULL); - #endif break; #endif } @@ -803,25 +770,16 @@ void audiod_init(void) { #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 case 0: tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_1)); - #endif break; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 case 1: tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_2)); - #endif break; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 case 2: tu_fifo_config(&audio->ep_out_ff, ep_out_sw_buf.buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ, 1, true); - #if CFG_FIFO_MUTEX - tu_fifo_config_mutex(&audio->ep_out_ff, NULL, osal_mutex_create(&ep_out_ff_mutex_rd_3)); - #endif break; #endif } -- cgit v1.3.1 From d4abf43f226b5594c935c60c38d05a90359763e1 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 17 Jun 2025 22:16:13 +0700 Subject: add common cdch_process_set_config() to safely complete set_config() when it failed. driver_process_set_config() also pass drv index with user_data --- examples/host/cdc_msc_hid/src/cdc_app.c | 13 +- src/class/cdc/cdc_host.c | 887 ++++++++++++++++---------------- 2 files changed, 453 insertions(+), 447 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index e68ec383b..6f4433f22 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -31,8 +31,7 @@ static size_t get_console_inputs(uint8_t* buf, size_t bufsize) { size_t count = 0; while (count < bufsize) { int ch = board_getchar(); - if (ch <= 0) break; - + if (ch <= 0) { break; } buf[count] = (uint8_t) ch; count++; } @@ -69,10 +68,12 @@ void tuh_cdc_rx_cb(uint8_t idx) { uint32_t const bufsize = sizeof(buf) - 1; // forward cdc interfaces -> console - uint32_t count = tuh_cdc_read(idx, buf, bufsize); - buf[count] = 0; - - printf("%s", (char*) buf); + const uint32_t count = tuh_cdc_read(idx, buf, bufsize); + if (count) { + buf[count] = 0; + printf("%s", (char*) buf); + fflush(stdout); + } } // Invoked when a device with CDC interface is mounted diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 5d5da9796..b6e9cb297 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -52,17 +52,6 @@ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) #define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %d", VAL) -// assert and set config complete -#define TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) \ - do { \ - if (!(_cond)) { _MESS_FAILED(); TU_BREAKPOINT(); set_config_complete(idx, _itf_offset, false); } \ - } while(0) - -#define TU_ASSERT_COMPLETE_1ARGS(_cond) TU_ASSERT_COMPLETE_DEFINE(_cond, 0) -#define TU_ASSERT_COMPLETE_2ARGS(_cond, _itf_offset) TU_ASSERT_COMPLETE_DEFINE(_cond, _itf_offset) - -#define TU_ASSERT_COMPLETE(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_COMPLETE_2ARGS, TU_ASSERT_COMPLETE_1ARGS, _dummy)(__VA_ARGS__) - // handle line control defines #if defined(CFG_TUH_CDC_LINE_CONTROL_ON_ENUM) && \ (defined(CFG_TUH_CDC_DTR_CONTROL_ON_ENUM) || defined(CFG_TUH_CDC_RTS_CONTROL_ON_ENUM)) @@ -142,9 +131,14 @@ CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; // Serial Driver //--------------------------------------------------------------------+ +// for process_set_config user_data: idx (byte1) and state (byte0) +#define PROCESS_CONFIG_STATE(_idx, _state) tu_u16(_idx, _state) + +static void cdch_process_set_config(tuh_xfer_t *xfer); + //------------- ACM prototypes -------------// static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static void acm_process_config(tuh_xfer_t * xfer); +static bool acm_process_set_config(tuh_xfer_t * xfer); static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -159,7 +153,7 @@ static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; #endif static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); -static void ftdi_process_config(tuh_xfer_t * xfer); +static bool ftdi_proccess_set_config(tuh_xfer_t * xfer); static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -172,7 +166,7 @@ static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST}; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static void cp210x_process_config(tuh_xfer_t * xfer); +static bool cp210x_process_set_config(tuh_xfer_t * xfer); static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -185,7 +179,7 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static void ch34x_process_config(tuh_xfer_t * xfer); +static bool ch34x_process_set_config(tuh_xfer_t *xfer); static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -201,7 +195,7 @@ static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = {PL2303_TYPE CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static void pl2303_process_config(tuh_xfer_t * xfer); +static bool pl2303_process_set_config(tuh_xfer_t *xfer); static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -236,7 +230,7 @@ typedef struct { uint16_t const (*vid_pid_list)[2]; uint16_t const vid_pid_count; bool (*const open)(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); - void (*const process_set_config)(tuh_xfer_t * xfer); + bool (*const process_set_config)(tuh_xfer_t * xfer); bool (*const set_control_line_state)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_baudrate)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); bool (*const set_data_format)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -252,7 +246,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_list = NULL, .vid_pid_count = 0, .open = acm_open, - .process_set_config = acm_process_config, + .process_set_config = acm_process_set_config, .set_control_line_state = acm_set_control_line_state, .set_baudrate = acm_set_baudrate, .set_data_format = acm_set_data_format, @@ -267,7 +261,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_list = ftdi_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ftdi_vid_pid_list), .open = ftdi_open, - .process_set_config = ftdi_process_config, + .process_set_config = ftdi_proccess_set_config, .set_control_line_state = ftdi_set_modem_ctrl, .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, @@ -283,7 +277,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_list = cp210x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(cp210x_vid_pid_list), .open = cp210x_open, - .process_set_config = cp210x_process_config, + .process_set_config = cp210x_process_set_config, .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, .set_data_format = cp210x_set_data_format, @@ -299,7 +293,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_list = ch34x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ch34x_vid_pid_list), .open = ch34x_open, - .process_set_config = ch34x_process_config, + .process_set_config = ch34x_process_set_config, .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, .set_data_format = ch34x_set_data_format, @@ -315,7 +309,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .vid_pid_list = pl2303_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(pl2303_vid_pid_list), .open = pl2303_open, - .process_set_config = pl2303_process_config, + .process_set_config = pl2303_process_set_config, .set_control_line_state = pl2303_set_modem_ctrl, .set_baudrate = pl2303_set_baudrate, .set_data_format = pl2303_set_data_format, @@ -378,9 +372,8 @@ static bool open_ep_stream_pair(cdch_interface_t * p_cdc , tusb_desc_endpoint_t uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num) { for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { const cdch_interface_t * p_cdc = &cdch_data[i]; - if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) return i; + if (p_cdc->daddr == daddr && p_cdc->bInterfaceNumber == itf_num) { return i; } } - return TUSB_INDEX_INVALID_8; } @@ -642,18 +635,18 @@ bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uin } bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - cdc_line_control_state_t const line_state = { .rts = rts_state, .dtr = p_cdc->line_state.dtr }; + cdc_line_control_state_t const line_state = {.rts = rts_state, .dtr = p_cdc->line_state.dtr}; return tuh_cdc_set_control_line_state_u(idx, line_state, complete_cb, user_data); } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set baudrate %lu", baudrate); - cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.bit_rate = baudrate; @@ -669,12 +662,12 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set data format %u%c%s", data_bits, CDC_LINE_CODING_PARITY_CHAR(parity), CDC_LINE_CODING_STOP_BITS_TEXT(stop_bits)); - cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding.stop_bits = stop_bits; p_cdc->requested_line_coding.parity = parity; @@ -692,15 +685,15 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin return ret; } -bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const * line_coding, +bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set line coding %lu %u%c%s", line_coding->bit_rate, line_coding->data_bits, CDC_LINE_CODING_PARITY_CHAR(line_coding->parity), CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); - cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; + cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_coding = *line_coding; @@ -722,8 +715,8 @@ bool cdch_init(void) { TU_LOG_DRV("sizeof(cdch_interface_t) = %u\r\n", sizeof(cdch_interface_t)); tu_memclr(cdch_data, sizeof(cdch_data)); for (size_t i = 0; i < CFG_TUH_CDC; i++) { - cdch_interface_t* p_cdc = &cdch_data[i]; - cdch_epbuf_t* epbuf = &cdch_epbuf[i]; + cdch_interface_t *p_cdc = &cdch_data[i]; + cdch_epbuf_t *epbuf = &cdch_epbuf[i]; tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, epbuf->tx, CFG_TUH_CDC_TX_EPSIZE); @@ -738,7 +731,7 @@ bool cdch_init(void) { bool cdch_deinit(void) { for (size_t i = 0; i < CFG_TUH_CDC; i++) { - cdch_interface_t* p_cdc = &cdch_data[i]; + cdch_interface_t *p_cdc = &cdch_data[i]; tu_edpt_stream_deinit(&p_cdc->stream.tx); tu_edpt_stream_deinit(&p_cdc->stream.rx); } @@ -747,7 +740,7 @@ bool cdch_deinit(void) { void cdch_close(uint8_t daddr) { for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { - cdch_interface_t * p_cdc = &cdch_data[idx]; + cdch_interface_t *p_cdc = &cdch_data[idx]; if (p_cdc->daddr == daddr) { TU_LOG_P_CDC("close"); @@ -770,7 +763,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t TU_VERIFY(event == XFER_RESULT_SUCCESS); uint8_t const idx = get_idx_by_ep_addr(daddr, ep_addr); - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc); if (ep_addr == p_cdc->stream.tx.ep_addr) { @@ -779,31 +772,36 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t tuh_cdc_tx_complete_cb(idx); } - if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) { + if (0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx)) { // If there is no data left, a ZLP should be sent if: // - xferred_bytes is multiple of EP Packet size and not zero tu_edpt_stream_write_zlp_if_needed(daddr, &p_cdc->stream.tx, xferred_bytes); } } else if (ep_addr == p_cdc->stream.rx.ep_addr) { #if CFG_TUH_CDC_FTDI - if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI && xferred_bytes > 2) { + if (p_cdc->serial_drid == SERIAL_DRIVER_FTDI) { // FTDI reserve 2 bytes for status // uint8_t status[2] = {p_cdc->stream.rx.ep_buf[0], p_cdc->stream.rx.ep_buf[1]}; - tu_edpt_stream_read_xfer_complete_with_buf(&p_cdc->stream.rx, p_cdc->stream.rx.ep_buf+2, xferred_bytes-2); - }else + if (xferred_bytes > 2) { + tu_edpt_stream_read_xfer_complete_with_buf(&p_cdc->stream.rx, p_cdc->stream.rx.ep_buf + 2, xferred_bytes - 2); + + if (tuh_cdc_rx_cb) { + tuh_cdc_rx_cb(idx); // invoke receive callback + } + } + } else #endif { tu_edpt_stream_read_xfer_complete(&p_cdc->stream.rx, xferred_bytes); - } - // invoke receive callback - if (tuh_cdc_rx_cb) { - tuh_cdc_rx_cb(idx); + if (tuh_cdc_rx_cb) { + tuh_cdc_rx_cb(idx); // invoke receive callback + } } // prepare for next transfer if needed tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); - }else if ( ep_addr == p_cdc->ep_notif ) { + } else if (ep_addr == p_cdc->ep_notif) { // TODO handle notification endpoint } else { TU_ASSERT(false); @@ -816,7 +814,7 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t // Enumeration //--------------------------------------------------------------------+ -static bool open_ep_stream_pair(cdch_interface_t * p_cdc, tusb_desc_endpoint_t const * desc_ep) { +static bool open_ep_stream_pair(cdch_interface_t *p_cdc, tusb_desc_endpoint_t const *desc_ep) { for (size_t i = 0; i < 2; i++) { TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer); @@ -834,9 +832,9 @@ static bool open_ep_stream_pair(cdch_interface_t * p_cdc, tusb_desc_endpoint_t c return true; } -bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { +bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; - cdch_serial_driver_t const * driver_detected = NULL; + cdch_serial_driver_t const *driver_detected = NULL; // For CDC: only support ACM subclass // Note: Protocol 0xFF can be RNDIS device @@ -849,7 +847,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { - cdch_serial_driver_t const * driver = &serial_drivers[dr]; + cdch_serial_driver_t const *driver = &serial_drivers[dr]; for (size_t i = 0; i < driver->vid_pid_count; i++) { if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { driver_detected = driver; @@ -865,7 +863,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ if (driver_detected) { TU_LOG_CDC("open", daddr, itf_desc->bInterfaceNumber, driver_detected->name); bool ret = driver_detected->open(daddr, itf_desc, max_len); -// TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); + // TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); return ret; } @@ -873,8 +871,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const * itf_ } static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); TU_LOG_P_CDC_BOOL("set config complete", success); if (success) { @@ -894,22 +892,32 @@ static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset); } +static void cdch_process_set_config(tuh_xfer_t *xfer) { + const uint8_t idx = tu_u32_byte1(xfer->user_data); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + + if (!serial_drivers[p_cdc->serial_drid].process_set_config(xfer)) { + const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; + set_config_complete(idx, itf_offset, false); + } +} + bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_P_CDC("set config"); // fake transfer to kick-off process_set_config() tuh_xfer_t xfer; - xfer.daddr = daddr; + xfer.daddr = daddr; xfer.result = XFER_RESULT_SUCCESS; - xfer.setup = &request; - xfer.user_data = 0; // initial state 0 - - serial_drivers[p_cdc->serial_drid].process_set_config(&xfer); + xfer.setup = &request; + xfer.user_data = PROCESS_CONFIG_STATE(idx, 0); // initial state 0 + cdch_process_set_config(&xfer); return true; } @@ -921,11 +929,11 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void acm_internal_control_complete(tuh_xfer_t * xfer) { +static void acm_internal_control_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC_BOOL("control complete", success); @@ -949,7 +957,7 @@ static void acm_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); tusb_control_request_t const request = { @@ -980,10 +988,10 @@ static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t c return true; } -static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm_capability.support_line_request); TU_VERIFY((p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8) || - p_cdc->requested_line_coding.data_bits == 16); + p_cdc->requested_line_coding.data_bits == 16); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -998,7 +1006,7 @@ static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete }; // use usbh enum buf to hold line coding since user line_coding variable does not live long enough - uint8_t * enum_buf = usbh_get_enum_buf(); + uint8_t *enum_buf = usbh_get_enum_buf(); memcpy(enum_buf, &p_cdc->requested_line_coding, sizeof(cdc_line_coding_t)); p_cdc->user_control_cb = complete_cb; @@ -1017,13 +1025,13 @@ static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete return true; } -static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; return acm_set_line_coding(p_cdc, complete_cb, user_data); } -static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool acm_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; @@ -1036,19 +1044,19 @@ static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb enum { CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, CONFIG_ACM_SET_LINE_CODING, - CONFIG_ACM_COMPLETE, + CONFIG_ACM_COMPLETE }; -static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { - uint8_t const * p_desc_end = ((uint8_t const *) itf_desc) + max_len; +static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { + uint8_t const *p_desc_end = ((uint8_t const *) itf_desc) + max_len; - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t *p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_ACM; //------------- Control Interface -------------// - uint8_t const * p_desc = tu_desc_next(itf_desc); + uint8_t const *p_desc = tu_desc_next(itf_desc); // Communication Functional Descriptors while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { @@ -1063,7 +1071,7 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint // Open notification endpoint of control interface if any if (itf_desc->bNumEndpoints == 1) { TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; TU_ASSERT(tuh_edpt_open(daddr, desc_ep)); p_cdc->ep_notif = desc_ep->bEndpointAddress; @@ -1084,31 +1092,31 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint return true; } -static void acm_process_config(tuh_xfer_t * xfer) { - uintptr_t const state = xfer->user_data; +static bool acm_process_set_config(tuh_xfer_t *xfer) { + const uint8_t state = (uint8_t) xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS, 1); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #ifdef LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(acm_set_control_line_state(p_cdc, acm_process_config, CONFIG_ACM_SET_LINE_CODING), 1); - break; - } + if (p_cdc->acm_capability.support_line_request) { + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_ACM_SET_LINE_CODING))); + break; + } #endif TU_ATTR_FALLTHROUGH; case CONFIG_ACM_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT_COMPLETE(acm_set_line_coding(p_cdc, acm_process_config, CONFIG_ACM_COMPLETE), 1); - break; - } + if (p_cdc->acm_capability.support_line_request) { + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(acm_set_line_coding(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_ACM_COMPLETE))); + break; + } #endif TU_ATTR_FALLTHROUGH; @@ -1118,9 +1126,10 @@ static void acm_process_config(tuh_xfer_t * xfer) { break; default: - set_config_complete(idx, 1, false); - break; + return false; // invalid state } + + return true; } //--------------------------------------------------------------------+ @@ -1128,14 +1137,14 @@ static void acm_process_config(tuh_xfer_t * xfer) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_FTDI -static bool ftdi_determine_type(cdch_interface_t * p_cdc); -static uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc); -static uint8_t ftdi_get_idx(tuh_xfer_t * xfer); +static bool ftdi_determine_type(cdch_interface_t *p_cdc); +static uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc); +static uint8_t ftdi_get_idx(tuh_xfer_t *xfer); //------------- Control Request -------------// // set request without data -static bool ftdi_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_t requesttype, +static bool ftdi_set_request(cdch_interface_t *p_cdc, uint8_t request, uint8_t requesttype, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType = requesttype, @@ -1167,37 +1176,36 @@ static int8_t ftdi_write_latency_timer(cdch_interface_t * p_cdc, uint16_t latenc } #endif -static inline bool ftdi_sio_reset(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ftdi_sio_reset(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ftdi_set_request(p_cdc, FTDI_SIO_RESET_REQUEST, FTDI_SIO_RESET_REQUEST_TYPE, FTDI_SIO_RESET_SIO, p_cdc->ftdi.channel, complete_cb, user_data); } -static bool ftdi_change_speed(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_change_speed(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint32_t index_value = ftdi_get_divisor(p_cdc); TU_VERIFY(index_value); uint16_t value = (uint16_t) index_value; uint16_t index = (uint16_t) (index_value >> 16); if (p_cdc->ftdi.channel) { - index = (uint16_t)((index << 8) | p_cdc->ftdi.channel); + index = (uint16_t) ((index << 8) | p_cdc->ftdi.channel); } return ftdi_set_request(p_cdc, FTDI_SIO_SET_BAUDRATE_REQUEST, FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE, value, index, complete_cb, user_data); } -static bool ftdi_set_data_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); - uint16_t value = (uint16_t) ( - (p_cdc->requested_line_coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 - (p_cdc->requested_line_coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding - (p_cdc->requested_line_coding.stop_bits & 0x3UL) << 11 ); // stop bits quantity is stored in bits 11-12, same coding - // not each FTDI supports 1.5 stop bits + uint16_t value = (uint16_t) ((p_cdc->requested_line_coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 + (p_cdc->requested_line_coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding + (p_cdc->requested_line_coding.stop_bits & 0x3UL) << 11); // stop bits quantity is stored in bits 11-12, same coding + // not each FTDI supports 1.5 stop bits return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, value, p_cdc->ftdi.channel, complete_cb, user_data); } -static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ftdi_update_mctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | (p_cdc->requested_line_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); @@ -1208,10 +1216,10 @@ static inline bool ftdi_update_mctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t com //------------- Driver API -------------// // internal control complete to update state such as line state, line_coding -static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { +static void ftdi_internal_control_complete(tuh_xfer_t *xfer) { uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC_BOOL("control complete", success); @@ -1238,24 +1246,24 @@ static void ftdi_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } -static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } -static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { +static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); uint8_t const itf_num = p_cdc->bInterfaceNumber; set_line_coding_stage1_complete(xfer, itf_num, ftdi_set_data_request, // control request function to set data format @@ -1272,7 +1280,7 @@ static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complet complete_cb, user_data); } -static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ftdi_update_mctrl(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); @@ -1293,19 +1301,19 @@ enum { CONFIG_FTDI_COMPLETE }; -static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len) { +static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint16_t max_len) { // FTDI Interface includes 1 vendor interface + 2 bulk endpoints TU_VERIFY(itf_desc->bInterfaceSubClass == 0xff && itf_desc->bInterfaceProtocol == 0xff && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2 * sizeof(tusb_desc_endpoint_t) <= max_len); - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t *p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_FTDI; // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); /* * NOTE: Some customers have programmed FT232R/FT245R devices @@ -1317,22 +1325,20 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uin return open_ep_stream_pair(p_cdc, desc_ep); } -static void ftdi_process_config(tuh_xfer_t * xfer) { - uintptr_t const state = xfer->user_data; +static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { + const uint8_t state = (uint8_t) xfer->user_data; uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); + cdch_interface_t *p_cdc = get_itf(idx); uint8_t const itf_num = p_cdc->bInterfaceNumber; + TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - switch(state) { - + switch (state) { // from here sequence overtaken from Linux Kernel function ftdi_port_probe() case CONFIG_FTDI_GET_DESC: // get device descriptor - p_cdc->user_control_cb = ftdi_process_config; // set once for whole process config - if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 - TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - ftdi_process_config, CONFIG_FTDI_DETERMINE_TYPE)); + if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 + TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_DETERMINE_TYPE))); break; } TU_ATTR_FALLTHROUGH; @@ -1340,66 +1346,67 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { case CONFIG_FTDI_DETERMINE_TYPE: // determine type if (itf_num == 0) { - TU_ASSERT_COMPLETE(ftdi_determine_type(p_cdc)); + TU_ASSERT(ftdi_determine_type(p_cdc)); } else { // other interfaces have same type as interface 0 uint8_t const idx_itf0 = tuh_cdc_itf_get_index(xfer->daddr, 0); - cdch_interface_t const * p_cdc_itf0 = get_itf(idx_itf0); - TU_ASSERT_COMPLETE(p_cdc_itf0); - if (p_cdc_itf0) { - p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type; - } + cdch_interface_t const *p_cdc_itf0 = get_itf(idx_itf0); + TU_ASSERT(p_cdc_itf0); + p_cdc->ftdi.chip_type = p_cdc_itf0->ftdi.chip_type; } TU_ATTR_FALLTHROUGH; case CONFIG_FTDI_WRITE_LATENCY: #ifdef CFG_TUH_CDC_FTDI_LATENCY - int8_t result = ftdi_write_latency_timer(p_cdc, CFG_TUH_CDC_FTDI_LATENCY, ftdi_process_config, - CONFIG_FTDI_SIO_RESET); - TU_ASSERT_COMPLETE(result != FTDI_FAIL); - if(result == FTDI_REQUESTED) { - break; - } // else FTDI_NOT_POSSIBLE => continue directly with next state + int8_t result = ftdi_write_latency_timer(p_cdc, CFG_TUH_CDC_FTDI_LATENCY, ftdi_process_config, + CONFIG_FTDI_SIO_RESET); + TU_ASSERT(result != FTDI_FAIL); + if (result == FTDI_REQUESTED) { + break; + }// else FTDI_NOT_POSSIBLE => continue directly with next state #endif TU_ATTR_FALLTHROUGH; - // from here sequence overtaken from Linux Kernel function ftdi_open() + // from here sequence overtaken from Linux Kernel function ftdi_open() case CONFIG_FTDI_SIO_RESET: - TU_ASSERT_COMPLETE(ftdi_sio_reset(p_cdc, ftdi_process_config, CONFIG_FTDI_SET_DATA)); + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_SET_DATA))); break; - // from here sequence overtaken from Linux Kernel function ftdi_set_termios() + // from here sequence overtaken from Linux Kernel function ftdi_set_termios() case CONFIG_FTDI_SET_DATA: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT_COMPLETE(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); - break; + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_SET_BAUDRATE))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_FTDI_SET_BAUDRATE: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - TU_ASSERT_COMPLETE(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); - break; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_FLOW_CONTROL))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_FTDI_FLOW_CONTROL: // disable flow control - TU_ASSERT_COMPLETE(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, - FTDI_SIO_DISABLE_FLOW_CTRL, p_cdc->ftdi.channel, - ftdi_process_config, CONFIG_FTDI_MODEM_CTRL)); + TU_ASSERT(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, FTDI_SIO_DISABLE_FLOW_CTRL, + p_cdc->ftdi.channel, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_MODEM_CTRL))); break; case CONFIG_FTDI_MODEM_CTRL: #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); - break; + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_COMPLETE))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_FTDI_COMPLETE: @@ -1407,15 +1414,15 @@ static void ftdi_process_config(tuh_xfer_t * xfer) { break; default: - TU_ASSERT_COMPLETE(false); - break; + return false; } + + return true; } //------------- Helper -------------// -static bool ftdi_determine_type(cdch_interface_t * p_cdc) -{ +static bool ftdi_determine_type(cdch_interface_t *p_cdc) { uint16_t const version = desc_dev->bcdDevice; uint8_t const itf_num = p_cdc->bInterfaceNumber; @@ -1527,28 +1534,27 @@ static bool ftdi_determine_type(cdch_interface_t * p_cdc) //} static uint32_t ftdi_232bm_baud_base_to_divisor(uint32_t baud, uint32_t base) { - uint8_t divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; + uint8_t divfrac[8] = {0, 3, 2, 4, 1, 5, 6, 7}; uint32_t divisor; /* divisor shifted 3 bits to the left */ uint32_t divisor3 = DIV_ROUND_CLOSEST(base, 2 * baud); divisor = divisor3 >> 3; - divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; + divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; /* Deal with special cases for highest baud rates. */ - if (divisor == 1) /* 1.0 */ + if (divisor == 1) /* 1.0 */ { divisor = 0; - else if (divisor == 0x4001) /* 1.5 */ + } else if (divisor == 0x4001) /* 1.5 */ { divisor = 1; + } return divisor; } -static inline uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) -{ - return ftdi_232bm_baud_base_to_divisor(baud, 48000000); +static inline uint32_t ftdi_232bm_baud_to_divisor(uint32_t baud) { + return ftdi_232bm_baud_base_to_divisor(baud, 48000000); } -static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, uint32_t base) -{ - static const unsigned char divfrac[8] = { 0, 3, 2, 4, 1, 5, 6, 7 }; +static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, uint32_t base) { + static const unsigned char divfrac[8] = {0, 3, 2, 4, 1, 5, 6, 7}; uint32_t divisor; uint32_t divisor3; @@ -1556,12 +1562,13 @@ static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, uint32_t base) divisor3 = DIV_ROUND_CLOSEST(8 * base, 10 * baud); divisor = divisor3 >> 3; - divisor |= (uint32_t)divfrac[divisor3 & 0x7] << 14; + divisor |= (uint32_t) divfrac[divisor3 & 0x7] << 14; /* Deal with special cases for highest baud rates. */ - if (divisor == 1) /* 1.0 */ + if (divisor == 1) /* 1.0 */ { divisor = 0; - else if (divisor == 0x4001) /* 1.5 */ + } else if (divisor == 0x4001) /* 1.5 */ { divisor = 1; + } /* * Set this bit to turn off a divide by 2.5 on baud rate generator * This enables baud rates up to 12Mbaud but cannot reach below 1200 @@ -1571,13 +1578,11 @@ static uint32_t ftdi_2232h_baud_base_to_divisor(uint32_t baud, uint32_t base) return divisor; } -static inline uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) -{ - return ftdi_2232h_baud_base_to_divisor(baud, (uint32_t) 120000000); +static inline uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) { + return ftdi_2232h_baud_base_to_divisor(baud, (uint32_t) 120000000); } -static inline uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc) -{ +static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { uint32_t baud = p_cdc->requested_line_coding.bit_rate; uint32_t div_value = 0; TU_VERIFY(baud); @@ -1646,13 +1651,13 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t * p_cdc) return div_value; } -static uint8_t ftdi_get_idx(tuh_xfer_t * xfer) { - uint8_t const channel = (uint8_t) tu_le16toh(xfer->setup->wIndex); // channel index, or 0 for legacy types +static uint8_t ftdi_get_idx(tuh_xfer_t *xfer) { + uint8_t const channel = (uint8_t) tu_le16toh(xfer->setup->wIndex);// channel index, or 0 for legacy types for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { - const cdch_interface_t * p_cdc = &cdch_data[i]; + const cdch_interface_t *p_cdc = &cdch_data[i]; if (p_cdc->daddr == xfer->daddr && (!p_cdc->ftdi.channel || // 0 for legacy types (only interface 0) - channel == p_cdc->ftdi.channel)) { // or multi-channel types (interfaces 0..n) + channel == p_cdc->ftdi.channel)) {// or multi-channel types (interfaces 0..n) return i; } } @@ -1703,29 +1708,28 @@ static bool cp210x_set_request(cdch_interface_t * p_cdc, uint8_t command, uint16 return tuh_control_xfer(&xfer); } -static inline bool cp210x_ifc_enable(cdch_interface_t * p_cdc, uint16_t enabled, +static inline bool cp210x_ifc_enable(cdch_interface_t *p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); } -static bool cp210x_set_baudrate_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_baudrate_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // Not every baud rate is supported. See datasheets and AN205 "CP210x Baud Rate Support" uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); } -static bool cp210x_set_line_ctl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_line_ctl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); - uint16_t lcr = (uint16_t) ( - (p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 - (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding - (p_cdc->requested_line_coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding + uint16_t lcr = (uint16_t) ((p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 + (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding + (p_cdc->requested_line_coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } -static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | @@ -1736,16 +1740,16 @@ static inline bool cp210x_set_mhs(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { +static void cp210x_internal_control_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC_BOOL("control complete", success); if (success) { - switch(xfer->setup->bRequest) { + switch (xfer->setup->bRequest) { case CP210X_SET_MHS: p_cdc->line_state = p_cdc->requested_line_state; break; @@ -1770,21 +1774,21 @@ static void cp210x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); return true; } -static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); return true; } -static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { +static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); set_line_coding_stage1_complete(xfer, itf_num, cp210x_set_line_ctl, // control request function to set data format @@ -1792,7 +1796,7 @@ static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { } // 2 stages: set baudrate (stage1) + set data format (stage2) -static bool cp210x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return set_line_coding_sequence(p_cdc, cp210x_set_baudrate_request, // control request function to set baudrate cp210x_set_line_ctl, // control request function to set data format @@ -1801,7 +1805,7 @@ static bool cp210x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t compl complete_cb, user_data); } -static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool cp210x_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); @@ -1818,64 +1822,66 @@ enum { CONFIG_CP210X_COMPLETE }; -static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { +static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { // CP210x Interface includes 1 vendor interface + 2 bulk endpoints TU_VERIFY(itf_desc->bInterfaceSubClass == 0 && itf_desc->bInterfaceProtocol == 0 && itf_desc->bNumEndpoints == 2); - TU_VERIFY(sizeof(tusb_desc_interface_t) + 2*sizeof(tusb_desc_endpoint_t) <= max_len); + TU_VERIFY(sizeof(tusb_desc_interface_t) + 2 * sizeof(tusb_desc_endpoint_t) <= max_len); - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t *p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_CP210X; // endpoint pair - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); // data endpoints expected to be in pairs return open_ep_stream_pair(p_cdc, desc_ep); } -static void cp210x_process_config(tuh_xfer_t * xfer) { - uintptr_t const state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); +static bool cp210x_process_set_config(tuh_xfer_t *xfer) { + const uint8_t state = (uint8_t) xfer->user_data; + uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); + TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { case CONFIG_CP210X_IFC_ENABLE: - p_cdc->user_control_cb = cp210x_process_config; // set once for whole process config - TU_ASSERT_COMPLETE(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cp210x_process_config, - CONFIG_CP210X_SET_BAUDRATE_REQUEST)); + TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, + PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_BAUDRATE_REQUEST))); break; case CONFIG_CP210X_SET_BAUDRATE_REQUEST: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT_COMPLETE(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, - CONFIG_CP210X_SET_LINE_CTL)); - break; + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, + PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_LINE_CTL))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_CP210X_SET_LINE_CTL: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - TU_ASSERT_COMPLETE(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, - CONFIG_CP210X_SET_DTR_RTS)); - break; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, + PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_DTR_RTS))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_CP210X_SET_DTR_RTS: #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, - CONFIG_CP210X_COMPLETE)); - break; + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, + PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_COMPLETE))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_CP210X_COMPLETE: @@ -1883,9 +1889,10 @@ static void cp210x_process_config(tuh_xfer_t * xfer) { break; default: - TU_ASSERT_COMPLETE(false); - break; + return false; } + + return true; } #endif @@ -1896,13 +1903,13 @@ static void cp210x_process_config(tuh_xfer_t * xfer) { #if CFG_TUH_CDC_CH34X -static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc); -static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc); +static uint8_t ch34x_get_lcr(cdch_interface_t *p_cdc); +static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t *p_cdc); //------------- Control Request -------------// -static bool ch34x_set_request(cdch_interface_t * p_cdc, uint8_t direction, uint8_t request, - uint16_t value, uint16_t index, uint8_t * buffer, uint16_t length, +static bool ch34x_set_request(cdch_interface_t *p_cdc, uint8_t direction, uint8_t request, + uint16_t value, uint16_t index, uint8_t *buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType_bit = { @@ -1917,7 +1924,7 @@ static bool ch34x_set_request(cdch_interface_t * p_cdc, uint8_t direction, uint8 }; // use usbh enum buf since application variable does not live long enough - uint8_t * enum_buf = NULL; + uint8_t *enum_buf = NULL; if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); @@ -1938,18 +1945,18 @@ static bool ch34x_set_request(cdch_interface_t * p_cdc, uint8_t direction, uint8 return tuh_control_xfer(&xfer); } -static inline bool ch34x_control_out(cdch_interface_t * p_cdc, uint8_t request, uint16_t value, uint16_t index, +static inline bool ch34x_control_out(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data); } -static inline bool ch34x_control_in(cdch_interface_t * p_cdc, uint8_t request, uint16_t value, uint16_t index, - uint8_t * buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static inline bool ch34x_control_in(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, + uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data); } -static inline bool ch34x_write_reg(cdch_interface_t * p_cdc, uint16_t reg, uint16_t reg_value, +static inline bool ch34x_write_reg(cdch_interface_t *p_cdc, uint16_t reg, uint16_t reg_value, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data); } @@ -1960,36 +1967,33 @@ static inline bool ch34x_write_reg(cdch_interface_t * p_cdc, uint16_t reg, uint1 // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} -static bool ch34x_write_reg_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_write_reg_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint8_t const lcr = ch34x_get_lcr(p_cdc); TU_VERIFY(lcr); - return ch34x_write_reg(p_cdc, CH32X_REG16_LCR2_LCR, lcr, complete_cb, user_data); } -static bool ch34x_write_reg_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_write_reg_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); TU_VERIFY(div_ps); - return ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data); } -static bool ch34x_modem_ctrl_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) | // CH34x signals are inverted +static bool ch34x_modem_ctrl_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) |// CH34x signals are inverted (p_cdc->requested_line_state.dtr ? CH34X_BIT_DTR : 0)); - return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { +static void ch34x_internal_control_complete(tuh_xfer_t *xfer) { // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC_BOOL("control complete", success); @@ -2028,21 +2032,21 @@ static void ch34x_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } -static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool ch34x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } -static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t * xfer) { +static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; set_line_coding_stage1_complete(xfer, itf_num, @@ -2103,20 +2107,19 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, ui return true; } -static void ch34x_process_config(tuh_xfer_t* xfer) { - uintptr_t const state = xfer->user_data; - // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; +static bool ch34x_process_set_config(tuh_xfer_t *xfer) { + const uint8_t state = (uint8_t) xfer->user_data; + uint8_t const itf_num = 0; // CH34x has only interface 0, since wIndex is used as payload uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT_COMPLETE(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - uint8_t buffer[2]; // TODO remove + cdch_interface_t *p_cdc = get_itf(idx); + uint8_t buffer[2];// TODO remove + + TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { case CONFIG_CH34X_READ_VERSION: - p_cdc->user_control_cb = ch34x_process_config; // set once for whole process config - TU_ASSERT_COMPLETE(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, - ch34x_process_config, CONFIG_CH34X_SERIAL_INIT)); + TU_ASSERT(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_SERIAL_INIT))); break; case CONFIG_CH34X_SERIAL_INIT: { @@ -2125,39 +2128,39 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { TU_LOG_P_CDC("Chip Version = 0x%02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming // see drivers from WCH vendor, Linux kernel and FreeBSD - TU_ASSERT_COMPLETE(version >= 0x30); - // init CH34x with line coding - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; - uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); - TU_ASSERT_COMPLETE(div_ps); - uint8_t const lcr = ch34x_get_lcr(p_cdc); - TU_ASSERT_COMPLETE(lcr); - TU_ASSERT_COMPLETE(ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, - ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE)); + if (version >= 0x30) { + // init CH34x with line coding + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; + uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); + uint8_t const lcr = ch34x_get_lcr(p_cdc); + TU_ASSERT(div_ps != 0 && lcr != 0); + TU_ASSERT(ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_SPECIAL_REG_WRITE))); + } break; } case CONFIG_CH34X_SPECIAL_REG_WRITE: // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; - TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, - ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL)); + TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_FLOW_CONTROL))); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control - TU_ASSERT_COMPLETE(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, - ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL)); + TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_MODEM_CONTROL))); break; case CONFIG_CH34X_MODEM_CONTROL: #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, - CONFIG_CH34X_COMPLETE)); - break; + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + p_cdc->user_control_cb = cdch_process_set_config; + TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_COMPLETE))); + break; #else - TU_ATTR_FALLTHROUGH; + TU_ATTR_FALLTHROUGH; #endif case CONFIG_CH34X_COMPLETE: @@ -2165,15 +2168,16 @@ static void ch34x_process_config(tuh_xfer_t* xfer) { break; default: - TU_ASSERT_COMPLETE(false); break; } + + return true; } //------------- Helper -------------// // calculate divisor and prescaler for baudrate, return it as 16-bit combined value -static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc) { +static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t *p_cdc) { uint32_t const baval = p_cdc->requested_line_coding.bit_rate; uint8_t a; uint8_t b; @@ -2219,20 +2223,20 @@ static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t * p_cdc) { // reg divisor = a, reg prescaler = b // According to linux code we need to set bit 7 of UCHCOM_REG_BPS_PRE, // otherwise the chip will buffer data. - return (uint16_t) ((uint16_t)a << 8 | 0x80 | b); + return (uint16_t) ((uint16_t) a << 8 | 0x80 | b); } // calculate lcr value from data coding -static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { +static uint8_t ch34x_get_lcr(cdch_interface_t *p_cdc) { uint8_t const stop_bits = p_cdc->requested_line_coding.stop_bits; - uint8_t const parity = p_cdc->requested_line_coding.parity; + uint8_t const parity = p_cdc->requested_line_coding.parity; uint8_t const data_bits = p_cdc->requested_line_coding.data_bits; uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; TU_VERIFY(data_bits >= 5 && data_bits <= 8); lcr |= (uint8_t) (data_bits - 5); - switch(parity) { + switch (parity) { case CDC_LINE_CODING_PARITY_NONE: break; @@ -2271,14 +2275,13 @@ static uint8_t ch34x_get_lcr(cdch_interface_t * p_cdc) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_PL2303 -static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, +static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); +static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); //------------- Control Request -------------// - -static bool pl2303_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_t requesttype, - uint16_t value, uint16_t index, uint8_t * buffer, uint16_t length, +static bool pl2303_set_request(cdch_interface_t *p_cdc, uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, uint8_t *buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request_setup = { .bmRequestType = requesttype, @@ -2289,7 +2292,7 @@ static bool pl2303_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_ }; // use usbh enum buf since application variable does not live long enough - uint8_t * enum_buf = NULL; + uint8_t *enum_buf = NULL; if (buffer && length > 0) { enum_buf = usbh_get_enum_buf(); @@ -2310,34 +2313,28 @@ static bool pl2303_set_request(cdch_interface_t * p_cdc, uint8_t request, uint8_ return tuh_control_xfer(&xfer); } -static bool pl2303_vendor_read(cdch_interface_t * p_cdc, uint16_t value, uint8_t * buf, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? - PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; +static bool pl2303_vendor_read(cdch_interface_t *p_cdc, uint16_t value, uint8_t *buf, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_READ_REQUEST_TYPE, value, 0, buf, 1, complete_cb, user_data); } -static bool pl2303_vendor_write(cdch_interface_t * p_cdc, uint16_t value, uint16_t index, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? - PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; +static bool pl2303_vendor_write(cdch_interface_t *p_cdc, uint16_t value, uint16_t index, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_WRITE_REQUEST_TYPE, value, index, NULL, 0, complete_cb, user_data); } -static inline bool pl2303_supports_hx_status(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static inline bool pl2303_supports_hx_status(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint8_t buf = 0; return pl2303_set_request(p_cdc, PL2303_VENDOR_READ_REQUEST, PL2303_VENDOR_READ_REQUEST_TYPE, PL2303_READ_TYPE_HX_STATUS, 0, &buf, 1, complete_cb, user_data); } -static inline bool pl2303_set_control_lines(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static inline bool pl2303_set_control_lines(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, p_cdc->requested_line_state.all, 0, NULL, 0, complete_cb, user_data); @@ -2348,7 +2345,7 @@ static inline bool pl2303_set_control_lines(cdch_interface_t * p_cdc, tuh_xfer_c // return pl2303_set_request(p_cdc, PL2303_GET_LINE_REQUEST, PL2303_GET_LINE_REQUEST_TYPE, 0, 0, buf, PL2303_LINE_CODING_BUFSIZE); //} -static bool pl2303_set_line_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool pl2303_set_line_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // the caller has to precheck, that the new line coding different than the current, else false returned uint8_t buf[PL2303_LINE_CODING_BUFSIZE]; /* @@ -2390,8 +2387,7 @@ static bool pl2303_set_line_request(cdch_interface_t * p_cdc, tuh_xfer_cb_t comp // return pl2303_set_request(p_cdc, PL2303_BREAK_REQUEST, PL2303_BREAK_REQUEST_TYPE, state, 0, NULL, 0); //} -static inline int pl2303_clear_halt(cdch_interface_t * p_cdc, uint8_t endp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) -{ +static inline int pl2303_clear_halt(cdch_interface_t *p_cdc, uint8_t endp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { /* we don't care if it wasn't halted first. in fact some devices * (like some ibmcam model 1 units) seem to expect hosts to make * this request for iso endpoints, which can't halt! @@ -2403,22 +2399,22 @@ static inline int pl2303_clear_halt(cdch_interface_t * p_cdc, uint8_t endp, tuh_ //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void pl2303_internal_control_complete(tuh_xfer_t * xfer) { +static void pl2303_internal_control_complete(tuh_xfer_t *xfer) { // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); TU_LOG_P_CDC_BOOL("control complete", success); if (success) { if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { + xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { p_cdc->line_coding = p_cdc->requested_line_coding; } if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { + xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { p_cdc->line_state = p_cdc->requested_line_state; } } @@ -2429,14 +2425,14 @@ static void pl2303_internal_control_complete(tuh_xfer_t * xfer) { } } -static bool pl2303_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); return true; } -static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool pl2303_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); @@ -2444,7 +2440,7 @@ static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t compl return true; } -static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool pl2303_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; @@ -2454,7 +2450,7 @@ static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete return true; } -static bool pl2303_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); @@ -2487,19 +2483,19 @@ enum { CONFIG_PL2303_COMPLETE }; -static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len) { +static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { // PL2303 Interface includes 1 vendor interface + 1 interrupt endpoints + 2 bulk TU_VERIFY(itf_desc->bNumEndpoints == 3); TU_VERIFY(sizeof(tusb_desc_interface_t) + 3 * sizeof(tusb_desc_endpoint_t) <= max_len); - cdch_interface_t * p_cdc = make_new_itf(daddr, itf_desc); + cdch_interface_t *p_cdc = make_new_itf(daddr, itf_desc); TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_PL2303; p_cdc->pl2303.serial_private.quirks = 0; p_cdc->pl2303.supports_hx_status = false; - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const * ) tu_desc_next(itf_desc); + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); // Interrupt endpoint: not used for now TU_ASSERT(TUSB_DESC_ENDPOINT == tu_desc_type(desc_ep) && @@ -2514,158 +2510,167 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, u return true; } -static void pl2303_process_config(tuh_xfer_t * xfer) { - uintptr_t const state = xfer->user_data; +static bool pl2303_process_set_config(tuh_xfer_t *xfer) { + const uint8_t state = (uint8_t) xfer->user_data; // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf(idx); // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() - TU_ASSERT_COMPLETE(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); uint8_t buf = 0; int8_t type; + TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); switch (state) { - // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_GET_DESC: - p_cdc->user_control_cb = pl2303_process_config; // set once for whole process config + p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config // get device descriptor - TU_ASSERT_COMPLETE(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - pl2303_process_config, CONFIG_PL2303_DETECT_TYPE)); + TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_DETECT_TYPE))); break; case CONFIG_PL2303_DETECT_TYPE: // get type and quirks (step 1) - type = pl2303_detect_type (p_cdc, 1, pl2303_process_config, CONFIG_PL2303_READ1); // step 1 - TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); + type = pl2303_detect_type(p_cdc, 1, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ1)); + TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); if (type == PL2303_SUPPORTS_HX_STATUS_TRIGGERED) { break; - } // else: no transfer triggered and continue with CONFIG_PL2303_READ1 + }// else: no transfer triggered and continue with CONFIG_PL2303_READ1 TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ1: // get supports_hx_status, type and quirks (step 2), do special read - p_cdc->pl2303.supports_hx_status = ( // will not be true, if coming directly from previous case - xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS ); - type = pl2303_detect_type (p_cdc, 2, NULL, 0); // step 2 now with supports_hx_status - TU_ASSERT_COMPLETE(type!=PL2303_DETECT_TYPE_FAILED); + p_cdc->pl2303.supports_hx_status = (// will not be true, if coming directly from previous case + xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS); + type = pl2303_detect_type(p_cdc, 2, NULL, 0); // step 2 now with supports_hx_status + TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; - #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0 // can be activated if necessary - TU_LOG_P_CDC("bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", - desc_dev->bDeviceClass, desc_dev->bMaxPacketSize0, - desc_dev->bcdUSB, desc_dev->bcdDevice ); - uint16_t vid, pid; - TU_ASSERT_COMPLETE(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); - TU_LOG_P_CDC("vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", - vid, pid, p_cdc->pl2303.supports_hx_status, - p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); + #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0// can be activated if necessary + TU_LOG_P_CDC("bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", + desc_dev->bDeviceClass, desc_dev->bMaxPacketSize0, + desc_dev->bcdUSB, desc_dev->bcdDevice); + uint16_t vid, pid; + TU_ASSERT(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); + TU_LOG_P_CDC("vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", + vid, pid, p_cdc->pl2303.supports_hx_status, + p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); #endif // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_WRITE1)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE1))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_WRITE1: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0x0404, 0, pl2303_process_config, CONFIG_PL2303_READ2)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 0, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ2))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ2: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_READ3)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ3))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ3: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8383, &buf, pl2303_process_config, CONFIG_PL2303_READ4)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ4))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ4: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_WRITE2)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE2))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_WRITE2: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0x0404, 1, pl2303_process_config, CONFIG_PL2303_READ5)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 1, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ5))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ5: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8484, &buf, pl2303_process_config, CONFIG_PL2303_READ6)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ6))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_READ6: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0x8383, &buf, pl2303_process_config, CONFIG_PL2303_WRITE3)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE3))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_WRITE3: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, 1, pl2303_process_config, CONFIG_PL2303_WRITE4)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0, 1, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE4))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_WRITE4: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 1, 0, pl2303_process_config, CONFIG_PL2303_WRITE5)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 1, 0, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE5))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; case CONFIG_PL2303_WRITE5: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 2, 0x24, pl2303_process_config, CONFIG_PL2303_RESET_ENDP1)); - } else { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 2, 0x44, pl2303_process_config, CONFIG_PL2303_RESET_ENDP1)); - } + uint16_t const windex = (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) ? 0x24 : 0x44; + TU_ASSERT(pl2303_vendor_write(p_cdc, 2, windex, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP1))); break; - } // else: continue with next step + }// else: continue with next step TU_ATTR_FALLTHROUGH; - // from here sequence overtaken from Linux Kernel function pl2303_open() + // from here sequence overtaken from Linux Kernel function pl2303_open() case CONFIG_PL2303_RESET_ENDP1: // step 1 if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT_COMPLETE(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, pl2303_process_config, CONFIG_PL2303_RESET_ENDP2)); + TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP2))); } else { /* reset upstream data pipes */ if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG, // skip CONFIG_PL2303_RESET_ENDP2, no 2nd step + TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG,// skip CONFIG_PL2303_RESET_ENDP2, no 2nd step PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, - pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); } else { - pl2303_vendor_write(p_cdc, 8, 0, pl2303_process_config, CONFIG_PL2303_RESET_ENDP2); + pl2303_vendor_write(p_cdc, 8, 0, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP2)); } } break; @@ -2673,91 +2678,96 @@ static void pl2303_process_config(tuh_xfer_t * xfer) { case CONFIG_PL2303_RESET_ENDP2: // step 2 if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT_COMPLETE(pl2303_clear_halt(p_cdc, PL2303_IN_EP, pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); } else { /* reset upstream data pipes */ if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { // here nothing to do, only structure of previous step overtaken for better reading and comparison } else { - TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 9, 0, pl2303_process_config, CONFIG_PL2303_LINE_CODING)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, + cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); } } break; - // from here sequence overtaken from Linux Kernel function pl2303_set_termios() - // unnecessary pl2303_get_line_request() is skipped due to a stall + // from here sequence overtaken from Linux Kernel function pl2303_set_termios() + // unnecessary pl2303_get_line_request() is skipped due to a stall case CONFIG_PL2303_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT_COMPLETE( pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, + PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_MODEM_CONTROL))); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif case CONFIG_PL2303_MODEM_CONTROL: - #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT_COMPLETE(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif + #ifdef LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, + PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif -// skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program -// case CONFIG_PL2303_FLOW_CTRL_READ: -// // read flow control register for modify & write back in next step -// if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { -// TU_LOG_P_CDC ( "1\r\n" ); -// TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, pl2303_process_config, -// CONFIG_PL2303_FLOW_CTRL_WRITE)); -// } else { -// TU_LOG_P_CDC ( "2\r\n" ); -// TU_ASSERT_COMPLETE(pl2303_vendor_read(p_cdc, 0, &buf, pl2303_process_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); -// } -// break; -// -// case CONFIG_PL2303_FLOW_CTRL_WRITE: -// // no flow control -// buf = xfer->buffer[0]; -// if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { -// buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; -// buf |= PL2303_HXN_FLOWCTRL_NONE; -// TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, pl2303_process_config, -// CONFIG_PL2303_COMPLETE)); -// } else { -// buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; -// TU_ASSERT_COMPLETE(pl2303_vendor_write(p_cdc, 0, buf, pl2303_process_config, CONFIG_PL2303_COMPLETE)); -// } -// break; + // skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program + // case CONFIG_PL2303_FLOW_CTRL_READ: + // // read flow control register for modify & write back in next step + // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + // TU_LOG_P_CDC ( "1\r\n" ); + // TU_ASSERT(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, + // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_FLOW_CTRL_WRITE))); + // } else { + // TU_LOG_P_CDC ( "2\r\n" ); + // TU_ASSERT(pl2303_vendor_read(p_cdc, 0, &buf, cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); + // } + // break; + // + // case CONFIG_PL2303_FLOW_CTRL_WRITE: + // // no flow control + // buf = xfer->buffer[0]; + // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + // buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; + // buf |= PL2303_HXN_FLOWCTRL_NONE; + // TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, + // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + // } else { + // buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; + // TU_ASSERT(pl2303_vendor_write(p_cdc, 0, buf, + // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + // } + // break; case CONFIG_PL2303_COMPLETE: set_config_complete(idx, 0, true); break; default: - TU_ASSERT_COMPLETE(false); - break; + return false; } + + return true; } //------------- Helper -------------// -static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, - tuh_xfer_cb_t complete_cb, uintptr_t user_data ) -{ +static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { /* * Legacy PL2303H, variants 0 and 1 (difference unknown). */ if (desc_dev->bDeviceClass == 0x02) { - return TYPE_H; /* variant 0 */ + return TYPE_H; /* variant 0 */ } if (desc_dev->bMaxPacketSize0 != 0x40) { if (desc_dev->bDeviceClass == 0x00 || desc_dev->bDeviceClass == 0xff) { - return TYPE_H; /* variant 1 */ + return TYPE_H; /* variant 1 */ } - return TYPE_H; /* variant 0 */ + return TYPE_H; /* variant 0 */ } switch (desc_dev->bcdUSB) { @@ -2782,7 +2792,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, case 0x300: /* GT / TA */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request - TU_ASSERT(pl2303_supports_hx_status (p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); + TU_ASSERT(pl2303_supports_hx_status(p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; } else { // step 2 use supports_hx_status @@ -2798,7 +2808,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, case 0x500: /* GE / TB */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request - TU_ASSERT(pl2303_supports_hx_status (p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); + TU_ASSERT(pl2303_supports_hx_status(p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; } else { // step 2 use supports_hx_status @@ -2829,8 +2839,7 @@ static int8_t pl2303_detect_type(cdch_interface_t * p_cdc, uint8_t step, * Returns the nearest supported baud rate that can be set directly without * using divisors. */ -static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) -{ +static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) { static const uint32_t baud_sup[] = { 75, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 14400, 19200, 28800, 38400, 57600, 115200, 230400, 460800, @@ -2859,8 +2868,7 @@ static uint32_t pl2303_get_supported_baud_rate(uint32_t baud) * NOTE: If unsupported baud rates are set directly, the PL2303 seems to * use 9600 baud. */ -static uint32_t pl2303_encode_baud_rate_direct(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) -{ +static uint32_t pl2303_encode_baud_rate_direct(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) { uint32_t baud_le = tu_htole32(baud); buf[0] = (uint8_t) ( baud_le & 0xff); buf[1] = (uint8_t) ((baud_le >> 8) & 0xff); @@ -2870,8 +2878,7 @@ static uint32_t pl2303_encode_baud_rate_direct(uint8_t buf[PL2303_LINE_CODING_BA return baud; } -static uint32_t pl2303_encode_baud_rate_divisor(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) -{ +static uint32_t pl2303_encode_baud_rate_divisor(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) { uint32_t baseline, mantissa, exponent; /* @@ -2899,7 +2906,7 @@ static uint32_t pl2303_encode_baud_rate_divisor(uint8_t buf[PL2303_LINE_CODING_B buf[3] = 0x80; buf[2] = 0; - buf[1] = (uint8_t) ((exponent << 1 | mantissa >> 8) & 0xff); + buf[1] = (uint8_t) ((exponent << 1 | mantissa >> 8) & 0xff); buf[0] = (uint8_t) (mantissa & 0xff); /* Calculate and return the exact baud rate. */ @@ -2908,8 +2915,7 @@ static uint32_t pl2303_encode_baud_rate_divisor(uint8_t buf[PL2303_LINE_CODING_B return baud; } -static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) -{ +static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE], uint32_t baud) { uint32_t baseline, mantissa, exponent; /* @@ -2922,7 +2928,7 @@ static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODI baseline = 12000000 * 32; mantissa = baseline / baud; if (mantissa == 0) { - mantissa = 1; /* Avoid dividing by zero if baud > 32 * 12M. */ + mantissa = 1; /* Avoid dividing by zero if baud > 32 * 12M. */ } exponent = 0; while (mantissa >= 2048) { @@ -2938,7 +2944,7 @@ static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODI buf[3] = 0x80; buf[2] = (uint8_t) (exponent & 0x01); - buf[1] = (uint8_t) (((exponent & (uint32_t) ~0x01) << 4 | mantissa >> 8 ) & 0xff); + buf[1] = (uint8_t) (((exponent & (uint32_t) ~0x01) << 4 | mantissa >> 8) & 0xff); buf[0] = (uint8_t) (mantissa & 0xff); /* Calculate and return the exact baud rate. */ @@ -2947,8 +2953,7 @@ static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODI return baud; } -static bool pl2303_encode_baud_rate(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]) -{ +static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]) { uint32_t baud = p_cdc->requested_line_coding.bit_rate; uint32_t baud_sup; -- cgit v1.3.1 From 506edc626709ca92dd9c38d6c6f5813f30a27692 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 18 Jun 2025 18:55:31 +0700 Subject: add get_itf_by_xfer() to better determine cdc interface from xfer complete callback --- src/class/cdc/cdc_host.c | 182 +++++++++++++++++++++++++++-------------------- 1 file changed, 105 insertions(+), 77 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index b6e9cb297..3be61e654 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -131,9 +131,6 @@ CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; // Serial Driver //--------------------------------------------------------------------+ -// for process_set_config user_data: idx (byte1) and state (byte0) -#define PROCESS_CONFIG_STATE(_idx, _state) tu_u16(_idx, _state) - static void cdch_process_set_config(tuh_xfer_t *xfer); //------------- ACM prototypes -------------// @@ -327,13 +324,16 @@ TU_VERIFY_STATIC(TU_ARRAY_SIZE(serial_drivers) == SERIAL_DRIVER_COUNT, "Serial d // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -static inline cdch_interface_t * get_itf(uint8_t idx) { +TU_ATTR_ALWAYS_INLINE static inline cdch_interface_t * get_itf(uint8_t idx) { TU_ASSERT(idx < CFG_TUH_CDC, NULL); cdch_interface_t * p_cdc = &cdch_data[idx]; - return (p_cdc->daddr != 0) ? p_cdc : NULL; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t get_idx_by_ptr(cdch_interface_t* p_cdc) { + return p_cdc - cdch_data; +} + static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { for(uint8_t i=0; idaddr != 0, NULL); + for(uint8_t i=0; idaddr == xfer->daddr) { + switch (p_cdc->serial_drid) { + #if CFG_TUH_CDC_CP210X + case SERIAL_DRIVER_CP210X: + #endif + case SERIAL_DRIVER_ACM: { + // Driver use wIndex for bInterfaceNumber + const uint8_t itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); + if (p_cdc->bInterfaceNumber == itf_num) { + return p_cdc; + } + break; + } + + #if CFG_TUH_CDC_FTDI + case SERIAL_DRIVER_FTDI: { + // FTDI uses wIndex for channel number, if channel is 0 then it is the default channel + const uint8_t channel = (uint8_t) tu_le16toh(xfer->setup->wIndex); + if (p_cdc->ftdi.channel == 0 || p_cdc->ftdi.channel == channel) { + return p_cdc; + } + break; + } + #endif + + #if CFG_TUH_CDC_CH34X + case SERIAL_DRIVER_CH34X: + // ch34x has only one interface + return p_cdc; + #endif + + #if CFG_TUH_CDC_PL2303 + case SERIAL_DRIVER_PL2303: + // pl2303 has only one interface + return p_cdc; + #endif + + default: + break; + } + } + } + + return NULL; +} + static cdch_interface_t * make_new_itf(uint8_t daddr, tusb_desc_interface_t const * itf_desc) { for(uint8_t i=0; iserial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set control line state dtr = %u rts = %u", line_state.dtr, line_state.rts ); + TU_LOG_P_CDC("set control line state dtr = %u rts = %u", line_state.dtr, line_state.rts); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line_state = line_state; @@ -614,8 +665,6 @@ bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line if (ret && !complete_cb) { p_cdc->line_state = line_state; } -// TU_LOG_P_CDC_BOOL("set control line state", ret); - return ret; } @@ -893,9 +942,9 @@ static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { } static void cdch_process_set_config(tuh_xfer_t *xfer) { - const uint8_t idx = tu_u32_byte1(xfer->user_data); - cdch_interface_t *p_cdc = get_itf(idx); + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + const uint8_t idx = get_idx_by_ptr(p_cdc); if (!serial_drivers[p_cdc->serial_drid].process_set_config(xfer)) { const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; @@ -916,7 +965,7 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { xfer.daddr = daddr; xfer.result = XFER_RESULT_SUCCESS; xfer.setup = &request; - xfer.user_data = PROCESS_CONFIG_STATE(idx, 0); // initial state 0 + xfer.user_data = 0; // initial state 0 cdch_process_set_config(&xfer); return true; @@ -1093,7 +1142,7 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1 } static bool acm_process_set_config(tuh_xfer_t *xfer) { - const uint8_t state = (uint8_t) xfer->user_data; + const uintptr_t state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); @@ -1104,7 +1153,7 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { #ifdef LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_ACM_SET_LINE_CODING))); + TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, CONFIG_ACM_SET_LINE_CODING)); break; } #endif @@ -1114,7 +1163,7 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM if (p_cdc->acm_capability.support_line_request) { p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_ACM_COMPLETE))); + TU_ASSERT(acm_set_line_coding(p_cdc, cdch_process_set_config, CONFIG_ACM_COMPLETE)); break; } #endif @@ -1326,7 +1375,7 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint } static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { - const uint8_t state = (uint8_t) xfer->user_data; + const uintptr_t state = xfer->user_data; uint8_t const idx = ftdi_get_idx(xfer); cdch_interface_t *p_cdc = get_itf(idx); uint8_t const itf_num = p_cdc->bInterfaceNumber; @@ -1338,7 +1387,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { // get device descriptor if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_DETERMINE_TYPE))); + cdch_process_set_config, CONFIG_FTDI_DETERMINE_TYPE)); break; } TU_ATTR_FALLTHROUGH; @@ -1370,7 +1419,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { // from here sequence overtaken from Linux Kernel function ftdi_open() case CONFIG_FTDI_SIO_RESET: p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_SET_DATA))); + TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, CONFIG_FTDI_SET_DATA)); break; // from here sequence overtaken from Linux Kernel function ftdi_set_termios() @@ -1378,7 +1427,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_SET_BAUDRATE))); + TU_ASSERT(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); break; #else TU_ATTR_FALLTHROUGH; @@ -1387,7 +1436,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_SET_BAUDRATE: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_FLOW_CONTROL))); + TU_ASSERT(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); break; #else TU_ATTR_FALLTHROUGH; @@ -1396,14 +1445,14 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_FLOW_CONTROL: // disable flow control TU_ASSERT(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, FTDI_SIO_DISABLE_FLOW_CTRL, - p_cdc->ftdi.channel, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_MODEM_CTRL))); + p_cdc->ftdi.channel, cdch_process_set_config, CONFIG_FTDI_MODEM_CTRL)); break; case CONFIG_FTDI_MODEM_CTRL: #ifdef LINE_CONTROL_ON_ENUM p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_FTDI_COMPLETE))); + TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -1840,7 +1889,7 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui } static bool cp210x_process_set_config(tuh_xfer_t *xfer) { - const uint8_t state = (uint8_t) xfer->user_data; + const uintptr_t state = xfer->user_data; uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); @@ -1848,16 +1897,14 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { switch (state) { case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, - PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_BAUDRATE_REQUEST))); + TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, CONFIG_CP210X_SET_BAUDRATE_REQUEST)); break; case CONFIG_CP210X_SET_BAUDRATE_REQUEST: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, - PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_LINE_CTL))); + TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_LINE_CTL)); break; #else TU_ATTR_FALLTHROUGH; @@ -1866,8 +1913,7 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CP210X_SET_LINE_CTL: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, - PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_SET_DTR_RTS))); + TU_ASSERT(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_DTR_RTS)); break; #else TU_ATTR_FALLTHROUGH; @@ -1877,8 +1923,7 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { #ifdef LINE_CONTROL_ON_ENUM p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, - PROCESS_CONFIG_STATE(idx, CONFIG_CP210X_COMPLETE))); + TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -2108,7 +2153,7 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, ui } static bool ch34x_process_set_config(tuh_xfer_t *xfer) { - const uint8_t state = (uint8_t) xfer->user_data; + const uintptr_t state = xfer->user_data; uint8_t const itf_num = 0; // CH34x has only interface 0, since wIndex is used as payload uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); @@ -2119,7 +2164,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { switch (state) { case CONFIG_CH34X_READ_VERSION: TU_ASSERT(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_SERIAL_INIT))); + cdch_process_set_config, CONFIG_CH34X_SERIAL_INIT)); break; case CONFIG_CH34X_SERIAL_INIT: { @@ -2135,7 +2180,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { uint8_t const lcr = ch34x_get_lcr(p_cdc); TU_ASSERT(div_ps != 0 && lcr != 0); TU_ASSERT(ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, tu_u16(lcr, 0x9c), div_ps, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_SPECIAL_REG_WRITE))); + cdch_process_set_config, CONFIG_CH34X_SPECIAL_REG_WRITE)); } break; } @@ -2144,20 +2189,20 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_FLOW_CONTROL))); + cdch_process_set_config, CONFIG_CH34X_FLOW_CONTROL)); break; case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_MODEM_CONTROL))); + cdch_process_set_config, CONFIG_CH34X_MODEM_CONTROL)); break; case CONFIG_CH34X_MODEM_CONTROL: #ifdef LINE_CONTROL_ON_ENUM p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; - TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, PROCESS_CONFIG_STATE(idx, CONFIG_CH34X_COMPLETE))); + TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -2511,7 +2556,7 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui } static bool pl2303_process_set_config(tuh_xfer_t *xfer) { - const uint8_t state = (uint8_t) xfer->user_data; + const uintptr_t state = xfer->user_data; // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber uint8_t const itf_num = 0; uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); @@ -2527,12 +2572,12 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config // get device descriptor TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_DETECT_TYPE))); + cdch_process_set_config, CONFIG_PL2303_DETECT_TYPE)); break; case CONFIG_PL2303_DETECT_TYPE: // get type and quirks (step 1) - type = pl2303_detect_type(p_cdc, 1, cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ1)); + type = pl2303_detect_type(p_cdc, 1, cdch_process_set_config, CONFIG_PL2303_READ1); TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); if (type == PL2303_SUPPORTS_HX_STATUS_TRIGGERED) { break; @@ -2559,8 +2604,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { #endif // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE1))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE1)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2568,8 +2612,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE1: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 0, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ2))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 0, cdch_process_set_config, CONFIG_PL2303_READ2)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2577,8 +2620,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ2: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ3))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ3)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2586,8 +2628,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ3: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ4))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_READ4)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2595,8 +2636,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ4: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE2))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE2)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2604,8 +2644,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE2: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 1, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ5))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 1, cdch_process_set_config, CONFIG_PL2303_READ5)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2613,8 +2652,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ5: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_READ6))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ6)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2622,8 +2660,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ6: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE3))); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE3)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2631,8 +2668,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE3: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_write(p_cdc, 0, 1, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE4))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 0, 1, cdch_process_set_config, CONFIG_PL2303_WRITE4)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2640,8 +2676,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE4: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { - TU_ASSERT(pl2303_vendor_write(p_cdc, 1, 0, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_WRITE5))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 1, 0, cdch_process_set_config, CONFIG_PL2303_WRITE5)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2650,8 +2685,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { uint16_t const windex = (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) ? 0x24 : 0x44; - TU_ASSERT(pl2303_vendor_write(p_cdc, 2, windex, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP1))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 2, windex, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP1)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2660,17 +2694,15 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_RESET_ENDP1: // step 1 if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP2))); + TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP2)); } else { /* reset upstream data pipes */ if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG,// skip CONFIG_PL2303_RESET_ENDP2, no 2nd step PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); + cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); } else { - pl2303_vendor_write(p_cdc, 8, 0, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_RESET_ENDP2)); + pl2303_vendor_write(p_cdc, 8, 0, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP2); } } break; @@ -2678,15 +2710,13 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_RESET_ENDP2: // step 2 if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); + TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); } else { /* reset upstream data pipes */ if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { // here nothing to do, only structure of previous step overtaken for better reading and comparison } else { - TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, - cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_LINE_CODING))); + TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); } } break; @@ -2696,8 +2726,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, - PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_MODEM_CONTROL))); + TU_ASSERT(pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); break; #else TU_ATTR_FALLTHROUGH; @@ -2706,8 +2735,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_MODEM_CONTROL: #ifdef LINE_CONTROL_ON_ENUM p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; - TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, - PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -2719,7 +2747,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { // TU_LOG_P_CDC ( "1\r\n" ); // TU_ASSERT(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, - // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_FLOW_CTRL_WRITE))); + // cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); // } else { // TU_LOG_P_CDC ( "2\r\n" ); // TU_ASSERT(pl2303_vendor_read(p_cdc, 0, &buf, cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); @@ -2733,11 +2761,11 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; // buf |= PL2303_HXN_FLOWCTRL_NONE; // TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, - // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); // } else { // buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; // TU_ASSERT(pl2303_vendor_write(p_cdc, 0, buf, - // cdch_process_set_config, PROCESS_CONFIG_STATE(idx, CONFIG_PL2303_COMPLETE))); + // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); // } // break; -- cgit v1.3.1 From 9503883ba7f99523a14082ce68a5f900585747b0 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 18 Jun 2025 23:35:44 +0700 Subject: usbh: add new API tuh_descriptor_get_device_local() cdc host: remove the local desc_dev and the get_device descriptor call for ftdi and pl2303 --- src/class/cdc/cdc_host.c | 141 +++++++++++++++-------------------------------- src/common/tusb_types.h | 1 - src/host/usbh.c | 58 ++++++++++++++----- src/host/usbh.h | 3 + 4 files changed, 91 insertions(+), 112 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 3be61e654..d704d82d7 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -123,10 +123,6 @@ typedef struct { static cdch_interface_t cdch_data[CFG_TUH_CDC]; CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; -#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_PL2303 - static tusb_desc_device_t desc_dev[CFG_TUH_ENUMERATION_BUFSIZE]; -#endif - //--------------------------------------------------------------------+ // Serial Driver //--------------------------------------------------------------------+ @@ -189,8 +185,6 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complet static uint16_t const pl2303_vid_pid_list[][2] = {CFG_TUH_CDC_PL2303_VID_PID_LIST}; static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = {PL2303_TYPE_DATA}; -CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN - static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool pl2303_process_set_config(tuh_xfer_t *xfer); @@ -331,7 +325,7 @@ TU_ATTR_ALWAYS_INLINE static inline cdch_interface_t * get_itf(uint8_t idx) { } TU_ATTR_ALWAYS_INLINE static inline uint8_t get_idx_by_ptr(cdch_interface_t* p_cdc) { - return p_cdc - cdch_data; + return (uint8_t) (p_cdc - cdch_data); } static inline uint8_t get_idx_by_ep_addr(uint8_t daddr, uint8_t ep_addr) { @@ -434,7 +428,7 @@ bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t * info) { info->daddr = p_cdc->daddr; - // re-construct descriptor + // re-construct interface descriptor tusb_desc_interface_t * desc = &info->desc; desc->bLength = sizeof(tusb_desc_interface_t); desc->bDescriptorType = TUSB_DESC_INTERFACE; @@ -975,8 +969,6 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { // ACM //--------------------------------------------------------------------+ -//------------- Driver API -------------// - // internal control complete to update state such as line state, encoding static void acm_internal_control_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); @@ -1089,7 +1081,6 @@ static bool acm_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, } //------------- Enumeration -------------// - enum { CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, CONFIG_ACM_SET_LINE_CODING, @@ -1339,8 +1330,7 @@ static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ //------------- Enumeration -------------// enum { - CONFIG_FTDI_GET_DESC = 0, - CONFIG_FTDI_DETERMINE_TYPE, + CONFIG_FTDI_DETERMINE_TYPE = 0, CONFIG_FTDI_WRITE_LATENCY, CONFIG_FTDI_SIO_RESET, CONFIG_FTDI_SET_DATA, @@ -1383,15 +1373,6 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { switch (state) { // from here sequence overtaken from Linux Kernel function ftdi_port_probe() - case CONFIG_FTDI_GET_DESC: - // get device descriptor - if (itf_num == 0) { // only necessary for 1st interface. other interface overtake type from interface 0 - TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - cdch_process_set_config, CONFIG_FTDI_DETERMINE_TYPE)); - break; - } - TU_ATTR_FALLTHROUGH; - case CONFIG_FTDI_DETERMINE_TYPE: // determine type if (itf_num == 0) { @@ -1472,7 +1453,9 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { //------------- Helper -------------// static bool ftdi_determine_type(cdch_interface_t *p_cdc) { - uint16_t const version = desc_dev->bcdDevice; + tusb_desc_device_t desc_dev; + TU_VERIFY(tuh_descriptor_get_device_local(p_cdc->daddr, &desc_dev)); + uint16_t const version = desc_dev.bcdDevice; uint8_t const itf_num = p_cdc->bInterfaceNumber; p_cdc->ftdi.chip_type = UNKNOWN; @@ -1482,8 +1465,7 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { switch (version) { case 0x200: - // FT232A not supported to keep it simple (no extra _read_latency_timer()) - // not testable + // FT232A not supported to keep it simple (no extra _read_latency_timer()) not testable // p_cdc->ftdi.chip_type = FT232A; // p_cdc->ftdi.baud_base = 48000000 / 2; // p_cdc->ftdi.channel = 0; @@ -1497,50 +1479,20 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { // p_cdc->ftdi.chip_type = FT232B; // } break; - case 0x400: - p_cdc->ftdi.chip_type = FT232B; - p_cdc->ftdi.channel = 0; - break; - case 0x500: - p_cdc->ftdi.chip_type = FT2232C; - break; - case 0x600: - p_cdc->ftdi.chip_type = FT232R; - p_cdc->ftdi.channel = 0; - break; - case 0x700: - p_cdc->ftdi.chip_type = FT2232H; - break; - case 0x800: - p_cdc->ftdi.chip_type = FT4232H; - break; - case 0x900: - p_cdc->ftdi.chip_type = FT232H; - break; - case 0x1000: - p_cdc->ftdi.chip_type = FTX; - break; - case 0x2800: - p_cdc->ftdi.chip_type = FT2233HP; - break; - case 0x2900: - p_cdc->ftdi.chip_type = FT4233HP; - break; - case 0x3000: - p_cdc->ftdi.chip_type = FT2232HP; - break; - case 0x3100: - p_cdc->ftdi.chip_type = FT4232HP; - break; - case 0x3200: - p_cdc->ftdi.chip_type = FT233HP; - break; - case 0x3300: - p_cdc->ftdi.chip_type = FT232HP; - break; - case 0x3600: - p_cdc->ftdi.chip_type = FT4232HA; - break; + case 0x400: p_cdc->ftdi.chip_type = FT232B; p_cdc->ftdi.channel = 0; break; + case 0x500: p_cdc->ftdi.chip_type = FT2232C; break; + case 0x600: p_cdc->ftdi.chip_type = FT232R; p_cdc->ftdi.channel = 0; break; + case 0x700: p_cdc->ftdi.chip_type = FT2232H; break; + case 0x800: p_cdc->ftdi.chip_type = FT4232H; break; + case 0x900: p_cdc->ftdi.chip_type = FT232H; break; + case 0x1000: p_cdc->ftdi.chip_type = FTX; break; + case 0x2800: p_cdc->ftdi.chip_type = FT2233HP; break; + case 0x2900: p_cdc->ftdi.chip_type = FT4233HP; break; + case 0x3000: p_cdc->ftdi.chip_type = FT2232HP; break; + case 0x3100: p_cdc->ftdi.chip_type = FT4232HP; break; + case 0x3200: p_cdc->ftdi.chip_type = FT233HP; break; + case 0x3300: p_cdc->ftdi.chip_type = FT232HP; break; + case 0x3600: p_cdc->ftdi.chip_type = FT4232HA; break; default: if (version < 0x200) { p_cdc->ftdi.chip_type = SIO; @@ -1550,7 +1502,7 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { } TU_LOG_P_CDC("%s detected (bcdDevice = 0x%04x)", - ftdi_chip_name[p_cdc->ftdi.chip_type], desc_dev->bcdDevice); + ftdi_chip_name[p_cdc->ftdi.chip_type], version); return (p_cdc->ftdi.chip_type != UNKNOWN); } @@ -2025,7 +1977,8 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t comp } static bool ch34x_modem_ctrl_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) |// CH34x signals are inverted + // CH34x signals are inverted + uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) | (p_cdc->requested_line_state.dtr ? CH34X_BIT_DTR : 0)); return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } @@ -2506,8 +2459,7 @@ static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet //------------- Enumeration -------------// enum { - CONFIG_PL2303_GET_DESC = 0, - CONFIG_PL2303_DETECT_TYPE, + CONFIG_PL2303_DETECT_TYPE = 0, CONFIG_PL2303_READ1, CONFIG_PL2303_WRITE1, CONFIG_PL2303_READ2, @@ -2568,14 +2520,8 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() - case CONFIG_PL2303_GET_DESC: - p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config - // get device descriptor - TU_ASSERT(tuh_descriptor_get_device(xfer->daddr, &desc_dev, sizeof(tusb_desc_device_t), - cdch_process_set_config, CONFIG_PL2303_DETECT_TYPE)); - break; - case CONFIG_PL2303_DETECT_TYPE: + p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config // get type and quirks (step 1) type = pl2303_detect_type(p_cdc, 1, cdch_process_set_config, CONFIG_PL2303_READ1); TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); @@ -2784,39 +2730,39 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - /* - * Legacy PL2303H, variants 0 and 1 (difference unknown). - */ - if (desc_dev->bDeviceClass == 0x02) { + tusb_desc_device_t desc_dev; + TU_VERIFY(tuh_descriptor_get_device_local(p_cdc->daddr, &desc_dev), PL2303_DETECT_TYPE_FAILED); + + // Legacy PL2303H, variants 0 and 1 (difference unknown). + if (desc_dev.bDeviceClass == 0x02) { return TYPE_H; /* variant 0 */ } - if (desc_dev->bMaxPacketSize0 != 0x40) { - if (desc_dev->bDeviceClass == 0x00 || desc_dev->bDeviceClass == 0xff) { + if (desc_dev.bMaxPacketSize0 != 0x40) { + if (desc_dev.bDeviceClass == 0x00 || desc_dev.bDeviceClass == 0xff) { return TYPE_H; /* variant 1 */ } return TYPE_H; /* variant 0 */ } - switch (desc_dev->bcdUSB) { + switch (desc_dev.bcdUSB) { case 0x101: /* USB 1.0.1? Let's assume they meant 1.1... */ TU_ATTR_FALLTHROUGH; case 0x110: - switch (desc_dev->bcdDevice) { - case 0x300: - return TYPE_HX; - case 0x400: - return TYPE_HXD; - default: - return TYPE_HX; + switch (desc_dev.bcdDevice) { + case 0x300: return TYPE_HX; + case 0x400: return TYPE_HXD; + default: return TYPE_HX; } break; + case 0x200: - switch (desc_dev->bcdDevice) { + switch (desc_dev.bcdDevice) { case 0x100: /* GC */ case 0x105: return TYPE_HXN; + case 0x300: /* GT / TA */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request @@ -2833,6 +2779,7 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, case 0x400: /* GL */ case 0x405: return TYPE_HXN; + case 0x500: /* GE / TB */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request @@ -2851,6 +2798,7 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, case 0x700: /* GR */ case 0x705: return TYPE_HXN; + default: break; } @@ -2858,8 +2806,7 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, default: break; } - TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev->bcdUSB); - + TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev.bcdUSB); return PL2303_DETECT_TYPE_FAILED; } diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index fd7f01b67..ff5d8b66a 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -345,7 +345,6 @@ typedef struct TU_ATTR_PACKED { uint8_t iManufacturer ; ///< Index of string descriptor describing manufacturer. uint8_t iProduct ; ///< Index of string descriptor describing product. uint8_t iSerialNumber ; ///< Index of string descriptor describing the device's serial number. - uint8_t bNumConfigurations ; ///< Number of possible configurations. } tusb_desc_device_t; diff --git a/src/host/usbh.c b/src/host/usbh.c index f2e5c1f0e..08c362171 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -94,26 +94,28 @@ TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_si typedef struct { tuh_bus_info_t bus_info; - // Device State - struct TU_ATTR_PACKED { - volatile uint8_t connected : 1; // After 1st transfer - volatile uint8_t addressed : 1; // After SET_ADDR - volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured - volatile uint8_t suspended : 1; // Bus suspended - // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh - }; - // Device Descriptor - uint8_t ep0_size; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; uint16_t idVendor; uint16_t idProduct; + uint16_t bcdDevice; uint8_t iManufacturer; uint8_t iProduct; uint8_t iSerialNumber; uint8_t bNumConfigurations; - // Configuration Descriptor - // uint8_t interface_count; // bNumInterfaces alias + // Device State + struct TU_ATTR_PACKED { + volatile uint8_t connected : 1; // After 1st transfer + volatile uint8_t addressed : 1; // After SET_ADDR + volatile uint8_t configured : 1; // After SET_CONFIG and all drivers are configured + volatile uint8_t suspended : 1; // Bus suspended + // volatile uint8_t removing : 1; // Physically disconnected, waiting to be processed by usbh + }; // Endpoint & Interface uint8_t itf2drv[CFG_TUH_INTERFACE_MAX]; // map interface number to driver (0xff is invalid) @@ -373,6 +375,28 @@ bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t *vid, uint16_t *pid) { return true; } +bool tuh_descriptor_get_device_local(uint8_t daddr, tusb_desc_device_t* desc_device) { + usbh_device_t *dev = get_device(daddr); + TU_VERIFY(dev && desc_device); + + desc_device->bLength = sizeof(tusb_desc_device_t); + desc_device->bDescriptorType = TUSB_DESC_DEVICE; + desc_device->bcdUSB = dev->bcdUSB; + desc_device->bDeviceClass = dev->bDeviceClass; + desc_device->bDeviceSubClass = dev->bDeviceSubClass; + desc_device->bDeviceProtocol = dev->bDeviceProtocol; + desc_device->bMaxPacketSize0 = dev->bMaxPacketSize0; + desc_device->idVendor = dev->idVendor; + desc_device->idProduct = dev->idProduct; + desc_device->bcdDevice = dev->bcdDevice; + desc_device->iManufacturer = dev->iManufacturer; + desc_device->iProduct = dev->iProduct; + desc_device->iSerialNumber = dev->iSerialNumber; + desc_device->bNumConfigurations = dev->bNumConfigurations; + + return true; +} + tusb_speed_t tuh_speed_get(uint8_t daddr) { tuh_bus_info_t bus_info; tuh_bus_info_get(daddr, &bus_info); @@ -1579,7 +1603,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { usbh_device_t* new_dev = get_device(new_addr); new_dev->bus_info = *dev0_bus; new_dev->connected = 1; - new_dev->ep0_size = desc_device->bMaxPacketSize0; + new_dev->bMaxPacketSize0 = desc_device->bMaxPacketSize0; TU_ASSERT(tuh_address_set(0, new_addr, process_enumeration, ENUM_GET_DEVICE_DESC),); break; @@ -1596,7 +1620,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { usbh_device_close(dev0_bus->rhport, 0); // close dev0 - TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->ep0_size),); // open new control endpoint + TU_ASSERT(usbh_edpt_control_open(new_addr, new_dev->bMaxPacketSize0),); // open new control endpoint TU_LOG_USBH("Get Device Descriptor\r\n"); TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), @@ -1609,8 +1633,14 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_GET_STRING_LANGUAGE_ID_LEN: { // save the received device descriptor tusb_desc_device_t const *desc_device = (tusb_desc_device_t const *) _usbh_epbuf.ctrl; + dev->bcdUSB = desc_device->bcdUSB; + dev->bDeviceClass = desc_device->bDeviceClass; + dev->bDeviceSubClass = desc_device->bDeviceSubClass; + dev->bDeviceProtocol = desc_device->bDeviceProtocol; + dev->bMaxPacketSize0 = desc_device->bMaxPacketSize0; dev->idVendor = desc_device->idVendor; dev->idProduct = desc_device->idProduct; + dev->bcdDevice = desc_device->bcdDevice; dev->iManufacturer = desc_device->iManufacturer; dev->iProduct = desc_device->iProduct; dev->iSerialNumber = desc_device->iSerialNumber; diff --git a/src/host/usbh.h b/src/host/usbh.h index 13eede869..1ee511722 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -204,6 +204,9 @@ bool tuh_rhport_reset_bus(uint8_t rhport, bool active); // Get VID/PID of device bool tuh_vid_pid_get(uint8_t daddr, uint16_t* vid, uint16_t* pid); +// Get local (cached) device descriptor once device is enumerated +bool tuh_descriptor_get_device_local(uint8_t daddr, tusb_desc_device_t* desc_device); + // Get speed of device tusb_speed_t tuh_speed_get(uint8_t daddr); -- cgit v1.3.1 From 2adb305ea71f69b38c6c01cc054d8e323dd25e0e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 19 Jun 2025 15:30:02 +0700 Subject: house keeping --- src/class/cdc/cdc_host.c | 183 ++++++++++++++++++++-------------------- src/class/cdc/serial/ftdi_sio.h | 74 ++++++++-------- src/class/cdc/serial/pl2303.h | 42 ++++----- 3 files changed, 151 insertions(+), 148 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index d704d82d7..ce98e3b3d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -111,13 +111,13 @@ typedef struct { tu_edpt_stream_t rx; uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; - uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; + uint8_t rx_ff_buf[CFG_TUH_CDC_RX_BUFSIZE]; } stream; } cdch_interface_t; typedef struct { TUH_EPBUF_DEF(tx, CFG_TUH_CDC_TX_EPSIZE); - TUH_EPBUF_DEF(rx, CFG_TUH_CDC_TX_EPSIZE); + TUH_EPBUF_DEF(rx, CFG_TUH_CDC_RX_EPSIZE); } cdch_epbuf_t; static cdch_interface_t cdch_data[CFG_TUH_CDC]; @@ -141,10 +141,6 @@ static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t c //------------- FTDI prototypes -------------// #if CFG_TUH_CDC_FTDI static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; -#if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - static uint8_t const * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; -#endif - static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); static bool ftdi_proccess_set_config(tuh_xfer_t * xfer); @@ -183,7 +179,7 @@ static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complet //------------- PL2303 prototypes -------------// #if CFG_TUH_CDC_PL2303 static uint16_t const pl2303_vid_pid_list[][2] = {CFG_TUH_CDC_PL2303_VID_PID_LIST}; -static const struct pl2303_type_data pl2303_type_data[TYPE_COUNT] = {PL2303_TYPE_DATA}; +static const pl2303_type_data_t pl2303_type_data[PL2303_TYPE_COUNT] = {PL2303_TYPE_DATA}; static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool pl2303_process_set_config(tuh_xfer_t *xfer); @@ -1209,7 +1205,7 @@ static bool ftdi_set_request(cdch_interface_t *p_cdc, uint8_t request, uint8_t r #ifdef CFG_TUH_CDC_FTDI_LATENCY static int8_t ftdi_write_latency_timer(cdch_interface_t * p_cdc, uint16_t latency, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - if (p_cdc->ftdi.chip_type == SIO /* || p_cdc->ftdi.chip_type == FT232A */ ) + if (p_cdc->ftdi.chip_type == FTDI_SIO /* || p_cdc->ftdi.chip_type == FT232A */ ) return FTDI_NOT_POSSIBLE; return ftdi_set_request(p_cdc, FTDI_SIO_SET_LATENCY_TIMER_REQUEST, FTDI_SIO_SET_LATENCY_TIMER_REQUEST_TYPE, latency, p_cdc->ftdi.channel, complete_cb, user_data) ? FTDI_REQUESTED : FTDI_FAIL; @@ -1458,7 +1454,7 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { uint16_t const version = desc_dev.bcdDevice; uint8_t const itf_num = p_cdc->bInterfaceNumber; - p_cdc->ftdi.chip_type = UNKNOWN; + p_cdc->ftdi.chip_type = FTDI_UNKNOWN; /* Assume Hi-Speed type */ p_cdc->ftdi.channel = CHANNEL_A + itf_num; @@ -1476,35 +1472,40 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { // */ // if (desc->iSerialNumber == 0 && // _read_latency_timer(port) >= 0) { - // p_cdc->ftdi.chip_type = FT232B; + // p_cdc->ftdi.chip_type = FTDI_FT232B; // } break; - case 0x400: p_cdc->ftdi.chip_type = FT232B; p_cdc->ftdi.channel = 0; break; - case 0x500: p_cdc->ftdi.chip_type = FT2232C; break; - case 0x600: p_cdc->ftdi.chip_type = FT232R; p_cdc->ftdi.channel = 0; break; - case 0x700: p_cdc->ftdi.chip_type = FT2232H; break; - case 0x800: p_cdc->ftdi.chip_type = FT4232H; break; - case 0x900: p_cdc->ftdi.chip_type = FT232H; break; - case 0x1000: p_cdc->ftdi.chip_type = FTX; break; - case 0x2800: p_cdc->ftdi.chip_type = FT2233HP; break; - case 0x2900: p_cdc->ftdi.chip_type = FT4233HP; break; - case 0x3000: p_cdc->ftdi.chip_type = FT2232HP; break; - case 0x3100: p_cdc->ftdi.chip_type = FT4232HP; break; - case 0x3200: p_cdc->ftdi.chip_type = FT233HP; break; - case 0x3300: p_cdc->ftdi.chip_type = FT232HP; break; - case 0x3600: p_cdc->ftdi.chip_type = FT4232HA; break; + + case 0x400 : p_cdc->ftdi.chip_type = FTDI_FT232B; p_cdc->ftdi.channel = 0; break; + case 0x500 : p_cdc->ftdi.chip_type = FTDI_FT2232C; break; + case 0x600 : p_cdc->ftdi.chip_type = FTDI_FT232R; p_cdc->ftdi.channel = 0; break; + case 0x700 : p_cdc->ftdi.chip_type = FTDI_FT2232H; break; + case 0x800 : p_cdc->ftdi.chip_type = FTDI_FT4232H; break; + case 0x900 : p_cdc->ftdi.chip_type = FTDI_FT232H; break; + case 0x1000: p_cdc->ftdi.chip_type = FTDI_FTX; break; + case 0x2800: p_cdc->ftdi.chip_type = FTDI_FT2233HP; break; + case 0x2900: p_cdc->ftdi.chip_type = FTDI_FT4233HP; break; + case 0x3000: p_cdc->ftdi.chip_type = FTDI_FT2232HP; break; + case 0x3100: p_cdc->ftdi.chip_type = FTDI_FT4232HP; break; + case 0x3200: p_cdc->ftdi.chip_type = FTDI_FT233HP; break; + case 0x3300: p_cdc->ftdi.chip_type = FTDI_FT232HP; break; + case 0x3600: p_cdc->ftdi.chip_type = FTDI_FT4232HA; break; + default: if (version < 0x200) { - p_cdc->ftdi.chip_type = SIO; + p_cdc->ftdi.chip_type = FTDI_SIO; p_cdc->ftdi.channel = 0; } break; } + #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + const char * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; TU_LOG_P_CDC("%s detected (bcdDevice = 0x%04x)", ftdi_chip_name[p_cdc->ftdi.chip_type], version); + #endif - return (p_cdc->ftdi.chip_type != UNKNOWN); + return (p_cdc->ftdi.chip_type != FTDI_UNKNOWN); } // FT232A not supported @@ -1589,9 +1590,9 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { TU_VERIFY(baud); switch (p_cdc->ftdi.chip_type) { - case UNKNOWN: + case FTDI_UNKNOWN: return 0; - case SIO: + case FTDI_SIO: switch (baud) { case 300: div_value = ftdi_sio_b300; break; case 600: div_value = ftdi_sio_b600; break; @@ -1620,23 +1621,23 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { // div_okay = false; // } // break; - case FT232B: - case FT2232C: - case FT232R: - case FTX: + case FTDI_FT232B: + case FTDI_FT2232C: + case FTDI_FT232R: + case FTDI_FTX: TU_VERIFY(baud <= 3000000); // else Baud rate too high! div_value = ftdi_232bm_baud_to_divisor(baud); break; - case FT232H: - case FT2232H: - case FT4232H: - case FT4232HA: - case FT232HP: - case FT233HP: - case FT2232HP: - case FT2233HP: - case FT4232HP: - case FT4233HP: + case FTDI_FT232H: + case FTDI_FT2232H: + case FTDI_FT4232H: + case FTDI_FT4232HA: + case FTDI_FT232HP: + case FTDI_FT233HP: + case FTDI_FT2232HP: + case FTDI_FT2233HP: + case FTDI_FT4232HP: + case FTDI_FT4233HP: default: TU_VERIFY(baud <= 12000000); // else Baud rate too high! if (baud >= 1200) { @@ -2273,8 +2274,7 @@ static uint8_t ch34x_get_lcr(cdch_interface_t *p_cdc) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_PL2303 -static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, - tuh_xfer_cb_t complete_cb, uintptr_t user_data); +static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step); static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); //------------- Control Request -------------// @@ -2313,14 +2313,13 @@ static bool pl2303_set_request(cdch_interface_t *p_cdc, uint8_t request, uint8_t static bool pl2303_vendor_read(cdch_interface_t *p_cdc, uint16_t value, uint8_t *buf, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; - + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN] ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_READ_REQUEST_TYPE, value, 0, buf, 1, complete_cb, user_data); } static bool pl2303_vendor_write(cdch_interface_t *p_cdc, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN] ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; + uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN] ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_WRITE_REQUEST_TYPE, value, index, NULL, 0, complete_cb, user_data); } @@ -2517,25 +2516,30 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { uint8_t buf = 0; int8_t type; - TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || xfer->user_data == CONFIG_PL2303_READ1)); + TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1)); switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_DETECT_TYPE: p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config // get type and quirks (step 1) - type = pl2303_detect_type(p_cdc, 1, cdch_process_set_config, CONFIG_PL2303_READ1); - TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); - if (type == PL2303_SUPPORTS_HX_STATUS_TRIGGERED) { + type = pl2303_detect_type(p_cdc, 1); + TU_ASSERT(type != PL2303_TYPE_UNKNOWN); + if (type == PL2303_TYPE_NEED_SUPPORTS_HX_STATUS) { + TU_ASSERT(pl2303_supports_hx_status(p_cdc, cdch_process_set_config, CONFIG_PL2303_READ1)); break; - }// else: no transfer triggered and continue with CONFIG_PL2303_READ1 - TU_ATTR_FALLTHROUGH; + } else { + // no transfer triggered and continue with CONFIG_PL2303_READ1 + TU_ATTR_FALLTHROUGH; + } case CONFIG_PL2303_READ1: // get supports_hx_status, type and quirks (step 2), do special read - p_cdc->pl2303.supports_hx_status = (// will not be true, if coming directly from previous case - xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS); - type = pl2303_detect_type(p_cdc, 2, NULL, 0); // step 2 now with supports_hx_status - TU_ASSERT(type != PL2303_DETECT_TYPE_FAILED); + // will not be true, if coming directly from previous case + if (xfer->user_data == CONFIG_PL2303_READ1 && xfer->result == XFER_RESULT_SUCCESS) { + p_cdc->pl2303.supports_hx_status = true; + } + type = pl2303_detect_type(p_cdc, 2); // step 2 now with supports_hx_status + TU_ASSERT(type != PL2303_TYPE_UNKNOWN); p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0// can be activated if necessary @@ -2549,7 +2553,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); #endif // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE1)); break; }// else: continue with next step @@ -2557,7 +2561,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE1: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 0, cdch_process_set_config, CONFIG_PL2303_READ2)); break; }// else: continue with next step @@ -2565,7 +2569,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ2: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ3)); break; }// else: continue with next step @@ -2573,7 +2577,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ3: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_READ4)); break; }// else: continue with next step @@ -2581,7 +2585,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ4: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE2)); break; }// else: continue with next step @@ -2589,7 +2593,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE2: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 1, cdch_process_set_config, CONFIG_PL2303_READ5)); break; }// else: continue with next step @@ -2597,7 +2601,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ5: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ6)); break; }// else: continue with next step @@ -2605,7 +2609,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ6: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE3)); break; }// else: continue with next step @@ -2613,7 +2617,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE3: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0, 1, cdch_process_set_config, CONFIG_PL2303_WRITE4)); break; }// else: continue with next step @@ -2621,7 +2625,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE4: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, 1, 0, cdch_process_set_config, CONFIG_PL2303_WRITE5)); break; }// else: continue with next step @@ -2629,7 +2633,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE5: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { uint16_t const windex = (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) ? 0x24 : 0x44; TU_ASSERT(pl2303_vendor_write(p_cdc, 2, windex, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP1)); break; @@ -2643,7 +2647,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP2)); } else { /* reset upstream data pipes */ - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG,// skip CONFIG_PL2303_RESET_ENDP2, no 2nd step PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); @@ -2659,7 +2663,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); } else { /* reset upstream data pipes */ - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { // here nothing to do, only structure of previous step overtaken for better reading and comparison } else { TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); @@ -2690,7 +2694,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program // case CONFIG_PL2303_FLOW_CTRL_READ: // // read flow control register for modify & write back in next step - // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { // TU_LOG_P_CDC ( "1\r\n" ); // TU_ASSERT(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, // cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); @@ -2703,7 +2707,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // case CONFIG_PL2303_FLOW_CTRL_WRITE: // // no flow control // buf = xfer->buffer[0]; - // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[TYPE_HXN]) { + // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { // buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; // buf |= PL2303_HXN_FLOWCTRL_NONE; // TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, @@ -2728,21 +2732,20 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { //------------- Helper -------------// -static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step) { tusb_desc_device_t desc_dev; - TU_VERIFY(tuh_descriptor_get_device_local(p_cdc->daddr, &desc_dev), PL2303_DETECT_TYPE_FAILED); + TU_VERIFY(tuh_descriptor_get_device_local(p_cdc->daddr, &desc_dev), PL2303_TYPE_UNKNOWN); // Legacy PL2303H, variants 0 and 1 (difference unknown). if (desc_dev.bDeviceClass == 0x02) { - return TYPE_H; /* variant 0 */ + return PL2303_TYPE_H; /* variant 0 */ } if (desc_dev.bMaxPacketSize0 != 0x40) { if (desc_dev.bDeviceClass == 0x00 || desc_dev.bDeviceClass == 0xff) { - return TYPE_H; /* variant 1 */ + return PL2303_TYPE_H; /* variant 1 */ } - return TYPE_H; /* variant 0 */ + return PL2303_TYPE_H; /* variant 0 */ } switch (desc_dev.bcdUSB) { @@ -2751,9 +2754,9 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, TU_ATTR_FALLTHROUGH; case 0x110: switch (desc_dev.bcdDevice) { - case 0x300: return TYPE_HX; - case 0x400: return TYPE_HXD; - default: return TYPE_HX; + case 0x300: return PL2303_TYPE_HX; + case 0x400: return PL2303_TYPE_HXD; + default: return PL2303_TYPE_HX; } break; @@ -2761,34 +2764,32 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, switch (desc_dev.bcdDevice) { case 0x100: /* GC */ case 0x105: - return TYPE_HXN; + return PL2303_TYPE_HXN; case 0x300: /* GT / TA */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request - TU_ASSERT(pl2303_supports_hx_status(p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); - return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; + return PL2303_TYPE_NEED_SUPPORTS_HX_STATUS; } else { // step 2 use supports_hx_status if (p_cdc->pl2303.supports_hx_status) { - return TYPE_TA; + return PL2303_TYPE_TA; } } TU_ATTR_FALLTHROUGH; case 0x305: case 0x400: /* GL */ case 0x405: - return TYPE_HXN; + return PL2303_TYPE_HXN; case 0x500: /* GE / TB */ if (step == 1) { // step 1 trigger pl2303_supports_hx_status() request - TU_ASSERT(pl2303_supports_hx_status(p_cdc, complete_cb, user_data), PL2303_DETECT_TYPE_FAILED); - return PL2303_SUPPORTS_HX_STATUS_TRIGGERED; + return PL2303_TYPE_NEED_SUPPORTS_HX_STATUS; } else { // step 2 use supports_hx_status if (p_cdc->pl2303.supports_hx_status) { - return TYPE_TB; + return PL2303_TYPE_TB; } } TU_ATTR_FALLTHROUGH; @@ -2797,7 +2798,7 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, case 0x605: case 0x700: /* GR */ case 0x705: - return TYPE_HXN; + return PL2303_TYPE_HXN; default: break; @@ -2807,7 +2808,7 @@ static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step, } TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev.bcdUSB); - return PL2303_DETECT_TYPE_FAILED; + return PL2303_TYPE_UNKNOWN; } /* diff --git a/src/class/cdc/serial/ftdi_sio.h b/src/class/cdc/serial/ftdi_sio.h index f621b3912..8abf74f11 100644 --- a/src/class/cdc/serial/ftdi_sio.h +++ b/src/class/cdc/serial/ftdi_sio.h @@ -165,48 +165,48 @@ enum ftdi_sio_baudrate { #define FTDI_RS_FIFO (1 << 7) // chip types and names -enum ftdi_chip_type { - SIO = 0, -// FT232A, - FT232B, - FT2232C, - FT232R, - FT232H, - FT2232H, - FT4232H, - FT4232HA, - FT232HP, - FT233HP, - FT2232HP, - FT2233HP, - FT4232HP, - FT4233HP, - FTX, - UNKNOWN -}; +typedef enum ftdi_chip_type { + FTDI_SIO = 0, +// FTDI_FT232A, + FTDI_FT232B, + FTDI_FT2232C, + FTDI_FT232R, + FTDI_FT232H, + FTDI_FT2232H, + FTDI_FT4232H, + FTDI_FT4232HA, + FTDI_FT232HP, + FTDI_FT233HP, + FTDI_FT2232HP, + FTDI_FT2233HP, + FTDI_FT4232HP, + FTDI_FT4233HP, + FTDI_FTX, + FTDI_UNKNOWN +} ftdi_chip_type_t; #define FTDI_CHIP_NAMES \ - [SIO] = (uint8_t const*) "SIO", /* the serial part of FT8U100AX */ \ -/* [FT232A] = (uint8_t const*) "FT232A", */ \ - [FT232B] = (uint8_t const*) "FT232B", \ - [FT2232C] = (uint8_t const*) "FT2232C/D", \ - [FT232R] = (uint8_t const*) "FT232R", \ - [FT232H] = (uint8_t const*) "FT232H", \ - [FT2232H] = (uint8_t const*) "FT2232H", \ - [FT4232H] = (uint8_t const*) "FT4232H", \ - [FT4232HA] = (uint8_t const*) "FT4232HA", \ - [FT232HP] = (uint8_t const*) "FT232HP", \ - [FT233HP] = (uint8_t const*) "FT233HP", \ - [FT2232HP] = (uint8_t const*) "FT2232HP", \ - [FT2233HP] = (uint8_t const*) "FT2233HP", \ - [FT4232HP] = (uint8_t const*) "FT4232HP", \ - [FT4233HP] = (uint8_t const*) "FT4233HP", \ - [FTX] = (uint8_t const*) "FT-X", \ - [UNKNOWN] = (uint8_t const*) "UNKNOWN" + [FTDI_SIO] = "SIO", /* the serial part of FT8U100AX */ \ +/* [FTDI_FT232A] = "FT232A", */ \ + [FTDI_FT232B] = "FT232B", \ + [FTDI_FT2232C] = "FT2232C/D", \ + [FTDI_FT232R] = "FT232R", \ + [FTDI_FT232H] = "FT232H", \ + [FTDI_FT2232H] = "FTDI_FT2232H", \ + [FTDI_FT4232H] = "FT4232H", \ + [FTDI_FT4232HA] = "FT4232HA", \ + [FTDI_FT232HP] = "FT232HP", \ + [FTDI_FT233HP] = "FT233HP", \ + [FTDI_FT2232HP] = "FT2232HP", \ + [FTDI_FT2233HP] = "FT2233HP", \ + [FTDI_FT4232HP] = "FT4232HP", \ + [FTDI_FT4233HP] = "FT4233HP", \ + [FTDI_FTX] = "FT-X", \ + [FTDI_UNKNOWN] = "UNKNOWN" // private interface data typedef struct ftdi_private { - enum ftdi_chip_type chip_type; + ftdi_chip_type_t chip_type; uint8_t channel; // channel index, or 0 for legacy types } ftdi_private_t; diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h index d69bdbfae..40311260d 100644 --- a/src/class/cdc/serial/pl2303.h +++ b/src/class/cdc/serial/pl2303.h @@ -96,51 +96,53 @@ #define PL2303_HXN_FLOWCTRL_XON_XOFF 0x0c // type data -enum pl2303_type { - TYPE_H, - TYPE_HX, - TYPE_TA, - TYPE_TB, - TYPE_HXD, - TYPE_HXN, - TYPE_COUNT -}; - -struct pl2303_type_data { +typedef enum pl2303_type { + PL2303_TYPE_H, + PL2303_TYPE_HX, + PL2303_TYPE_TA, + PL2303_TYPE_TB, + PL2303_TYPE_HXD, + PL2303_TYPE_HXN, + // PL2303_TYPE_NEED_SUPPORTS_HX_STATUS, + // PL2303_TYPE_UNKNOWN, + PL2303_TYPE_COUNT +} pl2303_type_t; + +typedef struct pl2303_type_data { uint8_t const *name; uint32_t const max_baud_rate; uint8_t const quirks; uint16_t const no_autoxonxoff:1; uint16_t const no_divisors:1; uint16_t const alt_divisors:1; -}; +} pl2303_type_data_t; #define PL2303_TYPE_DATA \ - [TYPE_H] = { \ + [PL2303_TYPE_H] = { \ .name = (uint8_t const*)"H", \ .max_baud_rate = 1228800, \ .quirks = PL2303_QUIRK_LEGACY, \ .no_autoxonxoff = true, \ }, \ - [TYPE_HX] = { \ + [PL2303_TYPE_HX] = { \ .name = (uint8_t const*)"HX", \ .max_baud_rate = 6000000, \ }, \ - [TYPE_TA] = { \ + [PL2303_TYPE_TA] = { \ .name = (uint8_t const*)"TA", \ .max_baud_rate = 6000000, \ .alt_divisors = true, \ }, \ - [TYPE_TB] = { \ + [PL2303_TYPE_TB] = { \ .name = (uint8_t const*)"TB", \ .max_baud_rate = 12000000, \ .alt_divisors = true, \ }, \ - [TYPE_HXD] = { \ + [PL2303_TYPE_HXD] = { \ .name = (uint8_t const*)"HXD", \ .max_baud_rate = 12000000, \ }, \ - [TYPE_HXN] = { \ + [PL2303_TYPE_HXN] = { \ .name = (uint8_t const*)"G (HXN)", \ .max_baud_rate = 12000000, \ .no_divisors = true, \ @@ -166,7 +168,7 @@ typedef struct TU_ATTR_PACKED { #define PL2303_IN_EP 0x83 // return values of pl2303_detect_type() -#define PL2303_SUPPORTS_HX_STATUS_TRIGGERED -1 -#define PL2303_DETECT_TYPE_FAILED -2 +#define PL2303_TYPE_NEED_SUPPORTS_HX_STATUS -1 +#define PL2303_TYPE_UNKNOWN -2 #endif // TUSB_PL2303_H -- cgit v1.3.1 From ec1a26251d0161d5e7c11f4ca552af154cf08dbd Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 19 Jun 2025 17:05:21 +0700 Subject: clean up pl2303 type data --- src/class/cdc/cdc_host.c | 130 +++++++++++++++++++----------------------- src/class/cdc/serial/pl2303.h | 46 +++++---------- 2 files changed, 74 insertions(+), 102 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ce98e3b3d..dae38ba42 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -2274,7 +2274,7 @@ static uint8_t ch34x_get_lcr(cdch_interface_t *p_cdc) { //--------------------------------------------------------------------+ #if CFG_TUH_CDC_PL2303 -static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step); +static pl2303_type_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step); static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]); //------------- Control Request -------------// @@ -2313,20 +2313,18 @@ static bool pl2303_set_request(cdch_interface_t *p_cdc, uint8_t request, uint8_t static bool pl2303_vendor_read(cdch_interface_t *p_cdc, uint16_t value, uint8_t *buf, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN] ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; + uint8_t request = p_cdc->pl2303.type == PL2303_TYPE_HXN ? PL2303_VENDOR_READ_NREQUEST : PL2303_VENDOR_READ_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_READ_REQUEST_TYPE, value, 0, buf, 1, complete_cb, user_data); } static bool pl2303_vendor_write(cdch_interface_t *p_cdc, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t request = p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN] ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; - + uint8_t request = p_cdc->pl2303.type == PL2303_TYPE_HXN ? PL2303_VENDOR_WRITE_NREQUEST : PL2303_VENDOR_WRITE_REQUEST; return pl2303_set_request(p_cdc, request, PL2303_VENDOR_WRITE_REQUEST_TYPE, value, index, NULL, 0, complete_cb, user_data); } static inline bool pl2303_supports_hx_status(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint8_t buf = 0; - return pl2303_set_request(p_cdc, PL2303_VENDOR_READ_REQUEST, PL2303_VENDOR_READ_REQUEST_TYPE, PL2303_READ_TYPE_HX_STATUS, 0, &buf, 1, complete_cb, user_data); } @@ -2425,7 +2423,6 @@ static void pl2303_internal_control_complete(tuh_xfer_t *xfer) { static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); - return true; } @@ -2433,7 +2430,6 @@ static bool pl2303_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t comple p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); - return true; } @@ -2443,7 +2439,6 @@ static bool pl2303_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); - return true; } @@ -2451,7 +2446,6 @@ static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet // PL2303 has the same bit coding p_cdc->user_control_cb = complete_cb; TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); - return true; } @@ -2488,7 +2482,7 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui TU_VERIFY(p_cdc); p_cdc->serial_drid = SERIAL_DRIVER_PL2303; - p_cdc->pl2303.serial_private.quirks = 0; + p_cdc->pl2303.quirks = 0; p_cdc->pl2303.supports_hx_status = false; tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc); @@ -2514,7 +2508,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() uint8_t buf = 0; - int8_t type; + pl2303_type_t type; TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1)); switch (state) { @@ -2540,20 +2534,13 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { } type = pl2303_detect_type(p_cdc, 2); // step 2 now with supports_hx_status TU_ASSERT(type != PL2303_TYPE_UNKNOWN); - p_cdc->pl2303.serial_private.type = &pl2303_type_data[type]; - p_cdc->pl2303.serial_private.quirks |= p_cdc->pl2303.serial_private.type->quirks; - #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL && 0// can be activated if necessary - TU_LOG_P_CDC("bDeviceClass = 0x%02x bMaxPacketSize0 = %u bcdUSB = 0x%04x bcdDevice = 0x%04x", - desc_dev->bDeviceClass, desc_dev->bMaxPacketSize0, - desc_dev->bcdUSB, desc_dev->bcdDevice); - uint16_t vid, pid; - TU_ASSERT(tuh_vid_pid_get(p_cdc->daddr, &vid, &pid)); - TU_LOG_P_CDC("vid = 0x%04x pid = 0x%04x supports_hx_status = %u type = %s quirks = %u", - vid, pid, p_cdc->pl2303.supports_hx_status, - p_cdc->pl2303.serial_private.type->name, p_cdc->pl2303.serial_private.quirks); - #endif + TU_LOG_DRV(" PL2303 type detected: %u\r\n", type); + + p_cdc->pl2303.type = type; + p_cdc->pl2303.quirks |= pl2303_type_data[type].quirks; + // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE1)); break; }// else: continue with next step @@ -2561,7 +2548,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE1: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 0, cdch_process_set_config, CONFIG_PL2303_READ2)); break; }// else: continue with next step @@ -2569,7 +2556,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ2: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ3)); break; }// else: continue with next step @@ -2577,7 +2564,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ3: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_READ4)); break; }// else: continue with next step @@ -2585,7 +2572,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ4: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE2)); break; }// else: continue with next step @@ -2593,7 +2580,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE2: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0x0404, 1, cdch_process_set_config, CONFIG_PL2303_READ5)); break; }// else: continue with next step @@ -2601,7 +2588,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ5: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ6)); break; }// else: continue with next step @@ -2609,7 +2596,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_READ6: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE3)); break; }// else: continue with next step @@ -2617,7 +2604,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE3: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, 0, 1, cdch_process_set_config, CONFIG_PL2303_WRITE4)); break; }// else: continue with next step @@ -2625,7 +2612,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE4: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, 1, 0, cdch_process_set_config, CONFIG_PL2303_WRITE5)); break; }// else: continue with next step @@ -2633,21 +2620,21 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_WRITE5: // purpose unknown, overtaken from Linux Kernel driver - if (p_cdc->pl2303.serial_private.type != &pl2303_type_data[PL2303_TYPE_HXN]) { - uint16_t const windex = (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) ? 0x24 : 0x44; + if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { + uint16_t const windex = (p_cdc->pl2303.quirks & PL2303_QUIRK_LEGACY) ? 0x24 : 0x44; TU_ASSERT(pl2303_vendor_write(p_cdc, 2, windex, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP1)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; - // from here sequence overtaken from Linux Kernel function pl2303_open() + // from here sequence overtaken from Linux Kernel function pl2303_open() case CONFIG_PL2303_RESET_ENDP1: // step 1 - if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { + if (p_cdc->pl2303.quirks & PL2303_QUIRK_LEGACY) { TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_OUT_EP, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP2)); } else { /* reset upstream data pipes */ - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG,// skip CONFIG_PL2303_RESET_ENDP2, no 2nd step PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); @@ -2659,11 +2646,11 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_RESET_ENDP2: // step 2 - if (p_cdc->pl2303.serial_private.quirks & PL2303_QUIRK_LEGACY) { + if (p_cdc->pl2303.quirks & PL2303_QUIRK_LEGACY) { TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); } else { /* reset upstream data pipes */ - if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { + if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { // here nothing to do, only structure of previous step overtaken for better reading and comparison } else { TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); @@ -2691,33 +2678,33 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { TU_ATTR_FALLTHROUGH; #endif - // skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program - // case CONFIG_PL2303_FLOW_CTRL_READ: - // // read flow control register for modify & write back in next step - // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { - // TU_LOG_P_CDC ( "1\r\n" ); - // TU_ASSERT(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, - // cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); - // } else { - // TU_LOG_P_CDC ( "2\r\n" ); - // TU_ASSERT(pl2303_vendor_read(p_cdc, 0, &buf, cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); - // } - // break; - // - // case CONFIG_PL2303_FLOW_CTRL_WRITE: - // // no flow control - // buf = xfer->buffer[0]; - // if (p_cdc->pl2303.serial_private.type == &pl2303_type_data[PL2303_TYPE_HXN]) { - // buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; - // buf |= PL2303_HXN_FLOWCTRL_NONE; - // TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, - // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); - // } else { - // buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; - // TU_ASSERT(pl2303_vendor_write(p_cdc, 0, buf, - // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); - // } - // break; + // skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program + // case CONFIG_PL2303_FLOW_CTRL_READ: + // // read flow control register for modify & write back in next step + // if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { + // TU_LOG_P_CDC ( "1\r\n" ); + // TU_ASSERT(pl2303_vendor_read(p_cdc, PL2303_HXN_FLOWCTRL_REG, &buf, + // cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); + // } else { + // TU_LOG_P_CDC ( "2\r\n" ); + // TU_ASSERT(pl2303_vendor_read(p_cdc, 0, &buf, cdch_process_set_config, CONFIG_PL2303_FLOW_CTRL_WRITE)); + // } + // break; + // + // case CONFIG_PL2303_FLOW_CTRL_WRITE: + // // no flow control + // buf = xfer->buffer[0]; + // if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { + // buf &= (uint8_t) ~PL2303_HXN_FLOWCTRL_MASK; + // buf |= PL2303_HXN_FLOWCTRL_NONE; + // TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_FLOWCTRL_REG, buf, + // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); + // } else { + // buf &= (uint8_t) ~PL2303_FLOWCTRL_MASK; + // TU_ASSERT(pl2303_vendor_write(p_cdc, 0, buf, + // cdch_process_set_config, CONFIG_PL2303_COMPLETE)); + // } + // break; case CONFIG_PL2303_COMPLETE: set_config_complete(idx, 0, true); @@ -2732,7 +2719,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { //------------- Helper -------------// -static int8_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step) { +static pl2303_type_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step) { tusb_desc_device_t desc_dev; TU_VERIFY(tuh_descriptor_get_device_local(p_cdc->daddr, &desc_dev), PL2303_TYPE_UNKNOWN); @@ -2932,13 +2919,14 @@ static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODI static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]) { uint32_t baud = p_cdc->requested_line_coding.bit_rate; uint32_t baud_sup; + const pl2303_type_data_t* type_data = &pl2303_type_data[p_cdc->pl2303.type]; - TU_VERIFY(baud && baud <= p_cdc->pl2303.serial_private.type->max_baud_rate); + TU_VERIFY(baud && baud <= type_data->max_baud_rate); /* * Use direct method for supported baud rates, otherwise use divisors. * Newer chip types do not support divisor encoding. */ - if (p_cdc->pl2303.serial_private.type->no_divisors) { + if (type_data->no_divisors) { baud_sup = baud; } else { baud_sup = pl2303_get_supported_baud_rate(baud); @@ -2946,7 +2934,7 @@ static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_ if (baud == baud_sup) { baud = pl2303_encode_baud_rate_direct(buf, baud); - } else if (p_cdc->pl2303.serial_private.type->alt_divisors) { + } else if (type_data->alt_divisors) { baud = pl2303_encode_baud_rate_divisor_alt(buf, baud); } else { baud = pl2303_encode_baud_rate_divisor(buf, baud); diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h index 40311260d..c01dac0e1 100644 --- a/src/class/cdc/serial/pl2303.h +++ b/src/class/cdc/serial/pl2303.h @@ -97,65 +97,53 @@ // type data typedef enum pl2303_type { - PL2303_TYPE_H, - PL2303_TYPE_HX, - PL2303_TYPE_TA, - PL2303_TYPE_TB, - PL2303_TYPE_HXD, - PL2303_TYPE_HXN, - // PL2303_TYPE_NEED_SUPPORTS_HX_STATUS, - // PL2303_TYPE_UNKNOWN, - PL2303_TYPE_COUNT + PL2303_TYPE_H = 0, // 0 + PL2303_TYPE_HX, // 1 + PL2303_TYPE_TA, // 2 + PL2303_TYPE_TB, // 3 + PL2303_TYPE_HXD, // 4 + PL2303_TYPE_HXN, // 5 + PL2303_TYPE_COUNT, + PL2303_TYPE_NEED_SUPPORTS_HX_STATUS, + PL2303_TYPE_UNKNOWN, } pl2303_type_t; typedef struct pl2303_type_data { - uint8_t const *name; uint32_t const max_baud_rate; - uint8_t const quirks; - uint16_t const no_autoxonxoff:1; - uint16_t const no_divisors:1; - uint16_t const alt_divisors:1; + uint8_t const quirks; + uint8_t const no_autoxonxoff : 1; + uint8_t const no_divisors : 1; + uint8_t const alt_divisors : 1; } pl2303_type_data_t; #define PL2303_TYPE_DATA \ [PL2303_TYPE_H] = { \ - .name = (uint8_t const*)"H", \ .max_baud_rate = 1228800, \ .quirks = PL2303_QUIRK_LEGACY, \ .no_autoxonxoff = true, \ }, \ [PL2303_TYPE_HX] = { \ - .name = (uint8_t const*)"HX", \ .max_baud_rate = 6000000, \ }, \ [PL2303_TYPE_TA] = { \ - .name = (uint8_t const*)"TA", \ .max_baud_rate = 6000000, \ .alt_divisors = true, \ }, \ [PL2303_TYPE_TB] = { \ - .name = (uint8_t const*)"TB", \ .max_baud_rate = 12000000, \ .alt_divisors = true, \ }, \ [PL2303_TYPE_HXD] = { \ - .name = (uint8_t const*)"HXD", \ .max_baud_rate = 12000000, \ }, \ [PL2303_TYPE_HXN] = { \ - .name = (uint8_t const*)"G (HXN)", \ .max_baud_rate = 12000000, \ .no_divisors = true, \ } -// private data types -struct pl2303_serial_private { - const struct pl2303_type_data* type; - uint8_t quirks; -}; - typedef struct TU_ATTR_PACKED { - struct pl2303_serial_private serial_private; + pl2303_type_t type; + uint8_t quirks; bool supports_hx_status; } pl2303_private_t; @@ -167,8 +155,4 @@ typedef struct TU_ATTR_PACKED { #define PL2303_OUT_EP 0x02 #define PL2303_IN_EP 0x83 -// return values of pl2303_detect_type() -#define PL2303_TYPE_NEED_SUPPORTS_HX_STATUS -1 -#define PL2303_TYPE_UNKNOWN -2 - #endif // TUSB_PL2303_H -- cgit v1.3.1 From fa3ec44533ff986688318c3f80e9f373f55318f0 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 19 Jun 2025 17:22:26 +0700 Subject: revert CFG_TUH_CDC_DTR/RTS_CONTROL_ON_ENUM --- examples/host/cdc_msc_hid/src/tusb_config.h | 5 +-- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 3 +- src/class/cdc/cdc.h | 14 +++---- src/class/cdc/cdc_host.c | 49 +++++++--------------- 4 files changed, 24 insertions(+), 47 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index 4bd5b0472..e610c5672 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -103,7 +103,7 @@ #define CFG_TUH_ENUMERATION_BUFSIZE 256 #define CFG_TUH_HUB 1 // number of supported hubs -#define CFG_TUH_CDC 1 // number of supported CDC devices. also activates CDC ACM +#define CFG_TUH_CDC 4 // number of supported CDC devices. also activates CDC ACM #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API @@ -122,8 +122,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -#define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM true -#define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM true +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM (CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 94b121672..05deecba0 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -127,8 +127,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: -#define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM true -#define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM true +#define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM (CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 10aed79ab..9f3ace63c 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -404,8 +404,7 @@ static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc) //--------------------------------------------------------------------+ // Requests //--------------------------------------------------------------------+ -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint32_t bit_rate; uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space @@ -414,14 +413,13 @@ typedef struct TU_ATTR_PACKED TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); -typedef union TU_ATTR_PACKED -{ +typedef union TU_ATTR_PACKED { struct { - uint8_t dtr : 1; - uint8_t rts : 1; - uint8_t : 6; + uint8_t dtr : 1; + uint8_t rts : 1; + uint8_t : 6; }; - uint8_t all; + uint8_t value; } cdc_line_control_state_t; TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 1, "size is not correct"); diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index dae38ba42..7259e819f 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -52,25 +52,6 @@ serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) #define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %d", VAL) -// handle line control defines -#if defined(CFG_TUH_CDC_LINE_CONTROL_ON_ENUM) && \ - (defined(CFG_TUH_CDC_DTR_CONTROL_ON_ENUM) || defined(CFG_TUH_CDC_RTS_CONTROL_ON_ENUM)) - TU_VERIFY_STATIC(false, "Contradictory line control defines"); -#endif - -#ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - #define LINE_CONTROL_ON_ENUM CFG_TUH_CDC_LINE_CONTROL_ON_ENUM -#elif defined(CFG_TUH_CDC_DTR_CONTROL_ON_ENUM) || defined(CFG_TUH_CDC_RTS_CONTROL_ON_ENUM) - #ifndef CFG_TUH_CDC_DTR_CONTROL_ON_ENUM - #define CFG_TUH_CDC_DTR_CONTROL_ON_ENUM 0 - #endif - #ifndef CFG_TUH_CDC_RTS_CONTROL_ON_ENUM - #define CFG_TUH_CDC_RTS_CONTROL_ON_ENUM 0 - #endif - #define LINE_CONTROL_ON_ENUM ( ( CFG_TUH_CDC_DTR_CONTROL_ON_ENUM ? CDC_CONTROL_LINE_STATE_DTR : 0 ) | \ - ( CFG_TUH_CDC_RTS_CONTROL_ON_ENUM ? CDC_CONTROL_LINE_STATE_RTS : 0 ) ) -#endif - //--------------------------------------------------------------------+ // Host CDC Interface //--------------------------------------------------------------------+ @@ -396,7 +377,7 @@ static cdch_interface_t * make_new_itf(uint8_t daddr, tusb_desc_interface_t cons p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; p_cdc->line_coding = (cdc_line_coding_t) { 0, 0, 0, 0 }; - p_cdc->line_state.all = 0; + p_cdc->line_state.value = 0; return p_cdc; } } @@ -661,7 +642,7 @@ bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // uses uint16_t for line_state => DTR (bit 0), RTS (bit 1) - return tuh_cdc_set_control_line_state_u(idx, (cdc_line_control_state_t) { .all = (uint8_t) line_state }, + return tuh_cdc_set_control_line_state_u(idx, (cdc_line_control_state_t) { .value = (uint8_t) line_state }, complete_cb, user_data); } @@ -1004,7 +985,7 @@ static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t co .direction = TUSB_DIR_OUT }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16((uint16_t) p_cdc->requested_line_state.all), + .wValue = tu_htole16((uint16_t) p_cdc->requested_line_state.value), .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = 0 }; @@ -1137,9 +1118,9 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: - #ifdef LINE_CONTROL_ON_ENUM + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, CONFIG_ACM_SET_LINE_CODING)); break; } @@ -1426,8 +1407,8 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { break; case CONFIG_FTDI_MODEM_CTRL: - #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); break; @@ -1735,7 +1716,7 @@ static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | - p_cdc->requested_line_state.all), + p_cdc->requested_line_state.value), NULL, 0, complete_cb, user_data); } @@ -1873,8 +1854,8 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { #endif case CONFIG_CP210X_SET_DTR_RTS: - #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; @@ -2153,8 +2134,8 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { break; case CONFIG_CH34X_MODEM_CONTROL: - #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; p_cdc->user_control_cb = cdch_process_set_config; TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; @@ -2332,7 +2313,7 @@ static inline bool pl2303_supports_hx_status(cdch_interface_t *p_cdc, tuh_xfer_c static inline bool pl2303_set_control_lines(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, - p_cdc->requested_line_state.all, 0, NULL, 0, complete_cb, user_data); + p_cdc->requested_line_state.value, 0, NULL, 0, complete_cb, user_data); } //static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) @@ -2670,8 +2651,8 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { #endif case CONFIG_PL2303_MODEM_CONTROL: - #ifdef LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.all = LINE_CONTROL_ON_ENUM; + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); break; #else -- cgit v1.3.1 From ce9140a150f685ae228362c5fcd0b85a7900e67a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 19 Jun 2025 17:57:21 +0700 Subject: rename tuh_cdc_get_local_line_coding to tuh_cdc_get_line_coding_local add tuh_cdc_get_control_line_state_local() implement tuh_cdc_get/set_dtr/rts() as inline --- src/class/cdc/cdc_host.c | 55 ++++++++---------------------------------------- src/class/cdc/cdc_host.h | 45 +++++++++++++++++++++++++++++---------- 2 files changed, 43 insertions(+), 57 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 7259e819f..80b01f928 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -427,27 +427,14 @@ bool tuh_cdc_mounted(uint8_t idx) { return p_cdc->mounted; } -bool tuh_cdc_get_dtr(uint8_t idx) { +bool tuh_cdc_get_control_line_state_local(uint8_t idx, uint16_t* line_state) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - - bool ret = p_cdc->line_state.dtr; -// TU_LOG_P_CDC_BOOL("get DTR", ret); - - return ret; -} - -bool tuh_cdc_get_rts(uint8_t idx) { - cdch_interface_t * p_cdc = get_itf(idx); - TU_VERIFY(p_cdc); - - bool ret = p_cdc->line_state.rts; -// TU_LOG_P_CDC_BOOL("get RTS", ret); - - return ret; + *line_state = p_cdc->line_state.value; + return true; } -bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t * line_coding) { +bool tuh_cdc_get_line_coding_local(uint8_t idx, cdc_line_coding_t * line_coding) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); @@ -622,46 +609,22 @@ static bool set_function_call ( } } -bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // uses cdc_line_control_state_t union for line_state +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set control line state dtr = %u rts = %u", line_state.dtr, line_state.rts); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_state = line_state; + p_cdc->requested_line_state.value = (uint8_t) line_state; + TU_LOG_P_CDC("set control line state dtr = %u rts = %u", p_cdc->requested_line_state.dtr, p_cdc->requested_line_state.rts); - bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); + const bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_state = line_state; + p_cdc->line_state = p_cdc->requested_line_state; } return ret; } -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // uses uint16_t for line_state => DTR (bit 0), RTS (bit 1) - - return tuh_cdc_set_control_line_state_u(idx, (cdc_line_control_state_t) { .value = (uint8_t) line_state }, - complete_cb, user_data); -} - -bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t * p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - cdc_line_control_state_t const line_state = { .dtr = dtr_state, .rts = p_cdc->line_state.rts }; - - return tuh_cdc_set_control_line_state_u(idx, line_state, complete_cb, user_data); -} - -bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - cdch_interface_t *p_cdc = get_itf(idx); - TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - cdc_line_control_state_t const line_state = {.rts = rts_state, .dtr = p_cdc->line_state.dtr}; - - return tuh_cdc_set_control_line_state_u(idx, line_state, complete_cb, user_data); -} - bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 63eb1fc0f..688164cb2 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -69,14 +69,27 @@ uint8_t tuh_cdc_itf_get_index(uint8_t daddr, uint8_t itf_num); // return true if index is correct and interface is currently mounted bool tuh_cdc_itf_get_info(uint8_t idx, tuh_itf_info_t* info); -// Check if a interface is mounted +// Check if an interface is mounted bool tuh_cdc_mounted(uint8_t idx); +// Get local (cached) line state +// This function should return correct values if tuh_cdc_set_control_line_state() / tuh_cdc_get_control_line_state() +// are invoked previously or CFG_TUH_CDC_LINE_STATE_ON_ENUM is defined. +bool tuh_cdc_get_control_line_state_local(uint8_t idx, uint16_t* line_state); + // Get current DTR status -bool tuh_cdc_get_dtr(uint8_t idx); +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_get_dtr(uint8_t idx) { + uint16_t line_state; + TU_VERIFY(tuh_cdc_get_control_line_state_local(idx, &line_state)); + return (line_state & CDC_CONTROL_LINE_STATE_DTR) != 0; +} // Get current RTS status -bool tuh_cdc_get_rts(uint8_t idx); +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_get_rts(uint8_t idx) { + uint16_t line_state; + TU_VERIFY(tuh_cdc_get_control_line_state_local(idx, &line_state)); + return (line_state & CDC_CONTROL_LINE_STATE_RTS) != 0; +} // Check if interface is connected (DTR active) TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) { @@ -87,7 +100,9 @@ TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) { // This function should return correct values if tuh_cdc_set_line_coding() / tuh_cdc_get_line_coding() // are invoked previously or CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined. // NOTE: This function does not make any USB transfer request to device. -bool tuh_cdc_get_local_line_coding(uint8_t idx, cdc_line_coding_t* line_coding); +bool tuh_cdc_get_line_coding_local(uint8_t idx, cdc_line_coding_t* line_coding); + +#define tuh_cdc_get_local_line_coding tuh_cdc_get_line_coding_local // backward compatibility //--------------------------------------------------------------------+ // Write API @@ -131,14 +146,22 @@ bool tuh_cdc_read_clear (uint8_t idx); // - The function will return true if transfer is successful, false otherwise. //--------------------------------------------------------------------+ -// Request to Set Control Line State -bool tuh_cdc_set_control_line_state_u(uint8_t idx, cdc_line_control_state_t line_state, // uses cdc_line_control_state_t union for line_state - tuh_xfer_cb_t complete_cb, uintptr_t user_data); -bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, // uses uint16_t for line_state (legacy function) - tuh_xfer_cb_t complete_cb, uintptr_t user_data); // DTR (bit 0), RTS (bit 1) +// Request to Set Control Line State: DTR (bit 0), RTS (bit 1) +bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Set DTR -bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data); // Request to Set RTS +// Request to Set DTR +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_set_dtr(uint8_t idx, bool dtr_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdc_line_control_state_t line_state = { .dtr = dtr_state }; + line_state.rts = tuh_cdc_get_rts(idx); + return tuh_cdc_set_control_line_state(idx, line_state.value, complete_cb, user_data); +} + +// Request to Set RTS +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_set_rts(uint8_t idx, bool rts_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + cdc_line_control_state_t line_state = { .rts = rts_state }; + line_state.dtr = tuh_cdc_get_dtr(idx); + return tuh_cdc_set_control_line_state(idx, line_state.value, complete_cb, user_data); +} // Request to set baudrate bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -- cgit v1.3.1 From 221b5288e43feff140c695af4481b7815f1b56cd Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 19 Jun 2025 18:14:24 +0700 Subject: union ftdi/pl2303/acm data to save memory. --- src/class/cdc/cdc_host.c | 281 ++++++++++++++++++++++++----------------------- 1 file changed, 142 insertions(+), 139 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 80b01f928..2fe2c85bc 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -65,27 +65,30 @@ typedef struct { uint8_t ep_notif; uint8_t serial_drid; // Serial Driver ID bool mounted; // Enumeration is complete - cdc_acm_capability_t acm_capability; - TU_ATTR_ALIGNED(4) cdc_line_coding_t line_coding; // Baudrate, stop bits, parity, data width - TU_ATTR_ALIGNED(4) cdc_line_coding_t requested_line_coding; - // 1 byte padding - - cdc_line_control_state_t line_state; - cdc_line_control_state_t requested_line_state; + struct { + TU_ATTR_ALIGNED(4) cdc_line_coding_t coding; // Baudrate, stop bits, parity, data width + cdc_line_control_state_t control_state; // DTR, RTS + } line, requested_line; - tuh_xfer_cb_t user_control_cb; + tuh_xfer_cb_t user_complete_cb; // required since we handle request internally first #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X tuh_xfer_cb_t requested_complete_cb; #endif - #if CFG_TUH_CDC_FTDI + union { + struct { + cdc_acm_capability_t capability; + } acm; + + #if CFG_TUH_CDC_FTDI ftdi_private_t ftdi; - #endif + #endif - #if CFG_TUH_CDC_PL2303 + #if CFG_TUH_CDC_PL2303 pl2303_private_t pl2303; - #endif + #endif + }; struct { tu_edpt_stream_t tx; @@ -376,8 +379,8 @@ static cdch_interface_t * make_new_itf(uint8_t daddr, tusb_desc_interface_t cons p_cdc->bInterfaceNumber = itf_desc->bInterfaceNumber; p_cdc->bInterfaceSubClass = itf_desc->bInterfaceSubClass; p_cdc->bInterfaceProtocol = itf_desc->bInterfaceProtocol; - p_cdc->line_coding = (cdc_line_coding_t) { 0, 0, 0, 0 }; - p_cdc->line_state.value = 0; + p_cdc->line.coding = (cdc_line_coding_t) { 0, 0, 0, 0 }; + p_cdc->line.control_state.value = 0; return p_cdc; } } @@ -430,7 +433,7 @@ bool tuh_cdc_mounted(uint8_t idx) { bool tuh_cdc_get_control_line_state_local(uint8_t idx, uint16_t* line_state) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - *line_state = p_cdc->line_state.value; + *line_state = p_cdc->line.control_state.value; return true; } @@ -438,10 +441,10 @@ bool tuh_cdc_get_line_coding_local(uint8_t idx, cdc_line_coding_t * line_coding) cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - *line_coding = p_cdc->line_coding; + *line_coding = p_cdc->line.coding; TU_LOG_P_CDC("get line coding %lu %u%c%s", - p_cdc->line_coding.bit_rate, p_cdc->line_coding.data_bits, - CDC_LINE_CODING_PARITY_CHAR(p_cdc->line_coding.parity), + p_cdc->line.coding.bit_rate, p_cdc->line.coding.data_bits, + CDC_LINE_CODING_PARITY_CHAR(p_cdc->line.coding.parity), CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); return true; @@ -533,7 +536,7 @@ static bool set_line_coding_sequence( // non-blocking // stage 1 set baudrate p_cdc->requested_complete_cb = complete_cb; // store complete_cb to be used in set_line_coding_stage1_complete() - p_cdc->user_control_cb = set_line_coding_stage1_complete; + p_cdc->user_complete_cb = set_line_coding_stage1_complete; return set_baudrate_request(p_cdc, internal_control_complete, user_data); } else { // blocking sequence @@ -549,7 +552,7 @@ static bool set_line_coding_sequence( TU_VERIFY(result == XFER_RESULT_SUCCESS); // overtake baudrate after successful request - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; // stage 2 set data format result = XFER_RESULT_INVALID; @@ -577,7 +580,7 @@ static void set_line_coding_stage1_complete( if (xfer->result == XFER_RESULT_SUCCESS) { // stage 1 success, continue with stage 2 - p_cdc->user_control_cb = p_cdc->requested_complete_cb; + p_cdc->user_complete_cb = p_cdc->requested_complete_cb; set_data_format_request(p_cdc, internal_control_complete, xfer->user_data); } else { // stage 1 failed, notify user @@ -614,13 +617,13 @@ bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_c TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_state.value = (uint8_t) line_state; - TU_LOG_P_CDC("set control line state dtr = %u rts = %u", p_cdc->requested_line_state.dtr, p_cdc->requested_line_state.rts); + p_cdc->requested_line.control_state.value = (uint8_t) line_state; + TU_LOG_P_CDC("set control line state dtr = %u rts = %u", p_cdc->requested_line.control_state.dtr, p_cdc->requested_line.control_state.rts); const bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; } return ret; } @@ -631,12 +634,12 @@ bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete TU_LOG_P_CDC("set baudrate %lu", baudrate); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_coding.bit_rate = baudrate; + p_cdc->requested_line.coding.bit_rate = baudrate; bool ret = set_function_call(p_cdc, driver->set_baudrate, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_coding.bit_rate = baudrate; + p_cdc->line.coding.bit_rate = baudrate; } // TU_LOG_P_CDC_BOOL("set baudrate", ret); @@ -652,16 +655,16 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin CDC_LINE_CODING_STOP_BITS_TEXT(stop_bits)); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_coding.stop_bits = stop_bits; - p_cdc->requested_line_coding.parity = parity; - p_cdc->requested_line_coding.data_bits = data_bits; + p_cdc->requested_line.coding.stop_bits = stop_bits; + p_cdc->requested_line.coding.parity = parity; + p_cdc->requested_line.coding.data_bits = data_bits; bool ret = set_function_call(p_cdc, driver->set_data_format, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_coding.stop_bits = stop_bits; - p_cdc->line_coding.parity = parity; - p_cdc->line_coding.data_bits = data_bits; + p_cdc->line.coding.stop_bits = stop_bits; + p_cdc->line.coding.parity = parity; + p_cdc->line.coding.data_bits = data_bits; } // TU_LOG_P_CDC_BOOL("set data format", ret); @@ -678,12 +681,12 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line_coding = *line_coding; + p_cdc->requested_line.coding = *line_coding; bool ret = set_function_call(p_cdc, driver->set_line_coding, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line_coding = *line_coding; + p_cdc->line.coding = *line_coding; } // TU_LOG_P_CDC_BOOL("set line coding", ret); @@ -921,25 +924,25 @@ static void acm_internal_control_complete(tuh_xfer_t *xfer) { if (success) { switch (xfer->setup->bRequest) { case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; break; case CDC_REQUEST_SET_LINE_CODING: - p_cdc->line_coding = p_cdc->requested_line_coding; + p_cdc->line.coding = p_cdc->requested_line.coding; break; default: break; } } - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->user_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } } static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->acm_capability.support_line_request); + TU_VERIFY(p_cdc->acm.capability.support_line_request); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -948,12 +951,12 @@ static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t co .direction = TUSB_DIR_OUT }, .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE, - .wValue = tu_htole16((uint16_t) p_cdc->requested_line_state.value), + .wValue = tu_htole16((uint16_t) p_cdc->requested_line.control_state.value), .wIndex = tu_htole16((uint16_t) p_cdc->bInterfaceNumber), .wLength = 0 }; - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; tuh_xfer_t xfer = { .daddr = p_cdc->daddr, @@ -970,9 +973,9 @@ static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t co } static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->acm_capability.support_line_request); - TU_VERIFY((p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8) || - p_cdc->requested_line_coding.data_bits == 16); + TU_VERIFY(p_cdc->acm.capability.support_line_request); + TU_VERIFY((p_cdc->requested_line.coding.data_bits >= 5 && p_cdc->requested_line.coding.data_bits <= 8) || + p_cdc->requested_line.coding.data_bits == 16); tusb_control_request_t const request = { .bmRequestType_bit = { @@ -988,9 +991,9 @@ static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ // use usbh enum buf to hold line coding since user line_coding variable does not live long enough uint8_t *enum_buf = usbh_get_enum_buf(); - memcpy(enum_buf, &p_cdc->requested_line_coding, sizeof(cdc_line_coding_t)); + memcpy(enum_buf, &p_cdc->requested_line.coding, sizeof(cdc_line_coding_t)); - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; tuh_xfer_t xfer = { .daddr = p_cdc->daddr, @@ -1007,15 +1010,15 @@ static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ } static bool acm_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; + p_cdc->requested_line.coding.bit_rate = p_cdc->line.coding.bit_rate; return acm_set_line_coding(p_cdc, complete_cb, user_data); } static bool acm_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; - p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; - p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; + p_cdc->requested_line.coding.stop_bits = p_cdc->line.coding.stop_bits; + p_cdc->requested_line.coding.parity = p_cdc->line.coding.parity; + p_cdc->requested_line.coding.data_bits = p_cdc->line.coding.data_bits; return acm_set_line_coding(p_cdc, complete_cb, user_data); } @@ -1042,7 +1045,7 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1 while ((p_desc < p_desc_end) && (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc))) { if (CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc)) { // save ACM bmCapabilities - p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; + p_cdc->acm.capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities; } p_desc = tu_desc_next(p_desc); @@ -1082,8 +1085,8 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + if (p_cdc->acm.capability.support_line_request) { + p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, CONFIG_ACM_SET_LINE_CODING)); break; } @@ -1092,8 +1095,8 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { case CONFIG_ACM_SET_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm_capability.support_line_request) { - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + if (p_cdc->acm.capability.support_line_request) { + p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; TU_ASSERT(acm_set_line_coding(p_cdc, cdch_process_set_config, CONFIG_ACM_COMPLETE)); break; } @@ -1175,10 +1178,10 @@ static bool ftdi_change_speed(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb } static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 7 && p_cdc->requested_line_coding.data_bits <= 8, 0); - uint16_t value = (uint16_t) ((p_cdc->requested_line_coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 - (p_cdc->requested_line_coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding - (p_cdc->requested_line_coding.stop_bits & 0x3UL) << 11); // stop bits quantity is stored in bits 11-12, same coding + TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 7 && p_cdc->requested_line.coding.data_bits <= 8, 0); + uint16_t value = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 + (p_cdc->requested_line.coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding + (p_cdc->requested_line.coding.stop_bits & 0x3UL) << 11); // stop bits quantity is stored in bits 11-12, same coding // not each FTDI supports 1.5 stop bits return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, @@ -1186,8 +1189,8 @@ static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet } static inline bool ftdi_update_mctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t value = (uint16_t) ((p_cdc->requested_line_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | - (p_cdc->requested_line_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); + uint16_t value = (uint16_t) ((p_cdc->requested_line.control_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | + (p_cdc->requested_line.control_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, value, p_cdc->ftdi.channel, complete_cb, user_data); @@ -1206,35 +1209,35 @@ static void ftdi_internal_control_complete(tuh_xfer_t *xfer) { if (success) { if (xfer->setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && xfer->setup->bmRequestType == FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE ) { - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; } if (xfer->setup->bRequest == FTDI_SIO_SET_DATA_REQUEST && xfer->setup->bmRequestType == FTDI_SIO_SET_DATA_REQUEST_TYPE ) { - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; + p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; + p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; } if (xfer->setup->bRequest == FTDI_SIO_SET_BAUDRATE_REQUEST && xfer->setup->bmRequestType == FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE ) { - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; } } - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->user_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } } static bool ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; } static bool ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; @@ -1261,7 +1264,7 @@ static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complet } static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ftdi_update_mctrl(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); return true; @@ -1339,15 +1342,15 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { // from here sequence overtaken from Linux Kernel function ftdi_open() case CONFIG_FTDI_SIO_RESET: - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, CONFIG_FTDI_SET_DATA)); break; // from here sequence overtaken from Linux Kernel function ftdi_set_termios() case CONFIG_FTDI_SET_DATA: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); break; #else @@ -1356,7 +1359,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_SET_BAUDRATE: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); break; #else @@ -1371,8 +1374,8 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_MODEM_CTRL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); break; #else @@ -1529,7 +1532,7 @@ static inline uint32_t ftdi_2232h_baud_to_divisor(uint32_t baud) { } static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { - uint32_t baud = p_cdc->requested_line_coding.bit_rate; + uint32_t baud = p_cdc->requested_line.coding.bit_rate; uint32_t div_value = 0; TU_VERIFY(baud); @@ -1661,16 +1664,16 @@ static inline bool cp210x_ifc_enable(cdch_interface_t *p_cdc, uint16_t enabled, static bool cp210x_set_baudrate_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // Not every baud rate is supported. See datasheets and AN205 "CP210x Baud Rate Support" - uint32_t baud_le = tu_htole32(p_cdc->requested_line_coding.bit_rate); + uint32_t baud_le = tu_htole32(p_cdc->requested_line.coding.bit_rate); return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); } static bool cp210x_set_line_ctl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); - uint16_t lcr = (uint16_t) ((p_cdc->requested_line_coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 - (p_cdc->requested_line_coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding - (p_cdc->requested_line_coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding + TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 5 && p_cdc->requested_line.coding.data_bits <= 8, 0); + uint16_t lcr = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 + (p_cdc->requested_line.coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding + (p_cdc->requested_line.coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } @@ -1679,7 +1682,7 @@ static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | - p_cdc->requested_line_state.value), + p_cdc->requested_line.control_state.value), NULL, 0, complete_cb, user_data); } @@ -1697,38 +1700,38 @@ static void cp210x_internal_control_complete(tuh_xfer_t *xfer) { if (success) { switch (xfer->setup->bRequest) { case CP210X_SET_MHS: - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; break; case CP210X_SET_LINE_CTL: - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; + p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; + p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; break; case CP210X_SET_BAUDRATE: - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; break; default: break; } } - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->user_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } } static bool cp210x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); return true; } static bool cp210x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); return true; @@ -1752,7 +1755,7 @@ static bool cp210x_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t comple } static bool cp210x_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); return true; @@ -1799,8 +1802,8 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CP210X_SET_BAUDRATE_REQUEST: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_LINE_CTL)); break; #else @@ -1809,7 +1812,7 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CP210X_SET_LINE_CTL: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_DTR_RTS)); break; #else @@ -1818,8 +1821,8 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CP210X_SET_DTR_RTS: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; #else @@ -1923,8 +1926,8 @@ static bool ch34x_write_reg_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t comp static bool ch34x_modem_ctrl_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // CH34x signals are inverted - uint8_t control = ~((p_cdc->requested_line_state.rts ? CH34X_BIT_RTS : 0) | - (p_cdc->requested_line_state.dtr ? CH34X_BIT_DTR : 0)); + uint8_t control = ~((p_cdc->requested_line.control_state.rts ? CH34X_BIT_RTS : 0) | + (p_cdc->requested_line.control_state.dtr ? CH34X_BIT_DTR : 0)); return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } @@ -1947,14 +1950,14 @@ static void ch34x_internal_control_complete(tuh_xfer_t *xfer) { switch (tu_le16toh(xfer->setup->wValue)) { case CH34X_REG16_DIVISOR_PRESCALER: // baudrate - p_cdc->line_coding.bit_rate = p_cdc->requested_line_coding.bit_rate; + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; break; case CH32X_REG16_LCR2_LCR: // data format - p_cdc->line_coding.stop_bits = p_cdc->requested_line_coding.stop_bits; - p_cdc->line_coding.parity = p_cdc->requested_line_coding.parity; - p_cdc->line_coding.data_bits = p_cdc->requested_line_coding.data_bits; + p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; + p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; + p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; break; default: break; @@ -1962,28 +1965,28 @@ static void ch34x_internal_control_complete(tuh_xfer_t *xfer) { break; case CH34X_REQ_MODEM_CTRL: - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; break; default: break; } } - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->user_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } } static bool ch34x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; } static bool ch34x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; @@ -2008,7 +2011,7 @@ static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple } static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); return true; @@ -2073,7 +2076,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { // see drivers from WCH vendor, Linux kernel and FreeBSD if (version >= 0x30) { // init CH34x with line coding - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; + p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); uint8_t const lcr = ch34x_get_lcr(p_cdc); TU_ASSERT(div_ps != 0 && lcr != 0); @@ -2085,7 +2088,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CH34X_SPECIAL_REG_WRITE: // overtake line coding and do special reg write, purpose unknown, overtaken from WCH driver - p_cdc->line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; + p_cdc->line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X; TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x0F, CH341_REG_0x2C), 0x0007, cdch_process_set_config, CONFIG_CH34X_FLOW_CONTROL)); break; @@ -2098,8 +2101,8 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CH34X_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_control_cb = cdch_process_set_config; + p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->user_complete_cb = cdch_process_set_config; TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; #else @@ -2121,7 +2124,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { // calculate divisor and prescaler for baudrate, return it as 16-bit combined value static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t *p_cdc) { - uint32_t const baval = p_cdc->requested_line_coding.bit_rate; + uint32_t const baval = p_cdc->requested_line.coding.bit_rate; uint8_t a; uint8_t b; uint32_t c; @@ -2171,9 +2174,9 @@ static uint16_t ch34x_get_divisor_prescaler(cdch_interface_t *p_cdc) { // calculate lcr value from data coding static uint8_t ch34x_get_lcr(cdch_interface_t *p_cdc) { - uint8_t const stop_bits = p_cdc->requested_line_coding.stop_bits; - uint8_t const parity = p_cdc->requested_line_coding.parity; - uint8_t const data_bits = p_cdc->requested_line_coding.data_bits; + uint8_t const stop_bits = p_cdc->requested_line.coding.stop_bits; + uint8_t const parity = p_cdc->requested_line.coding.parity; + uint8_t const data_bits = p_cdc->requested_line.coding.data_bits; uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX; TU_VERIFY(data_bits >= 5 && data_bits <= 8); @@ -2276,7 +2279,7 @@ static inline bool pl2303_supports_hx_status(cdch_interface_t *p_cdc, tuh_xfer_c static inline bool pl2303_set_control_lines(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, - p_cdc->requested_line_state.value, 0, NULL, 0, complete_cb, user_data); + p_cdc->requested_line.control_state.value, 0, NULL, 0, complete_cb, user_data); } //static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) @@ -2292,14 +2295,14 @@ static bool pl2303_set_line_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t compl * even to the same values as before. Thus we actually need to filter * in this specific case. */ - TU_VERIFY(p_cdc->requested_line_coding.data_bits != p_cdc->line_coding.data_bits || - p_cdc->requested_line_coding.stop_bits != p_cdc->line_coding.stop_bits || - p_cdc->requested_line_coding.parity != p_cdc->line_coding.parity || - p_cdc->requested_line_coding.bit_rate != p_cdc->line_coding.bit_rate ); + TU_VERIFY(p_cdc->requested_line.coding.data_bits != p_cdc->line.coding.data_bits || + p_cdc->requested_line.coding.stop_bits != p_cdc->line.coding.stop_bits || + p_cdc->requested_line.coding.parity != p_cdc->line.coding.parity || + p_cdc->requested_line.coding.bit_rate != p_cdc->line.coding.bit_rate ); /* For reference buf[6] data bits value */ - TU_VERIFY(p_cdc->requested_line_coding.data_bits >= 5 && p_cdc->requested_line_coding.data_bits <= 8, 0); - buf[6] = p_cdc->requested_line_coding.data_bits; + TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 5 && p_cdc->requested_line.coding.data_bits <= 8, 0); + buf[6] = p_cdc->requested_line.coding.data_bits; /* For reference buf[0]:buf[3] baud rate value */ TU_VERIFY(pl2303_encode_baud_rate(p_cdc, &buf[0])); @@ -2307,14 +2310,14 @@ static bool pl2303_set_line_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t compl /* For reference buf[4]=0 is 1 stop bits */ /* For reference buf[4]=1 is 1.5 stop bits */ /* For reference buf[4]=2 is 2 stop bits */ - buf[4] = p_cdc->requested_line_coding.stop_bits; // PL2303 has the same coding + buf[4] = p_cdc->requested_line.coding.stop_bits; // PL2303 has the same coding /* For reference buf[5]=0 is none parity */ /* For reference buf[5]=1 is odd parity */ /* For reference buf[5]=2 is even parity */ /* For reference buf[5]=3 is mark parity */ /* For reference buf[5]=4 is space parity */ - buf[5] = p_cdc->requested_line_coding.parity; // PL2303 has the same coding + buf[5] = p_cdc->requested_line.coding.parity; // PL2303 has the same coding return pl2303_set_request(p_cdc, PL2303_SET_LINE_REQUEST, PL2303_SET_LINE_REQUEST_TYPE, 0, 0, buf, PL2303_LINE_CODING_BUFSIZE, complete_cb, user_data); @@ -2350,45 +2353,45 @@ static void pl2303_internal_control_complete(tuh_xfer_t *xfer) { if (success) { if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { - p_cdc->line_coding = p_cdc->requested_line_coding; + p_cdc->line.coding = p_cdc->requested_line.coding; } if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { - p_cdc->line_state = p_cdc->requested_line_state; + p_cdc->line.control_state = p_cdc->requested_line.control_state; } } - xfer->complete_cb = p_cdc->user_control_cb; + xfer->complete_cb = p_cdc->user_complete_cb; if (xfer->complete_cb) { xfer->complete_cb(xfer); } } static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); return true; } static bool pl2303_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.bit_rate = p_cdc->line_coding.bit_rate; - p_cdc->user_control_cb = complete_cb; + p_cdc->requested_line.coding.bit_rate = p_cdc->line.coding.bit_rate; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); return true; } static bool pl2303_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line_coding.stop_bits = p_cdc->line_coding.stop_bits; - p_cdc->requested_line_coding.parity = p_cdc->line_coding.parity; - p_cdc->requested_line_coding.data_bits = p_cdc->line_coding.data_bits; - p_cdc->user_control_cb = complete_cb; + p_cdc->requested_line.coding.stop_bits = p_cdc->line.coding.stop_bits; + p_cdc->requested_line.coding.parity = p_cdc->line.coding.parity; + p_cdc->requested_line.coding.data_bits = p_cdc->line.coding.data_bits; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); return true; } static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding - p_cdc->user_control_cb = complete_cb; + p_cdc->user_complete_cb = complete_cb; TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); return true; } @@ -2458,7 +2461,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_DETECT_TYPE: - p_cdc->user_control_cb = cdch_process_set_config;// set once for whole process config + p_cdc->user_complete_cb = cdch_process_set_config;// set once for whole process config // get type and quirks (step 1) type = pl2303_detect_type(p_cdc, 1); TU_ASSERT(type != PL2303_TYPE_UNKNOWN); @@ -2606,7 +2609,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // unnecessary pl2303_get_line_request() is skipped due to a stall case CONFIG_PL2303_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; TU_ASSERT(pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); break; #else @@ -2615,7 +2618,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { case CONFIG_PL2303_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; + p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); break; #else @@ -2861,7 +2864,7 @@ static uint32_t pl2303_encode_baud_rate_divisor_alt(uint8_t buf[PL2303_LINE_CODI } static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_LINE_CODING_BAUDRATE_BUFSIZE]) { - uint32_t baud = p_cdc->requested_line_coding.bit_rate; + uint32_t baud = p_cdc->requested_line.coding.bit_rate; uint32_t baud_sup; const pl2303_type_data_t* type_data = &pl2303_type_data[p_cdc->pl2303.type]; -- cgit v1.3.1 From 5c974cee23e9ece208df43b60070740fc2eda0c3 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jun 2025 12:51:29 +0700 Subject: usbh make TU_API_SYNC() public, to implement sync() API, change return of sync API from uint8_t to tusb_xfer_result_t --- src/common/tusb_types.h | 2 ++ src/host/usbh.c | 47 ++----------------------------- src/host/usbh.h | 73 +++++++++++++++++++++++++++++++------------------ 3 files changed, 51 insertions(+), 71 deletions(-) (limited to 'src') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index ff5d8b66a..ec7aad796 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -278,6 +278,8 @@ typedef enum { XFER_RESULT_INVALID } xfer_result_t; +#define tusb_xfer_result_t xfer_result_t + // TODO remove enum { DESC_OFFSET_LEN = 0, diff --git a/src/host/usbh.c b/src/host/usbh.c index 08c362171..adaeef092 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1092,8 +1092,9 @@ TU_ATTR_FAST_FUNC void hcd_event_handler(hcd_event_t const* event, bool in_isr) // generic helper to get a descriptor // if blocking, user_data is pointed to xfer_result -static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline +bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { tusb_control_request_t const request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_DEVICE, @@ -1134,7 +1135,6 @@ bool tuh_descriptor_get_configuration(uint8_t daddr, uint8_t index, void* buffer } //------------- String Descriptor -------------// - bool tuh_descriptor_get_string(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return _get_descriptor(daddr, TUSB_DESC_STRING, index, language_id, buffer, len, complete_cb, user_data); @@ -1272,47 +1272,6 @@ bool tuh_interface_set(uint8_t daddr, uint8_t itf_num, uint8_t itf_alt, return tuh_control_xfer(&xfer); } -//--------------------------------------------------------------------+ -// Descriptor Sync -//--------------------------------------------------------------------+ - -#define _CONTROL_SYNC_API(_async_func, ...) \ - xfer_result_t result = XFER_RESULT_INVALID;\ - TU_VERIFY(_async_func(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \ - return (uint8_t) result - -uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get, daddr, type, index, buffer, len); -} - -uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_device, daddr, buffer, len); -} - -uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_configuration, daddr, index, buffer, len); -} - -uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len); -} - -uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_string, daddr, index, language_id, buffer, len); -} - -uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len); -} - -uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_product_string, daddr, language_id, buffer, len); -} - -uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { - _CONTROL_SYNC_API(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len); -} - //--------------------------------------------------------------------+ // Detaching //--------------------------------------------------------------------+ diff --git a/src/host/usbh.h b/src/host/usbh.h index 1ee511722..1e9bb26bc 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -234,8 +234,18 @@ bool tuh_bus_info_get(uint8_t daddr, tuh_bus_info_t* bus_info); //--------------------------------------------------------------------+ // Transfer API +// Each Function will make a USB transfer request to device. If +// - complete_cb != NULL, the function will return immediately and invoke the callback when request is complete. +// - complete_cb == NULL, the function will block until request is complete. +// In this case, user_data should be tusb_xfer_result_t* to hold the transfer result. //--------------------------------------------------------------------+ +// Helper to make Sync API from async one +#define TU_API_SYNC(_async_api, ...) \ + xfer_result_t result = XFER_RESULT_INVALID;\ + TU_VERIFY(_async_api(__VA_ARGS__, NULL, (uintptr_t) &result), XFER_RESULT_TIMEOUT); \ + return result + // Submit a control transfer // - async: complete callback invoked when finished. // - sync : blocking if complete callback is NULL. @@ -327,45 +337,54 @@ bool tuh_descriptor_get_serial_string(uint8_t daddr, uint16_t language_id, void* //--------------------------------------------------------------------+ // Descriptors Synchronous (blocking) +// Sync API which is blocking until transfer is complete. +// return transfer result //--------------------------------------------------------------------+ -// Sync (blocking) version of tuh_descriptor_get() -// return transfer result -uint8_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_sync(uint8_t daddr, uint8_t type, uint8_t index, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get, daddr, type, index, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_device() -// return transfer result -uint8_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_device() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_device_sync(uint8_t daddr, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_device, daddr, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_configuration() -// return transfer result -uint8_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_configuration() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_configuration_sync(uint8_t daddr, uint8_t index, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_configuration, daddr, index, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_hid_report() -// return transfer result -uint8_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_hid_report() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_hid_report_sync(uint8_t daddr, uint8_t itf_num, uint8_t desc_type, uint8_t index, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_hid_report, daddr, itf_num, desc_type, index, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_string() -// return transfer result -uint8_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_string() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_string_sync(uint8_t daddr, uint8_t index, uint16_t language_id, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_string, daddr, index, language_id, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_string_langid() -TU_ATTR_ALWAYS_INLINE static inline -uint8_t tuh_descriptor_get_string_langid_sync(uint8_t daddr, void* buffer, uint16_t len) { +// Sync version of tuh_descriptor_get_string_langid() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_string_langid_sync(uint8_t daddr, void* buffer, uint16_t len) { return tuh_descriptor_get_string_sync(daddr, 0, 0, buffer, len); } -// Sync (blocking) version of tuh_descriptor_get_manufacturer_string() -// return transfer result -uint8_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_manufacturer_string() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_manufacturer_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_manufacturer_string, daddr, language_id, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_product_string() -// return transfer result -uint8_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_product_string() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_product_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_product_string, daddr, language_id, buffer, len); +} -// Sync (blocking) version of tuh_descriptor_get_serial_string() -// return transfer result -uint8_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len); +// Sync version of tuh_descriptor_get_serial_string() +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_descriptor_get_serial_string_sync(uint8_t daddr, uint16_t language_id, void* buffer, uint16_t len) { + TU_API_SYNC(tuh_descriptor_get_serial_string, daddr, language_id, buffer, len); +} #ifdef __cplusplus } -- cgit v1.3.1 From adf6cbfe03523cd8f7e23cb7f2edbb4304a6cd89 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jun 2025 12:52:34 +0700 Subject: cdch clean up and refactor, add explicit sync() API --- examples/host/cdc_msc_hid/src/cdc_app.c | 2 +- src/class/cdc/cdc_host.c | 172 +++++++++++++------------------- src/class/cdc/cdc_host.h | 48 +++++++-- src/class/cdc/serial/pl2303.h | 33 +++--- 4 files changed, 127 insertions(+), 128 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/cdc_app.c b/examples/host/cdc_msc_hid/src/cdc_app.c index 6f4433f22..2fa9a8560 100644 --- a/examples/host/cdc_msc_hid/src/cdc_app.c +++ b/examples/host/cdc_msc_hid/src/cdc_app.c @@ -89,7 +89,7 @@ void tuh_cdc_mount_cb(uint8_t idx) { // If CFG_TUH_CDC_LINE_CODING_ON_ENUM is defined, line coding will be set by tinyusb stack // while eneumerating new cdc device cdc_line_coding_t line_coding = {0}; - if (tuh_cdc_get_local_line_coding(idx, &line_coding)) { + if (tuh_cdc_get_line_coding_local(idx, &line_coding)) { printf(" Baudrate: %" PRIu32 ", Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits); printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits); } diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 2fe2c85bc..50d0a020d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -42,15 +42,15 @@ // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUH_CDC_LOG_LEVEL - #define CFG_TUH_CDC_LOG_LEVEL CFG_TUH_LOG_LEVEL + #define CFG_TUH_CDC_LOG_LEVEL 1 #endif -#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) -#define TU_LOG_CDC(TXT,DADDR,ITF_NUM,NAME,...) TU_LOG_DRV("[:%u:%u] CDCh %s " TXT "\r\n", \ - DADDR, ITF_NUM, NAME, ##__VA_ARGS__) -#define TU_LOG_P_CDC(TXT,...) TU_LOG_CDC(TXT, p_cdc->daddr, p_cdc->bInterfaceNumber, \ - serial_drivers[p_cdc->serial_drid].name, ##__VA_ARGS__) -#define TU_LOG_P_CDC_BOOL(TXT,VAL) TU_LOG_P_CDC(TXT " " #VAL " = %d", VAL) +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_CDC(_cdc, _format, ...) TU_LOG_DRV("[:%u:%u] CDCh %s " _format "\r\n", _cdc->daddr, _cdc->bInterfaceNumber, \ + serial_drivers[_cdc->serial_drid].name, ##__VA_ARGS__) + +// Driver that need to set line coding in two stages: baudrate then data format. +#define DRIVER_2STAGE_SET_LINE_CODING (CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X) //--------------------------------------------------------------------+ // Host CDC Interface @@ -72,7 +72,8 @@ typedef struct { } line, requested_line; tuh_xfer_cb_t user_complete_cb; // required since we handle request internally first - #if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X + + #if DRIVER_2STAGE_SET_LINE_CODING tuh_xfer_cb_t requested_complete_cb; #endif @@ -197,49 +198,57 @@ enum { SERIAL_DRIVER_COUNT }; +typedef bool (*serial_driver_func_t)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + typedef struct { uint16_t const (*vid_pid_list)[2]; uint16_t const vid_pid_count; + bool is_2stage_line_coding; // true if driver requires to set baudrate then data format separately + bool (*const open)(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); bool (*const process_set_config)(tuh_xfer_t * xfer); - bool (*const set_control_line_state)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_baudrate)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_data_format)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); - bool (*const set_line_coding)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); + const serial_driver_func_t set_control_line_state; + const serial_driver_func_t set_baudrate; + const serial_driver_func_t set_data_format; + const serial_driver_func_t set_line_coding; #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - uint8_t const * name; + const char * name; #endif } cdch_serial_driver_t; +#if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL + #define DRIVER_NAME_DECLARE(_str) .name = _str +#else + #define DRIVER_NAME_DECLARE(_str) +#endif + // Note driver list must be in the same order as SERIAL_DRIVER enum static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = NULL, .vid_pid_count = 0, + .is_2stage_line_coding = false, .open = acm_open, .process_set_config = acm_process_set_config, .set_control_line_state = acm_set_control_line_state, .set_baudrate = acm_set_baudrate, .set_data_format = acm_set_data_format, .set_line_coding = acm_set_line_coding, - #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - .name = (uint8_t const *) "ACM" - #endif + DRIVER_NAME_DECLARE("ACM") }, #if CFG_TUH_CDC_FTDI { .vid_pid_list = ftdi_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ftdi_vid_pid_list), + .is_2stage_line_coding = true, .open = ftdi_open, .process_set_config = ftdi_proccess_set_config, .set_control_line_state = ftdi_set_modem_ctrl, .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, .set_line_coding = ftdi_set_line_coding, - #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - .name = (uint8_t const *) "FTDI" - #endif + DRIVER_NAME_DECLARE("FTDI") }, #endif @@ -247,15 +256,14 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = cp210x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(cp210x_vid_pid_list), + .is_2stage_line_coding = true, .open = cp210x_open, .process_set_config = cp210x_process_set_config, .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, .set_data_format = cp210x_set_data_format, .set_line_coding = cp210x_set_line_coding, - #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - .name = (uint8_t const *) "CP210x" - #endif + DRIVER_NAME_DECLARE("CP210x") }, #endif @@ -263,15 +271,14 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = ch34x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ch34x_vid_pid_list), + .is_2stage_line_coding = true, .open = ch34x_open, .process_set_config = ch34x_process_set_config, .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, .set_data_format = ch34x_set_data_format, .set_line_coding = ch34x_set_line_coding, - #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - .name = (uint8_t const *) "CH34x" - #endif + DRIVER_NAME_DECLARE("CH34x") }, #endif @@ -279,15 +286,14 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = pl2303_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(pl2303_vid_pid_list), + .is_2stage_line_coding = false, .open = pl2303_open, .process_set_config = pl2303_process_set_config, .set_control_line_state = pl2303_set_modem_ctrl, .set_baudrate = pl2303_set_baudrate, .set_data_format = pl2303_set_data_format, .set_line_coding = pl2303_set_line_coding, - #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL - .name = (uint8_t const *) "PL2303" - #endif + DRIVER_NAME_DECLARE("PL2303") } #endif }; @@ -440,13 +446,7 @@ bool tuh_cdc_get_control_line_state_local(uint8_t idx, uint16_t* line_state) { bool tuh_cdc_get_line_coding_local(uint8_t idx, cdc_line_coding_t * line_coding) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - *line_coding = p_cdc->line.coding; - TU_LOG_P_CDC("get line coding %lu %u%c%s", - p_cdc->line.coding.bit_rate, p_cdc->line.coding.data_bits, - CDC_LINE_CODING_PARITY_CHAR(p_cdc->line.coding.parity), - CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); - return true; } @@ -520,29 +520,27 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ +#if DRIVER_2STAGE_SET_LINE_CODING + // set line coding using sequence with 2 stages: set baudrate (stage1) + set data format (stage2) static bool set_line_coding_sequence( cdch_interface_t * p_cdc, - // control request function to set baudrate - bool (*set_baudrate_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), - // control request function to set data format - bool (*set_data_format_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), - // function to be called after stage 1 completed - void (*set_line_coding_stage1_complete)(tuh_xfer_t * xfer), - // control complete function to be called after request - void (*internal_control_complete)(tuh_xfer_t * xfer), + serial_driver_func_t set_baudrate, + serial_driver_func_t set_data_format, + tuh_xfer_cb_t set_line_coding_stage1_complete, // function to be called after stage 1 completed + tuh_xfer_cb_t internal_control_complete, // control complete function to be called after request tuh_xfer_cb_t complete_cb, uintptr_t user_data) { if (complete_cb) { // non-blocking // stage 1 set baudrate p_cdc->requested_complete_cb = complete_cb; // store complete_cb to be used in set_line_coding_stage1_complete() p_cdc->user_complete_cb = set_line_coding_stage1_complete; - return set_baudrate_request(p_cdc, internal_control_complete, user_data); + return set_baudrate(p_cdc, internal_control_complete, user_data); } else { // blocking sequence // stage 1 set baudrate xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL - bool ret = set_baudrate_request(p_cdc, NULL, (uintptr_t) &result); + bool ret = set_baudrate(p_cdc, NULL, (uintptr_t) &result); if (user_data) { *((xfer_result_t *) user_data) = result; @@ -556,7 +554,7 @@ static bool set_line_coding_sequence( // stage 2 set data format result = XFER_RESULT_INVALID; - ret = set_data_format_request(p_cdc, NULL, (uintptr_t) &result); + ret = set_data_format(p_cdc, NULL, (uintptr_t) &result); if (user_data) { *((xfer_result_t *) user_data) = result; @@ -590,58 +588,35 @@ static void set_line_coding_stage1_complete( } } } - -// call of (non-)blocking set-functions (to set line state, baudrate, ...) -static bool set_function_call ( - cdch_interface_t * p_cdc, - bool (*set_function)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - if (complete_cb) { - // non-blocking with call back - return set_function(p_cdc, complete_cb, user_data); - } else { - // blocking - xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL - bool ret = set_function(p_cdc, NULL, (uintptr_t) &result); - - if (user_data) { - *((xfer_result_t *) user_data) = result; - } - - return (ret && result == XFER_RESULT_SUCCESS); - } -} +#endif bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_CDC(p_cdc, "set control line state dtr = %u rts = %u", p_cdc->requested_line.control_state.dtr, p_cdc->requested_line.control_state.rts); cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line.control_state.value = (uint8_t) line_state; - TU_LOG_P_CDC("set control line state dtr = %u rts = %u", p_cdc->requested_line.control_state.dtr, p_cdc->requested_line.control_state.rts); - - const bool ret = set_function_call(p_cdc, driver->set_control_line_state, complete_cb, user_data); - + const bool ret = driver->set_control_line_state(p_cdc, complete_cb, user_data); if (ret && !complete_cb) { - p_cdc->line.control_state = p_cdc->requested_line.control_state; + // blocking, update line state if request was successful + p_cdc->line.control_state.value = (uint8_t) line_state; } + return ret; } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set baudrate %lu", baudrate); + TU_LOG_CDC(p_cdc, "set baudrate %lu", baudrate); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line.coding.bit_rate = baudrate; - - bool ret = set_function_call(p_cdc, driver->set_baudrate, complete_cb, user_data); - + const bool ret = driver->set_baudrate(p_cdc, complete_cb, user_data); if (ret && !complete_cb) { p_cdc->line.coding.bit_rate = baudrate; } -// TU_LOG_P_CDC_BOOL("set baudrate", ret); return ret; } @@ -650,7 +625,7 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set data format %u%c%s", + TU_LOG_CDC(p_cdc, "set data format %u%c%s", data_bits, CDC_LINE_CODING_PARITY_CHAR(parity), CDC_LINE_CODING_STOP_BITS_TEXT(stop_bits)); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; @@ -659,15 +634,13 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin p_cdc->requested_line.coding.parity = parity; p_cdc->requested_line.coding.data_bits = data_bits; - bool ret = set_function_call(p_cdc, driver->set_data_format, complete_cb, user_data); + const bool ret = driver->set_data_format(p_cdc, complete_cb, user_data); if (ret && !complete_cb) { p_cdc->line.coding.stop_bits = stop_bits; p_cdc->line.coding.parity = parity; p_cdc->line.coding.data_bits = data_bits; } -// TU_LOG_P_CDC_BOOL("set data format", ret); - return ret; } @@ -675,7 +648,7 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set line coding %lu %u%c%s", + TU_LOG_CDC(p_cdc, "set line coding %lu %u%c%s", line_coding->bit_rate, line_coding->data_bits, CDC_LINE_CODING_PARITY_CHAR(line_coding->parity), CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); @@ -683,12 +656,11 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, p_cdc->requested_line.coding = *line_coding; - bool ret = set_function_call(p_cdc, driver->set_line_coding, complete_cb, user_data); + const bool ret = driver->set_line_coding(p_cdc, complete_cb, user_data); if (ret && !complete_cb) { p_cdc->line.coding = *line_coding; } -// TU_LOG_P_CDC_BOOL("set line coding", ret); return ret; } @@ -728,7 +700,7 @@ void cdch_close(uint8_t daddr) { for (uint8_t idx = 0; idx < CFG_TUH_CDC; idx++) { cdch_interface_t *p_cdc = &cdch_data[idx]; if (p_cdc->daddr == daddr) { - TU_LOG_P_CDC("close"); + TU_LOG_CDC(p_cdc, "close"); // Invoke application callback if (tuh_cdc_umount_cb) { @@ -847,9 +819,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d } if (driver_detected) { - TU_LOG_CDC("open", daddr, itf_desc->bInterfaceNumber, driver_detected->name); - bool ret = driver_detected->open(daddr, itf_desc, max_len); - // TU_LOG_CDC("opened ret = %s", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "true" : "FALSE" ); + const bool ret = driver_detected->open(daddr, itf_desc, max_len); + TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "OK" : "FAILED"); return ret; } @@ -859,7 +830,6 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); - TU_LOG_P_CDC_BOOL("set config complete", success); if (success) { p_cdc->mounted = true; @@ -883,6 +853,8 @@ static void cdch_process_set_config(tuh_xfer_t *xfer) { TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); const uint8_t idx = get_idx_by_ptr(p_cdc); + TU_LOG_DRV(" state = %u\r\n", xfer->user_data); + if (!serial_drivers[p_cdc->serial_drid].process_set_config(xfer)) { const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; set_config_complete(idx, itf_offset, false); @@ -895,7 +867,7 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_P_CDC("set config"); + TU_LOG_CDC(p_cdc, "set config"); // fake transfer to kick-off process_set_config() tuh_xfer_t xfer; @@ -919,7 +891,6 @@ static void acm_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -1204,7 +1175,6 @@ static void ftdi_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC_BOOL("control complete", success); if (success) { if (xfer->setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && @@ -1232,14 +1202,12 @@ static void ftdi_internal_control_complete(tuh_xfer_t *xfer) { static bool ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); - return true; } static bool ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); - return true; } @@ -1271,7 +1239,6 @@ static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ } //------------- Enumeration -------------// - enum { CONFIG_FTDI_DETERMINE_TYPE = 0, CONFIG_FTDI_WRITE_LATENCY, @@ -1448,7 +1415,7 @@ static bool ftdi_determine_type(cdch_interface_t *p_cdc) { #if CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL const char * ftdi_chip_name[] = { FTDI_CHIP_NAMES }; - TU_LOG_P_CDC("%s detected (bcdDevice = 0x%04x)", + TU_LOG_CDC(p_cdc, "%s detected (bcdDevice = 0x%04x)", ftdi_chip_name[p_cdc->ftdi.chip_type], version); #endif @@ -1595,7 +1562,7 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { break; } - TU_LOG_P_CDC("Baudrate divisor = 0x%lu", div_value); + TU_LOG_CDC(p_cdc, "Baudrate divisor = 0x%lu", div_value); return div_value; } @@ -1695,7 +1662,6 @@ static void cp210x_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -1795,7 +1761,7 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - switch (state) { + switch (state) { case CONFIG_CP210X_IFC_ENABLE: TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, CONFIG_CP210X_SET_BAUDRATE_REQUEST)); break; @@ -1941,7 +1907,6 @@ static void ch34x_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC_BOOL("control complete", success); if (success) { switch (xfer->setup->bRequest) { @@ -2059,7 +2024,6 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); cdch_interface_t *p_cdc = get_itf(idx); uint8_t buffer[2];// TODO remove - TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { @@ -2071,7 +2035,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) uint8_t const version = xfer->buffer[0]; - TU_LOG_P_CDC("Chip Version = 0x%02x", version); + TU_LOG_CDC(p_cdc, "Chip Version = 0x%02x", version); // only versions >= 0x30 are tested, below 0x30 seems having other programming // see drivers from WCH vendor, Linux kernel and FreeBSD if (version >= 0x30) { @@ -2348,7 +2312,6 @@ static void pl2303_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf(idx); TU_ASSERT(p_cdc, ); bool const success = (xfer->result == XFER_RESULT_SUCCESS); - TU_LOG_P_CDC_BOOL("control complete", success); if (success) { if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && @@ -2458,6 +2421,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { pl2303_type_t type; TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1)); + switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_DETECT_TYPE: @@ -2741,7 +2705,7 @@ static pl2303_type_t pl2303_detect_type(cdch_interface_t *p_cdc, uint8_t step) { default: break; } - TU_LOG_P_CDC("unknown device type bcdUSB = 0x%04x", desc_dev.bcdUSB); + TU_LOG_CDC(p_cdc, "unknown device type bcdUSB = 0x%04x", desc_dev.bcdUSB); return PL2303_TYPE_UNKNOWN; } @@ -2886,7 +2850,7 @@ static bool pl2303_encode_baud_rate(cdch_interface_t *p_cdc, uint8_t buf[PL2303_ } else { baud = pl2303_encode_baud_rate_divisor(buf, baud); } - TU_LOG_P_CDC("real baudrate %lu", baud); + TU_LOG_CDC(p_cdc, "real baudrate %lu", baud); return true; } diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 688164cb2..37bfca270 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -137,13 +137,12 @@ bool tuh_cdc_peek(uint8_t idx, uint8_t* ch); bool tuh_cdc_read_clear (uint8_t idx); //--------------------------------------------------------------------+ -// Control Endpoint (Request) API +// Control Request API // Each Function will make a USB control transfer request to/from device // - If complete_cb is provided, the function will return immediately and invoke // the callback when request is complete. // - If complete_cb is NULL, the function will block until request is complete. -// - In this case, user_data should be pointed to xfer_result_t to hold the transfer result. -// - The function will return true if transfer is successful, false otherwise. +// In this case, user_data should be usb_xfer_result_t* to hold the transfer result. //--------------------------------------------------------------------+ // Request to Set Control Line State: DTR (bit 0), RTS (bit 1) @@ -179,17 +178,52 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const* line_coding, // bool tuh_cdc_get_line_coding(uint8_t idx, cdc_line_coding_t* coding); // Connect by set both DTR, RTS -TU_ATTR_ALWAYS_INLINE static inline -bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS, complete_cb, user_data); } // Disconnect by clear both DTR, RTS -TU_ATTR_ALWAYS_INLINE static inline -bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_disconnect(uint8_t idx, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return tuh_cdc_set_control_line_state(idx, 0x00, complete_cb, user_data); } +//--------------------------------------------------------------------+ +// Control Request Sync API +// Each Function will make a USB control transfer request to/from device the function will block until request is +// complete. The function will return the transfer request result +//--------------------------------------------------------------------+ +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_control_line_state_sync(uint8_t idx, uint16_t line_state) { + TU_API_SYNC(tuh_cdc_set_control_line_state, idx, line_state); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_dtr_sync(uint8_t idx, bool dtr_state) { + TU_API_SYNC(tuh_cdc_set_dtr, idx, dtr_state); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_rts_sync(uint8_t idx, bool rts_state) { + TU_API_SYNC(tuh_cdc_set_rts, idx, rts_state); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_baudrate_sync(uint8_t idx, uint32_t baudrate) { + TU_API_SYNC(tuh_cdc_set_baudrate, idx, baudrate); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_data_format_sync(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits) { + TU_API_SYNC(tuh_cdc_set_data_format, idx, stop_bits, parity, data_bits); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_set_line_coding_sync(uint8_t idx, cdc_line_coding_t const* line_coding) { + TU_API_SYNC(tuh_cdc_set_line_coding, idx, line_coding); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_connect_sync(uint8_t idx) { + TU_API_SYNC(tuh_cdc_connect, idx); +} + +TU_ATTR_ALWAYS_INLINE static inline tusb_xfer_result_t tuh_cdc_disconnect_sync(uint8_t idx) { + TU_API_SYNC(tuh_cdc_disconnect, idx); +} + //--------------------------------------------------------------------+ // CDC APPLICATION CALLBACKS //--------------------------------------------------------------------+ diff --git a/src/class/cdc/serial/pl2303.h b/src/class/cdc/serial/pl2303.h index c01dac0e1..63910c7bb 100644 --- a/src/class/cdc/serial/pl2303.h +++ b/src/class/cdc/serial/pl2303.h @@ -109,36 +109,37 @@ typedef enum pl2303_type { } pl2303_type_t; typedef struct pl2303_type_data { - uint32_t const max_baud_rate; - uint8_t const quirks; - uint8_t const no_autoxonxoff : 1; - uint8_t const no_divisors : 1; - uint8_t const alt_divisors : 1; + uint32_t max_baud_rate; + uint8_t quirks; + uint8_t no_autoxonxoff : 1; + uint8_t no_divisors : 1; + uint8_t alt_divisors : 1; } pl2303_type_data_t; #define PL2303_TYPE_DATA \ [PL2303_TYPE_H] = { \ - .max_baud_rate = 1228800, \ - .quirks = PL2303_QUIRK_LEGACY, \ - .no_autoxonxoff = true, \ + .max_baud_rate = 1228800, .quirks = PL2303_QUIRK_LEGACY, \ + .no_autoxonxoff = 1, .no_divisors = 0, .alt_divisors = 0 \ }, \ [PL2303_TYPE_HX] = { \ - .max_baud_rate = 6000000, \ + .max_baud_rate = 6000000, .quirks = 0, \ + .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 0 \ }, \ [PL2303_TYPE_TA] = { \ - .max_baud_rate = 6000000, \ - .alt_divisors = true, \ + .max_baud_rate = 6000000, .quirks = 0, \ + .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 1 \ }, \ [PL2303_TYPE_TB] = { \ - .max_baud_rate = 12000000, \ - .alt_divisors = true, \ + .max_baud_rate = 12000000, .quirks = 0, \ + .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 1 \ }, \ [PL2303_TYPE_HXD] = { \ - .max_baud_rate = 12000000, \ + .max_baud_rate = 12000000, .quirks = 0, \ + .no_autoxonxoff = 0, .no_divisors = 0, .alt_divisors = 0 \ }, \ [PL2303_TYPE_HXN] = { \ - .max_baud_rate = 12000000, \ - .no_divisors = true, \ + .max_baud_rate = 12000000, .quirks = 0, \ + .no_autoxonxoff = 0, .no_divisors = 1, .alt_divisors = 0 \ } typedef struct TU_ATTR_PACKED { -- cgit v1.3.1 From 900d0d974b177959ffeaa1f34de72daf2ef72694 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jun 2025 17:04:40 +0700 Subject: refactor change signature of serial driver's process_set_config adding serial driver's request_complete() --- src/class/cdc/cdc_host.c | 185 +++++++++++++++++++++-------------------------- 1 file changed, 84 insertions(+), 101 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 50d0a020d..f36487758 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -112,11 +112,13 @@ CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; // Serial Driver //--------------------------------------------------------------------+ +// General driver static void cdch_process_set_config(tuh_xfer_t *xfer); +static void cdch_internal_control_complete(tuh_xfer_t *xfer); //------------- ACM prototypes -------------// static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static bool acm_process_set_config(tuh_xfer_t * xfer); +static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -127,7 +129,8 @@ static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t c #if CFG_TUH_CDC_FTDI static uint16_t const ftdi_vid_pid_list[][2] = {CFG_TUH_CDC_FTDI_VID_PID_LIST}; static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); -static bool ftdi_proccess_set_config(tuh_xfer_t * xfer); +static bool ftdi_proccess_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); +static void ftdi_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t *xfer); static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -140,7 +143,9 @@ static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIST}; static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static bool cp210x_process_set_config(tuh_xfer_t * xfer); +static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); +static void acm_internal_control_complete(tuh_xfer_t *xfer); +static void cp210x_internal_control_complete(tuh_xfer_t *xfer); static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -153,7 +158,8 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST}; static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static bool ch34x_process_set_config(tuh_xfer_t *xfer); +static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); +static void ch34x_internal_control_complete(tuh_xfer_t *xfer); static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -167,7 +173,8 @@ static uint16_t const pl2303_vid_pid_list[][2] = {CFG_TUH_CDC_PL2303_VID_PID_LIS static const pl2303_type_data_t pl2303_type_data[PL2303_TYPE_COUNT] = {PL2303_TYPE_DATA}; static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); -static bool pl2303_process_set_config(tuh_xfer_t *xfer); +static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); +static void pl2303_internal_control_complete(tuh_xfer_t *xfer); static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -206,11 +213,11 @@ typedef struct { bool is_2stage_line_coding; // true if driver requires to set baudrate then data format separately bool (*const open)(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); - bool (*const process_set_config)(tuh_xfer_t * xfer); - const serial_driver_func_t set_control_line_state; - const serial_driver_func_t set_baudrate; - const serial_driver_func_t set_data_format; - const serial_driver_func_t set_line_coding; + bool (*const process_set_config)(cdch_interface_t * p_cdc, tuh_xfer_t * xfer); + void (*const request_complete)(cdch_interface_t * p_cdc, tuh_xfer_t * xfer); // internal request complete handler to update line state + + serial_driver_func_t set_control_line_state, set_baudrate, set_data_format, set_line_coding; + #if CFG_TUSB_DEBUG && CFG_TUSB_DEBUG >= CFG_TUH_CDC_LOG_LEVEL const char * name; #endif @@ -244,6 +251,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .is_2stage_line_coding = true, .open = ftdi_open, .process_set_config = ftdi_proccess_set_config, + .request_complete = ftdi_internal_control_complete, .set_control_line_state = ftdi_set_modem_ctrl, .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, @@ -827,11 +835,9 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d return false; } -static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - +static void set_config_complete(cdch_interface_t *p_cdc, uint8_t itf_offset, bool success) { if (success) { + const uint8_t idx = get_idx_by_ptr(p_cdc); p_cdc->mounted = true; if (tuh_cdc_mount_cb) { tuh_cdc_mount_cb(idx); @@ -848,19 +854,6 @@ static void set_config_complete(uint8_t idx, uint8_t itf_offset, bool success) { usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset); } -static void cdch_process_set_config(tuh_xfer_t *xfer) { - cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); - TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); - const uint8_t idx = get_idx_by_ptr(p_cdc); - - TU_LOG_DRV(" state = %u\r\n", xfer->user_data); - - if (!serial_drivers[p_cdc->serial_drid].process_set_config(xfer)) { - const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; - set_config_complete(idx, itf_offset, false); - } -} - bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { tusb_control_request_t request; request.wIndex = tu_htole16((uint16_t) itf_num); @@ -880,6 +873,32 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { return true; } + +static void cdch_process_set_config(tuh_xfer_t *xfer) { + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + TU_LOG_DRV(" state = %u\r\n", xfer->user_data); + + if (!serial_drivers[p_cdc->serial_drid].process_set_config(p_cdc, xfer)) { + const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; + set_config_complete(p_cdc, itf_offset, false); + } +} + +static void cdch_internal_control_complete(tuh_xfer_t *xfer) { + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + + TU_LOG_DRV(" request result = %u\r\n", xfer->result); + serial_drivers[p_cdc->serial_drid].request_complete(p_cdc, xfer); + + // Invoke application callback + xfer->complete_cb = p_cdc->user_complete_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + //--------------------------------------------------------------------+ // ACM //--------------------------------------------------------------------+ @@ -1046,13 +1065,9 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1 return true; } -static bool acm_process_set_config(tuh_xfer_t *xfer) { +static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); const uintptr_t state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - switch (state) { case CONFIG_ACM_SET_CONTROL_LINE_STATE: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM @@ -1076,7 +1091,7 @@ static bool acm_process_set_config(tuh_xfer_t *xfer) { case CONFIG_ACM_COMPLETE: // itf_num+1 to account for data interface as well - set_config_complete(idx, 1, true); + set_config_complete(p_cdc, 1, true); break; default: @@ -1159,55 +1174,38 @@ static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet value, p_cdc->ftdi.channel, complete_cb, user_data); } -static inline bool ftdi_update_mctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t value = (uint16_t) ((p_cdc->requested_line.control_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | - (p_cdc->requested_line.control_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); - - return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, - value, p_cdc->ftdi.channel, complete_cb, user_data); -} - //------------- Driver API -------------// // internal control complete to update state such as line state, line_coding -static void ftdi_internal_control_complete(tuh_xfer_t *xfer) { - uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); - - if (success) { - if (xfer->setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && - xfer->setup->bmRequestType == FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE ) { +static void ftdi_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t *xfer) { + const tusb_control_request_t * setup = xfer->setup; + if (xfer->result == XFER_RESULT_SUCCESS) { + if (setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && + setup->bmRequestType == FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE ) { p_cdc->line.control_state = p_cdc->requested_line.control_state; } - if (xfer->setup->bRequest == FTDI_SIO_SET_DATA_REQUEST && - xfer->setup->bmRequestType == FTDI_SIO_SET_DATA_REQUEST_TYPE ) { + if (setup->bRequest == FTDI_SIO_SET_DATA_REQUEST && + setup->bmRequestType == FTDI_SIO_SET_DATA_REQUEST_TYPE ) { p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; } - if (xfer->setup->bRequest == FTDI_SIO_SET_BAUDRATE_REQUEST && - xfer->setup->bmRequestType == FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE ) { + if (setup->bRequest == FTDI_SIO_SET_BAUDRATE_REQUEST && + setup->bmRequestType == FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE ) { p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; } } - - xfer->complete_cb = p_cdc->user_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); - } } static bool ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } static bool ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); + TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -1218,7 +1216,7 @@ static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = p_cdc->bInterfaceNumber; set_line_coding_stage1_complete(xfer, itf_num, ftdi_set_data_request, // control request function to set data format - ftdi_internal_control_complete); // control complete function to be called after request + cdch_internal_control_complete); // control complete function to be called after request } // 2 stages: set baudrate (stage1) + set data format (stage2) @@ -1227,15 +1225,16 @@ static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complet ftdi_change_speed, // control request function to set baudrate ftdi_set_data_request, // control request function to set data format ftdi_set_line_coding_stage1_complete, // function to be called after stage 1 completed - ftdi_internal_control_complete, // control complete function to be called after request + cdch_internal_control_complete, // control complete function to be called after request complete_cb, user_data); } static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + uint16_t line_state = (uint16_t) ((p_cdc->requested_line.control_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | + (p_cdc->requested_line.control_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ftdi_update_mctrl(p_cdc, complete_cb ? ftdi_internal_control_complete : NULL, user_data)); - - return true; + return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, + line_state, p_cdc->ftdi.channel, complete_cb ? cdch_internal_control_complete : NULL, user_data); } //------------- Enumeration -------------// @@ -1274,18 +1273,14 @@ static bool ftdi_open(uint8_t daddr, const tusb_desc_interface_t *itf_desc, uint return open_ep_stream_pair(p_cdc, desc_ep); } -static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { +static bool ftdi_proccess_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); const uintptr_t state = xfer->user_data; - uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t *p_cdc = get_itf(idx); - uint8_t const itf_num = p_cdc->bInterfaceNumber; - TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); - switch (state) { // from here sequence overtaken from Linux Kernel function ftdi_port_probe() case CONFIG_FTDI_DETERMINE_TYPE: // determine type - if (itf_num == 0) { + if (p_cdc->bInterfaceNumber == 0) { TU_ASSERT(ftdi_determine_type(p_cdc)); } else { // other interfaces have same type as interface 0 @@ -1318,7 +1313,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_set_data_request(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); + TU_ASSERT(ftdi_set_data_request(p_cdc, cdch_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); break; #else TU_ATTR_FALLTHROUGH; @@ -1327,7 +1322,7 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_SET_BAUDRATE: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_change_speed(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); + TU_ASSERT(ftdi_change_speed(p_cdc, cdch_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); break; #else TU_ATTR_FALLTHROUGH; @@ -1342,15 +1337,14 @@ static bool ftdi_proccess_set_config(tuh_xfer_t *xfer) { case CONFIG_FTDI_MODEM_CTRL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_update_mctrl(p_cdc, ftdi_internal_control_complete, CONFIG_FTDI_COMPLETE)); + TU_ASSERT(ftdi_set_modem_ctrl(p_cdc, cdch_process_set_config, CONFIG_FTDI_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; #endif case CONFIG_FTDI_COMPLETE: - set_config_complete(idx, 0, true); + set_config_complete(p_cdc, 0, true); break; default: @@ -1754,12 +1748,9 @@ static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui return open_ep_stream_pair(p_cdc, desc_ep); } -static bool cp210x_process_set_config(tuh_xfer_t *xfer) { +static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); const uintptr_t state = xfer->user_data; - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); switch (state) { case CONFIG_CP210X_IFC_ENABLE: @@ -1796,7 +1787,7 @@ static bool cp210x_process_set_config(tuh_xfer_t *xfer) { #endif case CONFIG_CP210X_COMPLETE: - set_config_complete(idx, 0, true); + set_config_complete(p_cdc, 0, true); break; default: @@ -2018,13 +2009,10 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, ui return true; } -static bool ch34x_process_set_config(tuh_xfer_t *xfer) { - const uintptr_t state = xfer->user_data; - uint8_t const itf_num = 0; // CH34x has only interface 0, since wIndex is used as payload - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); +static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { uint8_t buffer[2];// TODO remove - TU_ASSERT(p_cdc && xfer->result == XFER_RESULT_SUCCESS); + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); + const uintptr_t state = xfer->user_data; switch (state) { case CONFIG_CH34X_READ_VERSION: @@ -2074,7 +2062,7 @@ static bool ch34x_process_set_config(tuh_xfer_t *xfer) { #endif case CONFIG_CH34X_COMPLETE: - set_config_complete(idx, 0, true); + set_config_complete(p_cdc, 0, true); break; default: @@ -2410,18 +2398,13 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, ui return true; } -static bool pl2303_process_set_config(tuh_xfer_t *xfer) { - const uintptr_t state = xfer->user_data; - // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); +static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() + const uintptr_t state = xfer->user_data; + TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1); uint8_t buf = 0; pl2303_type_t type; - TU_ASSERT(p_cdc && (xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1)); - switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_DETECT_TYPE: @@ -2618,7 +2601,7 @@ static bool pl2303_process_set_config(tuh_xfer_t *xfer) { // break; case CONFIG_PL2303_COMPLETE: - set_config_complete(idx, 0, true); + set_config_complete(p_cdc, 0, true); break; default: -- cgit v1.3.1 From 470e12febca6e371de03120508ef44db28e8501d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 20 Jun 2025 17:25:58 +0700 Subject: refactor, add cdch_internal_control_complete() --- src/class/cdc/cdc_host.c | 233 +++++++++++++++++++---------------------------- 1 file changed, 95 insertions(+), 138 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f36487758..1786f7815 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -119,6 +119,7 @@ static void cdch_internal_control_complete(tuh_xfer_t *xfer); //------------- ACM prototypes -------------// static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); +static void acm_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -144,8 +145,7 @@ static uint16_t const cp210x_vid_pid_list[][2] = {CFG_TUH_CDC_CP210X_VID_PID_LIS static bool cp210x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); -static void acm_internal_control_complete(tuh_xfer_t *xfer); -static void cp210x_internal_control_complete(tuh_xfer_t *xfer); +static void cp210x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -159,7 +159,7 @@ static uint16_t const ch34x_vid_pid_list[][2] = {CFG_TUH_CDC_CH34X_VID_PID_LIST} static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); -static void ch34x_internal_control_complete(tuh_xfer_t *xfer); +static void ch34x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -174,7 +174,7 @@ static const pl2303_type_data_t pl2303_type_data[PL2303_TYPE_COUNT] = {PL2303_TY static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); -static void pl2303_internal_control_complete(tuh_xfer_t *xfer); +static void pl2303_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -237,6 +237,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .is_2stage_line_coding = false, .open = acm_open, .process_set_config = acm_process_set_config, + .request_complete = acm_internal_control_complete, + .set_control_line_state = acm_set_control_line_state, .set_baudrate = acm_set_baudrate, .set_data_format = acm_set_data_format, @@ -252,6 +254,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .open = ftdi_open, .process_set_config = ftdi_proccess_set_config, .request_complete = ftdi_internal_control_complete, + .set_control_line_state = ftdi_set_modem_ctrl, .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, @@ -267,6 +270,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .is_2stage_line_coding = true, .open = cp210x_open, .process_set_config = cp210x_process_set_config, + .request_complete = cp210x_internal_control_complete, + .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, .set_data_format = cp210x_set_data_format, @@ -282,6 +287,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .is_2stage_line_coding = true, .open = ch34x_open, .process_set_config = ch34x_process_set_config, + .request_complete = ch34x_internal_control_complete, + .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, .set_data_format = ch34x_set_data_format, @@ -297,6 +304,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .is_2stage_line_coding = false, .open = pl2303_open, .process_set_config = pl2303_process_set_config, + .request_complete = pl2303_internal_control_complete, + .set_control_line_state = pl2303_set_modem_ctrl, .set_baudrate = pl2303_set_baudrate, .set_data_format = pl2303_set_data_format, @@ -904,37 +913,28 @@ static void cdch_internal_control_complete(tuh_xfer_t *xfer) { //--------------------------------------------------------------------+ // internal control complete to update state such as line state, encoding -static void acm_internal_control_complete(tuh_xfer_t *xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); - - if (success) { - switch (xfer->setup->bRequest) { - case CDC_REQUEST_SET_CONTROL_LINE_STATE: - p_cdc->line.control_state = p_cdc->requested_line.control_state; - break; +static void acm_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY (xfer->result == XFER_RESULT_SUCCESS,); + const tusb_control_request_t * setup = xfer->setup; - case CDC_REQUEST_SET_LINE_CODING: - p_cdc->line.coding = p_cdc->requested_line.coding; - break; + switch (setup->bRequest) { + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + p_cdc->line.control_state = p_cdc->requested_line.control_state; + break; - default: break; - } - } + case CDC_REQUEST_SET_LINE_CODING: + p_cdc->line.coding = p_cdc->requested_line.coding; + break; - xfer->complete_cb = p_cdc->user_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); + default: + break; } } static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { TU_VERIFY(p_cdc->acm.capability.support_line_request); - tusb_control_request_t const request = { + const tusb_control_request_t request = { .bmRequestType_bit = { .recipient = TUSB_REQ_RCPT_INTERFACE, .type = TUSB_REQ_TYPE_CLASS, @@ -953,7 +953,7 @@ static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t co .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = complete_cb ? acm_internal_control_complete : NULL, + .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, .user_data = user_data }; @@ -990,7 +990,7 @@ static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ .ep_addr = 0, .setup = &request, .buffer = enum_buf, - .complete_cb = complete_cb ? acm_internal_control_complete : NULL, + .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, .user_data = user_data }; @@ -1178,6 +1178,7 @@ static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet // internal control complete to update state such as line state, line_coding static void ftdi_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); const tusb_control_request_t * setup = xfer->setup; if (xfer->result == XFER_RESULT_SUCCESS) { if (setup->bRequest == FTDI_SIO_SET_MODEM_CTRL_REQUEST && @@ -1650,50 +1651,36 @@ static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void cp210x_internal_control_complete(tuh_xfer_t *xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); - - if (success) { - switch (xfer->setup->bRequest) { - case CP210X_SET_MHS: - p_cdc->line.control_state = p_cdc->requested_line.control_state; - break; - - case CP210X_SET_LINE_CTL: - p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; - p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; - p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; - break; +static void cp210x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); + switch (xfer->setup->bRequest) { + case CP210X_SET_MHS: + p_cdc->line.control_state = p_cdc->requested_line.control_state; + break; - case CP210X_SET_BAUDRATE: - p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; - break; + case CP210X_SET_LINE_CTL: + p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; + p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; + p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; + break; - default: break; - } - } + case CP210X_SET_BAUDRATE: + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; + break; - xfer->complete_cb = p_cdc->user_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); + default: break; } } static bool cp210x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } static bool cp210x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -1701,7 +1688,7 @@ static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); set_line_coding_stage1_complete(xfer, itf_num, cp210x_set_line_ctl, // control request function to set data format - cp210x_internal_control_complete); // control complete function to be called after request + cdch_internal_control_complete); // control complete function to be called after request } // 2 stages: set baudrate (stage1) + set data format (stage2) @@ -1710,14 +1697,13 @@ static bool cp210x_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t comple cp210x_set_baudrate_request, // control request function to set baudrate cp210x_set_line_ctl, // control request function to set data format cp210x_set_line_coding_stage1_complete, // function to be called after stage 1 completed - cp210x_internal_control_complete, // control complete function to be called after request + cdch_internal_control_complete, // control complete function to be called after request complete_cb, user_data); } static bool cp210x_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cp210x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -1761,7 +1747,7 @@ static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_LINE_CTL)); + TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_SET_LINE_CTL)); break; #else TU_ATTR_FALLTHROUGH; @@ -1770,7 +1756,7 @@ static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_CP210X_SET_LINE_CTL: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_line_ctl(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_SET_DTR_RTS)); + TU_ASSERT(cp210x_set_line_ctl(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_SET_DTR_RTS)); break; #else TU_ATTR_FALLTHROUGH; @@ -1780,7 +1766,7 @@ static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_mhs(p_cdc, cp210x_internal_control_complete, CONFIG_CP210X_COMPLETE)); + TU_ASSERT(cp210x_set_mhs(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -1891,60 +1877,45 @@ static bool ch34x_modem_ctrl_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t comp //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void ch34x_internal_control_complete(tuh_xfer_t *xfer) { - // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); +static void ch34x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); + switch (xfer->setup->bRequest) { + case CH34X_REQ_WRITE_REG: + // register write request + switch (tu_le16toh(xfer->setup->wValue)) { + case CH34X_REG16_DIVISOR_PRESCALER: + // baudrate + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; + break; - if (success) { - switch (xfer->setup->bRequest) { - case CH34X_REQ_WRITE_REG: - // register write request - switch (tu_le16toh(xfer->setup->wValue)) { - case CH34X_REG16_DIVISOR_PRESCALER: - // baudrate - p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; - break; - - case CH32X_REG16_LCR2_LCR: - // data format - p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; - p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; - p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; - break; - - default: break; - } - break; + case CH32X_REG16_LCR2_LCR: + // data format + p_cdc->line.coding.stop_bits = p_cdc->requested_line.coding.stop_bits; + p_cdc->line.coding.parity = p_cdc->requested_line.coding.parity; + p_cdc->line.coding.data_bits = p_cdc->requested_line.coding.data_bits; + break; - case CH34X_REQ_MODEM_CTRL: - p_cdc->line.control_state = p_cdc->requested_line.control_state; - break; + default: break; + } + break; - default: break; - } - } + case CH34X_REQ_MODEM_CTRL: + p_cdc->line.control_state = p_cdc->requested_line.control_state; + break; - xfer->complete_cb = p_cdc->user_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); + default: break; } } static bool ch34x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } static bool ch34x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -1953,7 +1924,7 @@ static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { uint8_t const itf_num = 0; set_line_coding_stage1_complete(xfer, itf_num, ch34x_write_reg_data_format, // control request function to set data format - ch34x_internal_control_complete); // control complete function to be called after request + cdch_internal_control_complete); // control complete function to be called after request } // 2 stages: set baudrate (stage1) + set data format (stage2) @@ -1962,14 +1933,13 @@ static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t comple ch34x_write_reg_baudrate, // control request function to set baudrate ch34x_write_reg_data_format, // control request function to set data format ch34x_set_line_coding_stage1_complete, // function to be called after stage 1 completed - ch34x_internal_control_complete, // control complete function to be called after request + cdch_internal_control_complete, // control complete function to be called after request complete_cb, user_data); } static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, complete_cb ? ch34x_internal_control_complete : NULL, user_data)); - + TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -2055,7 +2025,7 @@ static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, ch34x_internal_control_complete, CONFIG_CH34X_COMPLETE)); + TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, cdch_internal_control_complete, CONFIG_CH34X_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; @@ -2293,41 +2263,28 @@ static inline int pl2303_clear_halt(cdch_interface_t *p_cdc, uint8_t endp, tuh_x //------------- Driver API -------------// // internal control complete to update state such as line state, encoding -static void pl2303_internal_control_complete(tuh_xfer_t *xfer) { - // PL2303 has only interface 0, because wIndex is used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - uint8_t idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - bool const success = (xfer->result == XFER_RESULT_SUCCESS); - - if (success) { - if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { - p_cdc->line.coding = p_cdc->requested_line.coding; - } - if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { - p_cdc->line.control_state = p_cdc->requested_line.control_state; - } +static void pl2303_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); + if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { + p_cdc->line.coding = p_cdc->requested_line.coding; } - - xfer->complete_cb = p_cdc->user_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); + if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { + p_cdc->line.control_state = p_cdc->requested_line.control_state; } } static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } static bool pl2303_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { p_cdc->requested_line.coding.bit_rate = p_cdc->line.coding.bit_rate; p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -2336,14 +2293,14 @@ static bool pl2303_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ p_cdc->requested_line.coding.parity = p_cdc->line.coding.parity; p_cdc->requested_line.coding.data_bits = p_cdc->line.coding.data_bits; p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? pl2303_internal_control_complete : NULL, user_data)); + TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); return true; } @@ -2557,7 +2514,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_LINE_CODING: #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(pl2303_set_line_request(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); + TU_ASSERT(pl2303_set_line_request(p_cdc, cdch_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); break; #else TU_ATTR_FALLTHROUGH; @@ -2566,7 +2523,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_MODEM_CONTROL: #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(pl2303_set_control_lines(p_cdc, pl2303_internal_control_complete, CONFIG_PL2303_COMPLETE)); + TU_ASSERT(pl2303_set_control_lines(p_cdc, cdch_internal_control_complete, CONFIG_PL2303_COMPLETE)); break; #else TU_ATTR_FALLTHROUGH; -- cgit v1.3.1 From 4ae433fa6ef451cccb2b09aa3748978b46aade5f Mon Sep 17 00:00:00 2001 From: milek7 Date: Wed, 25 Jun 2025 03:35:40 +0200 Subject: stm32_fsdev: Allow configuring single-buffered isochronous endpoints. Controlled by the embedder defining CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP in tusb_config.h. If hardware does have SBUF_ISO bit it will use only one half of endpoint pair register. --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 47 ++++++++++++++++++++++----- src/portable/st/stm32_fsdev/fsdev_ch32.h | 5 +++ src/portable/st/stm32_fsdev/fsdev_stm32.h | 38 ++++++++++++++++++++++ 3 files changed, 82 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ef58957bb..ad733b16a 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -331,8 +331,13 @@ static void handle_ctr_rx(uint32_t ep_id) { xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, TUSB_DIR_OUT); uint8_t buf_id; - if (is_iso) { - buf_id = (ep_reg & USB_EP_DTOG_RX) ? 0 : 1; // ISO are double buffered +#if FSDEV_USE_SBUF_ISO == 0 + bool const dbl_buf = is_iso; +#else + bool const dbl_buf = false; +#endif + if (dbl_buf) { + buf_id = (ep_reg & USB_EP_DTOG_RX) ? 0 : 1; } else { buf_id = BTABLE_BUF_RX; } @@ -527,10 +532,16 @@ static uint8_t dcd_ep_alloc(uint8_t ep_addr, uint8_t ep_type) return i; } +#if FSDEV_USE_SBUF_ISO == 0 + bool const dbl_buf = ep_type == TUSB_XFER_ISOCHRONOUS; +#else + bool const dbl_buf = false; +#endif + // If EP of current direction is not allocated - // Except for ISO endpoint, both direction should be free + // For double-buffered mode both directions needs to be free if (!ep_alloc_status[i].allocated[dir] && - (ep_type != TUSB_XFER_ISOCHRONOUS || !ep_alloc_status[i].allocated[dir ^ 1])) { + (!dbl_buf || !ep_alloc_status[i].allocated[dir ^ 1])) { // Check if EP number is the same if (ep_alloc_status[i].ep_num == 0xFF || ep_alloc_status[i].ep_num == epnum) { // One EP pair has to be the same type @@ -652,9 +663,7 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const ep_idx = dcd_ep_alloc(ep_addr, TUSB_XFER_ISOCHRONOUS); - /* Create a packet memory buffer area. Enable double buffering for devices with 2048 bytes PMA, - for smaller devices double buffering occupy too much space. */ -#if FSDEV_PMA_SIZE > 1024u +#if CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP != 0 uint32_t pma_addr = dcd_pma_alloc(largest_packet_size, true); uint16_t pma_addr2 = pma_addr >> 16; #else @@ -662,8 +671,12 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet uint16_t pma_addr2 = pma_addr; #endif +#if FSDEV_USE_SBUF_ISO == 0 btable_set_addr(ep_idx, 0, pma_addr); btable_set_addr(ep_idx, 1, pma_addr2); +#else + btable_set_addr(ep_idx, dir == TUSB_DIR_IN ? BTABLE_BUF_TX : BTABLE_BUF_RX, pma_addr); +#endif xfer_ctl_t* xfer = xfer_ctl_ptr(ep_num, dir); xfer->ep_idx = ep_idx; @@ -684,10 +697,23 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) uint32_t ep_reg = ep_read(ep_idx) & ~USB_EPREG_MASK; ep_reg |= tu_edpt_number(ep_addr) | USB_EP_ISOCHRONOUS | USB_EP_CTR_TX | USB_EP_CTR_RX; +#if FSDEV_USE_SBUF_ISO != 0 + ep_reg |= USB_EP_KIND; + + ep_change_status(&ep_reg, dir, EP_STAT_DISABLED); + ep_change_dtog(&ep_reg, dir, 0); + + if (dir == TUSB_DIR_IN) { + ep_reg &= ~(USB_EPRX_STAT | USB_EP_DTOG_RX); + } else { + ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX); + } +#else ep_change_status(&ep_reg, TUSB_DIR_IN, EP_STAT_DISABLED); ep_change_status(&ep_reg, TUSB_DIR_OUT, EP_STAT_DISABLED); ep_change_dtog(&ep_reg, dir, 0); ep_change_dtog(&ep_reg, (tusb_dir_t)(1 - dir), 1); +#endif ep_write(ep_idx, ep_reg, true); @@ -702,7 +728,12 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) { bool const is_iso = ep_is_iso(ep_reg); uint8_t buf_id; - if (is_iso) { +#if FSDEV_USE_SBUF_ISO == 0 + bool const dbl_buf = is_iso; +#else + bool const dbl_buf = false; +#endif + if (dbl_buf) { buf_id = (ep_reg & USB_EP_DTOG_TX) ? 1 : 0; } else { buf_id = BTABLE_BUF_TX; diff --git a/src/portable/st/stm32_fsdev/fsdev_ch32.h b/src/portable/st/stm32_fsdev/fsdev_ch32.h index 518197c47..ceebb6dab 100644 --- a/src/portable/st/stm32_fsdev/fsdev_ch32.h +++ b/src/portable/st/stm32_fsdev/fsdev_ch32.h @@ -54,9 +54,14 @@ #endif #define FSDEV_PMA_SIZE (512u) +#define FSDEV_USE_SBUF_ISO 0 #define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) #define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) +#ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP + #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 0 +#endif + /**************************** ISTR interrupt events *************************/ #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index ccf31e035..770baa05a 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -36,6 +36,7 @@ #include "stm32f0xx.h" #define FSDEV_PMA_SIZE (1024u) #define FSDEV_REG_BASE USB_BASE + #define FSDEV_HAS_SBUF_ISO 0 // F0x2 models are crystal-less // All have internal D+ pull-up // 070RB: 2 x 16 bits/word memory LPM Support, BCD Support @@ -44,6 +45,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32F1 #include "stm32f1xx.h" #define FSDEV_PMA_SIZE (512u) + #define FSDEV_HAS_SBUF_ISO 0 // NO internal Pull-ups // *B, and *C: 2 x 16 bits/word @@ -55,6 +57,7 @@ defined(STM32F373xC) #include "stm32f3xx.h" #define FSDEV_PMA_SIZE (512u) + #define FSDEV_HAS_SBUF_ISO 0 // NO internal Pull-ups // *B, and *C: 1 x 16 bits/word // PMA dedicated to USB (no sharing with CAN) @@ -64,6 +67,7 @@ defined(STM32F303xD) || defined(STM32F303xE) #include "stm32f3xx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 // NO internal Pull-ups // *6, *8, *D, and *E: 2 x 16 bits/word LPM Support // When CAN clock is enabled, USB can use first 768 bytes ONLY. @@ -71,18 +75,22 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32L0 #include "stm32l0xx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 #elif CFG_TUSB_MCU == OPT_MCU_STM32L1 #include "stm32l1xx.h" #define FSDEV_PMA_SIZE (512u) + #define FSDEV_HAS_SBUF_ISO 0 #elif CFG_TUSB_MCU == OPT_MCU_STM32G4 #include "stm32g4xx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 #include "stm32g0xx.h" #define FSDEV_PMA_SIZE (2048u) + #define FSDEV_HAS_SBUF_ISO 1 #define USB USB_DRD_FS #define USB_EP_CTR_RX USB_EP_VTRX @@ -107,6 +115,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32C0 #include "stm32c0xx.h" #define FSDEV_PMA_SIZE (2048u) + #define FSDEV_HAS_SBUF_ISO 1 #define USB USB_DRD_FS #define USB_EP_CTR_RX USB_CHEP_VTRX #define USB_EP_CTR_TX USB_CHEP_VTTX @@ -121,6 +130,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 #include "stm32h5xx.h" #define FSDEV_PMA_SIZE (2048u) + #define FSDEV_HAS_SBUF_ISO 1 #define USB USB_DRD_FS #define USB_EP_CTR_RX USB_EP_VTRX @@ -145,16 +155,19 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32WB #include "stm32wbxx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 /* ST provided header has incorrect value of USB_PMAADDR */ #define FSDEV_PMA_BASE USB1_PMAADDR #elif CFG_TUSB_MCU == OPT_MCU_STM32L4 #include "stm32l4xx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 #elif CFG_TUSB_MCU == OPT_MCU_STM32L5 #include "stm32l5xx.h" #define FSDEV_PMA_SIZE (1024u) + #define FSDEV_HAS_SBUF_ISO 0 #ifndef USB_PMAADDR #define USB_PMAADDR (USB_BASE + (USB_PMAADDR_NS - USB_BASE_NS)) @@ -163,6 +176,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 #include "stm32u5xx.h" #define FSDEV_PMA_SIZE (2048u) + #define FSDEV_HAS_SBUF_ISO 1 #define USB USB_DRD_FS #define USB_EP_CTR_RX USB_EP_VTRX @@ -187,6 +201,7 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 #include "stm32u0xx.h" #define FSDEV_PMA_SIZE (2048u) + #define FSDEV_HAS_SBUF_ISO 1 #define USB USB_DRD_FS #define USB_EP_CTR_RX USB_EP_VTRX @@ -248,6 +263,29 @@ #define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \ USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED ) +#ifndef FSDEV_HAS_SBUF_ISO + #error "FSDEV_HAS_SBUF_ISO not defined" +#endif + +#ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP + // Defaults to double-buffered isochronous endpoints on devices with >1KB PMA + #if FSDEV_PMA_SIZE > 1024u + #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 1 + #else + #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 0 + #endif +#endif + +#if FSDEV_HAS_SBUF_ISO != 0 && CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP == 0 + // If hardware has SBUF_ISO bit single-buffered endpoints consume only + // one half of endpoint pair register. + #define FSDEV_USE_SBUF_ISO 1 +#else + // Otherwise it consumes entire endpoint pair but we can at least save + // memory by configuring the same buffer twice. + #define FSDEV_USE_SBUF_ISO 0 +#endif + //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -- cgit v1.3.1 From 2843eb405252ba4f8475c86d346b95547fb4020c Mon Sep 17 00:00:00 2001 From: milek7 Date: Thu, 26 Jun 2025 00:03:25 +0200 Subject: audio_device: Fix data IN endpoints with implicit feedback --- src/class/audio/audio_device.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 11a3d4a73..a877dc900 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -1003,20 +1003,22 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint ep_fb = desc_ep->bEndpointAddress; } #endif - // Data EP - if (desc_ep->bmAttributes.usage == 0) { - if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { #if CFG_TUD_AUDIO_ENABLE_EP_IN - ep_in = desc_ep->bEndpointAddress; - ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); + // Data or data with implicit feedback IN EP + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN + && (desc_ep->bmAttributes.usage == 0 || desc_ep->bmAttributes.usage == 2)) { + ep_in = desc_ep->bEndpointAddress; + ep_in_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_in_size); + } #endif - } else { #if CFG_TUD_AUDIO_ENABLE_EP_OUT - ep_out = desc_ep->bEndpointAddress; - ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); - #endif - } + // Data OUT EP + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_OUT + && desc_ep->bmAttributes.usage == 0) { + ep_out = desc_ep->bEndpointAddress; + ep_out_size = TU_MAX(tu_edpt_packet_size(desc_ep), ep_out_size); } + #endif } } @@ -1052,10 +1054,10 @@ uint16_t audiod_open(uint8_t rhport, tusb_desc_interface_t const *itf_desc, uint if (tu_desc_type(p_desc) == TUSB_DESC_ENDPOINT) { tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { - if (desc_ep->bmAttributes.usage == 0) { - if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { - _audiod_fct[i].interval_tx = desc_ep->bInterval; - } + // For data or data with implicit feedback IN EP + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN + && (desc_ep->bmAttributes.usage == 0 || desc_ep->bmAttributes.usage == 2)) { + _audiod_fct[i].interval_tx = desc_ep->bInterval; } } } else if (tu_desc_type(p_desc) == TUSB_DESC_CS_INTERFACE && tu_desc_subtype(p_desc) == AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL) { @@ -1227,7 +1229,8 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p usbd_edpt_clear_stall(rhport, ep_addr); #if CFG_TUD_AUDIO_ENABLE_EP_IN - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && desc_ep->bmAttributes.usage == 0x00)// Check if usage is data EP + // For data or data with implicit feedback IN EP + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN && (desc_ep->bmAttributes.usage == 0 || desc_ep->bmAttributes.usage == 2)) { // Save address audio->ep_in = ep_addr; -- cgit v1.3.1 From 8b5d703f74153c75dd9e4cfb224dbe74e4e262fa Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Jun 2025 15:57:18 +0700 Subject: major refactor to generalize cdch serial driver - add common 2 stage set line coding for driver without direct set_line_coding support e.g ftdi, cp210x, ch34x - add common cdch_process_line_state_on_enum() to handle cfg line state on enum e.g CFG_TUH_CDC_LINE_CONTROL/CODING_ON_ENUM - refactor cdch_internal_control_complete and user_complete_cb to be managed by tuh_cdc_ API instead of serial driver --- src/class/cdc/cdc_host.c | 661 ++++++++++++++++--------------------------- src/class/cdc/serial/ch34x.h | 4 +- 2 files changed, 245 insertions(+), 420 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 1786f7815..7926aa9fc 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -45,12 +45,9 @@ #define CFG_TUH_CDC_LOG_LEVEL 1 #endif -#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) -#define TU_LOG_CDC(_cdc, _format, ...) TU_LOG_DRV("[:%u:%u] CDCh %s " _format "\r\n", _cdc->daddr, _cdc->bInterfaceNumber, \ - serial_drivers[_cdc->serial_drid].name, ##__VA_ARGS__) - -// Driver that need to set line coding in two stages: baudrate then data format. -#define DRIVER_2STAGE_SET_LINE_CODING (CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X) +#define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) +#define TU_LOG_CDC(_cdc, _format, ...) TU_LOG_DRV("[:%u:%u] CDCh %s " _format "\r\n", _cdc->daddr, _cdc->bInterfaceNumber, \ + serial_drivers[_cdc->serial_drid].name, ##__VA_ARGS__) //--------------------------------------------------------------------+ // Host CDC Interface @@ -73,10 +70,6 @@ typedef struct { tuh_xfer_cb_t user_complete_cb; // required since we handle request internally first - #if DRIVER_2STAGE_SET_LINE_CODING - tuh_xfer_cb_t requested_complete_cb; - #endif - union { struct { cdc_acm_capability_t capability; @@ -114,7 +107,10 @@ CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; // General driver static void cdch_process_set_config(tuh_xfer_t *xfer); +static void cdch_process_line_state_on_enum(tuh_xfer_t *xfer); // invoked after set config is processed static void cdch_internal_control_complete(tuh_xfer_t *xfer); +static void cdch_set_line_coding_stage1_baudrate_complete(tuh_xfer_t *xfer); +static void cdch_set_line_coding_stage2_data_format_complete(tuh_xfer_t *xfer); //------------- ACM prototypes -------------// static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint16_t max_len); @@ -135,7 +131,6 @@ static void ftdi_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t * static bool ftdi_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ftdi_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -149,7 +144,6 @@ static void cp210x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t static bool cp210x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool cp210x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool cp210x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -163,7 +157,6 @@ static void ch34x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t static bool ch34x_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -210,8 +203,6 @@ typedef bool (*serial_driver_func_t)(cdch_interface_t * p_cdc, tuh_xfer_cb_t com typedef struct { uint16_t const (*vid_pid_list)[2]; uint16_t const vid_pid_count; - bool is_2stage_line_coding; // true if driver requires to set baudrate then data format separately - bool (*const open)(uint8_t daddr, const tusb_desc_interface_t * itf_desc, uint16_t max_len); bool (*const process_set_config)(cdch_interface_t * p_cdc, tuh_xfer_t * xfer); void (*const request_complete)(cdch_interface_t * p_cdc, tuh_xfer_t * xfer); // internal request complete handler to update line state @@ -234,7 +225,6 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = NULL, .vid_pid_count = 0, - .is_2stage_line_coding = false, .open = acm_open, .process_set_config = acm_process_set_config, .request_complete = acm_internal_control_complete, @@ -250,15 +240,13 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = ftdi_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ftdi_vid_pid_list), - .is_2stage_line_coding = true, .open = ftdi_open, .process_set_config = ftdi_proccess_set_config, .request_complete = ftdi_internal_control_complete, - .set_control_line_state = ftdi_set_modem_ctrl, .set_baudrate = ftdi_set_baudrate, .set_data_format = ftdi_set_data_format, - .set_line_coding = ftdi_set_line_coding, + .set_line_coding = NULL, // 2 stage set line coding DRIVER_NAME_DECLARE("FTDI") }, #endif @@ -267,15 +255,13 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = cp210x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(cp210x_vid_pid_list), - .is_2stage_line_coding = true, .open = cp210x_open, .process_set_config = cp210x_process_set_config, .request_complete = cp210x_internal_control_complete, - .set_control_line_state = cp210x_set_modem_ctrl, .set_baudrate = cp210x_set_baudrate, .set_data_format = cp210x_set_data_format, - .set_line_coding = cp210x_set_line_coding, + .set_line_coding = NULL, // 2 stage set line coding DRIVER_NAME_DECLARE("CP210x") }, #endif @@ -284,7 +270,6 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = ch34x_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(ch34x_vid_pid_list), - .is_2stage_line_coding = true, .open = ch34x_open, .process_set_config = ch34x_process_set_config, .request_complete = ch34x_internal_control_complete, @@ -292,7 +277,7 @@ static const cdch_serial_driver_t serial_drivers[] = { .set_control_line_state = ch34x_set_modem_ctrl, .set_baudrate = ch34x_set_baudrate, .set_data_format = ch34x_set_data_format, - .set_line_coding = ch34x_set_line_coding, + .set_line_coding = NULL, // 2 stage set line coding DRIVER_NAME_DECLARE("CH34x") }, #endif @@ -301,11 +286,9 @@ static const cdch_serial_driver_t serial_drivers[] = { { .vid_pid_list = pl2303_vid_pid_list, .vid_pid_count = TU_ARRAY_SIZE(pl2303_vid_pid_list), - .is_2stage_line_coding = false, .open = pl2303_open, .process_set_config = pl2303_process_set_config, .request_complete = pl2303_internal_control_complete, - .set_control_line_state = pl2303_set_modem_ctrl, .set_baudrate = pl2303_set_baudrate, .set_data_format = pl2303_set_data_format, @@ -474,28 +457,24 @@ bool tuh_cdc_get_line_coding_local(uint8_t idx, cdc_line_coding_t * line_coding) uint32_t tuh_cdc_write(uint8_t idx, void const * buffer, uint32_t bufsize) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write(p_cdc->daddr, &p_cdc->stream.tx, buffer, bufsize); } uint32_t tuh_cdc_write_flush(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write_xfer(p_cdc->daddr, &p_cdc->stream.tx); } bool tuh_cdc_write_clear(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_clear(&p_cdc->stream.tx); } uint32_t tuh_cdc_write_available(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_write_available(p_cdc->daddr, &p_cdc->stream.tx); } @@ -506,21 +485,18 @@ uint32_t tuh_cdc_write_available(uint8_t idx) { uint32_t tuh_cdc_read (uint8_t idx, void * buffer, uint32_t bufsize) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_read(p_cdc->daddr, &p_cdc->stream.rx, buffer, bufsize); } uint32_t tuh_cdc_read_available(uint8_t idx) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_read_available(&p_cdc->stream.rx); } bool tuh_cdc_peek(uint8_t idx, uint8_t * ch) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc); - return tu_edpt_stream_peek(&p_cdc->stream.rx, ch); } @@ -537,105 +513,40 @@ bool tuh_cdc_read_clear (uint8_t idx) { // Control Endpoint API //--------------------------------------------------------------------+ -#if DRIVER_2STAGE_SET_LINE_CODING - -// set line coding using sequence with 2 stages: set baudrate (stage1) + set data format (stage2) -static bool set_line_coding_sequence( - cdch_interface_t * p_cdc, - serial_driver_func_t set_baudrate, - serial_driver_func_t set_data_format, - tuh_xfer_cb_t set_line_coding_stage1_complete, // function to be called after stage 1 completed - tuh_xfer_cb_t internal_control_complete, // control complete function to be called after request - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - if (complete_cb) { - // non-blocking - // stage 1 set baudrate - p_cdc->requested_complete_cb = complete_cb; // store complete_cb to be used in set_line_coding_stage1_complete() - p_cdc->user_complete_cb = set_line_coding_stage1_complete; - return set_baudrate(p_cdc, internal_control_complete, user_data); - } else { - // blocking sequence - // stage 1 set baudrate - xfer_result_t result = XFER_RESULT_INVALID; // use local result, because user_data ptr may be NULL - bool ret = set_baudrate(p_cdc, NULL, (uintptr_t) &result); - - if (user_data) { - *((xfer_result_t *) user_data) = result; - } - - TU_ASSERT(ret); - TU_VERIFY(result == XFER_RESULT_SUCCESS); - - // overtake baudrate after successful request - p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; - - // stage 2 set data format - result = XFER_RESULT_INVALID; - ret = set_data_format(p_cdc, NULL, (uintptr_t) &result); - - if (user_data) { - *((xfer_result_t *) user_data) = result; - } - - TU_ASSERT(ret); - return (result == XFER_RESULT_SUCCESS); - // the overtaking of remaining requested_line_coding will be done in tuh_cdc_set_line_coding() - } -} - -static void set_line_coding_stage1_complete( - tuh_xfer_t * xfer, uint8_t const itf_num, - // control request function to set data format - bool (*set_data_format_request)(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data), - // control complete function to be called after request - void (*internal_control_complete)(tuh_xfer_t * xfer)) { - uint8_t const idx = tuh_cdc_itf_get_index(xfer->daddr, itf_num); - cdch_interface_t * p_cdc = get_itf(idx); - TU_ASSERT(p_cdc,); - - if (xfer->result == XFER_RESULT_SUCCESS) { - // stage 1 success, continue with stage 2 - p_cdc->user_complete_cb = p_cdc->requested_complete_cb; - set_data_format_request(p_cdc, internal_control_complete, xfer->user_data); - } else { - // stage 1 failed, notify user - xfer->complete_cb = p_cdc->requested_complete_cb; - if (xfer->complete_cb) { - xfer->complete_cb(xfer); - } - } -} -#endif - bool tuh_cdc_set_control_line_state(uint8_t idx, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t * p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_CDC(p_cdc, "set control line state dtr = %u rts = %u", p_cdc->requested_line.control_state.dtr, p_cdc->requested_line.control_state.rts); - cdch_serial_driver_t const * driver = &serial_drivers[p_cdc->serial_drid]; + const cdch_serial_driver_t * driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line.control_state.value = (uint8_t) line_state; - const bool ret = driver->set_control_line_state(p_cdc, complete_cb, user_data); - if (ret && !complete_cb) { + p_cdc->user_complete_cb = complete_cb; + TU_VERIFY(driver->set_control_line_state(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); + + if (!complete_cb) { // blocking, update line state if request was successful p_cdc->line.control_state.value = (uint8_t) line_state; } - return ret; + return true; } bool tuh_cdc_set_baudrate(uint8_t idx, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { cdch_interface_t *p_cdc = get_itf(idx); TU_VERIFY(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); TU_LOG_CDC(p_cdc, "set baudrate %lu", baudrate); - cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; + const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line = p_cdc->line; // keep current line coding p_cdc->requested_line.coding.bit_rate = baudrate; - const bool ret = driver->set_baudrate(p_cdc, complete_cb, user_data); - if (ret && !complete_cb) { + p_cdc->user_complete_cb = complete_cb; + TU_VERIFY(driver->set_baudrate(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); + + if (!complete_cb) { p_cdc->line.coding.bit_rate = baudrate; } - return ret; + return true; } bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uint8_t data_bits, @@ -645,20 +556,24 @@ bool tuh_cdc_set_data_format(uint8_t idx, uint8_t stop_bits, uint8_t parity, uin TU_LOG_CDC(p_cdc, "set data format %u%c%s", data_bits, CDC_LINE_CODING_PARITY_CHAR(parity), CDC_LINE_CODING_STOP_BITS_TEXT(stop_bits)); - cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; + const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; + p_cdc->requested_line = p_cdc->line; // keep current line coding p_cdc->requested_line.coding.stop_bits = stop_bits; p_cdc->requested_line.coding.parity = parity; p_cdc->requested_line.coding.data_bits = data_bits; - const bool ret = driver->set_data_format(p_cdc, complete_cb, user_data); + p_cdc->user_complete_cb = complete_cb; + TU_VERIFY(driver->set_data_format(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - if (ret && !complete_cb) { + if (!complete_cb) { + // blocking p_cdc->line.coding.stop_bits = stop_bits; p_cdc->line.coding.parity = parity; p_cdc->line.coding.data_bits = data_bits; } - return ret; + + return true; } bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, @@ -670,16 +585,43 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, CDC_LINE_CODING_PARITY_CHAR(line_coding->parity), CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; - p_cdc->requested_line.coding = *line_coding; - const bool ret = driver->set_line_coding(p_cdc, complete_cb, user_data); + if (driver->set_line_coding) { + // driver support set_line_coding request + TU_VERIFY(driver->set_line_coding(p_cdc, complete_cb, user_data)); + + if (!complete_cb) { + p_cdc->line.coding = *line_coding; + } + } else { + // driver does not support set_line_coding and need 2 stage to set baudrate and data format separately + if (complete_cb) { + // non-blocking + p_cdc->user_complete_cb = complete_cb; + TU_VERIFY(driver->set_baudrate(p_cdc, cdch_set_line_coding_stage1_baudrate_complete, user_data)); + } else { + // blocking + xfer_result_t result = XFER_RESULT_INVALID; + + TU_VERIFY(driver->set_baudrate(p_cdc, NULL, (uintptr_t) &result)); + if (user_data) { + *((xfer_result_t *) user_data) = result; + } + TU_VERIFY(result == XFER_RESULT_SUCCESS); + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; // update baudrate - if (ret && !complete_cb) { - p_cdc->line.coding = *line_coding; + result = XFER_RESULT_INVALID; + TU_VERIFY(driver->set_data_format(p_cdc, NULL, (uintptr_t) &result)); + if (user_data) { + *((xfer_result_t *) user_data) = result; + } + TU_VERIFY(result == XFER_RESULT_SUCCESS); + p_cdc->line.coding = p_cdc->requested_line.coding; // update data format + } } - return ret; + return true; } //--------------------------------------------------------------------+ @@ -809,41 +751,50 @@ static bool open_ep_stream_pair(cdch_interface_t *p_cdc, tusb_desc_endpoint_t co bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { (void) rhport; - cdch_serial_driver_t const *driver_detected = NULL; - // For CDC: only support ACM subclass // Note: Protocol 0xFF can be RNDIS device if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { return acm_open(daddr, itf_desc, max_len); - } else if (SERIAL_DRIVER_COUNT > 1 && - TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { - uint16_t vid, pid; - TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); - - for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { - cdch_serial_driver_t const *driver = &serial_drivers[dr]; - for (size_t i = 0; i < driver->vid_pid_count; i++) { - if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { - driver_detected = driver; - break; + } else if (SERIAL_DRIVER_COUNT > 1 && + TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { + uint16_t vid, pid; + TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); + + for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { + const cdch_serial_driver_t *driver = &serial_drivers[dr]; + for (size_t i = 0; i < driver->vid_pid_count; i++) { + if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { + const bool ret = driver->open(daddr, itf_desc, max_len); + TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver->name, ret ? "OK" : "FAILED"); + return ret; + } + } } - } - if (driver_detected) { - break; - } - } - } - - if (driver_detected) { - const bool ret = driver_detected->open(daddr, itf_desc, max_len); - TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver_detected->name, ret ? "OK" : "FAILED"); - return ret; - } + } return false; } +bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { + tusb_control_request_t request; + request.wIndex = tu_htole16((uint16_t) itf_num); + uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); + cdch_interface_t *p_cdc = get_itf(idx); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); + TU_LOG_CDC(p_cdc, "set config"); + + // fake transfer to kick-off process_set_config() + tuh_xfer_t xfer; + xfer.daddr = daddr; + xfer.result = XFER_RESULT_SUCCESS; + xfer.setup = &request; + xfer.user_data = 0; // initial state 0 + cdch_process_set_config(&xfer); + + return true; +} + static void set_config_complete(cdch_interface_t *p_cdc, uint8_t itf_offset, bool success) { if (success) { const uint8_t idx = get_idx_by_ptr(p_cdc); @@ -863,43 +814,81 @@ static void set_config_complete(cdch_interface_t *p_cdc, uint8_t itf_offset, boo usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset); } -bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { - tusb_control_request_t request; - request.wIndex = tu_htole16((uint16_t) itf_num); - uint8_t const idx = tuh_cdc_itf_get_index(daddr, itf_num); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT); - TU_LOG_CDC(p_cdc, "set config"); +static void cdch_process_set_config(tuh_xfer_t *xfer) { + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + TU_LOG_DRV(" state = %u\r\n", xfer->user_data); + const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; - // fake transfer to kick-off process_set_config() - tuh_xfer_t xfer; - xfer.daddr = daddr; - xfer.result = XFER_RESULT_SUCCESS; - xfer.setup = &request; - xfer.user_data = 0; // initial state 0 - cdch_process_set_config(&xfer); + if (!driver->process_set_config(p_cdc, xfer)) { + const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; + set_config_complete(p_cdc, itf_offset, false); + } +} + +static bool set_line_state_on_enum(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + enum { + ENUM_SET_LINE_CODING = 0, + ENUM_SET_LINE_CONTROL, + ENUM_SET_LINE_COMPLETE, + }; + const uint8_t idx = get_idx_by_ptr(p_cdc); + const uintptr_t state = xfer->user_data; + + switch (state) { + case ENUM_SET_LINE_CODING: { + #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + // ch34x already set line coding in serial init + if (p_cdc->serial_drid != SERIAL_DRIVER_CH34X) { + const cdc_line_coding_t line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; + TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, + cdch_process_line_state_on_enum, ENUM_SET_LINE_CONTROL)); + break; + } + #endif + TU_ATTR_FALLTHROUGH; + } + + case ENUM_SET_LINE_CONTROL: + #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM + TU_ASSERT(tuh_cdc_set_control_line_state(idx, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, + cdch_process_line_state_on_enum, ENUM_SET_LINE_COMPLETE)); + break; + #else + TU_ATTR_FALLTHROUGH; + #endif + + case ENUM_SET_LINE_COMPLETE: { + const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; + set_config_complete(p_cdc, itf_offset, true); + break; + } + + default: + return false; + } return true; } - -static void cdch_process_set_config(tuh_xfer_t *xfer) { +static void cdch_process_line_state_on_enum(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); - TU_LOG_DRV(" state = %u\r\n", xfer->user_data); + TU_LOG_DRV(" xfer result = %u\r\n", xfer->result); - if (!serial_drivers[p_cdc->serial_drid].process_set_config(p_cdc, xfer)) { + if (xfer->result != XFER_RESULT_SUCCESS || !set_line_state_on_enum(p_cdc, xfer)) { const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; set_config_complete(p_cdc, itf_offset, false); } } + static void cdch_internal_control_complete(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); - TU_LOG_DRV(" request result = %u\r\n", xfer->result); - serial_drivers[p_cdc->serial_drid].request_complete(p_cdc, xfer); + const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; + driver->request_complete(p_cdc, xfer); // Invoke application callback xfer->complete_cb = p_cdc->user_complete_cb; @@ -908,6 +897,38 @@ static void cdch_internal_control_complete(tuh_xfer_t *xfer) { } } +static void cdch_set_line_coding_stage1_baudrate_complete(tuh_xfer_t *xfer) { + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + TU_LOG_DRV(" stage1 set baudrate result = %u\r\n", xfer->result); + const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; + + if (xfer->result == XFER_RESULT_SUCCESS) { + p_cdc->line.coding.bit_rate = p_cdc->requested_line.coding.bit_rate; // update baudrate + TU_ASSERT(driver->set_data_format(p_cdc, cdch_set_line_coding_stage2_data_format_complete, xfer->user_data),); + } else { + xfer->complete_cb = p_cdc->user_complete_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } + } +} + +static void cdch_set_line_coding_stage2_data_format_complete(tuh_xfer_t *xfer) { + cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); + TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); + TU_LOG_DRV(" stage2 set data format result = %u\r\n", xfer->result); + + if (xfer->result == XFER_RESULT_SUCCESS) { + p_cdc->line.coding = p_cdc->requested_line.coding; // update data format + } + + xfer->complete_cb = p_cdc->user_complete_cb; + if (xfer->complete_cb) { + xfer->complete_cb(xfer); + } +} + //--------------------------------------------------------------------+ // ACM //--------------------------------------------------------------------+ @@ -1000,16 +1021,10 @@ static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ } static bool acm_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line.coding.bit_rate = p_cdc->line.coding.bit_rate; - return acm_set_line_coding(p_cdc, complete_cb, user_data); } static bool acm_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line.coding.stop_bits = p_cdc->line.coding.stop_bits; - p_cdc->requested_line.coding.parity = p_cdc->line.coding.parity; - p_cdc->requested_line.coding.data_bits = p_cdc->line.coding.data_bits; - return acm_set_line_coding(p_cdc, complete_cb, user_data); } @@ -1108,7 +1123,6 @@ static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { static bool ftdi_determine_type(cdch_interface_t *p_cdc); static uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc); -static uint8_t ftdi_get_idx(tuh_xfer_t *xfer); //------------- Control Request -------------// @@ -1150,29 +1164,6 @@ static inline bool ftdi_sio_reset(cdch_interface_t *p_cdc, tuh_xfer_cb_t complet p_cdc->ftdi.channel, complete_cb, user_data); } -static bool ftdi_change_speed(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint32_t index_value = ftdi_get_divisor(p_cdc); - TU_VERIFY(index_value); - uint16_t value = (uint16_t) index_value; - uint16_t index = (uint16_t) (index_value >> 16); - if (p_cdc->ftdi.channel) { - index = (uint16_t) ((index << 8) | p_cdc->ftdi.channel); - } - - return ftdi_set_request(p_cdc, FTDI_SIO_SET_BAUDRATE_REQUEST, FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE, - value, index, complete_cb, user_data); -} - -static bool ftdi_set_data_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 7 && p_cdc->requested_line.coding.data_bits <= 8, 0); - uint16_t value = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 - (p_cdc->requested_line.coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding - (p_cdc->requested_line.coding.stop_bits & 0x3UL) << 11); // stop bits quantity is stored in bits 11-12, same coding - // not each FTDI supports 1.5 stop bits - - return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, - value, p_cdc->ftdi.channel, complete_cb, user_data); -} //------------- Driver API -------------// @@ -1199,41 +1190,31 @@ static void ftdi_internal_control_complete(cdch_interface_t* p_cdc, tuh_xfer_t * } static bool ftdi_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ftdi_set_data_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 7 && p_cdc->requested_line.coding.data_bits <= 8, 0); + uint16_t value = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) | // data bit quantity is stored in bits 0-3 + (p_cdc->requested_line.coding.parity & 0x7UL) << 8 | // parity is stored in bits 8-10, same coding + (p_cdc->requested_line.coding.stop_bits & 0x3UL) << 11); // stop bits quantity is stored in bits 11-12, same coding + // not each FTDI supports 1.5 stop bits + return ftdi_set_request(p_cdc, FTDI_SIO_SET_DATA_REQUEST, FTDI_SIO_SET_DATA_REQUEST_TYPE, + value, p_cdc->ftdi.channel, complete_cb, user_data); } static bool ftdi_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ftdi_change_speed(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - -static void ftdi_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { - uint8_t const idx = ftdi_get_idx(xfer); - cdch_interface_t *p_cdc = get_itf(idx); - TU_ASSERT(p_cdc, ); - uint8_t const itf_num = p_cdc->bInterfaceNumber; - set_line_coding_stage1_complete(xfer, itf_num, - ftdi_set_data_request, // control request function to set data format - cdch_internal_control_complete); // control complete function to be called after request -} + uint32_t index_value = ftdi_get_divisor(p_cdc); + TU_VERIFY(index_value); + uint16_t value = (uint16_t) index_value; + uint16_t index = (uint16_t) (index_value >> 16); + if (p_cdc->ftdi.channel) { + index = (uint16_t) ((index << 8) | p_cdc->ftdi.channel); + } -// 2 stages: set baudrate (stage1) + set data format (stage2) -static bool ftdi_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return set_line_coding_sequence(p_cdc, - ftdi_change_speed, // control request function to set baudrate - ftdi_set_data_request, // control request function to set data format - ftdi_set_line_coding_stage1_complete, // function to be called after stage 1 completed - cdch_internal_control_complete, // control complete function to be called after request - complete_cb, user_data); + return ftdi_set_request(p_cdc, FTDI_SIO_SET_BAUDRATE_REQUEST, FTDI_SIO_SET_BAUDRATE_REQUEST_TYPE, + value, index, complete_cb, user_data); } static bool ftdi_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { uint16_t line_state = (uint16_t) ((p_cdc->requested_line.control_state.dtr ? FTDI_SIO_SET_DTR_HIGH : FTDI_SIO_SET_DTR_LOW) | (p_cdc->requested_line.control_state.rts ? FTDI_SIO_SET_RTS_HIGH : FTDI_SIO_SET_RTS_LOW)); - p_cdc->user_complete_cb = complete_cb; return ftdi_set_request(p_cdc, FTDI_SIO_SET_MODEM_CTRL_REQUEST, FTDI_SIO_SET_MODEM_CTRL_REQUEST_TYPE, line_state, p_cdc->ftdi.channel, complete_cb ? cdch_internal_control_complete : NULL, user_data); } @@ -1243,10 +1224,7 @@ enum { CONFIG_FTDI_DETERMINE_TYPE = 0, CONFIG_FTDI_WRITE_LATENCY, CONFIG_FTDI_SIO_RESET, - CONFIG_FTDI_SET_DATA, - CONFIG_FTDI_SET_BAUDRATE, CONFIG_FTDI_FLOW_CONTROL, - CONFIG_FTDI_MODEM_CTRL, CONFIG_FTDI_COMPLETE }; @@ -1305,48 +1283,20 @@ static bool ftdi_proccess_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) // from here sequence overtaken from Linux Kernel function ftdi_open() case CONFIG_FTDI_SIO_RESET: - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, CONFIG_FTDI_SET_DATA)); - break; - - // from here sequence overtaken from Linux Kernel function ftdi_set_termios() - case CONFIG_FTDI_SET_DATA: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_set_data_request(p_cdc, cdch_internal_control_complete, CONFIG_FTDI_SET_BAUDRATE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_FTDI_SET_BAUDRATE: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ftdi_change_speed(p_cdc, cdch_internal_control_complete, CONFIG_FTDI_FLOW_CONTROL)); + TU_ASSERT(ftdi_sio_reset(p_cdc, cdch_process_set_config, CONFIG_FTDI_FLOW_CONTROL)); break; - #else - TU_ATTR_FALLTHROUGH; - #endif case CONFIG_FTDI_FLOW_CONTROL: // disable flow control TU_ASSERT(ftdi_set_request(p_cdc, FTDI_SIO_SET_FLOW_CTRL_REQUEST, FTDI_SIO_SET_FLOW_CTRL_REQUEST_TYPE, FTDI_SIO_DISABLE_FLOW_CTRL, - p_cdc->ftdi.channel, cdch_process_set_config, CONFIG_FTDI_MODEM_CTRL)); + p_cdc->ftdi.channel, cdch_process_set_config, CONFIG_FTDI_COMPLETE)); break; - case CONFIG_FTDI_MODEM_CTRL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(ftdi_set_modem_ctrl(p_cdc, cdch_process_set_config, CONFIG_FTDI_COMPLETE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_FTDI_COMPLETE: - set_config_complete(p_cdc, 0, true); + case CONFIG_FTDI_COMPLETE: { + xfer->user_data = 0; // kick-off set line state on enum + cdch_process_line_state_on_enum(xfer); break; + } default: return false; @@ -1562,20 +1512,6 @@ static inline uint32_t ftdi_get_divisor(cdch_interface_t *p_cdc) { return div_value; } -static uint8_t ftdi_get_idx(tuh_xfer_t *xfer) { - uint8_t const channel = (uint8_t) tu_le16toh(xfer->setup->wIndex);// channel index, or 0 for legacy types - for (uint8_t i = 0; i < CFG_TUH_CDC; i++) { - const cdch_interface_t *p_cdc = &cdch_data[i]; - if (p_cdc->daddr == xfer->daddr && - (!p_cdc->ftdi.channel || // 0 for legacy types (only interface 0) - channel == p_cdc->ftdi.channel)) {// or multi-channel types (interfaces 0..n) - return i; - } - } - - return TUSB_INDEX_INVALID_8; -} - #endif //--------------------------------------------------------------------+ @@ -1619,32 +1555,14 @@ static bool cp210x_set_request(cdch_interface_t * p_cdc, uint8_t command, uint16 return tuh_control_xfer(&xfer); } -static inline bool cp210x_ifc_enable(cdch_interface_t *p_cdc, uint16_t enabled, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool cp210x_ifc_enable(cdch_interface_t *p_cdc, uint16_t enabled, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return cp210x_set_request(p_cdc, CP210X_IFC_ENABLE, enabled, NULL, 0, complete_cb, user_data); } -static bool cp210x_set_baudrate_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // Not every baud rate is supported. See datasheets and AN205 "CP210x Baud Rate Support" - uint32_t baud_le = tu_htole32(p_cdc->requested_line.coding.bit_rate); - - return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); -} - -static bool cp210x_set_line_ctl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 5 && p_cdc->requested_line.coding.data_bits <= 8, 0); - uint16_t lcr = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 - (p_cdc->requested_line.coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding - (p_cdc->requested_line.coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding - - return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); -} - -static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool cp210x_set_mhs(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // CP210x has the same bit coding return cp210x_set_request(p_cdc, CP210X_SET_MHS, - (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | - p_cdc->requested_line.control_state.value), + (uint16_t) (CP210X_CONTROL_WRITE_DTR | CP210X_CONTROL_WRITE_RTS | p_cdc->requested_line.control_state.value), NULL, 0, complete_cb, user_data); } @@ -1673,47 +1591,28 @@ static void cp210x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t } static bool cp210x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_baudrate_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + // Not every baud rate is supported. See datasheets and AN205 "CP210x Baud Rate Support" + uint32_t baud_le = tu_htole32(p_cdc->requested_line.coding.bit_rate); + return cp210x_set_request(p_cdc, CP210X_SET_BAUDRATE, 0, (uint8_t *) &baud_le, 4, complete_cb, user_data); } static bool cp210x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_line_ctl(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - -static void cp210x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { - uint8_t const itf_num = (uint8_t) tu_le16toh(xfer->setup->wIndex); - set_line_coding_stage1_complete(xfer, itf_num, - cp210x_set_line_ctl, // control request function to set data format - cdch_internal_control_complete); // control complete function to be called after request -} + TU_VERIFY(p_cdc->requested_line.coding.data_bits >= 5 && p_cdc->requested_line.coding.data_bits <= 8, 0); + uint16_t lcr = (uint16_t) ((p_cdc->requested_line.coding.data_bits & 0xfUL) << 8 | // data bit quantity is stored in bits 8-11 + (p_cdc->requested_line.coding.parity & 0xfUL) << 4 | // parity is stored in bits 4-7, same coding + (p_cdc->requested_line.coding.stop_bits & 0xfUL)); // parity is stored in bits 0-3, same coding -// 2 stages: set baudrate (stage1) + set data format (stage2) -static bool cp210x_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return set_line_coding_sequence(p_cdc, - cp210x_set_baudrate_request, // control request function to set baudrate - cp210x_set_line_ctl, // control request function to set data format - cp210x_set_line_coding_stage1_complete, // function to be called after stage 1 completed - cdch_internal_control_complete, // control complete function to be called after request - complete_cb, user_data); + return cp210x_set_request(p_cdc, CP210X_SET_LINE_CTL, lcr, NULL, 0, complete_cb, user_data); } static bool cp210x_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(cp210x_set_mhs(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + return cp210x_set_mhs(p_cdc, complete_cb, user_data); } //------------- Enumeration -------------// enum { CONFIG_CP210X_IFC_ENABLE = 0, - CONFIG_CP210X_SET_BAUDRATE_REQUEST, - CONFIG_CP210X_SET_LINE_CTL, - CONFIG_CP210X_SET_DTR_RTS, CONFIG_CP210X_COMPLETE }; @@ -1740,40 +1639,12 @@ static bool cp210x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) switch (state) { case CONFIG_CP210X_IFC_ENABLE: - TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, CONFIG_CP210X_SET_BAUDRATE_REQUEST)); + TU_ASSERT(cp210x_ifc_enable(p_cdc, CP210X_UART_ENABLE, cdch_process_set_config, CONFIG_CP210X_COMPLETE)); break; - case CONFIG_CP210X_SET_BAUDRATE_REQUEST: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_baudrate_request(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_SET_LINE_CTL)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_CP210X_SET_LINE_CTL: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_line_ctl(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_SET_DTR_RTS)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_CP210X_SET_DTR_RTS: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(cp210x_set_mhs(p_cdc, cdch_internal_control_complete, CONFIG_CP210X_COMPLETE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - case CONFIG_CP210X_COMPLETE: - set_config_complete(p_cdc, 0, true); + xfer->user_data = 0;// kick-off set line state on enum + cdch_process_line_state_on_enum(xfer); break; default: @@ -1833,19 +1704,19 @@ static bool ch34x_set_request(cdch_interface_t *p_cdc, uint8_t direction, uint8_ return tuh_control_xfer(&xfer); } -static inline bool ch34x_control_out(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool ch34x_control_out(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_OUT, request, value, index, NULL, 0, complete_cb, user_data); } -static inline bool ch34x_control_in(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, - uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool ch34x_control_in(cdch_interface_t *p_cdc, uint8_t request, uint16_t value, uint16_t index, + uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_set_request(p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data); } -static inline bool ch34x_write_reg(cdch_interface_t *p_cdc, uint16_t reg, uint16_t reg_value, - tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +TU_ATTR_ALWAYS_INLINE static inline bool ch34x_write_reg(cdch_interface_t *p_cdc, uint16_t reg, uint16_t reg_value, + tuh_xfer_cb_t complete_cb, uintptr_t user_data) { return ch34x_control_out(p_cdc, CH34X_REQ_WRITE_REG, reg, reg_value, complete_cb, user_data); } @@ -1855,25 +1726,6 @@ static inline bool ch34x_write_reg(cdch_interface_t *p_cdc, uint16_t reg, uint16 // return ch34x_control_in ( p_cdc, CH34X_REQ_READ_REG, reg, 0, buffer, buffersize, complete_cb, user_data ); //} -static bool ch34x_write_reg_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint8_t const lcr = ch34x_get_lcr(p_cdc); - TU_VERIFY(lcr); - return ch34x_write_reg(p_cdc, CH32X_REG16_LCR2_LCR, lcr, complete_cb, user_data); -} - -static bool ch34x_write_reg_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - uint16_t const div_ps = ch34x_get_divisor_prescaler(p_cdc); - TU_VERIFY(div_ps); - return ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data); -} - -static bool ch34x_modem_ctrl_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // CH34x signals are inverted - uint8_t control = ~((p_cdc->requested_line.control_state.rts ? CH34X_BIT_RTS : 0) | - (p_cdc->requested_line.control_state.dtr ? CH34X_BIT_DTR : 0)); - return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); -} - //------------- Driver API -------------// // internal control complete to update state such as line state, encoding @@ -1908,39 +1760,22 @@ static void ch34x_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t } static bool ch34x_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_write_reg_data_format(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + const uint8_t lcr = ch34x_get_lcr(p_cdc); + TU_VERIFY(lcr); + return ch34x_write_reg(p_cdc, CH32X_REG16_LCR2_LCR, lcr, complete_cb, user_data); } static bool ch34x_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_write_reg_baudrate(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - -static void ch34x_set_line_coding_stage1_complete(tuh_xfer_t *xfer) { - // CH34x has only interface 0, because wIndex is used as payload and not for bInterfaceNumber - uint8_t const itf_num = 0; - set_line_coding_stage1_complete(xfer, itf_num, - ch34x_write_reg_data_format, // control request function to set data format - cdch_internal_control_complete); // control complete function to be called after request -} - -// 2 stages: set baudrate (stage1) + set data format (stage2) -static bool ch34x_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return set_line_coding_sequence(p_cdc, - ch34x_write_reg_baudrate, // control request function to set baudrate - ch34x_write_reg_data_format, // control request function to set data format - ch34x_set_line_coding_stage1_complete, // function to be called after stage 1 completed - cdch_internal_control_complete, // control complete function to be called after request - complete_cb, user_data); + const uint16_t div_ps = ch34x_get_divisor_prescaler(p_cdc); + TU_VERIFY(div_ps); + return ch34x_write_reg(p_cdc, CH34X_REG16_DIVISOR_PRESCALER, div_ps, complete_cb, user_data); } static bool ch34x_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + // CH34x signals are inverted + uint8_t control = ~((p_cdc->requested_line.control_state.rts ? CH34X_BIT_RTS : 0) | + (p_cdc->requested_line.control_state.dtr ? CH34X_BIT_DTR : 0)); + return ch34x_control_out(p_cdc, CH34X_REQ_MODEM_CTRL, control, 0, complete_cb, user_data); } //------------- Enumeration -------------// @@ -1950,7 +1785,6 @@ enum { CONFIG_CH34X_SERIAL_INIT, CONFIG_CH34X_SPECIAL_REG_WRITE, CONFIG_CH34X_FLOW_CONTROL, - CONFIG_CH34X_MODEM_CONTROL, CONFIG_CH34X_COMPLETE }; @@ -2018,25 +1852,16 @@ static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_CH34X_FLOW_CONTROL: // no hardware flow control TU_ASSERT(ch34x_write_reg(p_cdc, TU_U16(CH341_REG_0x27, CH341_REG_0x27), 0x0000, - cdch_process_set_config, CONFIG_CH34X_MODEM_CONTROL)); + cdch_process_set_config, CONFIG_CH34X_COMPLETE)); break; - case CONFIG_CH34X_MODEM_CONTROL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - p_cdc->user_complete_cb = cdch_process_set_config; - TU_ASSERT(ch34x_modem_ctrl_request(p_cdc, cdch_internal_control_complete, CONFIG_CH34X_COMPLETE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - case CONFIG_CH34X_COMPLETE: - set_config_complete(p_cdc, 0, true); + xfer->user_data = 0; // kick-off set line state on enum + cdch_process_line_state_on_enum(xfer); break; default: - break; + return false; } return true; diff --git a/src/class/cdc/serial/ch34x.h b/src/class/cdc/serial/ch34x.h index 7d91f01fe..0e08b0acd 100644 --- a/src/class/cdc/serial/ch34x.h +++ b/src/class/cdc/serial/ch34x.h @@ -34,9 +34,9 @@ // set line_coding @ enumeration #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM + #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X CFG_TUH_CDC_LINE_CODING_ON_ENUM #else // this default is necessary to work properly -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } + #define CFG_TUH_CDC_LINE_CODING_ON_ENUM_CH34X { 9600, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } #endif // USB requests -- cgit v1.3.1 From f4d049e61ba12c8ba6fcd23c18fe5089ff899186 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Jun 2025 17:05:49 +0700 Subject: update acm and pl2303 to match the rest of drivers --- src/class/cdc/cdc_host.c | 218 +++++++++++++---------------------------------- 1 file changed, 59 insertions(+), 159 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 7926aa9fc..81337cde4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -117,8 +117,6 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, uint static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static void acm_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); -static bool acm_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool acm_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool acm_set_control_line_state(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); @@ -169,8 +167,6 @@ static bool pl2303_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, u static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); static void pl2303_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer); -static bool pl2303_set_baudrate(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); -static bool pl2303_set_data_format(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_set_line_coding(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); static bool pl2303_set_modem_ctrl(cdch_interface_t * p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data); #endif @@ -228,10 +224,9 @@ static const cdch_serial_driver_t serial_drivers[] = { .open = acm_open, .process_set_config = acm_process_set_config, .request_complete = acm_internal_control_complete, - .set_control_line_state = acm_set_control_line_state, - .set_baudrate = acm_set_baudrate, - .set_data_format = acm_set_data_format, + .set_baudrate = acm_set_line_coding, + .set_data_format = acm_set_line_coding, .set_line_coding = acm_set_line_coding, DRIVER_NAME_DECLARE("ACM") }, @@ -290,8 +285,8 @@ static const cdch_serial_driver_t serial_drivers[] = { .process_set_config = pl2303_process_set_config, .request_complete = pl2303_internal_control_complete, .set_control_line_state = pl2303_set_modem_ctrl, - .set_baudrate = pl2303_set_baudrate, - .set_data_format = pl2303_set_data_format, + .set_baudrate = pl2303_set_line_coding, + .set_data_format = pl2303_set_line_coding, .set_line_coding = pl2303_set_line_coding, DRIVER_NAME_DECLARE("PL2303") } @@ -586,10 +581,11 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, CDC_LINE_CODING_STOP_BITS_TEXT(line_coding->stop_bits)); cdch_serial_driver_t const *driver = &serial_drivers[p_cdc->serial_drid]; p_cdc->requested_line.coding = *line_coding; + p_cdc->user_complete_cb = complete_cb; if (driver->set_line_coding) { // driver support set_line_coding request - TU_VERIFY(driver->set_line_coding(p_cdc, complete_cb, user_data)); + TU_VERIFY(driver->set_line_coding(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); if (!complete_cb) { p_cdc->line.coding = *line_coding; @@ -598,7 +594,6 @@ bool tuh_cdc_set_line_coding(uint8_t idx, cdc_line_coding_t const *line_coding, // driver does not support set_line_coding and need 2 stage to set baudrate and data format separately if (complete_cb) { // non-blocking - p_cdc->user_complete_cb = complete_cb; TU_VERIFY(driver->set_baudrate(p_cdc, cdch_set_line_coding_stage1_baudrate_complete, user_data)); } else { // blocking @@ -795,7 +790,7 @@ bool cdch_set_config(uint8_t daddr, uint8_t itf_num) { return true; } -static void set_config_complete(cdch_interface_t *p_cdc, uint8_t itf_offset, bool success) { +static void set_config_complete(cdch_interface_t *p_cdc, bool success) { if (success) { const uint8_t idx = get_idx_by_ptr(p_cdc); p_cdc->mounted = true; @@ -811,6 +806,7 @@ static void set_config_complete(cdch_interface_t *p_cdc, uint8_t itf_offset, boo } // notify usbh that driver enumeration is complete + const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; usbh_driver_set_config_complete(p_cdc->daddr, p_cdc->bInterfaceNumber + itf_offset); } @@ -821,8 +817,7 @@ static void cdch_process_set_config(tuh_xfer_t *xfer) { const cdch_serial_driver_t *driver = &serial_drivers[p_cdc->serial_drid]; if (!driver->process_set_config(p_cdc, xfer)) { - const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; - set_config_complete(p_cdc, itf_offset, false); + set_config_complete(p_cdc, false); } } @@ -858,11 +853,9 @@ static bool set_line_state_on_enum(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { TU_ATTR_FALLTHROUGH; #endif - case ENUM_SET_LINE_COMPLETE: { - const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; - set_config_complete(p_cdc, itf_offset, true); + case ENUM_SET_LINE_COMPLETE: + set_config_complete(p_cdc, true); break; - } default: return false; @@ -874,11 +867,8 @@ static bool set_line_state_on_enum(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { static void cdch_process_line_state_on_enum(tuh_xfer_t *xfer) { cdch_interface_t *p_cdc = get_itf_by_xfer(xfer); TU_ASSERT(p_cdc && p_cdc->serial_drid < SERIAL_DRIVER_COUNT,); - TU_LOG_DRV(" xfer result = %u\r\n", xfer->result); - if (xfer->result != XFER_RESULT_SUCCESS || !set_line_state_on_enum(p_cdc, xfer)) { - const uint8_t itf_offset = (p_cdc->serial_drid == SERIAL_DRIVER_ACM) ? 1 : 0; - set_config_complete(p_cdc, itf_offset, false); + set_config_complete(p_cdc, false); } } @@ -967,20 +957,16 @@ static bool acm_set_control_line_state(cdch_interface_t *p_cdc, tuh_xfer_cb_t co .wLength = 0 }; - p_cdc->user_complete_cb = complete_cb; - tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, .setup = &request, .buffer = NULL, - .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, + .complete_cb = complete_cb, .user_data = user_data }; - TU_ASSERT(tuh_control_xfer(&xfer)); - - return true; + return tuh_control_xfer(&xfer); } static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { @@ -1004,35 +990,21 @@ static bool acm_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_ uint8_t *enum_buf = usbh_get_enum_buf(); memcpy(enum_buf, &p_cdc->requested_line.coding, sizeof(cdc_line_coding_t)); - p_cdc->user_complete_cb = complete_cb; - tuh_xfer_t xfer = { .daddr = p_cdc->daddr, .ep_addr = 0, .setup = &request, .buffer = enum_buf, - .complete_cb = complete_cb ? cdch_internal_control_complete : NULL, + .complete_cb = complete_cb, .user_data = user_data }; - TU_ASSERT(tuh_control_xfer(&xfer)); - - return true; -} - -static bool acm_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return acm_set_line_coding(p_cdc, complete_cb, user_data); -} - -static bool acm_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - return acm_set_line_coding(p_cdc, complete_cb, user_data); + return tuh_control_xfer(&xfer); } //------------- Enumeration -------------// enum { - CONFIG_ACM_SET_CONTROL_LINE_STATE = 0, - CONFIG_ACM_SET_LINE_CODING, - CONFIG_ACM_COMPLETE + CONFIG_ACM_COMPLETE = 0 }; static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len) { @@ -1084,30 +1056,11 @@ static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); const uintptr_t state = xfer->user_data; switch (state) { - case CONFIG_ACM_SET_CONTROL_LINE_STATE: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - if (p_cdc->acm.capability.support_line_request) { - p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(acm_set_control_line_state(p_cdc, cdch_process_set_config, CONFIG_ACM_SET_LINE_CODING)); - break; - } - #endif - TU_ATTR_FALLTHROUGH; - - case CONFIG_ACM_SET_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - if (p_cdc->acm.capability.support_line_request) { - p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(acm_set_line_coding(p_cdc, cdch_process_set_config, CONFIG_ACM_COMPLETE)); - break; - } - #endif - TU_ATTR_FALLTHROUGH; - - case CONFIG_ACM_COMPLETE: - // itf_num+1 to account for data interface as well - set_config_complete(p_cdc, 1, true); + case CONFIG_ACM_COMPLETE: { + xfer->user_data = 0; // kick-off set line state on enum + cdch_process_line_state_on_enum(xfer); break; + } default: return false; // invalid state @@ -2023,18 +1976,40 @@ static inline bool pl2303_supports_hx_status(cdch_interface_t *p_cdc, tuh_xfer_c &buf, 1, complete_cb, user_data); } -static inline bool pl2303_set_control_lines(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - // PL2303 has the same bit coding - return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, - p_cdc->requested_line.control_state.value, 0, NULL, 0, complete_cb, user_data); -} - -//static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) -//{ +//static bool pl2303_get_line_request(cdch_interface_t * p_cdc, uint8_t buf[PL2303_LINE_CODING_BUFSIZE]) { // return pl2303_set_request(p_cdc, PL2303_GET_LINE_REQUEST, PL2303_GET_LINE_REQUEST_TYPE, 0, 0, buf, PL2303_LINE_CODING_BUFSIZE); //} -static bool pl2303_set_line_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { +//static bool pl2303_set_break(cdch_interface_t * p_cdc, bool enable) { +// uint16_t state = enable ? PL2303_BREAK_ON : PL2303_BREAK_OFF; +// return pl2303_set_request(p_cdc, PL2303_BREAK_REQUEST, PL2303_BREAK_REQUEST_TYPE, state, 0, NULL, 0); +//} + +static inline int pl2303_clear_halt(cdch_interface_t *p_cdc, uint8_t endp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { + /* we don't care if it wasn't halted first. in fact some devices + * (like some ibmcam model 1 units) seem to expect hosts to make + * this request for iso endpoints, which can't halt! + */ + return pl2303_set_request(p_cdc, TUSB_REQ_CLEAR_FEATURE, PL2303_CLEAR_HALT_REQUEST_TYPE, TUSB_REQ_FEATURE_EDPT_HALT, endp, + NULL, 0, complete_cb, user_data); +} + +//------------- Driver API -------------// + +// internal control complete to update state such as line state, encoding +static void pl2303_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { + TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); + if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { + p_cdc->line.coding = p_cdc->requested_line.coding; + } + if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && + xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { + p_cdc->line.control_state = p_cdc->requested_line.control_state; + } +} + +static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // the caller has to precheck, that the new line coding different than the current, else false returned uint8_t buf[PL2303_LINE_CODING_BUFSIZE]; /* @@ -2070,63 +2045,10 @@ static bool pl2303_set_line_request(cdch_interface_t *p_cdc, tuh_xfer_cb_t compl buf, PL2303_LINE_CODING_BUFSIZE, complete_cb, user_data); } -//static bool pl2303_set_break(cdch_interface_t * p_cdc, bool enable) -//{ -// uint16_t state = enable ? PL2303_BREAK_ON : PL2303_BREAK_OFF; -// return pl2303_set_request(p_cdc, PL2303_BREAK_REQUEST, PL2303_BREAK_REQUEST_TYPE, state, 0, NULL, 0); -//} - -static inline int pl2303_clear_halt(cdch_interface_t *p_cdc, uint8_t endp, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - /* we don't care if it wasn't halted first. in fact some devices - * (like some ibmcam model 1 units) seem to expect hosts to make - * this request for iso endpoints, which can't halt! - */ - return pl2303_set_request(p_cdc, TUSB_REQ_CLEAR_FEATURE, PL2303_CLEAR_HALT_REQUEST_TYPE, TUSB_REQ_FEATURE_EDPT_HALT, endp, - NULL, 0, complete_cb, user_data); -} - -//------------- Driver API -------------// - -// internal control complete to update state such as line state, encoding -static void pl2303_internal_control_complete(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { - TU_VERIFY(xfer->result == XFER_RESULT_SUCCESS,); - if (xfer->setup->bRequest == PL2303_SET_LINE_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_LINE_REQUEST_TYPE) { - p_cdc->line.coding = p_cdc->requested_line.coding; - } - if (xfer->setup->bRequest == PL2303_SET_CONTROL_REQUEST && - xfer->setup->bmRequestType == PL2303_SET_CONTROL_REQUEST_TYPE) { - p_cdc->line.control_state = p_cdc->requested_line.control_state; - } -} - -static bool pl2303_set_line_coding(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - -static bool pl2303_set_data_format(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line.coding.bit_rate = p_cdc->line.coding.bit_rate; - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - -static bool pl2303_set_baudrate(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { - p_cdc->requested_line.coding.stop_bits = p_cdc->line.coding.stop_bits; - p_cdc->requested_line.coding.parity = p_cdc->line.coding.parity; - p_cdc->requested_line.coding.data_bits = p_cdc->line.coding.data_bits; - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_line_request(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; -} - static bool pl2303_set_modem_ctrl(cdch_interface_t *p_cdc, tuh_xfer_cb_t complete_cb, uintptr_t user_data) { // PL2303 has the same bit coding - p_cdc->user_complete_cb = complete_cb; - TU_ASSERT(pl2303_set_control_lines(p_cdc, complete_cb ? cdch_internal_control_complete : NULL, user_data)); - return true; + return pl2303_set_request(p_cdc, PL2303_SET_CONTROL_REQUEST, PL2303_SET_CONTROL_REQUEST_TYPE, + p_cdc->requested_line.control_state.value, 0, NULL, 0, complete_cb, user_data); } //------------- Enumeration -------------// @@ -2146,8 +2068,6 @@ enum { CONFIG_PL2303_WRITE5, CONFIG_PL2303_RESET_ENDP1, CONFIG_PL2303_RESET_ENDP2, - CONFIG_PL2303_LINE_CODING, - CONFIG_PL2303_MODEM_CONTROL, // CONFIG_PL2303_FLOW_CTRL_READ, // CONFIG_PL2303_FLOW_CTRL_WRITE, CONFIG_PL2303_COMPLETE @@ -2190,7 +2110,6 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) switch (state) { // from here sequence overtaken from Linux Kernel function pl2303_startup() case CONFIG_PL2303_DETECT_TYPE: - p_cdc->user_complete_cb = cdch_process_set_config;// set once for whole process config // get type and quirks (step 1) type = pl2303_detect_type(p_cdc, 1); TU_ASSERT(type != PL2303_TYPE_UNKNOWN); @@ -2313,7 +2232,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { TU_ASSERT(pl2303_vendor_write(p_cdc, PL2303_HXN_RESET_REG,// skip CONFIG_PL2303_RESET_ENDP2, no 2nd step PL2303_HXN_RESET_UPSTREAM_PIPE | PL2303_HXN_RESET_DOWNSTREAM_PIPE, - cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); + cdch_process_set_config, CONFIG_PL2303_COMPLETE)); } else { pl2303_vendor_write(p_cdc, 8, 0, cdch_process_set_config, CONFIG_PL2303_RESET_ENDP2); } @@ -2323,37 +2242,17 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_RESET_ENDP2: // step 2 if (p_cdc->pl2303.quirks & PL2303_QUIRK_LEGACY) { - TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); + TU_ASSERT(pl2303_clear_halt(p_cdc, PL2303_IN_EP, cdch_process_set_config, CONFIG_PL2303_COMPLETE)); } else { /* reset upstream data pipes */ if (p_cdc->pl2303.type == PL2303_TYPE_HXN) { // here nothing to do, only structure of previous step overtaken for better reading and comparison } else { - TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, cdch_process_set_config, CONFIG_PL2303_LINE_CODING)); + TU_ASSERT(pl2303_vendor_write(p_cdc, 9, 0, cdch_process_set_config, CONFIG_PL2303_COMPLETE)); } } break; - // from here sequence overtaken from Linux Kernel function pl2303_set_termios() - // unnecessary pl2303_get_line_request() is skipped due to a stall - case CONFIG_PL2303_LINE_CODING: - #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM - p_cdc->requested_line.coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; - TU_ASSERT(pl2303_set_line_request(p_cdc, cdch_internal_control_complete, CONFIG_PL2303_MODEM_CONTROL)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - - case CONFIG_PL2303_MODEM_CONTROL: - #ifdef CFG_TUH_CDC_LINE_CONTROL_ON_ENUM - p_cdc->requested_line.control_state.value = CFG_TUH_CDC_LINE_CONTROL_ON_ENUM; - TU_ASSERT(pl2303_set_control_lines(p_cdc, cdch_internal_control_complete, CONFIG_PL2303_COMPLETE)); - break; - #else - TU_ATTR_FALLTHROUGH; - #endif - // skipped, because it's not working with each PL230x. flow control can be also set by PL2303 EEPROM Writer Program // case CONFIG_PL2303_FLOW_CTRL_READ: // // read flow control register for modify & write back in next step @@ -2383,7 +2282,8 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) // break; case CONFIG_PL2303_COMPLETE: - set_config_complete(p_cdc, 0, true); + xfer->user_data = 0; // kick-off set line state on enum + cdch_process_line_state_on_enum(xfer); break; default: -- cgit v1.3.1 From 0194b8434f318b2bd7357ba954291d03d3b26286 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Jun 2025 17:25:20 +0700 Subject: use enum buf for process_set_config for ch34x and pl2303 --- src/class/cdc/cdc_host.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 81337cde4..ebbd9c18c 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -1054,7 +1054,9 @@ static bool acm_open(uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint1 static bool acm_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); + (void) p_cdc; const uintptr_t state = xfer->user_data; + switch (state) { case CONFIG_ACM_COMPLETE: { xfer->user_data = 0; // kick-off set line state on enum @@ -1767,15 +1769,16 @@ static bool ch34x_open(uint8_t daddr, tusb_desc_interface_t const * itf_desc, ui } static bool ch34x_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { - uint8_t buffer[2];// TODO remove TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS); const uintptr_t state = xfer->user_data; switch (state) { - case CONFIG_CH34X_READ_VERSION: - TU_ASSERT(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, + case CONFIG_CH34X_READ_VERSION: { + uint8_t* enum_buf = usbh_get_enum_buf(); + TU_ASSERT(ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, enum_buf, 2, cdch_process_set_config, CONFIG_CH34X_SERIAL_INIT)); break; + } case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, set CH34x line coding (incl. baudrate) @@ -2104,7 +2107,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) // state CONFIG_PL2303_READ1 may have no success due to expected stall by pl2303_supports_hx_status() const uintptr_t state = xfer->user_data; TU_ASSERT(xfer->result == XFER_RESULT_SUCCESS || state == CONFIG_PL2303_READ1); - uint8_t buf = 0; + uint8_t* enum_buf = usbh_get_enum_buf(); pl2303_type_t type; switch (state) { @@ -2136,7 +2139,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE1)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, enum_buf, cdch_process_set_config, CONFIG_PL2303_WRITE1)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2152,7 +2155,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_READ2: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ3)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, enum_buf, cdch_process_set_config, CONFIG_PL2303_READ3)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2160,7 +2163,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_READ3: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_READ4)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, enum_buf, cdch_process_set_config, CONFIG_PL2303_READ4)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2168,7 +2171,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_READ4: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE2)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, enum_buf, cdch_process_set_config, CONFIG_PL2303_WRITE2)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2184,7 +2187,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_READ5: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, &buf, cdch_process_set_config, CONFIG_PL2303_READ6)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8484, enum_buf, cdch_process_set_config, CONFIG_PL2303_READ6)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; @@ -2192,7 +2195,7 @@ static bool pl2303_process_set_config(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) case CONFIG_PL2303_READ6: // purpose unknown, overtaken from Linux Kernel driver if (p_cdc->pl2303.type != PL2303_TYPE_HXN) { - TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, &buf, cdch_process_set_config, CONFIG_PL2303_WRITE3)); + TU_ASSERT(pl2303_vendor_read(p_cdc, 0x8383, enum_buf, cdch_process_set_config, CONFIG_PL2303_WRITE3)); break; }// else: continue with next step TU_ATTR_FALLTHROUGH; -- cgit v1.3.1 From d86362414e9c467d93f37672228e220a718de81d Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Jun 2025 17:57:26 +0700 Subject: clean up --- examples/host/cdc_msc_hid/src/tusb_config.h | 3 +- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 1 + src/class/cdc/cdc_host.c | 34 +++++++++++----------- 3 files changed, 20 insertions(+), 18 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index e610c5672..2f8cb5e03 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -103,7 +103,7 @@ #define CFG_TUH_ENUMERATION_BUFSIZE 256 #define CFG_TUH_HUB 1 // number of supported hubs -#define CFG_TUH_CDC 4 // number of supported CDC devices. also activates CDC ACM +#define CFG_TUH_CDC 2 // number of supported CDC devices. also activates CDC ACM #define CFG_TUH_CDC_FTDI 1 // FTDI Serial. FTDI is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CP210X 1 // CP210x Serial. CP210X is not part of CDC class, only to re-use CDC driver API #define CFG_TUH_CDC_CH34X 1 // CH340 or CH341 Serial. CH34X is not part of CDC class, only to re-use CDC driver API @@ -122,6 +122,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: +// DTR ( bit 0), RTS (bit 1) #define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM (CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 05deecba0..bc8887211 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -127,6 +127,7 @@ //------------- CDC -------------// // Set Line Control state on enumeration/mounted: +// DTR ( bit 0), RTS (bit 1) #define CFG_TUH_CDC_LINE_CONTROL_ON_ENUM (CDC_CONTROL_LINE_STATE_DTR | CDC_CONTROL_LINE_STATE_RTS) // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index ebbd9c18c..f4567fac4 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -42,7 +42,7 @@ // Level where CFG_TUSB_DEBUG must be at least for this driver is logged #ifndef CFG_TUH_CDC_LOG_LEVEL - #define CFG_TUH_CDC_LOG_LEVEL 1 + #define CFG_TUH_CDC_LOG_LEVEL 2 #endif #define TU_LOG_DRV(...) TU_LOG(CFG_TUH_CDC_LOG_LEVEL, __VA_ARGS__) @@ -748,25 +748,25 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d (void) rhport; // For CDC: only support ACM subclass // Note: Protocol 0xFF can be RNDIS device - if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && + if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { return acm_open(daddr, itf_desc, max_len); - } else if (SERIAL_DRIVER_COUNT > 1 && - TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { - uint16_t vid, pid; - TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); - - for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { - const cdch_serial_driver_t *driver = &serial_drivers[dr]; - for (size_t i = 0; i < driver->vid_pid_count; i++) { - if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { - const bool ret = driver->open(daddr, itf_desc, max_len); - TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver->name, ret ? "OK" : "FAILED"); - return ret; - } - } + } else if (SERIAL_DRIVER_COUNT > 1 && + TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { + uint16_t vid, pid; + TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); + + for (size_t dr = 1; dr < SERIAL_DRIVER_COUNT; dr++) { + const cdch_serial_driver_t *driver = &serial_drivers[dr]; + for (size_t i = 0; i < driver->vid_pid_count; i++) { + if (driver->vid_pid_list[i][0] == vid && driver->vid_pid_list[i][1] == pid) { + const bool ret = driver->open(daddr, itf_desc, max_len); + TU_LOG_DRV("[:%u:%u] CDCh %s open %s\r\n", daddr, itf_desc->bInterfaceNumber, driver->name, ret ? "OK" : "FAILED"); + return ret; } - } + } + } + } return false; } -- cgit v1.3.1 From d22cbe4cb5b88c869754e91c97eff513ed8b7b33 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Jul 2025 20:13:21 +0700 Subject: refactor async io, add in_isr argument to tud_msc_async_io_done() use cbw.command[0] for pending IO command --- src/class/msc/msc_device.c | 209 +++++++++++++++++++++------------------------ src/class/msc/msc_device.h | 70 ++++++--------- 2 files changed, 122 insertions(+), 157 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index e583f6ba8..709734b87 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -52,36 +52,27 @@ enum { MSC_STAGE_NEED_RESET, }; -enum { - MSC_NEXT_OP_NONE = 0, - MSC_NEXT_OP_READ10, - MSC_NEXT_OP_WRITE10, - MSC_NEXT_OP_STATUS -}; - typedef struct { - TU_ATTR_ALIGNED(4) msc_cbw_t cbw; - TU_ATTR_ALIGNED(4) msc_csw_t csw; - + TU_ATTR_ALIGNED(4) msc_cbw_t cbw; // 31 bytes uint8_t rhport; + + TU_ATTR_ALIGNED(4) msc_csw_t csw; // 13 bytes uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; - // Bulk Only Transfer (BOT) Protocol - uint8_t stage; - uint32_t total_len; // byte to be transferred, can be smaller than total_bytes in cbw uint32_t xferred_len; // numbered of bytes transferred so far in the Data Stage - // Sense Response Data + // Bulk Only Transfer (BOT) Protocol + uint8_t stage; + + // SCSI Sense Response Data uint8_t sense_key; uint8_t add_sense_code; uint8_t add_sense_qualifier; - // Async IO - uint8_t next_op; - uint32_t xferred_bytes; + uint8_t pending_io; // pending async IO }mscd_interface_t; static mscd_interface_t _mscd_itf; @@ -95,12 +86,11 @@ CFG_TUD_MEM_SECTION static struct { //--------------------------------------------------------------------+ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_t* buffer, uint32_t bufsize); static void proc_read10_cmd(mscd_interface_t* p_msc); -static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes); +static void proc_read_io_data(mscd_interface_t* p_msc, int32_t nbytes); static void proc_write10_cmd(mscd_interface_t* p_msc); -static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_bytes); -static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes); +static void proc_write10_host_data(mscd_interface_t* p_msc, uint32_t xferred_bytes); +static void proc_write_io_data(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes); static bool proc_stage_status(mscd_interface_t* p_msc); -static void tud_msc_async_io_done_cb(void* bytes_processed); TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); @@ -195,30 +185,31 @@ static uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { return status; } -static bool proc_stage_status(mscd_interface_t* p_msc) { +static bool proc_stage_status(mscd_interface_t *p_msc) { uint8_t rhport = p_msc->rhport; - msc_cbw_t const* p_cbw = &p_msc->cbw; + msc_cbw_t const *p_cbw = &p_msc->cbw; + // skip status if epin is currently stalled, will do it when received Clear Stall request - if (!usbd_edpt_stalled(rhport, p_msc->ep_in)) { - if ((p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir)) { - // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status - // TU_LOG_DRV(" SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); - usbd_edpt_stall(rhport, p_msc->ep_in); - } else { - TU_ASSERT(send_csw(p_msc)); - } + if (!usbd_edpt_stalled(rhport, p_msc->ep_in)) { + if ((p_cbw->total_bytes > p_msc->xferred_len) && is_data_in(p_cbw->dir)) { + // 6.7 The 13 Cases: case 5 (Hi > Di): STALL before status + // TU_LOG_DRV(" SCSI case 5 (Hi > Di): %lu > %lu\r\n", p_cbw->total_bytes, p_msc->xferred_len); + usbd_edpt_stall(rhport, p_msc->ep_in); + } else { + TU_ASSERT(send_csw(p_msc)); } + } - #if TU_CHECK_MCU(OPT_MCU_CXD56) - // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. - // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and - // hope everything will work - if ( usbd_edpt_stalled(rhport, p_msc->ep_in) ) { - usbd_edpt_clear_stall(rhport, p_msc->ep_in); - send_csw(p_msc); - } - #endif - return true; + #if TU_CHECK_MCU(OPT_MCU_CXD56) + // WORKAROUND: cxd56 has its own nuttx usb stack which does not forward Set/ClearFeature(Endpoint) to DCD. + // There is no way for us to know when EP is un-stall, therefore we will unconditionally un-stall here and + // hope everything will work + if (usbd_edpt_stalled(rhport, p_msc->ep_in)) { + usbd_edpt_clear_stall(rhport, p_msc->ep_in); + send_csw(p_msc); + } + #endif + return true; } //--------------------------------------------------------------------+ @@ -258,39 +249,57 @@ bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, u return true; } -static inline void set_sense_medium_not_present(uint8_t lun) { +TU_ATTR_ALWAYS_INLINE static inline void set_sense_medium_not_present(uint8_t lun) { // default sense is NOT READY, MEDIUM NOT PRESENT tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00); } -void tud_msc_async_io_done(int32_t bytes_processed) { - // Precheck to avoid queueing multiple RW done callback - TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); - // Call usbd_edpt_xfer() in tud_task() to avoid racing condition - usbd_defer_func(tud_msc_async_io_done_cb, (void*) (intptr_t)bytes_processed, false); +static void proc_async_io_done(void *bytes_processed) { + mscd_interface_t *p_msc = &_mscd_itf; + TU_VERIFY(p_msc->pending_io, ); + const int32_t nbytes = (int32_t) (intptr_t) bytes_processed; + const uint8_t cmd = p_msc->cbw.command[0]; + + p_msc->pending_io = 0; + switch (cmd) { + case SCSI_CMD_READ_10: + proc_read_io_data(p_msc, nbytes); + break; + + case SCSI_CMD_WRITE_10: + proc_write_io_data(p_msc, (uint32_t) nbytes, nbytes); + break; + + default: break; + } + + // send status if stage is transitioned to STATUS + if (p_msc->stage == MSC_STAGE_STATUS) { + proc_stage_status(p_msc); + } } -static void tud_msc_async_io_done_cb(void* bytes_processed) { - TU_VERIFY(_mscd_itf.next_op != MSC_NEXT_OP_NONE,); - uint8_t next_op = _mscd_itf.next_op; - _mscd_itf.next_op = MSC_NEXT_OP_NONE; - int32_t nbytes = (int32_t)(intptr_t)bytes_processed; - // READ10 - if (next_op == MSC_NEXT_OP_READ10) { - proc_read10_next(&_mscd_itf, nbytes); - } else if (next_op == MSC_NEXT_OP_WRITE10) { - proc_write10_next(&_mscd_itf, _mscd_itf.xferred_bytes, nbytes); - // Need to manually invoke CSW transfer - if (_mscd_itf.stage == MSC_STAGE_STATUS) { - proc_stage_status(&_mscd_itf); - } +bool tud_msc_async_io_done(int32_t bytes_io, bool in_isr) { + // Precheck to avoid queueing multiple RW done callback + TU_VERIFY(_mscd_itf.pending_io); + if (bytes_io == 0) { + bytes_io = TUD_MSC_RET_ERROR; // 0 is treated as error, no sense to call this with BUSY here + } + + if (in_isr) { + usbd_defer_func(proc_async_io_done, (void*) (intptr_t)bytes_io, in_isr); + } else { + proc_async_io_done((void*)(intptr_t) bytes_io); } + + return true; } //--------------------------------------------------------------------+ // USBD Driver API //--------------------------------------------------------------------+ void mscd_init(void) { + TU_LOG_INT(CFG_TUD_MSC_LOG_LEVEL, sizeof(mscd_interface_t)); tu_memclr(&_mscd_itf, sizeof(mscd_interface_t)); } @@ -528,7 +537,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t proc_read10_cmd(p_msc); } } else if (SCSI_CMD_WRITE_10 == p_cbw->command[0]) { - proc_write10_new_data(p_msc, xferred_bytes); + proc_write10_host_data(p_msc, xferred_bytes); } else { p_msc->xferred_len += xferred_bytes; @@ -560,7 +569,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t break; case MSC_STAGE_STATUS_SENT: - // Wait for the Status phase to complete + // Status phase is complete if ((ep_addr == p_msc->ep_in) && (xferred_bytes == sizeof(msc_csw_t))) { TU_LOG_DRV(" SCSI Status [Lun%u] = %u\r\n", p_cbw->lun, p_csw->status); // TU_LOG_MEM(CFG_TUD_MSC_LOG_LEVEL, p_csw, xferred_bytes, 2); @@ -590,7 +599,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t TU_ASSERT(prepare_cbw(p_msc)); } else { - // Any xfer ended here is consider unknown error, ignore it + // Any xfer ended here is considered unknown error, ignore it TU_LOG1(" Warning expect SCSI Status but received unknown data\r\n"); } break; @@ -696,8 +705,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ break; case SCSI_CMD_READ_FORMAT_CAPACITY: { - scsi_read_format_capacity_data_t read_fmt_capa = - { + scsi_read_format_capacity_data_t read_fmt_capa = { .list_length = 8, .block_num = 0, .descriptor_type = 2, // formatted media @@ -729,8 +737,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ break; case SCSI_CMD_INQUIRY: { - scsi_inquiry_resp_t inquiry_rsp = - { + scsi_inquiry_resp_t inquiry_rsp = { .is_removable = 1, .version = 2, .response_data_format = 2, @@ -750,8 +757,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ break; case SCSI_CMD_MODE_SENSE_6: { - scsi_mode_sense6_resp_t mode_resp = - { + scsi_mode_sense6_resp_t mode_resp = { .data_len = 3, .medium_type = 0, .write_protected = false, @@ -772,8 +778,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ break; case SCSI_CMD_REQUEST_SENSE: { - scsi_sense_fixed_resp_t sense_rsp = - { + scsi_sense_fixed_resp_t sense_rsp = { .response_code = 0x70, // current, fixed format .valid = 1 }; @@ -805,32 +810,27 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ static void proc_read10_cmd(mscd_interface_t* p_msc) { msc_cbw_t const* p_cbw = &p_msc->cbw; - - // block size already verified not zero - uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - - // Adjust lba with transferred bytes + uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); // already verified non-zero + // Adjust lba & offset with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); + uint32_t const offset = p_msc->xferred_len % block_sz; // remaining bytes capped at class buffer int32_t nbytes = (int32_t)tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes - p_msc->xferred_len); - // Application can consume smaller bytes - uint32_t const offset = p_msc->xferred_len % block_sz; - - p_msc->next_op = MSC_NEXT_OP_READ10; + p_msc->pending_io = 1; nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, (uint32_t)nbytes); if (nbytes != TUD_MSC_RET_ASYNC) { - p_msc->next_op = MSC_NEXT_OP_NONE; - proc_read10_next(p_msc, nbytes); + p_msc->pending_io = 0; + proc_read_io_data(p_msc, nbytes); } } -static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes) { +static void proc_read_io_data(mscd_interface_t* p_msc, int32_t nbytes) { uint8_t rhport = p_msc->rhport; if (nbytes < 0) { // negative means error -> endpoint is stalled & status in CSW set to failed - TU_LOG_DRV(" tud_msc_read10_cb() return -1\r\n"); + TU_LOG_DRV(" IO read() failed\r\n"); // set sense msc_cbw_t const* p_cbw = &p_msc->cbw; @@ -838,7 +838,7 @@ static void proc_read10_next(mscd_interface_t* p_msc, int32_t nbytes) { fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else if (nbytes == 0) { - // zero means not ready -> simulate an transfer complete so that this driver callback will fired again + // zero means not ready -> fake a transfer complete so that this driver callback will fire again dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false); } else { TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_epbuf.buf, (uint16_t) nbytes),); @@ -864,55 +864,42 @@ static void proc_write10_cmd(mscd_interface_t* p_msc) { // remaining bytes capped at class buffer uint16_t nbytes = (uint16_t)tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes - p_msc->xferred_len); // Write10 callback will be called later when usb transfer complete - uint8_t rhport = p_msc->rhport; - TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_epbuf.buf, nbytes),); + TU_ASSERT(usbd_edpt_xfer(p_msc->rhport, p_msc->ep_out, _mscd_epbuf.buf, nbytes),); } // process new data arrived from WRITE10 -static void proc_write10_new_data(mscd_interface_t* p_msc, uint32_t xferred_bytes) { +static void proc_write10_host_data(mscd_interface_t* p_msc, uint32_t xferred_bytes) { msc_cbw_t const* p_cbw = &p_msc->cbw; + uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); // already verified non-zero - // block size already verified not zero - uint16_t const block_sz = rdwr10_get_blocksize(p_cbw); - - // Adjust lba with transferred bytes + // Adjust lba & offset with transferred bytes uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); - - // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; - p_msc->next_op = MSC_NEXT_OP_WRITE10; - p_msc->xferred_bytes = xferred_bytes; + p_msc->pending_io = 1; int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_epbuf.buf, xferred_bytes); if (nbytes != TUD_MSC_RET_ASYNC) { - p_msc->next_op = MSC_NEXT_OP_NONE; - proc_write10_next(p_msc, xferred_bytes, nbytes); + p_msc->pending_io = 0; + proc_write_io_data(p_msc, xferred_bytes, nbytes); } } -static void proc_write10_next(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes) { +static void proc_write_io_data(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes) { if (nbytes < 0) { // negative means error -> failed this scsi op - TU_LOG_DRV(" tud_msc_write10_cb() return -1\r\n"); - - // update actual byte before failed - p_msc->xferred_len += xferred_bytes; - - msc_cbw_t const* p_cbw = &p_msc->cbw; - set_sense_medium_not_present(p_cbw->lun); + TU_LOG_DRV(" IO write() failed\r\n"); + set_sense_medium_not_present(p_msc->cbw.lun); fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); } else { if ((uint32_t)nbytes < xferred_bytes) { // Application consume less than what we got (including zero) const uint32_t left_over = xferred_bytes - (uint32_t)nbytes; if (nbytes > 0) { - p_msc->xferred_len += (uint16_t)nbytes; memmove(_mscd_epbuf.buf, _mscd_epbuf.buf + nbytes, left_over); } - // simulate a transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter - uint8_t rhport = p_msc->rhport; - dcd_event_xfer_complete(rhport, p_msc->ep_out, left_over, XFER_RESULT_SUCCESS, false); + // fake a transfer complete with adjusted parameters --> callback will be invoked with adjusted parameters + dcd_event_xfer_complete(p_msc->rhport, p_msc->ep_out, left_over, XFER_RESULT_SUCCESS, false); } else { // Application consume all bytes in our buffer p_msc->xferred_len += xferred_bytes; diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 7162b11e4..2ad31c245 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -49,10 +49,11 @@ #endif // Return value of callback functions -// Error -#define TUD_MSC_RET_ERROR -1 -// Asynchronous IO -#define TUD_MSC_RET_ASYNC -16 +enum { + TUD_MSC_RET_BUSY = 0, // Busy, e.g disk I/O is not ready + TUD_MSC_RET_ERROR = -1, + TUD_MSC_RET_ASYNC = -2, // Asynchronous IO +}; TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); @@ -63,54 +64,31 @@ TU_VERIFY_STATIC(CFG_TUD_MSC_EP_BUFSIZE < UINT16_MAX, "Size is not correct"); // Set SCSI sense response bool tud_msc_set_sense(uint8_t lun, uint8_t sense_key, uint8_t add_sense_code, uint8_t add_sense_qualifier); -// Called once asynchronous read/write operation is done -// bytes_processed has the same meaning of tud_msc_read10_cb() / -// tud_msc_write10_cb() return value -void tud_msc_async_io_done(int32_t bytes_processed); +// Called by Application once asynchronous I/O operation is done +// bytes_io is number of bytes in I/O op, typically the bufsize in read/write_cb() or +// TUD_MSC_RET_ERROR (-1) for error. Note TUD_MSC_RET_BUSY (0) will be treated as error as well. +bool tud_msc_async_io_done(int32_t bytes_io, bool in_isr); //--------------------------------------------------------------------+ // Application Callbacks (WEAK is optional) //--------------------------------------------------------------------+ -// Invoked when received SCSI READ10 command -// - Address = lba * BLOCK_SIZE + offset -// - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. -// -// - Application fill the buffer (up to bufsize) with address contents and return number of bytes read or status. -// -// - ret < bufsize : These bytes are transferred first and callback will be invoked again for remaining data. -// -// - ret == 0 : Indicate application is not ready yet e.g disk I/O busy. -// Callback will be invoked again with the same parameters later on. -// -// - ret == TUD_MSC_RET_ERROR (-1) -// : Indicate application error e.g invalid address. This request will be STALLed -// and return failed status in command status wrapper phase. -// -// - ret == TUD_MSC_RET_ASYNC (-16) -// : Data reading will be done asynchronously in a background task. Application should return immediately. -// tud_msc_async_io_done() must be called once reading is done to signal completion. +/* + Invoked when received SCSI READ10/WRITE10 command + - Address = lba * BLOCK_SIZE + offset + - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. + - Application fill the buffer (up to bufsize) with address contents and return number of bytes read or status. + - 0 < ret < bufsize: These bytes are transferred first and callback will be invoked again for remaining data. + - ret == TUD_MSC_RET_BUSY + Application is buys e.g disk I/O not ready. + Callback will be invoked again with the same parameters later on. + - ret == TUD_MSC_RET_ERROR + error such as invalid address. This request will be STALLed and scsi command will be failed + - ret == TUD_MSC_RET_ASYNC + Data I/O will be done asynchronously in a background task. Application should return immediately. + tud_msc_async_io_done() must be called once IO/ is done to signal completion. +*/ int32_t tud_msc_read10_cb (uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize); - -// Invoked when received SCSI WRITE10 command -// - Address = lba * BLOCK_SIZE + offset -// - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. -// -// - Application writes data from buffer to address contents (up to bufsize) and returns the number of bytes written or status. -// -// - ret < bufsize : Callback will be invoked again with remaining data later on. -// -// - ret == 0 : Indicate application is not ready yet e.g disk I/O busy. -// Callback will be invoked again with the same parameters later on. -// -// - ret == TUD_MSC_RET_ERROR (-1) -// : Indicate application error e.g invalid address. This request will be STALLed -// and return failed status in command status wrapper phase. -// -// - ret == TUD_MSC_RET_ASYNC (-16) -// : Data writing will be done asynchronously in a background task. Application should return immediately. -// tud_msc_async_io_done() must be called once writing is done to signal completion. -// TODO change buffer to const uint8_t* int32_t tud_msc_write10_cb (uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize); // Invoked when received SCSI_CMD_INQUIRY -- cgit v1.3.1 From 216a35e59a095e6ccb70f7c9bd4f7bc737f44140 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Jul 2025 20:15:16 +0700 Subject: update example --- examples/device/cdc_msc_freertos/src/msc_disk.c | 117 +++++++++------------ examples/device/cdc_msc_freertos/src/tusb_config.h | 6 -- src/class/msc/msc_device.c | 6 +- 3 files changed, 55 insertions(+), 74 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index c2aaca847..d1ff2f71b 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -28,8 +28,13 @@ #if CFG_TUD_MSC -#if CFG_EXAMPLE_MSC_ASYNC_IO +// Use async IO in example or not +#define CFG_EXAMPLE_MSC_ASYNC_IO 1 + +// Simulate read/write operation delay +#define CFG_EXAMPLE_MSC_IO_DELAY_MS 0 +#if CFG_EXAMPLE_MSC_ASYNC_IO #define IO_STACK_SIZE configMINIMAL_STACK_SIZE typedef struct { @@ -66,8 +71,7 @@ static bool ejected = false; If you find any bugs or get any questions, feel free to file an\r\n\ issue at github.com/hathach/tinyusb" -enum -{ +enum { DISK_BLOCK_NUM = 16, // 8KB is the smallest size that windows allow to mount DISK_BLOCK_SIZE = 512 }; @@ -162,18 +166,20 @@ static void io_task(void *params) { io_ops_t io_ops; while (1) { if (xQueueReceive(io_queue, &io_ops, portMAX_DELAY)) { + const uint8_t* addr = msc_disk[io_ops.lba] + io_ops.offset; + int32_t nbytes = io_ops.bufsize; if (io_ops.is_read) { - uint8_t const* addr = msc_disk[io_ops.lba] + io_ops.offset; memcpy(io_ops.buffer, addr, io_ops.bufsize); } else { #ifndef CFG_EXAMPLE_MSC_READONLY - uint8_t* addr = msc_disk[io_ops.lba] + io_ops.offset; - memcpy(addr, io_ops.buffer, io_ops.bufsize); + memcpy((uint8_t*) addr, io_ops.buffer, io_ops.bufsize); +#else + nbytes = -1; // failed to write #endif } tusb_time_delay_ms_api(CFG_EXAMPLE_MSC_IO_DELAY_MS); - tud_msc_async_io_done(io_ops.bufsize); + tud_msc_async_io_done(nbytes, false); } } } @@ -184,14 +190,11 @@ void msc_disk_init() {} // Invoked when received SCSI_CMD_INQUIRY // Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) -{ +void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { (void) lun; - const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id , vid, strlen(vid)); memcpy(product_id , pid, strlen(pid)); memcpy(product_rev, rev, strlen(rev)); @@ -199,8 +202,7 @@ void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16 // Invoked when received Test Unit Ready command. // return true allowing host to read/write this LUN e.g SD card inserted -bool tud_msc_test_unit_ready_cb(uint8_t lun) -{ +bool tud_msc_test_unit_ready_cb(uint8_t lun) { (void) lun; // RAM disk is ready until ejected @@ -215,10 +217,8 @@ bool tud_msc_test_unit_ready_cb(uint8_t lun) // Invoked when received SCSI_CMD_READ_CAPACITY_10 and SCSI_CMD_READ_FORMAT_CAPACITY to determine the disk size // Application update block count and block size -void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size) -{ +void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_size) { (void) lun; - *block_count = DISK_BLOCK_NUM; *block_size = DISK_BLOCK_SIZE; } @@ -226,18 +226,14 @@ void tud_msc_capacity_cb(uint8_t lun, uint32_t* block_count, uint16_t* block_siz // Invoked when received Start Stop Unit command // - Start = 0 : stopped power mode, if load_eject = 1 : unload disk storage // - Start = 1 : active mode, if load_eject = 1 : load disk storage -bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) -{ +bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, bool load_eject) { (void) lun; (void) power_condition; - if ( load_eject ) - { - if (start) - { + if (load_eject) { + if (start) { // load disk storage - }else - { + } else { // unload disk storage ejected = true; } @@ -248,116 +244,107 @@ bool tud_msc_start_stop_cb(uint8_t lun, uint8_t power_condition, bool start, boo // Callback invoked when received READ10 command. // Copy disk's data to buffer (up to bufsize) and return number of copied bytes. -int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) -{ +int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize) { (void) lun; // out of ramdisk - if ( lba >= DISK_BLOCK_NUM ) { + if (lba >= DISK_BLOCK_NUM) { return TUD_MSC_RET_ERROR; } // Check for overflow of offset + bufsize - if ( lba * DISK_BLOCK_SIZE + offset + bufsize > DISK_BLOCK_NUM * DISK_BLOCK_SIZE ) { + if (lba * DISK_BLOCK_SIZE + offset + bufsize > DISK_BLOCK_NUM * DISK_BLOCK_SIZE) { return TUD_MSC_RET_ERROR; } -#if CFG_EXAMPLE_MSC_ASYNC_IO - io_ops_t io_ops = { .is_read = true, .lun = lun, .lba = lba, .offset = offset, .buffer = buffer, .bufsize = bufsize }; + #if CFG_EXAMPLE_MSC_ASYNC_IO + io_ops_t io_ops = {.is_read = true, .lun = lun, .lba = lba, .offset = offset, .buffer = buffer, .bufsize = bufsize}; // Send IO operation to IO task TU_ASSERT(xQueueSend(io_queue, &io_ops, 0) == pdPASS); return TUD_MSC_RET_ASYNC; -#else - uint8_t const* addr = msc_disk[lba] + offset; + #else + uint8_t const *addr = msc_disk[lba] + offset; memcpy(buffer, addr, bufsize); - tusb_time_delay_ms_api(CFG_EXAMPLE_MSC_IO_DELAY_MS); - return bufsize; -#endif + #endif } -bool tud_msc_is_writable_cb (uint8_t lun) -{ +bool tud_msc_is_writable_cb (uint8_t lun) { (void) lun; -#ifdef CFG_EXAMPLE_MSC_READONLY + #ifdef CFG_EXAMPLE_MSC_READONLY return false; -#else + #else return true; -#endif + #endif } // Callback invoked when received WRITE10 command. // Process data in buffer to disk's storage and return number of written bytes -int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) -{ +int32_t tud_msc_write10_cb(uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize) { // out of ramdisk - if ( lba >= DISK_BLOCK_NUM ) { + if (lba >= DISK_BLOCK_NUM) { return TUD_MSC_RET_ERROR; } // Check for overflow of offset + bufsize - if ( lba * DISK_BLOCK_SIZE + offset + bufsize > DISK_BLOCK_NUM * DISK_BLOCK_SIZE ) { + if (lba * DISK_BLOCK_SIZE + offset + bufsize > DISK_BLOCK_NUM * DISK_BLOCK_SIZE) { return TUD_MSC_RET_ERROR; } -#ifdef CFG_EXAMPLE_MSC_READONLY - (void) lun; (void) buffer; + #ifdef CFG_EXAMPLE_MSC_READONLY + (void) lun; + (void) buffer; return bufsize; -#endif + #endif -#if CFG_EXAMPLE_MSC_ASYNC_IO - io_ops_t io_ops = { .is_read = false, .lun = lun, .lba = lba, .offset = offset, .buffer = buffer, .bufsize = bufsize }; + #if CFG_EXAMPLE_MSC_ASYNC_IO + io_ops_t io_ops = {.is_read = false, .lun = lun, .lba = lba, .offset = offset, .buffer = buffer, .bufsize = bufsize}; // Send IO operation to IO task TU_ASSERT(xQueueSend(io_queue, &io_ops, 0) == pdPASS); return TUD_MSC_RET_ASYNC; -#else - uint8_t* addr = msc_disk[lba] + offset; + #else + uint8_t *addr = msc_disk[lba] + offset; memcpy(addr, buffer, bufsize); tusb_time_delay_ms_api(CFG_EXAMPLE_MSC_IO_DELAY_MS); return bufsize; -#endif + #endif } // Callback invoked when received an SCSI command not in built-in list below // - READ_CAPACITY10, READ_FORMAT_CAPACITY, INQUIRY, MODE_SENSE6, REQUEST_SENSE // - READ10 and WRITE10 has their own callbacks -int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) -{ +int32_t tud_msc_scsi_cb (uint8_t lun, uint8_t const scsi_cmd[16], void* buffer, uint16_t bufsize) { // read10 & write10 has their own callback and MUST not be handled here - void const* response = NULL; + void const *response = NULL; int32_t resplen = 0; // most scsi handled is input bool in_xfer = true; - switch (scsi_cmd[0]) - { + switch (scsi_cmd[0]) { default: // Set Sense = Invalid Command Operation tud_msc_set_sense(lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); // negative means error -> tinyusb could stall and/or response with failed status resplen = -1; - break; + break; } // return resplen must not larger than bufsize - if ( resplen > bufsize ) resplen = bufsize; + if (resplen > bufsize) { resplen = bufsize; } - if ( response && (resplen > 0) ) - { - if(in_xfer) - { + if (response && (resplen > 0)) { + if (in_xfer) { memcpy(buffer, response, (size_t) resplen); - }else - { + } else { // SCSI output } } diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index d70456287..c3f2f7fb5 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -114,12 +114,6 @@ // MSC Buffer size of Device Mass storage #define CFG_TUD_MSC_EP_BUFSIZE 512 -// Use async IO in example or not -#define CFG_EXAMPLE_MSC_ASYNC_IO 1 - -// Simulate read/write operation delay -#define CFG_EXAMPLE_MSC_IO_DELAY_MS 0 - #ifdef __cplusplus } #endif diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 709734b87..a8c52b6bd 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -828,8 +828,8 @@ static void proc_read10_cmd(mscd_interface_t* p_msc) { static void proc_read_io_data(mscd_interface_t* p_msc, int32_t nbytes) { uint8_t rhport = p_msc->rhport; - if (nbytes < 0) { - // negative means error -> endpoint is stalled & status in CSW set to failed + if (nbytes == TUD_MSC_RET_ERROR) { + // error -> endpoint is stalled & status in CSW set to failed TU_LOG_DRV(" IO read() failed\r\n"); // set sense @@ -837,7 +837,7 @@ static void proc_read_io_data(mscd_interface_t* p_msc, int32_t nbytes) { set_sense_medium_not_present(p_cbw->lun); fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); - } else if (nbytes == 0) { + } else if (nbytes == TUD_MSC_RET_BUSY) { // zero means not ready -> fake a transfer complete so that this driver callback will fire again dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false); } else { -- cgit v1.3.1 From c96cc4369f1b97efe85575f3e5633e38598e9fc2 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 1 Jul 2025 21:52:57 +0700 Subject: defer proc_async_io_done() --- src/class/msc/msc_device.c | 64 +++++++++++++++++++++++++--------------------- src/class/msc/msc_device.h | 9 +++---- 2 files changed, 39 insertions(+), 34 deletions(-) (limited to 'src') diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index a8c52b6bd..747ad03ed 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -254,10 +254,10 @@ TU_ATTR_ALWAYS_INLINE static inline void set_sense_medium_not_present(uint8_t lu tud_msc_set_sense(lun, SCSI_SENSE_NOT_READY, 0x3A, 0x00); } -static void proc_async_io_done(void *bytes_processed) { +static void proc_async_io_done(void *bytes_io) { mscd_interface_t *p_msc = &_mscd_itf; TU_VERIFY(p_msc->pending_io, ); - const int32_t nbytes = (int32_t) (intptr_t) bytes_processed; + const int32_t nbytes = (int32_t) (intptr_t) bytes_io; const uint8_t cmd = p_msc->cbw.command[0]; p_msc->pending_io = 0; @@ -283,15 +283,9 @@ bool tud_msc_async_io_done(int32_t bytes_io, bool in_isr) { // Precheck to avoid queueing multiple RW done callback TU_VERIFY(_mscd_itf.pending_io); if (bytes_io == 0) { - bytes_io = TUD_MSC_RET_ERROR; // 0 is treated as error, no sense to call this with BUSY here + bytes_io = TUD_MSC_RET_ERROR; // 0 is treated as error, no reason to call this with BUSY here } - - if (in_isr) { - usbd_defer_func(proc_async_io_done, (void*) (intptr_t)bytes_io, in_isr); - } else { - proc_async_io_done((void*)(intptr_t) bytes_io); - } - + usbd_defer_func(proc_async_io_done, (void *) (intptr_t) bytes_io, in_isr); return true; } @@ -827,21 +821,26 @@ static void proc_read10_cmd(mscd_interface_t* p_msc) { } static void proc_read_io_data(mscd_interface_t* p_msc, int32_t nbytes) { - uint8_t rhport = p_msc->rhport; - if (nbytes == TUD_MSC_RET_ERROR) { - // error -> endpoint is stalled & status in CSW set to failed - TU_LOG_DRV(" IO read() failed\r\n"); - - // set sense - msc_cbw_t const* p_cbw = &p_msc->cbw; - set_sense_medium_not_present(p_cbw->lun); - - fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); - } else if (nbytes == TUD_MSC_RET_BUSY) { - // zero means not ready -> fake a transfer complete so that this driver callback will fire again - dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false); - } else { + const uint8_t rhport = p_msc->rhport; + if (nbytes > 0) { TU_ASSERT(usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_epbuf.buf, (uint16_t) nbytes),); + } else { + // nbytes is status + switch (nbytes) { + case TUD_MSC_RET_ERROR: + // error -> endpoint is stalled & status in CSW set to failed + TU_LOG_DRV(" IO read() failed\r\n"); + set_sense_medium_not_present(p_msc->cbw.lun); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); + break; + + case TUD_MSC_RET_BUSY: + // not ready yet -> fake a transfer complete so that this driver callback will fire again + dcd_event_xfer_complete(rhport, p_msc->ep_in, 0, XFER_RESULT_SUCCESS, false); + break; + + default: break; + } } } @@ -886,13 +885,20 @@ static void proc_write10_host_data(mscd_interface_t* p_msc, uint32_t xferred_byt static void proc_write_io_data(mscd_interface_t* p_msc, uint32_t xferred_bytes, int32_t nbytes) { if (nbytes < 0) { - // negative means error -> failed this scsi op - TU_LOG_DRV(" IO write() failed\r\n"); - set_sense_medium_not_present(p_msc->cbw.lun); - fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); + // nbytes is status + switch (nbytes) { + case TUD_MSC_RET_ERROR: + // IO error -> failed this scsi op + TU_LOG_DRV(" IO write() failed\r\n"); + set_sense_medium_not_present(p_msc->cbw.lun); + fail_scsi_op(p_msc, MSC_CSW_STATUS_FAILED); + break; + + default: break; + } } else { if ((uint32_t)nbytes < xferred_bytes) { - // Application consume less than what we got (including zero) + // Application consume less than what we got including TUD_MSC_RET_BUSY (0) const uint32_t left_over = xferred_bytes - (uint32_t)nbytes; if (nbytes > 0) { memmove(_mscd_epbuf.buf, _mscd_epbuf.buf + nbytes, left_over); diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 2ad31c245..f2ea256b4 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -79,12 +79,11 @@ bool tud_msc_async_io_done(int32_t bytes_io, bool in_isr); - offset is only needed if CFG_TUD_MSC_EP_BUFSIZE is smaller than BLOCK_SIZE. - Application fill the buffer (up to bufsize) with address contents and return number of bytes read or status. - 0 < ret < bufsize: These bytes are transferred first and callback will be invoked again for remaining data. - - ret == TUD_MSC_RET_BUSY - Application is buys e.g disk I/O not ready. - Callback will be invoked again with the same parameters later on. - - ret == TUD_MSC_RET_ERROR + - TUD_MSC_RET_BUSY + Application is buys e.g disk I/O not ready. Callback will be invoked again with the same parameters later on. + - TUD_MSC_RET_ERROR error such as invalid address. This request will be STALLed and scsi command will be failed - - ret == TUD_MSC_RET_ASYNC + - TUD_MSC_RET_ASYNC Data I/O will be done asynchronously in a background task. Application should return immediately. tud_msc_async_io_done() must be called once IO/ is done to signal completion. */ -- cgit v1.3.1 From 41606a533dbe4bb7e031267d2869401243d2a0aa Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Jul 2025 13:42:05 +0700 Subject: make notify API and memory configurable with CFG_TUD_CDC_NOTIFY add tud_cdc_n_notify_conn_speed_change() add tud_cdc_notify_complete_cb() --- examples/device/cdc_dual_ports/src/main.c | 13 ++- examples/device/cdc_dual_ports/src/tusb_config.h | 2 + .../device/cdc_dual_ports/src/usb_descriptors.c | 47 +++++------ src/class/cdc/cdc.h | 95 ++++++++++++---------- src/class/cdc/cdc_device.c | 81 ++++++++++-------- src/class/cdc/cdc_device.h | 34 ++++++-- 6 files changed, 150 insertions(+), 122 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index e5432eb23..5a3e18358 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -102,16 +102,13 @@ void tud_umount_cb(void) { // USB CDC //--------------------------------------------------------------------+ static void cdc_task(void) { - uint8_t itf; - - for (itf = 0; itf < CFG_TUD_CDC; itf++) { + for (uint8_t itf = 0; itf < CFG_TUD_CDC; itf++) { // connected() check for DTR bit // Most but not all terminal client set this when making connection // if ( tud_cdc_n_connected(itf) ) { if (tud_cdc_n_available(itf)) { uint8_t buf[64]; - uint32_t count = tud_cdc_n_read(itf, buf, sizeof(buf)); // echo back to both serial ports @@ -121,11 +118,11 @@ static void cdc_task(void) { // Press on-board button to send Uart status notification static uint32_t btn_prev = 0; - static cdc_uart_state_t state = {0}; - uint32_t btn = board_button_read(); + static cdc_notify_uart_state_t uart_state = { .value = 0 }; + const uint32_t btn = board_button_read(); if (!btn_prev && btn) { - state.bTxCarrier ^= 1; - tud_cdc_send_uart_state(state); + uart_state.dsr ^= 1; + tud_cdc_notify_uart_state(&uart_state); } btn_prev = btn; } diff --git a/examples/device/cdc_dual_ports/src/tusb_config.h b/examples/device/cdc_dual_ports/src/tusb_config.h index 070f08ed1..7f7df3909 100644 --- a/examples/device/cdc_dual_ports/src/tusb_config.h +++ b/examples/device/cdc_dual_ports/src/tusb_config.h @@ -97,6 +97,8 @@ #define CFG_TUD_MIDI 0 #define CFG_TUD_VENDOR 0 +#define CFG_TUD_CDC_NOTIFY 1 // Enable use of notification endpoint + // CDC FIFO size of TX and RX #define CFG_TUD_CDC_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) #define CFG_TUD_CDC_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index 68eedd964..87309abbb 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -130,36 +130,32 @@ enum #define EPNUM_CDC_1_IN 0x84 #endif -uint8_t const desc_fs_configuration[] = -{ +uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 10, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 64), + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 16, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 64), // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 10, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 64), + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 16, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 64), }; #if TUD_OPT_HIGH_SPEED // Per USB specs: high speed capable device must report device_qualifier and other_speed_configuration - -uint8_t const desc_hs_configuration[] = -{ +uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), // 1st CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 10, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 512), + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_0, 4, EPNUM_CDC_0_NOTIF, 16, EPNUM_CDC_0_OUT, EPNUM_CDC_0_IN, 512), // 2nd CDC: Interface number, string index, EP notification address and size, EP data address (out, in) and size. - TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 10, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 512), + TUD_CDC_DESCRIPTOR(ITF_NUM_CDC_1, 4, EPNUM_CDC_1_NOTIF, 16, EPNUM_CDC_1_OUT, EPNUM_CDC_1_IN, 512), }; // device qualifier is mostly similar to device descriptor since we don't change configuration based on speed -tusb_desc_device_qualifier_t const desc_device_qualifier = -{ +tusb_desc_device_qualifier_t const desc_device_qualifier = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = USB_BCD, @@ -177,34 +173,31 @@ tusb_desc_device_qualifier_t const desc_device_qualifier = // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete. // device_qualifier descriptor describes information about a high-speed capable device that would // change if the device were operating at the other speed. If not highspeed capable stall this request. -uint8_t const* tud_descriptor_device_qualifier_cb(void) -{ - return (uint8_t const*) &desc_device_qualifier; +uint8_t const *tud_descriptor_device_qualifier_cb(void) { + return (uint8_t const *) &desc_device_qualifier; } // Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request // Application return pointer to descriptor, whose contents must exist long enough for transfer to complete // Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa -uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index) -{ - (void) index; // for multiple configurations +uint8_t const *tud_descriptor_other_speed_configuration_cb(uint8_t index) { + (void) index;// for multiple configurations // if link speed is high return fullspeed config, and vice versa - return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration; + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_fs_configuration : desc_hs_configuration; } -#endif // highspeed +#endif// highspeed // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) -{ - (void) index; // for multiple configurations +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) { + (void) index;// for multiple configurations #if TUD_OPT_HIGH_SPEED // Although we are highspeed, host may be fullspeed. - return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; #else return desc_fs_configuration; #endif @@ -223,8 +216,7 @@ enum { }; // array of pointer to string descriptors -char const *string_desc_arr[] = -{ +char const *string_desc_arr[] = { (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) "TinyUSB", // 1: Manufacturer "TinyUSB Device", // 2: Product @@ -254,14 +246,14 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL; + if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) { return NULL; } const char *str = string_desc_arr[index]; // Cap at max char chr_count = strlen(str); size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type - if ( chr_count > max_count ) chr_count = max_count; + if ( chr_count > max_count ) { chr_count = max_count; } // Convert ASCII string into UTF-16 for ( size_t i = 0; i < chr_count; i++ ) { @@ -272,6 +264,5 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { // first byte is length (including header), second byte is string type _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); - return _desc_str; } diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index a403d77fa..10ba16a7c 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -221,18 +221,20 @@ typedef enum { // Management Element Notification (Notification Endpoint) //--------------------------------------------------------------------+ +#define CDC_REQ_TYPE_NOTIF 0xA1 ///< Direction IN; Type Class; Recipient Interface + /// 6.3 Notification Codes typedef enum { - CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status. - CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request. + CDC_NOTIF_NETWORK_CONNECTION = 0x00, // notify the host about network connection status. + CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, // notify the host that a response is available. CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08, CDC_NOTIF_RING_DETECT = 0x09, CDC_NOTIF_SERIAL_STATE = 0x20, CDC_NOTIF_CALL_STATE_CHANGE = 0x28, CDC_NOTIF_LINE_STATE_CHANGE = 0x29, - CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred + CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, // notify the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40, -}cdc_notification_request_t; +} cdc_notify_request_t; //--------------------------------------------------------------------+ // Class Specific Functional Descriptor (Communication Interface) @@ -243,8 +245,7 @@ TU_ATTR_PACKED_BEGIN TU_ATTR_BIT_FIELD_ORDER_BEGIN /// Header Functional Descriptor (Communication Interface) -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUNC_DESC_ @@ -252,8 +253,7 @@ typedef struct TU_ATTR_PACKED }cdc_desc_func_header_t; /// Union Functional Descriptor (Communication Interface) -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_ @@ -271,14 +271,13 @@ typedef struct TU_ATTR_PACKED } /// Country Selection Functional Descriptor (Communication Interface) -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_ uint8_t iCountryCodeRelDate ; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes. uint16_t wCountryCode ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country. -}cdc_desc_func_country_selection_t; +} cdc_desc_func_country_selection_t; #define cdc_desc_func_country_selection_n_t(no_country) \ struct TU_ATTR_PACKED { \ @@ -295,8 +294,7 @@ typedef struct TU_ATTR_PACKED /// \brief Call Management Functional Descriptor /// \details This functional descriptor describes the processing of calls for the Communications Class interface. -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_ @@ -310,8 +308,7 @@ typedef struct TU_ATTR_PACKED uint8_t bDataInterface; }cdc_desc_func_call_management_t; -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t support_comm_request : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. uint8_t support_line_request : 1; ///< Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State. uint8_t support_send_break : 1; ///< Device supports the request Send_Break @@ -323,8 +320,7 @@ TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compile /// Abstract Control Management Functional Descriptor /// This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_ @@ -333,8 +329,7 @@ typedef struct TU_ATTR_PACKED /// \brief Direct Line Management Functional Descriptor /// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint8_t bLength ; ///< Size of this descriptor in bytes. uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_ @@ -396,8 +391,7 @@ typedef struct TU_ATTR_PACKED }cdc_desc_func_telephone_call_state_reporting_capabilities_t; // TODO remove -static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc) -{ +TU_ATTR_ALWAYS_INLINE static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc) { return p_desc[2]; } @@ -414,7 +408,7 @@ typedef struct TU_ATTR_PACKED { TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct"); typedef union TU_ATTR_PACKED { - struct { + struct TU_ATTR_PACKED { uint8_t dtr : 1; uint8_t rts : 1; uint8_t : 6; @@ -427,31 +421,44 @@ TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 1, "size is not correct"); //--------------------------------------------------------------------+ // Notifications //--------------------------------------------------------------------+ -typedef struct TU_ATTR_PACKED -{ - uint16_t bRxCarrier : 1; - uint16_t bTxCarrier : 1; - uint16_t bBreak : 1; - uint16_t bRingSignal : 1; - uint16_t bFraming : 1; - uint16_t bParity : 1; - uint16_t bOverRun : 1; - uint16_t : 9; -} cdc_uart_state_t; +// PSTN 1.2 section 6.5.4 table 31 +typedef union TU_ATTR_PACKED { + struct TU_ATTR_PACKED { + uint16_t bRxCarrier : 1; // DCD + uint16_t bTxCarrier : 1; // DSR + uint16_t bBreak : 1; // Break Detected + uint16_t bRingSignal : 1; + uint16_t bFraming : 1; + uint16_t bParity : 1; + uint16_t bOverRun : 1; + uint16_t : 9; + }; + struct TU_ATTR_PACKED { + uint16_t dcd : 1; + uint16_t dsr : 1; + uint16_t brk : 1; + uint16_t :13; + }; + uint16_t value; +} cdc_notify_uart_state_t; -typedef struct TU_ATTR_PACKED -{ - uint8_t bmRequestType; - uint8_t bNotification; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; - cdc_uart_state_t bmUartState; -} cdc_notif_serial_state_t; +TU_VERIFY_STATIC(sizeof(cdc_notify_uart_state_t) == 2, "size is not correct"); -TU_VERIFY_STATIC(sizeof(cdc_notif_serial_state_t) == 10, "size is not correct"); +// CDC 1.2 section 6.3.3 table 21 +typedef struct TU_ATTR_PACKED { + uint32_t upstream_bitrate; + uint32_t downstream_bitrate; +} cdc_notify_conn_speed_change_t; -#define CDC_REQ_TYPE_NOTIF 0xA1 ///< Direction IN; Type Class; Recipient Interface +typedef struct TU_ATTR_PACKED { + tusb_control_request_t request; + union { + cdc_notify_uart_state_t serial_state; + cdc_notify_conn_speed_change_t conn_speed_change; + }; +} cdc_notify_msg_t; + +TU_VERIFY_STATIC(sizeof(cdc_notify_msg_t) == 16, "size is not correct"); TU_ATTR_PACKED_END // End of all packed definitions TU_ATTR_BIT_FIELD_ORDER_END diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index 786c3aa55..4e4e01eaf 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -48,12 +48,11 @@ typedef struct { uint8_t rhport; uint8_t itf_num; - uint8_t ep_notif; uint8_t ep_in; uint8_t ep_out; - // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send) - uint8_t line_state; + uint8_t ep_notify; + uint8_t line_state; // Bit 0: DTR, Bit 1: RTS /*------------- From this point, data is not cleared by bus reset -------------*/ char wanted_char; @@ -75,7 +74,10 @@ typedef struct { typedef struct { TUD_EPBUF_DEF(epout, CFG_TUD_CDC_EP_BUFSIZE); TUD_EPBUF_DEF(epin, CFG_TUD_CDC_EP_BUFSIZE); - TUD_EPBUF_TYPE_DEF(cdc_notif_serial_state_t, epnotif); + + #if CFG_TUD_CDC_NOTIFY + TUD_EPBUF_TYPE_DEF(cdc_notify_msg_t, epnotify); + #endif } cdcd_epbuf_t; //--------------------------------------------------------------------+ @@ -120,7 +122,6 @@ static bool _prep_out_transaction(uint8_t itf) { //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ - bool tud_cdc_configure(const tud_cdc_configure_t* driver_cfg) { TU_VERIFY(driver_cfg); _cdcd_cfg = *driver_cfg; @@ -144,26 +145,41 @@ void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding) { (*coding) = _cdcd_itf[itf].line_coding; } -bool tud_cdc_n_send_uart_state (uint8_t itf, cdc_uart_state_t state) { +#if CFG_TUD_CDC_NOTIFY +bool tud_cdc_n_notify_uart_state (uint8_t itf, const cdc_notify_uart_state_t *state) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; + TU_VERIFY(tud_ready() && p_cdc->ep_notify != 0); + TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notify)); + + cdc_notify_msg_t* notify_msg = &p_epbuf->epnotify; + notify_msg->request.bmRequestType = CDC_REQ_TYPE_NOTIF; + notify_msg->request.bRequest = CDC_NOTIF_SERIAL_STATE; + notify_msg->request.wValue = 0; + notify_msg->request.wIndex = p_cdc->itf_num; + notify_msg->request.wLength = sizeof(cdc_notify_uart_state_t); + notify_msg->serial_state = *state; + + return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_notify, (uint8_t *)notify_msg, 8 + sizeof(cdc_notify_uart_state_t)); +} - // Skip if usb is not ready yet - TU_VERIFY(tud_ready(), 0); - - // claim endpoint - TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notif)); - - p_epbuf->epnotif.bmRequestType = CDC_REQ_TYPE_NOTIF; - p_epbuf->epnotif.bNotification = CDC_NOTIF_SERIAL_STATE; - p_epbuf->epnotif.wValue = 0; - p_epbuf->epnotif.wIndex = p_cdc->itf_num; - p_epbuf->epnotif.wLength = 2; - p_epbuf->epnotif.bmUartState = state; - - // transfer - return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_notif, (uint8_t *)&p_epbuf->epnotif, sizeof(cdc_notif_serial_state_t)); +bool tud_cdc_n_notify_conn_speed_change(uint8_t itf, const cdc_notify_conn_speed_change_t* conn_speed_change) { + cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; + cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; + TU_VERIFY(tud_ready() && p_cdc->ep_notify != 0); + TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_notify)); + + cdc_notify_msg_t* notify_msg = &p_epbuf->epnotify; + notify_msg->request.bmRequestType = CDC_REQ_TYPE_NOTIF; + notify_msg->request.bRequest = CDC_NOTIF_CONNECTION_SPEED_CHANGE; + notify_msg->request.wValue = 0; + notify_msg->request.wIndex = p_cdc->itf_num; + notify_msg->request.wLength = sizeof(cdc_notify_conn_speed_change_t); + notify_msg->conn_speed_change = *conn_speed_change; + + return usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_notify, (uint8_t *)notify_msg, 8 + sizeof(cdc_notify_conn_speed_change_t)); } +#endif void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted) { _cdcd_itf[itf].wanted_char = wanted; @@ -215,25 +231,20 @@ uint32_t tud_cdc_n_write(uint8_t itf, const void* buffer, uint32_t bufsize) { uint32_t tud_cdc_n_write_flush(uint8_t itf) { cdcd_interface_t* p_cdc = &_cdcd_itf[itf]; cdcd_epbuf_t* p_epbuf = &_cdcd_epbuf[itf]; - - // Skip if usb is not ready yet - TU_VERIFY(tud_ready(), 0); + TU_VERIFY(tud_ready(), 0); // Skip if usb is not ready yet // No data to send if (!tu_fifo_count(&p_cdc->tx_ff)) { return 0; } - const uint8_t rhport = 0; - - // Claim the endpoint - TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0); + TU_VERIFY(usbd_edpt_claim(p_cdc->rhport, p_cdc->ep_in), 0); // Claim the endpoint // Pull data from FIFO const uint16_t count = tu_fifo_read_n(&p_cdc->tx_ff, p_epbuf->epin, CFG_TUD_CDC_EP_BUFSIZE); if (count) { - TU_ASSERT(usbd_edpt_xfer(rhport, p_cdc->ep_in, p_epbuf->epin, count), 0); + TU_ASSERT(usbd_edpt_xfer(p_cdc->rhport, p_cdc->ep_in, p_epbuf->epin, count), 0); return count; } else { // Release endpoint since we don't make any transfer @@ -357,9 +368,8 @@ uint16_t cdcd_open(uint8_t rhport, const tusb_desc_interface_t* itf_desc, uint16 if (TUSB_DESC_ENDPOINT == tu_desc_type(p_desc)) { // notification endpoint const tusb_desc_endpoint_t* desc_ep = (const tusb_desc_endpoint_t*) p_desc; - TU_ASSERT(usbd_edpt_open(rhport, desc_ep), 0); - p_cdc->ep_notif = desc_ep->bEndpointAddress; + p_cdc->ep_notify = desc_ep->bEndpointAddress; drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); @@ -479,7 +489,7 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ // Identify which interface to use for (itf = 0; itf < CFG_TUD_CDC; itf++) { p_cdc = &_cdcd_itf[itf]; - if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in) || (ep_addr == p_cdc->ep_notif)) { + if ((ep_addr == p_cdc->ep_out) || (ep_addr == p_cdc->ep_in) || (ep_addr == p_cdc->ep_notify)) { break; } } @@ -528,7 +538,12 @@ bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_ } } - // nothing to do with notif endpoint for now + // Sent notification to host + if (ep_addr == p_cdc->ep_notify) { + if (tud_cdc_notify_complete_cb) { + tud_cdc_notify_complete_cb(itf); + } + } return true; } diff --git a/src/class/cdc/cdc_device.h b/src/class/cdc/cdc_device.h index f6fa5abf8..a34e07e1d 100644 --- a/src/class/cdc/cdc_device.h +++ b/src/class/cdc/cdc_device.h @@ -32,6 +32,10 @@ //--------------------------------------------------------------------+ // Class Driver Configuration //--------------------------------------------------------------------+ +#ifndef CFG_TUD_CDC_NOTIFY + #define CFG_TUD_CDC_NOTIFY 0 +#endif + #if !defined(CFG_TUD_CDC_EP_BUFSIZE) && defined(CFG_TUD_CDC_EPSIZE) #warning CFG_TUD_CDC_EPSIZE is renamed to CFG_TUD_CDC_EP_BUFSIZE, please update to use the new name #define CFG_TUD_CDC_EP_BUFSIZE CFG_TUD_CDC_EPSIZE @@ -83,9 +87,6 @@ uint8_t tud_cdc_n_get_line_state(uint8_t itf); // Get current line encoding: bit rate, stop bits parity etc .. void tud_cdc_n_get_line_coding(uint8_t itf, cdc_line_coding_t* coding); -// Send UART status notification: DCD, DSR etc .. -bool tud_cdc_n_send_uart_state(uint8_t itf, cdc_uart_state_t state); - // Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving void tud_cdc_n_set_wanted_char(uint8_t itf, char wanted); @@ -129,6 +130,23 @@ uint32_t tud_cdc_n_write_available(uint8_t itf); // Clear the transmit FIFO bool tud_cdc_n_write_clear(uint8_t itf); + +#if CFG_TUD_CDC_NOTIFY +// Send UART status notification: DCD, DSR etc .. +bool tud_cdc_n_notify_uart_state(uint8_t itf, const cdc_notify_uart_state_t *state); + +// Send connection speed change notification +bool tud_cdc_n_notify_conn_speed_change(uint8_t itf, const cdc_notify_conn_speed_change_t* conn_speed_change); + +TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_notify_uart_state(const cdc_notify_uart_state_t* state) { + return tud_cdc_n_notify_uart_state(0, state); +} + +TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_notify_conn_speed_change(const cdc_notify_conn_speed_change_t* conn_speed_change) { + return tud_cdc_n_notify_conn_speed_change(0, conn_speed_change); +} +#endif + //--------------------------------------------------------------------+ // Application API (Single Port) //--------------------------------------------------------------------+ @@ -149,11 +167,6 @@ TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_get_line_coding(cdc_line_coding tud_cdc_n_get_line_coding(0, coding); } -TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_send_uart_state(cdc_uart_state_t state) { - return tud_cdc_n_send_uart_state(0, state); -} - - TU_ATTR_ALWAYS_INLINE static inline void tud_cdc_set_wanted_char(char wanted) { tud_cdc_n_set_wanted_char(0, wanted); } @@ -203,7 +216,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool tud_cdc_write_clear(void) { } //--------------------------------------------------------------------+ -// Application Callback API (weak is optional) +// Application Callback API //--------------------------------------------------------------------+ // Invoked when received new data @@ -215,6 +228,9 @@ TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char); // Invoked when a TX is complete and therefore space becomes available in TX buffer TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf); +// Invoked when a notification is sent to host +TU_ATTR_WEAK void tud_cdc_notify_complete_cb(uint8_t itf); + // Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts); -- cgit v1.3.1 From 89da5a724dbd692527ee1d25d5ae71226d1dae56 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Jul 2025 14:28:44 +0700 Subject: reduce bInterval for default CDC descriptor from 16ms to 1ms --- src/device/usbd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/device/usbd.h b/src/device/usbd.h index de6007fb3..e5a848809 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -244,7 +244,7 @@ bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_requ /* CDC Union */\ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\ /* Endpoint Notification */\ - 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 16,\ + 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\ /* CDC Data Interface */\ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\ /* Endpoint Out */\ -- cgit v1.3.1 From 6e88895dbc2b09e60b971f1587d19d3a2487c2f8 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 5 Jul 2025 11:26:48 +0700 Subject: always define CFG_TUH_WCH_USBIP_USBFS=1 for ch32v20x since only port1 support host mode reformat hcd usbfs add uart rx for ch32v20x bsp --- hw/bsp/ch32v20x/family.c | 67 +-- hw/bsp/ch32v20x/family.cmake | 28 +- src/common/tusb_mcu.h | 8 +- src/portable/wch/dcd_ch32_usbhs.c | 2 +- src/portable/wch/hcd_ch32_usbfs.c | 943 +++++++++++++++++--------------------- 5 files changed, 477 insertions(+), 571 deletions(-) (limited to 'src') diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 2c212a82b..510f82981 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -20,59 +20,56 @@ manufacturer: WCH #include "bsp/board_api.h" #include "board.h" -/* CH32v203 depending on variants can support 2 USB IPs: FSDEV and USBFS. +/* CH32v203 depending on variants can support 2 USB IPs: FSDEV (port0) and USBFS (port1). * By default, we use FSDEV, but you can explicitly select by define: * - CFG_TUD_WCH_USBIP_FSDEV * - CFG_TUD_WCH_USBIP_USBFS */ -// USBFS -__attribute__((interrupt)) __attribute__((used)) -void USBHD_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_USBFS +// Port0: USBD (fsdev) +__attribute__((interrupt)) __attribute__((used)) void USB_LP_CAN1_RX0_IRQHandler(void) { + #if CFG_TUD_WCH_USBIP_FSDEV tud_int_handler(0); #endif - #if defined(CFG_TUH_WCH_USBIP_USBFS) && CFG_TUH_WCH_USBIP_USBFS - tuh_int_handler(0); - #endif } -__attribute__((interrupt)) __attribute__((used)) -void USBHDWakeUp_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_USBFS +__attribute__((interrupt)) __attribute__((used)) void USB_HP_CAN1_TX_IRQHandler(void) { + #if CFG_TUD_WCH_USBIP_FSDEV tud_int_handler(0); #endif + } -// USBD (fsdev) -__attribute__((interrupt)) __attribute__((used)) -void USB_LP_CAN1_RX0_IRQHandler(void) { +__attribute__((interrupt)) __attribute__((used)) void USBWakeUp_IRQHandler(void) { #if CFG_TUD_WCH_USBIP_FSDEV tud_int_handler(0); #endif } -__attribute__((interrupt)) __attribute__((used)) -void USB_HP_CAN1_TX_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_FSDEV - tud_int_handler(0); +// Port1: USBFS +__attribute__((interrupt)) __attribute__((used)) void USBHD_IRQHandler(void) { + #if CFG_TUD_ENABLED && CFG_TUD_WCH_USBIP_USBFS + tud_int_handler(1); #endif + #if CFG_TUH_ENABLED + tuh_int_handler(1); + #endif } -__attribute__((interrupt)) __attribute__((used)) -void USBWakeUp_IRQHandler(void) { - #if CFG_TUD_WCH_USBIP_FSDEV +__attribute__((interrupt)) __attribute__((used)) void USBHDWakeUp_IRQHandler(void) { + #if CFG_TUD_WCH_USBIP_USBFS tud_int_handler(0); #endif } - +//--------------------------------------------------------------------+ +// Board API +//--------------------------------------------------------------------+ #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -__attribute__((interrupt)) -void SysTick_Handler(void) { +__attribute__((interrupt)) void SysTick_Handler(void) { SysTick->SR = 0; system_ticks++; } @@ -111,7 +108,7 @@ void board_init(void) { #ifdef UART_DEV UART_CLOCK_EN(); GPIO_InitTypeDef usart_init = { - .GPIO_Pin = UART_TX_PIN, + .GPIO_Pin = UART_TX_PIN | UART_RX_PIN, .GPIO_Speed = GPIO_Speed_50MHz, .GPIO_Mode = GPIO_Mode_AF_PP, }; @@ -122,7 +119,7 @@ void board_init(void) { .USART_WordLength = USART_WordLength_8b, .USART_StopBits = USART_StopBits_1, .USART_Parity = USART_Parity_No, - .USART_Mode = USART_Mode_Tx, + .USART_Mode = USART_Mode_Tx | USART_Mode_Rx, .USART_HardwareFlowControl = USART_HardwareFlowControl_None, }; USART_Init(UART_DEV, &usart); @@ -192,9 +189,19 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { } int board_uart_read(uint8_t *buf, int len) { - (void) buf; - (void) len; +#ifdef UART_DEV + int count; + for (count = 0; count < len; count++) { + if (USART_GetFlagStatus(UART_DEV, USART_FLAG_RXNE) == RESET) { + break; + } + buf[count] = USART_ReceiveData(UART_DEV); + } + return count; +#else + (void) buf; (void) len; return 0; +#endif } int board_uart_write(void const *buf, int len) { @@ -210,7 +217,3 @@ int board_uart_write(void const *buf, int len) { return len; } - -//-------------------------------------------------------------------- -// Neopixel -//-------------------------------------------------------------------- diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index 6092abc8d..10044d5b3 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -16,9 +16,12 @@ set(FAMILY_MCUS CH32V20X CACHE INTERNAL "") set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg") # Port0 use FSDev, Port1 use USBFS -if (NOT DEFINED PORT) - set(PORT 0) -endif() +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () + +# only port1 support host mode +set(RHPORT_HOST 1) #------------------------------------ # BOARD_TARGET @@ -56,19 +59,16 @@ function(add_board_target BOARD_TARGET) ) target_compile_definitions(${BOARD_TARGET} PUBLIC CH32V20x_${MCU_VARIANT} + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUH_RHPORT=${RHPORT_HOST} ) - if (PORT EQUAL 0) - target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_WCH_USBIP_FSDEV=1 - CFG_TUH_WCH_USBIP_USBFS=1 - ) - elseif (PORT EQUAL 1) - target_compile_definitions(${BOARD_TARGET} PUBLIC - CFG_TUD_WCH_USBIP_USBFS=1 - ) + if (RHPORT_DEVICE EQUAL 0) + target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUD_WCH_USBIP_FSDEV=1) + elseif (RHPORT_DEVICE EQUAL 1) + target_compile_definitions(${BOARD_TARGET} PUBLIC CFG_TUH_WCH_USBIP_USBFS=1) else() - message(FATAL_ERROR "Invalid PORT ${PORT}") + message(FATAL_ERROR "Invalid RHPORT_DEVICE ${RHPORT_DEVICE}") endif() update_board(${BOARD_TARGET}) @@ -133,8 +133,6 @@ function(family_configure_example TARGET RTOS) ) target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - - # Flashing family_add_bin_hex(${TARGET}) family_flash_openocd_wch(${TARGET}) diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 2ee2132bf..a08ed79c8 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -503,11 +503,17 @@ #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_CH32V20X) - // v20x support both FSDEV (USBD) and USBFS, default to FSDEV + // v20x support both port0 FSDEV (USBD) and port1 USBFS #define TUP_USBIP_WCH_USBFS + + #ifndef CFG_TUH_WCH_USBIP_USBFS + #define CFG_TUH_WCH_USBIP_USBFS 1 + #endif + #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_CH32 + // default to FSDEV for device #if !defined(CFG_TUD_WCH_USBIP_USBFS) #define CFG_TUD_WCH_USBIP_USBFS 0 #endif diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c index f8bf3c889..4a208b9df 100644 --- a/src/portable/wch/dcd_ch32_usbhs.c +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -27,7 +27,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBHS) && CFG_TUD_WCH_USBIP_USBHS +#if CFG_TUD_ENABLED && defined(TUP_USBIP_WCH_USBHS) && defined(CFG_TUD_WCH_USBIP_USBHS) && CFG_TUD_WCH_USBIP_USBHS #include "ch32_usbhs_reg.h" #include "device/dcd.h" diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 800390989..d176f40c5 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -37,20 +37,20 @@ #include "ch32v20x.h" #include "ch32v20x_usb.h" -void osal_task_delay(uint32_t msec) { - uint32_t start = board_millis(); - while (board_millis() - start < msec) {} -} - #define USBFS_RX_BUF_LEN 64 #define USBFS_TX_BUF_LEN 64 -__attribute__((aligned(4))) static uint8_t USBFS_RX_Buf[USBFS_RX_BUF_LEN]; -__attribute__((aligned(4))) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; +TU_ATTR_ALIGNED(4) static uint8_t USBFS_RX_Buf[USBFS_RX_BUF_LEN]; +TU_ATTR_ALIGNED(4) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; #define USB_XFER_TIMEOUT_MILLIS 100 // #define USB_INTERRUPT_XFER_TIMEOUT_MILLIS 1 -#define PANIC(...) do { printf("%s() L%d: ", __func__, __LINE__); printf("\r\n[PANIC] " __VA_ARGS__); while (true) { } } while (false) +#define PANIC(...) \ + do { \ + printf("%s() L%d: ", __func__, __LINE__); \ + printf("\r\n[PANIC] " __VA_ARGS__); \ + while (true) {} \ + } while (false) #define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) @@ -70,106 +70,87 @@ __attribute__((aligned(4))) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; // Endpoint status -typedef struct usb_edpt -{ - // Is this a valid struct - bool configured; +typedef struct usb_edpt { + // Is this a valid struct + bool configured; - uint8_t dev_addr; - uint8_t ep_addr; - uint8_t max_packet_size; + uint8_t dev_addr; + uint8_t ep_addr; + uint8_t max_packet_size; - uint8_t xfer_type; + uint8_t xfer_type; - // Data toggle (0 or not 0) for DATA0/1 - uint8_t data_toggle; + // Data toggle (0 or not 0) for DATA0/1 + uint8_t data_toggle; } usb_edpt_t; - static usb_edpt_t usb_edpt_list[CFG_TUH_DEVICE_MAX * 6] = {}; - typedef struct usb_current_xfer_st { - bool is_busy; - uint8_t dev_addr; - uint8_t ep_addr; - // Xfer started time in millis for timeout - uint32_t start_ms; - uint8_t* buffer; - uint16_t bufferlen; - uint16_t xferred_len; + bool is_busy; + uint8_t dev_addr; + uint8_t ep_addr; + // Xfer started time in millis for timeout + uint32_t start_ms; + uint8_t *buffer; + uint16_t bufferlen; + uint16_t xferred_len; } usb_current_xfer_t; static volatile usb_current_xfer_t usb_current_xfer_info = {}; - -static usb_edpt_t* get_edpt_record(uint8_t dev_addr, uint8_t ep_addr) -{ - for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) - { - usb_edpt_t* cur = &usb_edpt_list[i]; - if (cur->configured && cur->dev_addr == dev_addr && cur->ep_addr == ep_addr) - { - return cur; - } +static usb_edpt_t *get_edpt_record(uint8_t dev_addr, uint8_t ep_addr) { + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) { + usb_edpt_t *cur = &usb_edpt_list[i]; + if (cur->configured && cur->dev_addr == dev_addr && cur->ep_addr == ep_addr) { + return cur; } - return NULL; + } + return NULL; } -static usb_edpt_t* get_empty_record_slot(void) -{ - for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) - { - if (!usb_edpt_list[i].configured) - { - return &usb_edpt_list[i]; - } +static usb_edpt_t *get_empty_record_slot(void) { + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) { + if (!usb_edpt_list[i].configured) { + return &usb_edpt_list[i]; } - return NULL; + } + return NULL; } -static usb_edpt_t* add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) -{ - usb_edpt_t* slot = get_empty_record_slot(); - if (slot == NULL) { - PANIC("add_edpt_record(0x%02x, 0x%02x, ...) no slot for new record\r\n", dev_addr, ep_addr); - } - TU_ASSERT(slot != NULL, NULL); +static usb_edpt_t *add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) { + usb_edpt_t *slot = get_empty_record_slot(); + if (slot == NULL) { + PANIC("add_edpt_record(0x%02x, 0x%02x, ...) no slot for new record\r\n", dev_addr, ep_addr); + } + TU_ASSERT(slot != NULL, NULL); - slot->dev_addr = dev_addr; - slot->ep_addr = ep_addr; - slot->max_packet_size = max_packet_size; - slot->xfer_type = xfer_type; - slot->data_toggle = 0; + slot->dev_addr = dev_addr; + slot->ep_addr = ep_addr; + slot->max_packet_size = max_packet_size; + slot->xfer_type = xfer_type; + slot->data_toggle = 0; - slot->configured = true; + slot->configured = true; - return slot; + return slot; } -static usb_edpt_t* get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) -{ - usb_edpt_t* ret = get_edpt_record(dev_addr, ep_addr); - if (ret != NULL) - { - return ret; - } - else - { - return add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type); - } +static usb_edpt_t *get_or_add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) { + usb_edpt_t *ret = get_edpt_record(dev_addr, ep_addr); + if (ret != NULL) { + return ret; + } else { + return add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type); + } } - -static void remove_edpt_record_for_device(uint8_t dev_addr) -{ - for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) - { - if (usb_edpt_list[i].configured && usb_edpt_list[i].dev_addr == dev_addr) - { - usb_edpt_list[i].configured = false; - } +static void remove_edpt_record_for_device(uint8_t dev_addr) { + for (size_t i = 0; i < TU_ARRAY_SIZE(usb_edpt_list); i++) { + if (usb_edpt_list[i].configured && usb_edpt_list[i].dev_addr == dev_addr) { + usb_edpt_list[i].configured = false; } + } } // static void dump_edpt_record_list() { @@ -183,544 +164,462 @@ static void remove_edpt_record_for_device(uint8_t dev_addr) // } // } - static bool interrupt_enabled = false; /** Enable or disable USBFS Host function */ -static void hardware_init_host(bool enabled) -{ - // Reset USBOTG module - USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; +static void hardware_init_host(bool enabled) { + // Reset USBOTG module + USBOTG_H_FS->BASE_CTRL = USBFS_UC_RESET_SIE | USBFS_UC_CLR_ALL; - osal_task_delay(1); - USBOTG_H_FS->BASE_CTRL = 0; + tusb_time_delay_ms_api(1); + USBOTG_H_FS->BASE_CTRL = 0; - if (!enabled) - { - // Disable all feature - USBOTG_H_FS->BASE_CTRL = 0; - } - else - { - // Enable USB Host features - // NVIC_DisableIRQ(USBFS_IRQn); - hcd_int_disable(0); - USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; - USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN; - USBOTG_H_FS->HOST_RX_DMA = (uint32_t)USBFS_RX_Buf; - USBOTG_H_FS->HOST_TX_DMA = (uint32_t)USBFS_TX_Buf; - // USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; - USBOTG_H_FS->INT_EN = USBFS_UIE_DETECT; - } + if (!enabled) { + // Disable all feature + USBOTG_H_FS->BASE_CTRL = 0; + } else { + // Enable USB Host features + // NVIC_DisableIRQ(USBFS_IRQn); + hcd_int_disable(0); + USBOTG_H_FS->BASE_CTRL = USBFS_UC_HOST_MODE | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBOTG_H_FS->HOST_EP_MOD = USBFS_UH_EP_TX_EN | USBFS_UH_EP_RX_EN; + USBOTG_H_FS->HOST_RX_DMA = (uint32_t) USBFS_RX_Buf; + USBOTG_H_FS->HOST_TX_DMA = (uint32_t) USBFS_TX_Buf; + // USBOTG_H_FS->INT_EN = USBFS_UIE_TRANSFER | USBFS_UIE_DETECT; + USBOTG_H_FS->INT_EN = USBFS_UIE_DETECT; + } } -static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggle) -{ - LOG_CH32_USBFSH("hardware_start_xfer(pid=%s(0x%02x), ep_addr=0x%02x, toggle=%d)\r\n", - pid == USB_PID_IN ? "IN" : pid == USB_PID_OUT ? "OUT" : pid == USB_PID_SETUP ? "SETUP" : "(other)", - pid, ep_addr, data_toggle); - - // if (pid == USB_PID_IN) - // { // FIXME: long delay needed (at release build) about 30msec - // loopdelay(SystemCoreClock / 1000 * 30); - // } - - uint8_t pid_edpt = (pid << 4) | (tu_edpt_number(ep_addr) & 0x0f); - USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; - USBOTG_H_FS->HOST_RX_CTRL = (data_toggle != 0) ? USBFS_UH_R_TOG : 0; - USBOTG_H_FS->HOST_EP_PID = pid_edpt; - USBOTG_H_FS->INT_EN |= USBFS_UIE_TRANSFER; - USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; - return true; +static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggle) { + LOG_CH32_USBFSH("hardware_start_xfer(pid=%s(0x%02x), ep_addr=0x%02x, toggle=%d)\r\n", + pid == USB_PID_IN ? "IN" : pid == USB_PID_OUT ? "OUT" + : pid == USB_PID_SETUP ? "SETUP" + : "(other)", + pid, ep_addr, data_toggle); + + // if (pid == USB_PID_IN) + // { // FIXME: long delay needed (at release build) about 30msec + // loopdelay(SystemCoreClock / 1000 * 30); + // } + + uint8_t pid_edpt = (pid << 4) | (tu_edpt_number(ep_addr) & 0x0f); + USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; + USBOTG_H_FS->HOST_RX_CTRL = (data_toggle != 0) ? USBFS_UH_R_TOG : 0; + USBOTG_H_FS->HOST_EP_PID = pid_edpt; + USBOTG_H_FS->INT_EN |= USBFS_UIE_TRANSFER; + USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; + return true; } /** Set device address to communicate */ -static void hardware_update_device_address(uint8_t dev_addr) -{ - // Keep the bit of GP_BIT. Other 7bits are actual device address. - USBOTG_H_FS->DEV_ADDR = (USBOTG_H_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | (dev_addr & USBFS_USB_ADDR_MASK); +static void hardware_update_device_address(uint8_t dev_addr) { + // Keep the bit of GP_BIT. Other 7bits are actual device address. + USBOTG_H_FS->DEV_ADDR = (USBOTG_H_FS->DEV_ADDR & USBFS_UDA_GP_BIT) | (dev_addr & USBFS_USB_ADDR_MASK); } /** Set port speed */ -static void hardware_update_port_speed(tusb_speed_t speed) -{ - LOG_CH32_USBFSH("hardware_update_port_speed(%s)\r\n", speed == TUSB_SPEED_FULL ? "Full" : speed == TUSB_SPEED_LOW ? "Low" : "(invalid)"); - switch (speed) { +static void hardware_update_port_speed(tusb_speed_t speed) { + LOG_CH32_USBFSH("hardware_update_port_speed(%s)\r\n", speed == TUSB_SPEED_FULL ? "Full" : speed == TUSB_SPEED_LOW ? "Low" + : "(invalid)"); + switch (speed) { case TUSB_SPEED_LOW: - USBOTG_H_FS->BASE_CTRL |= USBFS_UC_LOW_SPEED; - USBOTG_H_FS->HOST_CTRL |= USBFS_UH_LOW_SPEED; - USBOTG_H_FS->HOST_SETUP |= USBFS_UH_PRE_PID_EN; - return; + USBOTG_H_FS->BASE_CTRL |= USBFS_UC_LOW_SPEED; + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_LOW_SPEED; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_PRE_PID_EN; + return; case TUSB_SPEED_FULL: - USBOTG_H_FS->BASE_CTRL &= ~USBFS_UC_LOW_SPEED; - USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; - USBOTG_H_FS->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN; - return; + USBOTG_H_FS->BASE_CTRL &= ~USBFS_UC_LOW_SPEED; + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; + USBOTG_H_FS->HOST_SETUP &= ~USBFS_UH_PRE_PID_EN; + return; default: - PANIC("hardware_update_port_speed(%d)\r\n", speed); - } + PANIC("hardware_update_port_speed(%d)\r\n", speed); + } } - static void hardware_set_port_address_speed(uint8_t dev_addr) { - hardware_update_device_address(dev_addr); - tusb_speed_t rhport_speed = hcd_port_speed_get(0); - tusb_speed_t dev_speed = tuh_speed_get(dev_addr); - hardware_update_port_speed(dev_speed); - if (rhport_speed == TUSB_SPEED_FULL && dev_speed == TUSB_SPEED_LOW) { - USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; - } + hardware_update_device_address(dev_addr); + tusb_speed_t rhport_speed = hcd_port_speed_get(0); + tusb_speed_t dev_speed = tuh_speed_get(dev_addr); + hardware_update_port_speed(dev_speed); + if (rhport_speed == TUSB_SPEED_FULL && dev_speed == TUSB_SPEED_LOW) { + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_LOW_SPEED; + } } - -static bool hardware_device_attached(void) -{ - return USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH; +static bool hardware_device_attached(void) { + return USBOTG_H_FS->MIS_ST & USBFS_UMS_DEV_ATTACH; } - //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ -bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) -{ - (void)rhport; - (void)rh_init; - hardware_init_host(true); +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t *rh_init) { + (void) rhport; + (void) rh_init; + hardware_init_host(true); - return true; + return true; } -bool hcd_deinit(uint8_t rhport) -{ - (void)rhport; - hardware_init_host(false); +bool hcd_deinit(uint8_t rhport) { + (void) rhport; + hardware_init_host(false); - return true; + return true; } - static bool int_state_for_portreset = false; -void hcd_port_reset(uint8_t rhport) -{ - (void)rhport; - LOG_CH32_USBFSH("hcd_port_reset()\r\n"); - int_state_for_portreset = interrupt_enabled; - // NVIC_DisableIRQ(USBFS_IRQn); - hcd_int_disable(rhport); - hardware_update_device_address(0x00); +void hcd_port_reset(uint8_t rhport) { + (void) rhport; + LOG_CH32_USBFSH("hcd_port_reset()\r\n"); + int_state_for_portreset = interrupt_enabled; + // NVIC_DisableIRQ(USBFS_IRQn); + hcd_int_disable(rhport); + hardware_update_device_address(0x00); - // USBOTG_H_FS->HOST_SETUP = 0x00; + // USBOTG_H_FS->HOST_SETUP = 0x00; - USBOTG_H_FS->HOST_CTRL |= USBFS_UH_BUS_RESET; + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_BUS_RESET; - return; + return; } -void hcd_port_reset_end(uint8_t rhport) -{ - (void)rhport; - LOG_CH32_USBFSH("hcd_port_reset_end()\r\n"); +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; + LOG_CH32_USBFSH("hcd_port_reset_end()\r\n"); - USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_BUS_RESET; - osal_task_delay(2); + USBOTG_H_FS->HOST_CTRL &= ~USBFS_UH_BUS_RESET; + tusb_time_delay_ms_api(2); - if ((USBOTG_H_FS->HOST_CTRL & USBFS_UH_PORT_EN) == 0) - { - if (hcd_port_speed_get(0) == TUSB_SPEED_LOW) - { - hardware_update_port_speed(TUSB_SPEED_LOW); - } + if ((USBOTG_H_FS->HOST_CTRL & USBFS_UH_PORT_EN) == 0) { + if (hcd_port_speed_get(0) == TUSB_SPEED_LOW) { + hardware_update_port_speed(TUSB_SPEED_LOW); } + } - USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; - USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; - - // Suppress the attached event - USBOTG_H_FS->INT_FG |= USBFS_UIF_DETECT; + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; - if (int_state_for_portreset) { - hcd_int_enable(rhport); - } + // Suppress the attached event + USBOTG_H_FS->INT_FG |= USBFS_UIF_DETECT; - return; + if (int_state_for_portreset) { + hcd_int_enable(rhport); + } } -bool hcd_port_connect_status(uint8_t rhport) -{ - (void)rhport; +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; - return hardware_device_attached(); + return hardware_device_attached(); } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ - (void)rhport; - if (USBOTG_H_FS->MIS_ST & USBFS_UMS_DM_LEVEL) - { - return TUSB_SPEED_LOW; - } - else - { - return TUSB_SPEED_FULL; - } +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + if (USBOTG_H_FS->MIS_ST & USBFS_UMS_DM_LEVEL) { + return TUSB_SPEED_LOW; + } else { + return TUSB_SPEED_FULL; + } } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - LOG_CH32_USBFSH("hcd_device_close(%d, 0x%02x)\r\n", rhport, dev_addr); - remove_edpt_record_for_device(dev_addr); - - return; +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + LOG_CH32_USBFSH("hcd_device_close(%d, 0x%02x)\r\n", rhport, dev_addr); + remove_edpt_record_for_device(dev_addr); } -uint32_t hcd_frame_number(uint8_t rhport) -{ - (void)rhport; +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; - return board_millis(); + return board_millis(); } -void hcd_int_enable(uint8_t rhport) -{ - (void)rhport; - NVIC_EnableIRQ(USBFS_IRQn); - interrupt_enabled = true; - - return; +void hcd_int_enable(uint8_t rhport) { + (void) rhport; + NVIC_EnableIRQ(USBFS_IRQn); + interrupt_enabled = true; } -void hcd_int_disable(uint8_t rhport) -{ - (void)rhport; - NVIC_DisableIRQ(USBFS_IRQn); - interrupt_enabled = false; +void hcd_int_disable(uint8_t rhport) { + (void) rhport; + NVIC_DisableIRQ(USBFS_IRQn); + interrupt_enabled = false; +} +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) rhport; + (void) in_isr; + + if (USBOTG_H_FS->INT_FG & USBFS_UIF_DETECT) { + // Clear the flag + USBOTG_H_FS->INT_FG = USBFS_UIF_DETECT; + // Read the detection state + bool attached = hardware_device_attached(); + LOG_CH32_USBFSH("hcd_int_handler() attached = %d\r\n", attached ? 1 : 0); + if (attached) { + hcd_event_device_attach(rhport, true); + } else { + hcd_event_device_remove(rhport, true); + } return; -} + } + + if (USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) { + // Disable transfer interrupt + USBOTG_H_FS->INT_EN &= ~USBFS_UIE_TRANSFER; + // Clear the flag + // USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; + // Copy PID and Endpoint + uint8_t pid_edpt = USBOTG_H_FS->HOST_EP_PID; + uint8_t status = USBOTG_H_FS->INT_ST; + uint8_t dev_addr = USBOTG_H_FS->DEV_ADDR & USBFS_USB_ADDR_MASK; + // Clear register to stop transfer + // USBOTG_H_FS->HOST_EP_PID = 0x00; + + LOG_CH32_USBFSH("hcd_int_handler() pid_edpt=0x%02x\r\n", pid_edpt); + + uint8_t request_pid = pid_edpt >> 4; + uint8_t response_pid = status & USBFS_UIS_H_RES_MASK; + uint8_t ep_addr = pid_edpt & 0x0f; + if (request_pid == USB_PID_IN) { + ep_addr |= 0x80; + } -void hcd_int_handler(uint8_t rhport, bool in_isr) -{ - (void)rhport; - (void)in_isr; - - if (USBOTG_H_FS->INT_FG & USBFS_UIF_DETECT) - { - // Clear the flag - USBOTG_H_FS->INT_FG = USBFS_UIF_DETECT; - // Read the detection state - bool attached = hardware_device_attached(); - LOG_CH32_USBFSH("hcd_int_handler() attached = %d\r\n", attached ? 1 : 0); - if (attached) - { - hcd_event_device_attach(rhport, true); - } - else - { - hcd_event_device_remove(rhport, true); - } - return; + usb_edpt_t *edpt_info = get_edpt_record(dev_addr, ep_addr); + if (edpt_info == NULL) { + PANIC("\r\nget_edpt_record(0x%02x, 0x%02x) returned NULL in USBHD_IRQHandler\r\n", dev_addr, ep_addr); } - if (USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) - { - // Disable transfer interrupt - USBOTG_H_FS->INT_EN &= ~USBFS_UIE_TRANSFER; - // Clear the flag - // USBOTG_H_FS->INT_FG = USBFS_UIF_TRANSFER; - // Copy PID and Endpoint - uint8_t pid_edpt = USBOTG_H_FS->HOST_EP_PID; - uint8_t status = USBOTG_H_FS->INT_ST; - uint8_t dev_addr = USBOTG_H_FS->DEV_ADDR & USBFS_USB_ADDR_MASK; - // Clear register to stop transfer - // USBOTG_H_FS->HOST_EP_PID = 0x00; - - LOG_CH32_USBFSH("hcd_int_handler() pid_edpt=0x%02x\r\n", pid_edpt); - - uint8_t request_pid = pid_edpt >> 4; - uint8_t response_pid = status & USBFS_UIS_H_RES_MASK; - uint8_t ep_addr = pid_edpt & 0x0f; - if (request_pid == USB_PID_IN) - { - ep_addr |= 0x80; + if (status & USBFS_UIS_TOG_OK) { + edpt_info->data_toggle ^= 0x01; + + switch (request_pid) { + case USB_PID_SETUP: + case USB_PID_OUT: { + uint16_t tx_len = USBOTG_H_FS->HOST_TX_LEN; + usb_current_xfer_info.bufferlen -= tx_len; + usb_current_xfer_info.xferred_len += tx_len; + if (usb_current_xfer_info.bufferlen == 0) { + LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.xferred_len); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.xferred_len, XFER_RESULT_SUCCESS, true); + return; + } else { + LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); + usb_current_xfer_info.buffer += tx_len; + uint16_t copylen = USBFS_TX_BUF_LEN; + if (copylen > usb_current_xfer_info.bufferlen) { + copylen = usb_current_xfer_info.bufferlen; + } + memcpy(USBFS_TX_Buf, usb_current_xfer_info.buffer, copylen); + hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); + return; + } } - - usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); - if (edpt_info == NULL) - { - PANIC("\r\nget_edpt_record(0x%02x, 0x%02x) returned NULL in USBHD_IRQHandler\r\n", dev_addr, ep_addr); + case USB_PID_IN: { + uint16_t received_len = USBOTG_H_FS->RX_LEN; + usb_current_xfer_info.xferred_len += received_len; + uint16_t xferred_len = usb_current_xfer_info.xferred_len; + LOG_CH32_USBFSH("Read %d bytes\r\n", received_len); + // if (received_len > 0 && (usb_current_xfer_info.buffer == NULL || usb_current_xfer_info.bufferlen == 0)) { + // PANIC("Data received but buffer not set\r\n"); + // } + memcpy(usb_current_xfer_info.buffer, USBFS_RX_Buf, received_len); + usb_current_xfer_info.buffer += received_len; + if ((received_len < edpt_info->max_packet_size) || (xferred_len == usb_current_xfer_info.bufferlen)) { + // USB device sent all data. + LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); + return; + } else { + // USB device may send more data. + LOG_CH32_USBFSH("Read more data\r\n"); + hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); + return; + } } - - if (status & USBFS_UIS_TOG_OK) - { - edpt_info->data_toggle ^= 0x01; - - switch (request_pid) - { - case USB_PID_SETUP: - case USB_PID_OUT: - { - uint16_t tx_len = USBOTG_H_FS->HOST_TX_LEN; - usb_current_xfer_info.bufferlen -= tx_len; - usb_current_xfer_info.xferred_len += tx_len; - if (usb_current_xfer_info.bufferlen == 0) - { - LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.xferred_len); - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.xferred_len, XFER_RESULT_SUCCESS, true); - return; - } - else - { - LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); - usb_current_xfer_info.buffer += tx_len; - uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > usb_current_xfer_info.bufferlen) - { - copylen = usb_current_xfer_info.bufferlen; - } - memcpy(USBFS_TX_Buf, usb_current_xfer_info.buffer, copylen); - hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); - return; - } - } - case USB_PID_IN: - { - uint16_t received_len = USBOTG_H_FS->RX_LEN; - usb_current_xfer_info.xferred_len += received_len; - uint16_t xferred_len = usb_current_xfer_info.xferred_len; - LOG_CH32_USBFSH("Read %d bytes\r\n", received_len); - // if (received_len > 0 && (usb_current_xfer_info.buffer == NULL || usb_current_xfer_info.bufferlen == 0)) { - // PANIC("Data received but buffer not set\r\n"); - // } - memcpy(usb_current_xfer_info.buffer, USBFS_RX_Buf, received_len); - usb_current_xfer_info.buffer += received_len; - if ((received_len < edpt_info->max_packet_size) || (xferred_len == usb_current_xfer_info.bufferlen)) - { - // USB device sent all data. - LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); - return; - } - else - { - // USB device may send more data. - LOG_CH32_USBFSH("Read more data\r\n"); - hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); - return; - } - } - default: - { - PANIC("Unknown PID: 0x%02x\n", request_pid); - } - } + default: { + PANIC("Unknown PID: 0x%02x\n", request_pid); } - else - { - if (response_pid == USB_PID_STALL) - { - LOG_CH32_USBFSH("STALL response\r\n"); - hcd_edpt_clear_stall(0, dev_addr, ep_addr); - edpt_info->data_toggle = 0; - hardware_start_xfer(request_pid, ep_addr, 0); - return; - } - else if (response_pid == USB_PID_NAK) - { - LOG_CH32_USBFSH("NAK reposense\r\n"); - uint32_t elapsed_time = board_millis() - usb_current_xfer_info.start_ms; - if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT) - { - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); - } - else if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) - { - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); - } - else - { - hardware_start_xfer(request_pid, ep_addr, edpt_info->data_toggle); - } - return; - } - else if (response_pid == USB_PID_DATA0 || response_pid == USB_PID_DATA1) - { - LOG_CH32_USBFSH("Data toggle mismatched and DATA0/1 (not STALL). RX_LEN=%d\r\n", USBOTG_H_FS->RX_LEN); - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); - return; - } - else - { - LOG_CH32_USBFSH("In USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); - return; - } + } + } else { + if (response_pid == USB_PID_STALL) { + LOG_CH32_USBFSH("STALL response\r\n"); + hcd_edpt_clear_stall(0, dev_addr, ep_addr); + edpt_info->data_toggle = 0; + hardware_start_xfer(request_pid, ep_addr, 0); + return; + } else if (response_pid == USB_PID_NAK) { + LOG_CH32_USBFSH("NAK reposense\r\n"); + uint32_t elapsed_time = board_millis() - usb_current_xfer_info.start_ms; + if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT) { + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); + } else if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) { + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + } else { + hardware_start_xfer(request_pid, ep_addr, edpt_info->data_toggle); } + return; + } else if (response_pid == USB_PID_DATA0 || response_pid == USB_PID_DATA1) { + LOG_CH32_USBFSH("Data toggle mismatched and DATA0/1 (not STALL). RX_LEN=%d\r\n", USBOTG_H_FS->RX_LEN); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + return; + } else { + LOG_CH32_USBFSH("In USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + return; + } } + } } //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ - (void)rhport; - uint8_t ep_addr = ep_desc->bEndpointAddress; - uint8_t ep_num = tu_edpt_number(ep_addr); - uint16_t max_packet_size = ep_desc->wMaxPacketSize; - uint8_t xfer_type = ep_desc->bmAttributes.xfer; - LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d,xfer_type=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size, xfer_type); - - if (ep_num == 0x00) - { - TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size, xfer_type) != NULL, false); - TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size, xfer_type) != NULL, false); - } - else - { - TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type) != NULL, false); - } +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc) { + (void) rhport; + uint8_t ep_addr = ep_desc->bEndpointAddress; + uint8_t ep_num = tu_edpt_number(ep_addr); + uint16_t max_packet_size = ep_desc->wMaxPacketSize; + uint8_t xfer_type = ep_desc->bmAttributes.xfer; + LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d,xfer_type=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size, xfer_type); + if (ep_num == 0x00) { + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size, xfer_type) != NULL, false); + TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size, xfer_type) != NULL, false); + } else { + TU_ASSERT(get_or_add_edpt_record(dev_addr, ep_addr, max_packet_size, xfer_type) != NULL, false); + } - USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; - USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; + USBOTG_H_FS->HOST_CTRL |= USBFS_UH_PORT_EN; + USBOTG_H_FS->HOST_SETUP |= USBFS_UH_SOF_EN; - hardware_set_port_address_speed(dev_addr); + hardware_set_port_address_speed(dev_addr); - return true; + return true; } -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) -{ - (void)rhport; +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { + (void) rhport; - LOG_CH32_USBFSH("hcd_edpt_xfer(%d, 0x%02x, 0x%02x, ...)\r\n", rhport, dev_addr, ep_addr); + LOG_CH32_USBFSH("hcd_edpt_xfer(%d, 0x%02x, 0x%02x, ...)\r\n", rhport, dev_addr, ep_addr); - while (usb_current_xfer_info.is_busy) { } + while (usb_current_xfer_info.is_busy) {} + usb_current_xfer_info.is_busy = true; - usb_current_xfer_info.is_busy = true; + usb_edpt_t *edpt_info = get_edpt_record(dev_addr, ep_addr); + if (edpt_info == NULL) { + PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); + } - usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); - if (edpt_info == NULL) - { - PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); - } - - hardware_set_port_address_speed(dev_addr); - - usb_current_xfer_info.dev_addr = dev_addr; - usb_current_xfer_info.ep_addr = ep_addr; - usb_current_xfer_info.buffer = buffer; - usb_current_xfer_info.bufferlen = buflen; - usb_current_xfer_info.start_ms = board_millis(); - usb_current_xfer_info.xferred_len = 0; - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) - { - LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); - return hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); - } - else - { - LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); - uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > buflen) - { - copylen = buflen; - } - USBOTG_H_FS->HOST_TX_LEN = copylen; - memcpy(USBFS_TX_Buf, buffer, copylen); - return hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); + hardware_set_port_address_speed(dev_addr); + + usb_current_xfer_info.dev_addr = dev_addr; + usb_current_xfer_info.ep_addr = ep_addr; + usb_current_xfer_info.buffer = buffer; + usb_current_xfer_info.bufferlen = buflen; + usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.xferred_len = 0; + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { + LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); + return hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); + } else { + LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); + uint16_t copylen = USBFS_TX_BUF_LEN; + if (copylen > buflen) { + copylen = buflen; } + USBOTG_H_FS->HOST_TX_LEN = copylen; + memcpy(USBFS_TX_Buf, buffer, copylen); + return hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); + } } -bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) -{ - (void) rhport; - (void) dev_addr; - (void) ep_addr; +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; - return false; + return false; } -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ - (void)rhport; - - while (usb_current_xfer_info.is_busy) { } - - usb_current_xfer_info.is_busy = true; - - LOG_CH32_USBFSH("hcd_setup_send(rhport=%d, dev_addr=0x%02x, %p)\r\n", rhport, dev_addr, setup_packet); - - hardware_set_port_address_speed(dev_addr); - - usb_edpt_t* edpt_info_tx = get_edpt_record(dev_addr, 0x00); - usb_edpt_t* edpt_info_rx = get_edpt_record(dev_addr, 0x80); - TU_ASSERT(edpt_info_tx != NULL, false); - TU_ASSERT(edpt_info_rx != NULL, false); - - // Initialize data toggle (SETUP always starts with DATA0) - // Data toggle for OUT is toggled in hcd_int_handler() - edpt_info_tx->data_toggle = 0; - // Data toggle for IN must be set 0x01 manually. - edpt_info_rx->data_toggle = 0x01; - const uint16_t setup_packet_datalen = 8; - memcpy(USBFS_TX_Buf, setup_packet, setup_packet_datalen); - USBOTG_H_FS->HOST_TX_LEN = setup_packet_datalen; - uint8_t ep_addr = (setup_packet[0] & 0x80) ? 0x80 : 0x00; - usb_current_xfer_info.dev_addr = dev_addr; - usb_current_xfer_info.ep_addr = ep_addr; - usb_current_xfer_info.start_ms = board_millis(); - usb_current_xfer_info.buffer = USBFS_TX_Buf; - usb_current_xfer_info.bufferlen = setup_packet_datalen; - usb_current_xfer_info.xferred_len = 0; - - hardware_start_xfer(USB_PID_SETUP, 0, 0); - - return true; -} +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { + (void) rhport; -bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) -{ - (void) rhport; - (void) dev_addr; - LOG_CH32_USBFSH("hcd_edpt_clear_stall(rhport=%d, dev_addr=0x%02x, ep_addr=0x%02x)\r\n", rhport, dev_addr, ep_addr); - // PANIC("\r\install\r\n"); - uint8_t edpt_num = tu_edpt_number(ep_addr); - uint8_t setup_request_clear_stall[8] = { - 0x02, 0x01, 0x00, 0x00, edpt_num, 0x00, 0x00, 0x00 - }; - memcpy(USBFS_TX_Buf, setup_request_clear_stall, 8); - USBOTG_H_FS->HOST_TX_LEN = 8; - - bool prev_int_state = interrupt_enabled; - hcd_int_disable(0); + while (usb_current_xfer_info.is_busy) {} + + usb_current_xfer_info.is_busy = true; + + LOG_CH32_USBFSH("hcd_setup_send(rhport=%d, dev_addr=0x%02x, %p)\r\n", rhport, dev_addr, setup_packet); + + hardware_set_port_address_speed(dev_addr); + + usb_edpt_t *edpt_info_tx = get_edpt_record(dev_addr, 0x00); + usb_edpt_t *edpt_info_rx = get_edpt_record(dev_addr, 0x80); + TU_ASSERT(edpt_info_tx != NULL, false); + TU_ASSERT(edpt_info_rx != NULL, false); - USBOTG_H_FS->HOST_EP_PID = (USB_PID_SETUP << 4) | 0x00; - USBOTG_H_FS->INT_FG |= USBFS_UIF_TRANSFER; - while ((USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) == 0) { } - USBOTG_H_FS->HOST_EP_PID = 0; - uint8_t response_pid = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; - (void)response_pid; - LOG_CH32_USBFSH("hcd_edpt_clear_stall() response pid=0x%02x\r\n", response_pid); + // Initialize data toggle (SETUP always starts with DATA0) + // Data toggle for OUT is toggled in hcd_int_handler() + edpt_info_tx->data_toggle = 0; + // Data toggle for IN must be set 0x01 manually. + edpt_info_rx->data_toggle = 0x01; + const uint16_t setup_packet_datalen = 8; + memcpy(USBFS_TX_Buf, setup_packet, setup_packet_datalen); + USBOTG_H_FS->HOST_TX_LEN = setup_packet_datalen; + uint8_t ep_addr = (setup_packet[0] & 0x80) ? 0x80 : 0x00; + usb_current_xfer_info.dev_addr = dev_addr; + usb_current_xfer_info.ep_addr = ep_addr; + usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.buffer = USBFS_TX_Buf; + usb_current_xfer_info.bufferlen = setup_packet_datalen; + usb_current_xfer_info.xferred_len = 0; - if (prev_int_state) { + hardware_start_xfer(USB_PID_SETUP, 0, 0); + + return true; +} + +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + LOG_CH32_USBFSH("hcd_edpt_clear_stall(rhport=%d, dev_addr=0x%02x, ep_addr=0x%02x)\r\n", rhport, dev_addr, ep_addr); + // PANIC("\r\install\r\n"); + uint8_t edpt_num = tu_edpt_number(ep_addr); + uint8_t setup_request_clear_stall[8] = { + 0x02, 0x01, 0x00, 0x00, edpt_num, 0x00, 0x00, 0x00 + }; + memcpy(USBFS_TX_Buf, setup_request_clear_stall, 8); + USBOTG_H_FS->HOST_TX_LEN = 8; + + bool prev_int_state = interrupt_enabled; + hcd_int_disable(0); + + USBOTG_H_FS->HOST_EP_PID = (USB_PID_SETUP << 4) | 0x00; + USBOTG_H_FS->INT_FG |= USBFS_UIF_TRANSFER; + while ((USBOTG_H_FS->INT_FG & USBFS_UIF_TRANSFER) == 0) {} + USBOTG_H_FS->HOST_EP_PID = 0; + uint8_t response_pid = USBOTG_H_FS->INT_ST & USBFS_UIS_H_RES_MASK; + (void) response_pid; + LOG_CH32_USBFSH("hcd_edpt_clear_stall() response pid=0x%02x\r\n", response_pid); + + if (prev_int_state) { hcd_int_enable(0); - } + } - return true; + return true; } #endif -- cgit v1.3.1 From 3287cfaf76fb37644aa17c2e639d7d59b2764e59 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 5 Jul 2025 12:35:47 +0200 Subject: Use DMA enable for DCache condition Signed-off-by: HiFiPhile --- src/common/tusb_mcu.h | 15 +++++++++------ src/common/tusb_types.h | 12 ++++++------ src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/dwc2_stm32.h | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 2 +- src/tusb_option.h | 14 -------------- 6 files changed, 18 insertions(+), 29 deletions(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 8b30c98cd..4205239f1 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -220,8 +220,9 @@ #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS #endif - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 #elif TU_CHECK_MCU(OPT_MCU_STM32H7) @@ -232,8 +233,9 @@ #define TUP_DCD_ENDPOINT_MAX 9 #if __CORTEX_M == 7 - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 #endif @@ -333,8 +335,9 @@ // MCU with on-chip HS Phy #define TUP_RHPORT_HIGHSPEED 1 - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 //--------------------------------------------------------------------+ diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 4735c983a..ee97069bd 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -36,39 +36,39 @@ #endif //------------- Device DCache declaration -------------// -#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \ +#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \ (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) // Declare an endpoint buffer with uint8_t[size] #define TUD_EPBUF_DEF(_name, _size) \ union { \ CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ - TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ + TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ } // Declare an endpoint buffer with a type #define TUD_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUD_MEM_ALIGN _type _name; \ - TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ + TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ } //------------- Host DCache declaration -------------// -#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \ +#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \ (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size)) // Declare an endpoint buffer with uint8_t[size] #define TUH_EPBUF_DEF(_name, _size) \ union { \ CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \ - TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ + TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ } // Declare an endpoint buffer with a type #define TUH_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUH_MEM_ALIGN _type _name; \ - TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ + TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ } diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f7e9aacfe..5f86d6b76 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- -#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE +#if CFG_TUD_MEM_DCACHE_ENABLE bool dcd_dcache_clean(const void* addr, uint32_t data_size) { TU_VERIFY(addr && data_size); return dwc2_dcache_clean(addr, data_size); diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index f01d11fe8..f9aa5301b 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -280,7 +280,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { } //------------- DCache -------------// -#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE) +#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE typedef struct { diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 6b48c2346..257fa2833 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA; } -#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE +#if CFG_TUH_MEM_DCACHE_ENABLE bool hcd_dcache_clean(const void* addr, uint32_t data_size) { TU_VERIFY(addr && data_size); return dwc2_dcache_clean(addr, data_size); diff --git a/src/tusb_option.h b/src/tusb_option.h index b8a4059a8..867babc33 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -465,13 +465,6 @@ #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif -#if CFG_TUD_MEM_DCACHE_ENABLE && \ - (CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS)) - #define TUD_EPBUF_DCACHE_ALIGNED 1 -#else - #define TUD_EPBUF_DCACHE_ALIGNED 0 -#endif - #ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 #endif @@ -591,13 +584,6 @@ #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif -#if CFG_TUH_MEM_DCACHE_ENABLE && \ - (CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS)) - #define TUH_EPBUF_DCACHE_ALIGNED 1 -#else - #define TUH_EPBUF_DCACHE_ALIGNED 0 -#endif - //------------- CLASS -------------// #ifndef CFG_TUH_HUB -- cgit v1.3.1 From 59a3720795681ad05157016bd21090340a298af7 Mon Sep 17 00:00:00 2001 From: YixingShen Date: Mon, 7 Jul 2025 00:26:12 +0800 Subject: fixed CFG_TUD_VENDOR > 1 vendord_open tud_vendor_n_write_flush tud_vendor_n_write_flush argument should be 0,1,2,..., but p_vendor - _vendord_itf is 0, sizeof(vendord_interface_t), 2*sizeof(vendord_interface_t), ... --- src/class/vendor/vendor_device.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 7f1fd8c41..df1518111 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -201,9 +201,10 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin // Find available interface vendord_interface_t* p_vendor = NULL; - for(uint8_t i=0; ibEndpointAddress) == TUSB_DIR_IN) { if (p_vendor->tx.stream.ep_addr == 0) { tu_edpt_stream_open(&p_vendor->tx.stream, desc_ep); - tud_vendor_n_write_flush((uint8_t)(p_vendor - _vendord_itf)); + tud_vendor_n_write_flush(itf); } } else { if (p_vendor->rx.stream.ep_addr == 0) { -- cgit v1.3.1 From 73bf9aeaa6e1ffd453b7bffa4dd3818773e6a763 Mon Sep 17 00:00:00 2001 From: zhiqiang Date: Mon, 7 Jul 2025 14:13:15 +0800 Subject: support at32 mcu --- .../at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f402_405/at32f402_405_clock.c | 127 + hw/bsp/at32f402_405/at32f402_405_clock.h | 44 + hw/bsp/at32f402_405/at32f402_405_conf.h | 151 + hw/bsp/at32f402_405/at32f402_405_int.c | 140 + hw/bsp/at32f402_405/at32f402_405_int.h | 56 + .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 154 + .../boards/AT_START_F402_405/AT32F405xx_v2.svd | 45983 +++++++++++++++ .../at32f402_405/boards/AT_START_F402_405/board.h | 169 + .../at32f402_405/boards/AT_START_F402_405/board.mk | 4 + hw/bsp/at32f402_405/family.c | 297 + hw/bsp/at32f402_405/family.mk | 45 + hw/bsp/at32f402_405/startup_at32f402_405.s | 486 + .../at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f403a_407/at32f403a_407_clock.c | 87 + hw/bsp/at32f403a_407/at32f403a_407_clock.h | 44 + hw/bsp/at32f403a_407/at32f403a_407_conf.h | 161 + hw/bsp/at32f403a_407/at32f403a_407_int.c | 117 + hw/bsp/at32f403a_407/at32f403a_407_int.h | 56 + .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 154 + .../boards/AT_START_F403A_407/AT32F407xx_v2.svd | 28047 +++++++++ .../boards/AT_START_F403A_407/board.h | 61 + .../boards/AT_START_F403A_407/board.mk | 4 + hw/bsp/at32f403a_407/family.c | 287 + hw/bsp/at32f403a_407/family.mk | 42 + hw/bsp/at32f403a_407/startup_at32f403a_407.s | 478 + hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f413/at32f413_clock.c | 94 + hw/bsp/at32f413/at32f413_clock.h | 44 + hw/bsp/at32f413/at32f413_conf.h | 157 + hw/bsp/at32f413/at32f413_int.c | 141 + hw/bsp/at32f413/at32f413_int.h | 56 + .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 168 + .../boards/AT_START_F413/AT32F413xx_v2.svd | 23368 ++++++++ hw/bsp/at32f413/boards/AT_START_F413/board.h | 62 + hw/bsp/at32f413/boards/AT_START_F413/board.mk | 4 + hw/bsp/at32f413/family.c | 286 + hw/bsp/at32f413/family.mk | 42 + hw/bsp/at32f413/startup_at32f413.s | 431 + hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f415/at32f415_clock.c | 92 + hw/bsp/at32f415/at32f415_clock.h | 44 + hw/bsp/at32f415/at32f415_conf.h | 145 + hw/bsp/at32f415/at32f415_int.c | 119 + hw/bsp/at32f415/at32f415_int.h | 56 + .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 154 + .../boards/AT_START_F415/AT32F415xx_v2.svd | 27108 +++++++++ hw/bsp/at32f415/boards/AT_START_F415/board.h | 80 + hw/bsp/at32f415/boards/AT_START_F415/board.mk | 4 + hw/bsp/at32f415/family.c | 287 + hw/bsp/at32f415/family.mk | 43 + hw/bsp/at32f415/startup_at32f415.s | 407 + hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f423/at32f423_clock.c | 128 + hw/bsp/at32f423/at32f423_clock.h | 44 + hw/bsp/at32f423/at32f423_conf.h | 153 + hw/bsp/at32f423/at32f423_int.c | 140 + hw/bsp/at32f423/at32f423_int.h | 56 + .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 154 + .../boards/AT_START_F423/AT32F423xx_v2.svd | 36050 ++++++++++++ hw/bsp/at32f423/boards/AT_START_F423/board.h | 91 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 4 + hw/bsp/at32f423/family.c | 294 + hw/bsp/at32f423/family.mk | 44 + hw/bsp/at32f423/startup_at32f423.s | 483 + hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f425/at32f425_clock.c | 91 + hw/bsp/at32f425/at32f425_clock.h | 44 + hw/bsp/at32f425/at32f425_conf.h | 145 + hw/bsp/at32f425/at32f425_int.c | 140 + hw/bsp/at32f425/at32f425_int.h | 56 + .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 153 + .../boards/AT_START_F425/AT32F425xx_v2.svd | 30790 ++++++++++ hw/bsp/at32f425/boards/AT_START_F425/board.h | 90 + hw/bsp/at32f425/boards/AT_START_F425/board.mk | 4 + hw/bsp/at32f425/family.c | 298 + hw/bsp/at32f425/family.mk | 43 + hw/bsp/at32f425/startup_at32f425.s | 309 + .../at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h | 177 + hw/bsp/at32f435_437/at32f435_437_clock.c | 119 + hw/bsp/at32f435_437/at32f435_437_clock.h | 44 + hw/bsp/at32f435_437/at32f435_437_conf.h | 173 + hw/bsp/at32f435_437/at32f435_437_int.c | 120 + hw/bsp/at32f435_437/at32f435_437_int.h | 56 + .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 154 + .../boards/AT_START_F435_437/AT32F437xx_v2.svd | 58291 +++++++++++++++++++ .../at32f435_437/boards/AT_START_F435_437/board.h | 182 + .../at32f435_437/boards/AT_START_F435_437/board.mk | 4 + hw/bsp/at32f435_437/family.c | 370 + hw/bsp/at32f435_437/family.mk | 45 + hw/bsp/at32f435_437/startup_at32f435_437.s | 569 + src/common/tusb_mcu.h | 38 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 + src/portable/st/stm32_fsdev/fsdev_at32.h | 224 + src/portable/synopsys/dwc2/dwc2_at32.h | 135 + src/portable/synopsys/dwc2/dwc2_common.c | 14 +- src/portable/synopsys/dwc2/dwc2_common.h | 2 + src/tusb_option.h | 9 + tools/get_deps.py | 21 + 99 files changed, 262200 insertions(+), 1 deletion(-) create mode 100644 hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_clock.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_conf.h create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.c create mode 100644 hw/bsp/at32f402_405/at32f402_405_int.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h create mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk create mode 100644 hw/bsp/at32f402_405/family.c create mode 100644 hw/bsp/at32f402_405/family.mk create mode 100644 hw/bsp/at32f402_405/startup_at32f402_405.s create mode 100644 hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_clock.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_conf.h create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.c create mode 100644 hw/bsp/at32f403a_407/at32f403a_407_int.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk create mode 100644 hw/bsp/at32f403a_407/family.c create mode 100644 hw/bsp/at32f403a_407/family.mk create mode 100644 hw/bsp/at32f403a_407/startup_at32f403a_407.s create mode 100644 hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f413/at32f413_clock.c create mode 100644 hw/bsp/at32f413/at32f413_clock.h create mode 100644 hw/bsp/at32f413/at32f413_conf.h create mode 100644 hw/bsp/at32f413/at32f413_int.c create mode 100644 hw/bsp/at32f413/at32f413_int.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.h create mode 100644 hw/bsp/at32f413/boards/AT_START_F413/board.mk create mode 100644 hw/bsp/at32f413/family.c create mode 100644 hw/bsp/at32f413/family.mk create mode 100644 hw/bsp/at32f413/startup_at32f413.s create mode 100644 hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f415/at32f415_clock.c create mode 100644 hw/bsp/at32f415/at32f415_clock.h create mode 100644 hw/bsp/at32f415/at32f415_conf.h create mode 100644 hw/bsp/at32f415/at32f415_int.c create mode 100644 hw/bsp/at32f415/at32f415_int.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.h create mode 100644 hw/bsp/at32f415/boards/AT_START_F415/board.mk create mode 100644 hw/bsp/at32f415/family.c create mode 100644 hw/bsp/at32f415/family.mk create mode 100644 hw/bsp/at32f415/startup_at32f415.s create mode 100644 hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f423/at32f423_clock.c create mode 100644 hw/bsp/at32f423/at32f423_clock.h create mode 100644 hw/bsp/at32f423/at32f423_conf.h create mode 100644 hw/bsp/at32f423/at32f423_int.c create mode 100644 hw/bsp/at32f423/at32f423_int.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.h create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.mk create mode 100644 hw/bsp/at32f423/family.c create mode 100644 hw/bsp/at32f423/family.mk create mode 100644 hw/bsp/at32f423/startup_at32f423.s create mode 100644 hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f425/at32f425_clock.c create mode 100644 hw/bsp/at32f425/at32f425_clock.h create mode 100644 hw/bsp/at32f425/at32f425_conf.h create mode 100644 hw/bsp/at32f425/at32f425_int.c create mode 100644 hw/bsp/at32f425/at32f425_int.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.h create mode 100644 hw/bsp/at32f425/boards/AT_START_F425/board.mk create mode 100644 hw/bsp/at32f425/family.c create mode 100644 hw/bsp/at32f425/family.mk create mode 100644 hw/bsp/at32f425/startup_at32f425.s create mode 100644 hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_clock.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_conf.h create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.c create mode 100644 hw/bsp/at32f435_437/at32f435_437_int.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h create mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk create mode 100644 hw/bsp/at32f435_437/family.c create mode 100644 hw/bsp/at32f435_437/family.mk create mode 100644 hw/bsp/at32f435_437/startup_at32f435_437.s create mode 100644 src/portable/st/stm32_fsdev/fsdev_at32.h create mode 100644 src/portable/synopsys/dwc2/dwc2_at32.h (limited to 'src') diff --git a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d86c92542 --- /dev/null +++ b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f402_405.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd new file mode 100644 index 000000000..94a12b0f4 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd @@ -0,0 +1,45983 @@ + + + + + + + + Keil + ArteryTek + AT32F405xx_v2 + AT32F405 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 168MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000012 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + PLLUSTBL + PLLU clock ready flag + 26 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FP + PLLP post-division + 16 + 4 + read-write + + + PLL_FU + PLLU post-division + 20 + 3 + read-write + + + PLLU_EN + PLLU enable + 29 + 1 + read-write + + + PLLRCS + PLL reference clock select + 30 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + I2S5CLKSEL + I2S clock select + 22 + 2 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + OTGHSRST + OTGHS interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + I2S5RST + I2S5 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + OTGHSPHYRST + OTGHS phy reset + 31 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + OTGHSEN + OTGHS clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + I2S5EN + I2S5 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + OTGHSLPEN + OTGHS clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + I2S5LPEN + I2S5 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + OTGHSPHYLPEN + OTGHS phy clock enable during sleep mode + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + OTGHS + OTGHS + OTGHS register + 0x78 + 0x20 + 0x00000000 + + + XTLSEL + PHY clock source select + 0 + 1 + read-write + + + USBHS_PHY12_SEL + USBHS phy12 select value + 3 + 2 + read-write + + + USBHS_PHY30_SEL + USBHS phy12 select value + 8 + 2 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + PLLU_USB48_SEL + USB clock source select + 10 + 1 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + toggle bit 0 + 0 + 1 + + + IOTB1 + toggle bit 1 + 1 + 1 + + + IOTB2 + toggle bit 2 + 2 + 1 + + + IOTB3 + toggle bit 3 + 3 + 1 + + + IOTB4 + toggle bit 4 + 4 + 1 + + + IOTB5 + toggle bit 5 + 5 + 1 + + + IOTB6 + toggle bit 6 + 6 + 1 + + + IOTB7 + toggle bit 7 + 7 + 1 + + + IOTB8 + toggle bit 8 + 8 + 1 + + + IOTB9 + toggle bit 9 + 9 + 1 + + + IOTB10 + toggle bit 10 + 10 + 1 + + + IOTB11 + toggle bit 11 + 11 + 1 + + + IOTB12 + toggle bit 12 + 12 + 1 + + + IOTB13 + toggle bit 13 + 13 + 1 + + + IOTB14 + toggle bit 14 + 14 + 1 + + + IOTB15 + toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + OTGHS_WKUP + OTGHS_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Window value + 0 + 12 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40010000 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + TMR1_CH + TMR1 channel interrupt + 27 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode + selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TRGOUT2EN + TRGOUT2 enable + 31 + 1 + + + C4IOS + Channel 4 idle output state + 14 + 1 + + + C3CIOS + Channel 3 complementary idle output state + 13 + 1 + + + C3IOS + Channel 3 idle output state + 12 + 1 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + C1INSEL + C1IN selection + 7 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + ESP + External signal polarity + 15 + 1 + + + ECMBEN + External clock mode B enable + 14 + 1 + + + ESDIV + External signal divider + 12 + 2 + + + ESF + External signal filter + 8 + 4 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + 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CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + + TMR14 + 0x40002000 + + + RMP + RMP + TMR14 channel 1 input remap + 0x50 + 0x20 + read-write + 0x00000000 + + + TMR14_CH1_IRMP + TMR14 channel 1 input remap + 6 + 2 + + + + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2SF5 + Serial peripheral interface + SPI + 0x40015000 + + 0x0 + 0x400 + registers + + + I2SF5 + I2SF5 global interrupt + 85 + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SFDUPEN + I2S full duplex mode enable + 13 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + MISC1 + MISC1 + MISC1 register + 0x30 + 0x20 + read-write + 00000000 + + + I2SFPCMCKSEL + I2S PCM clock edge select + 0 + 1 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CMDF + Character match detection flag + 17 + 1 + read-write + + + RTODF + Reiceiver time out detection flag + 11 + 1 + read-write + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + RTODEN + Receiver time out detection enable + 27 + 1 + + + RETODIE + Receiver time out detection interrupt enable + 26 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + CMDIE + Character match detection interrupt enable + 14 + 1 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + IDH + bit 7-4 for usart identification + 28 + 4 + + + MTF + MSB transmit first + 19 + 1 + + + DTREV + DT register polarity reverse + 18 + 1 + + + TXREV + TX polarity reverse + 17 + 1 + + + RXREV + RX polarity reverse + 16 + 1 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + IDL + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + RTOV + RTOV + Receiver time out value register + 0x1C + 0x20 + read-write + 0x0000 + + + RTOV + Receiver time out value + 0 + 24 + + + + + IFC + IFC + Interruption flag clear register + 0x20 + 0x20 + read-write + 0x0000 + + + CMDFC + Character match detection flag clear + 17 + 1 + + + RTODFC + Receiver time out detection flag clear + 11 + 1 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART4 + 0x40004C00 + + USART4 + USART4 global interrupt + 52 + + + + USART5 + 0x40005000 + + USART5 + USART5 global interrupt + 53 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + + + + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + + 17 + 3 + + + PCTEN + + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB1 + F4FB1 + Filter bank 4 filtrate bit register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB2 + F4FB2 + Filter bank 4 filtrate bit register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter 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synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTGHS_GLOBAL + USB on the go high speed + USB_OTGHS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGHS + USB On The Go HS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGHS control and status register + (OTGHS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGHS interrupt register + (OTGHS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGHS AHB configuration register + (OTGHS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst Length + 1 + 4 + + + DMAEN + DMA Enable + 5 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGHS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + HS timeout calibration + 0 + 3 + read-write + + + PHYIF + PHY Interface + 3 + 1 + read-write + + + PHYSEL + USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial + Transceiver Select + 6 + 1 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGHS reset register + (OTGHS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA Request Signal + 30 + 1 + read-only + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGHS core interrupt register + (OTGHS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTGHS interrupt mask register + (OTGHS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGHS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGHS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGHS Receive FIFO size register + (OTGHS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGHS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGHS non-periodic transmit FIFO/queue + status register (OTGHS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGHS general core configuration register + (OTGHS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + WAIT_CLK_RCV + Wait Clock Soure Recover + 22 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGHS Host periodic transmit FIFO size + register (OTGHS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGHS device IN endpoint transmit FIFO size + register (OTGHS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGHS_HOST + USB on the go high speed + USB_OTGHS + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGHS host configuration register + (OTGHS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGHS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGHS host frame number/frame time + remaining register (OTGHS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGHS_Host periodic transmit FIFO/queue + status register (OTGHS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-only + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGHS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGHS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGHS host port control and status register + (OTGHS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGHS host channel-0 characteristics + register (OTGHS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGHS host channel-1 characteristics + register (OTGHS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGHS host channel-2 characteristics + register (OTGHS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGHS host channel-3 characteristics + register (OTGHS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGHS host channel-4 characteristics + register (OTGHS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGHS host channel-5 characteristics + register (OTGHS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGHS host channel-6 characteristics + register (OTGHS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGHS host channel-8 characteristics + register (OTGHS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGHS host channel-9 characteristics + register (OTGHS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGHS host channel-10 characteristics + register (OTGHS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGHS host channel-7 characteristics + register (OTGHS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGHS host channel-12 characteristics + register (OTGHS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGHS host channel-13 characteristics + register (OTGHS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGHS host channel-14 characteristics + register (OTGHS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGHS host channel-15 characteristics + register (OTGHS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCSPLT0 + HCSPLT0 + Host Channel 0 Split Control Register + 0x104 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT1 + HCSPLT1 + Host Channel 1 Split Control Register + 0x124 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT2 + HCSPLT2 + Host Channel 2 Split Control Register + 0x144 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT3 + HCSPLT3 + Host Channel 3 Split Control Register + 0x164 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT4 + HCSPLT4 + Host Channel 1 Split Control Register + 0x184 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT5 + HCSPLT5 + Host Channel 5 Split Control Register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT6 + HCSPLT6 + Host Channel 6 Split Control Register + 0x1C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT7 + HCSPLT7 + Host Channel 7 Split Control Register + 0x1E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT8 + HCSPLT8 + Host Channel 8 Split Control Register + 0x204 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT9 + HCSPLT9 + Host Channel 9 Split Control Register + 0x224 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT10 + HCSPLT10 + Host Channel 10 Split Control Register + 0x244 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT11 + HCSPLT11 + Host Channel 11 Split Control Register + 0x264 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT12 + HCSPLT12 + Host Channel 12 Split Control Register + 0x284 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT13 + HCSPLT13 + Host Channel 13 Split Control Register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT14 + HCSPLT14 + Host Channel 14 Split Control Register + 0x2C4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCSPLT15 + HCSPLT15 + Host Channel 15 Split Control Register + 0x2E4 + 0x20 + read-write + 0x00000000 + + + PRTADDR + Port Address + 0 + 7 + + + HUBADDR + Hub Address + 7 + 7 + + + XACTPOS + Transaction Position + 14 + 2 + + + COMPSPLT + Do Complete Split + 16 + 1 + + + SPLTENA + Split Enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGHS host channel-0 interrupt register + (OTGHS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTGHS host channel-1 interrupt register + (OTGHS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGHS host channel-2 interrupt register + (OTGHS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGHS host channel-3 interrupt register + (OTGHS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGHS host channel-4 interrupt register + (OTGHS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGHS host channel-5 interrupt register + (OTGHS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGHS host channel-6 interrupt register + (OTGHS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGHS host channel-7 interrupt register + (OTGHS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGHS host channel-8 interrupt register + (OTGHS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGHS host channel-9 interrupt register + (OTGHS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGHS host channel-10 interrupt register + (OTGHS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGHS host channel-11 interrupt register + (OTGHS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGHS host channel-12 interrupt register + (OTGHS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGHS host channel-13 interrupt register + (OTGHS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGHS host channel-14 interrupt register + (OTGHS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGHS host channel-15 interrupt register + (OTGHS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + AHBERR + AHB Error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + NYET Response Received + interrupt + 6 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGHS host channel-0 mask register + (OTGHS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGHS host channel-1 mask register + (OTGHS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGHS host channel-2 mask register + (OTGHS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGHS host channel-3 mask register + (OTGHS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGHS host channel-4 mask register + (OTGHS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGHS host channel-5 mask register + (OTGHS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGHS host channel-6 mask register + (OTGHS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGHS host channel-7 mask register + (OTGHS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGHS host channel-8 mask register + (OTGHS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGHS host channel-9 mask register + (OTGHS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGHS host channel-10 mask register + (OTGHS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGHS host channel-11 mask register + (OTGHS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGHS host channel-12 mask register + (OTGHS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGHS host channel-13 mask register + (OTGHS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGHS host channel-14 mask register + (OTGHS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGHS host channel-15 mask register + (OTGHS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + AHBERRMSK + AHB Error Mask + 2 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYETMSK + NYET Response Received + interrupt mask + 6 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGHS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ1 + HCTSIZ1 + OTGHS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ2 + HCTSIZ2 + OTGHS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ3 + HCTSIZ3 + OTGHS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ4 + HCTSIZ4 + OTGHS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ5 + HCTSIZ5 + OTGHS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ6 + HCTSIZ6 + OTGHS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ7 + HCTSIZ7 + OTGHS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ8 + HCTSIZ8 + OTGHS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ9 + HCTSIZ9 + OTGHS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ10 + HCTSIZ10 + OTGHS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ11 + HCTSIZ11 + OTGHS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ12 + HCTSIZ12 + OTGHS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ13 + HCTSIZ13 + OTGHS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ14 + HCTSIZ14 + OTGHS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCTSIZ15 + HCTSIZ15 + OTGHS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + DOPNG + Do Ping + 31 + 1 + + + + + HCDMA0 + HCDMA0 + Host channel 0 DMA address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA1 + HCDMA1 + Host channel 1 DMA address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA2 + HCDMA2 + Host channel 2 DMA address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA3 + HCDMA3 + Host channel 3 DMA address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA4 + HCDMA4 + Host channel 4 DMA address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA5 + HCDMA5 + Host channel 5 DMA address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA6 + HCDMA6 + Host channel 6 DMA address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA7 + HCDMA7 + Host channel 7 DMA address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA8 + HCDMA8 + Host channel 8 DMA address + register + 0x214 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA9 + HCDMA9 + Host channel 9 DMA address + register + 0x234 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA10 + HCDMA10 + Host channel 10 DMA address + register + 0x254 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA11 + HCDMA11 + Host channel 11 DMA address + register + 0x274 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA12 + HCDMA12 + Host channel 12 DMA address + register + 0x294 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA13 + HCDMA13 + Host channel 13 DMA address + register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA14 + HCDMA14 + Host channel 14 DMA address + register + 0x2D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + HCDMA15 + HCDMA15 + Host channel 15 DMA address + register + 0x2F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_DEVICE + USB on the go high speed + USB_OTGHS + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGHS device configuration register + (OTGHS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGHS device control register + (OTGHS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + DEVLNSTS + Device Line Status + 22 + 2 + + + + + DIEPMSK + DIEPMSK + OTGHS device IN endpoint common interrupt + mask register (OTGHS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPMSK + DOEPMSK + OTGHS device OUT endpoint common interrupt + mask register (OTGHS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DAINT + DAINT + OTGHS device all endpoints interrupt + register (OTGHS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGHS all endpoints interrupt mask register + (OTGHS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGHS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DEACHINT + DEACHINT + ODevice Each Endpoints + Interrupt Register + 0x38 + 0x20 + read-write + 0x00000000 + + + ECHINEPINT + Each IN Endpoint Interrupt + bits + 0 + 16 + + + ECHOUTEPINT + Each OUT Endpoint Interrupt + bits + 16 + 16 + + + + + DEACHINTMSK + DEACHINTMSK + Device Each Endpoints + Interrupt Mask Register + 0x3C + 0x20 + read-write + 0x00000000 + + + ECHINEPINTMSK + Each IN Endpoint Interrupt Mask + bits + 0 + 16 + + + ECHOUTEPINTMSK + Each OUT Endpoint Interrupt Mask + bits + 16 + 16 + + + + + DIEPEACHMSK1 + DIEPEACHMSK1 + Device Each IN Endpoint 1 Interrupt Register + 0x44 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + + + DOEPEACHMSK1 + DOEPEACHMSK1 + Device Each OUT Endpoint 1 Interrupt Register + 0x84 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + AHBERRMSK + AHB Error + mask + 2 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + STSPHSERCVDMSK + Status Phase Received + mask + 5 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + BBLEERRMSK + Babble Error interrupt + mask + 12 + 1 + + + NAKMSK + NAK interrupt + mask + 13 + 1 + + + NYETMSK + NYET interrupt + mask + 14 + 1 + + + + + DIEPCTL0 + DIEPCTL0 + OTGHS device control IN endpoint 0 control + register (OTGHS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL1 + DIEPCTL1 + OTGHS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGHS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGHS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGHS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGHS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGHS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGHS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGHS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGHS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGHS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGHS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGHS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGHS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGHS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGHS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGHS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + OTGHS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + OTGHS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + OTGHS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT4 + DIEPINT4 + OTGHS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT5 + DIEPINT5 + OTGHS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT6 + DIEPINT6 + OTGHS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DIEPINT7 + DIEPINT7 + OTGHS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + AHBERR + AHB Error + interrupt + 2 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + TXFIFOUNDRN + Fifo Underrun + 8 + 1 + read-write + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + OTGHS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT1 + DOEPINT1 + OTGHS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT2 + DOEPINT2 + OTGHS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT3 + DOEPINT3 + OTGHS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT4 + DOEPINT4 + OTGHS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT5 + DOEPINT5 + OTGHS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT6 + DOEPINT6 + OTGHS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DOEPINT7 + DOEPINT7 + OTGHS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + OUTPKTERR + OUT Packet Error + 8 + 1 + + + BNAINTR + Buffer Not Available Error + 9 + 1 + + + PKTDRPSTS + Packet Drop Status + 11 + 1 + read-write + + + BBLEERR + BBLE error + 12 + 1 + read-write + + + NAKINTPT + NAK interrupt + 13 + 1 + read-write + + + NYETINTPT + NYET interrupt + 14 + 1 + read-write + + + STUPPKTRCVD + Setup Packet Received + 15 + 1 + read-write + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGHS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGHS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGHS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGHS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPDMA0 + DIEPDMA0 + Device IN Endpoint 0 DMA Address + register + 0x114 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA1 + DIEPDMA1 + Device IN Endpoint 1 DMA Address + register + 0x134 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA2 + DIEPDMA2 + Device IN Endpoint 2 DMA Address + register + 0x154 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA3 + DIEPDMA3 + Device IN Endpoint 3 DMA Address + register + 0x174 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA4 + DIEPDMA4 + Device IN Endpoint 4 DMA Address + register + 0x194 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA5 + DIEPDMA5 + Device IN Endpoint 5 DMA Address + register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA6 + DIEPDMA6 + Device IN Endpoint 6 DMA Address + register + 0x1D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DIEPDMA7 + DIEPDMA7 + Device IN Endpoint 7 DMA Address + register + 0x1F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DTXFSTS0 + DTXFSTS0 + OTGHS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGHS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGHS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGHS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGHS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGHS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGHS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGHS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGHS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGHS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGHS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGHS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGHS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGHS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGHS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPDMA0 + DOEPDMA0 + Device OUT Endpoint 0 DMA Address + register + 0x314 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA1 + DOEPDMA1 + Device OUT Endpoint 1 DMA Address + register + 0x334 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA2 + DOEPDMA2 + Device OUT Endpoint 2 DMA Address + register + 0x354 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA3 + DOEPDMA3 + Device OUT Endpoint 3 DMA Address + register + 0x374 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA4 + DOEPDMA4 + Device OUT Endpoint 4 DMA Address + register + 0x394 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA5 + DOEPDMA5 + Device OUT Endpoint 5 DMA Address + register + 0x3B4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA6 + DOEPDMA6 + Device OUT Endpoint 6 DMA Address + register + 0x3D4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + DOEPDMA7 + DOEPDMA7 + Device OUT Endpoint 7 DMA Address + register + 0x3F4 + 0x20 + read-write + 0x00000000 + + + DMAADDR + DMA Address + 0 + 32 + + + + + + + USB_OTGHS_PWRCLK + USB on the go high speed + USB_OTGHS + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGHS power and clock gating control + register (OTGHS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4F LOCKUP bit enable + 0 + 1 + + + SRAM_OPERR_LK + SRAM odd parity error lock enable + 1 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + SRAM_OPERR_STS + SRAM odd parity error status + 8 + 1 + + + I2S_FD + I2S full duplex config + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 5 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 5 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h new file mode 100644 index 000000000..9c07bf192 --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h @@ -0,0 +1,169 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOF +#define LED_PIN GPIO_PINS_4 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOF_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +//USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID USB_OTG1_ID + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_FULL_SPEED_CORE_ID + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID USB_OTG2_ID + #define OTG_CLOCK CRM_OTGHS_PERIPH_CLOCK + #define OTG_IRQ OTGHS_IRQn + #define OTG_IRQ_HANDLER OTGHS_IRQHandler + #define OTG_WKUP_IRQ OTGHS_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGHS_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_10 + #define USB_SPEED_CORE_ID USB_HIGH_SPEED_CORE_ID + #endif +#endif + +//Vbus +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk new file mode 100644 index 000000000..527d3706b --- /dev/null +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F405xC_FLASH.ld + +CFLAGS += \ + -DAT32F405RCT7 diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c new file mode 100644 index 000000000..dd8e7de10 --- /dev/null +++ b/hw/bsp/at32f402_405/family.c @@ -0,0 +1,297 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f402_405_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +void usb_gpio_config(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGHS_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* config usb io*/ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + SysTick_Config(system_core_clock / 1000); + + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #else + NVIC_SetPriority(OTG_IRQ, 0); + #endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart to printf */ + uart_print_init(115200); + // printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN | GPIO_PINS_5 | GPIO_PINS_6; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, GPIO_PINS_5); + gpio_bits_set(LED_PORT, GPIO_PINS_6); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + crm_pllu_output_set(TRUE); + /* wait till pll is ready */ + while(crm_flag_get(CRM_PLLU_STABLE_FLAG) != SET){} + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_PLLU); + } +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk new file mode 100644 index 000000000..9dbdb1a55 --- /dev/null +++ b/hw/bsp/at32f402_405/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F402_405_SDK = hw/mcu/artery/at32f402_405 +DEPS_SUBMODULES += $(AT32F402_405_SDK) + +# AT32 SDK path +AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F402_405 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_gpio.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_misc.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_usart.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_crm.c \ + $(AT32F402_405_SDK_SRC)/drivers/src/at32f402_405_acc.c \ + $(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support/system_at32f402_405.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F402_405_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F402_405_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f402_405.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s new file mode 100644 index 000000000..251ec5058 --- /dev/null +++ b/hw/bsp/at32f402_405/startup_at32f402_405.s @@ -0,0 +1,486 @@ +/** + ****************************************************************************** + * @file startup_at32f402_405.s + * @brief at32f402_405 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word OTGHS_EP1_OUT_IRQHandler /* OTGHS endpoint1 out */ + .word OTGHS_EP1_IN_IRQHandler /* OTGHS endpoint1 in */ + .word OTGHS_WKUP_IRQHandler /* OTGHS Wakeup from suspend */ + .word OTGHS_IRQHandler /* OTGHS */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word 0 /* Reserved */ + .word I2SF5_IRQHandler /* I2SF5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGHS_EP1_OUT_IRQHandler + .thumb_set OTGHS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTGHS_EP1_IN_IRQHandler + .thumb_set OTGHS_EP1_IN_IRQHandler,Default_Handler + + .weak OTGHS_WKUP_IRQHandler + .thumb_set OTGHS_WKUP_IRQHandler,Default_Handler + + .weak OTGHS_IRQHandler + .thumb_set OTGHS_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak I2SF5_IRQHandler + .thumb_set I2SF5_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..d63959c4e --- /dev/null +++ b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f403a_407.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd new file mode 100644 index 000000000..323218b23 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd @@ -0,0 +1,28047 @@ + + + + + + + + Keil + ArteryTek + AT32F407xx_v2 + AT32F407 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGMEM + BK2TMGMEM + Regular memory space timing register 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGATT + BK2TMGATT + special memory space timing register 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + BUSLATW2W + 0 + 8 + + + BUSLATR2R + BUSLATR2R + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOERST + IO port E reset + 6 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + ADC3RST + ADC3 reset + 15 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + USART6RST + USART6 reset + 24 + 1 + + + UART7RST + UART7 reset + 25 + 1 + + + UART8RST + UART8 reset + 26 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR12RST + Timer 12 reset + 6 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI4RST + SPI4 reset + 16 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + XMCEN + XMC clock enable + 8 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + SDIO2EN + SDIO2 clock enable + 11 + 1 + + + EMACEN + EMACEN clock enable + 14 + 1 + + + EMACTXEN + EMACEN Tx clock enable + 15 + 1 + + + EMACRXEN + EMACEN Rx clock enable + 16 + 1 + + + EMACPTPEN + EMACPTP clock enable + 28 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOEEN + I/O port E clock enable + 6 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + ADC2EN + ADC2 clock + enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + ADC3EN + ADC3 clock enable + 15 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + USART6EN + USART6 clock enable + 24 + 1 + + + UART7EN + UART7 clock enable + 25 + 1 + + + UART8EN + UART8 clock enable + 26 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI4EN + SPI4 clock enable + 16 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BPREN + Barrery powered domain register clock + enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + EMACRST + EMAC reset + 14 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + HEXTDIV + HEXT division + 12 + 2 + read-write + + + EMAC_PPS_SEL + Ethernet pulse width Select + 15 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + HDRV + HDRV + Port configuration driver + register + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port hdrv bit 0 + 0 + 1 + + + HDRV1 + Port hdrv bit 1 + 1 + 1 + + + HDRV2 + Port hdrv bit 2 + 2 + 1 + + + HDRV3 + Port hdrv bit 3 + 3 + 1 + + + HDRV4 + Port hdrv bit 4 + 4 + 1 + + + HDRV5 + Port hdrv bit 5 + 5 + 1 + + + HDRV6 + Port hdrv bit 6 + 6 + 1 + + + HDRV7 + Port hdrv bit 7 + 7 + 1 + + + HDRV8 + Port hdrv bit 8 + 8 + 1 + + + HDRV9 + Port hdrv bit 9 + 9 + 1 + + + HDRV10 + Port hdrv bit 10 + 10 + 1 + + + HDRV11 + Port hdrv bit 11 + 11 + 1 + + + HDRV12 + Port hdrv bit 12 + 12 + 1 + + + HDRV13 + Port hdrv bit 13 + 13 + 1 + + + HDRV14 + Port hdrv bit 14 + 14 + 1 + + + HDRV15 + Port hdrv bit 15 + 15 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + (IOMUX_REMAP) + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART2_MUX + USART2 muxing + 3 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + TMR4_MUX + TMR4 muxing + 12 + 1 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + EMAC_MUX + Ethernet MAC muxing + 21 + 1 + read-write + + + CAN2_MUX + CAN2 muxing + 22 + 1 + read-write + + + MII_RMII_SEL_MUX + MII_RMII select muxing + 23 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI3_MUX + SPI3 muxing + 28 + 1 + read-write + + + TMR2ITR1_MUX + TMR2 internal trigger 1 + muxing + 29 + 1 + read-write + + + PTP_PPS_MUX + PTP_PPS muxing + 30 + 1 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + (IOMUX_REMAP2) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR9_MUX + TMR9 muxing + 5 + 1 + + + XMC_NADV_MUX + NADV connect/disconnect + 10 + 1 + + + SPI4_MUX + SPI4 muxing + 17 + 1 + + + I2C3_MUX + I2C3 muxing + 18 + 1 + + + SDIO2_MUX + SDIO2 muxing + 19 + 2 + + + EXT_SPIM_EN_MUX + SPIM enable muxing + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + (IOMUX_REMAP3) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + (IOMUX_REMAP4) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 2 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 + muxing + 6 + 2 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR4_GMUX + TMR4 muxing + 12 + 4 + + + TMR5CH4_GMUX + TMR5 channel4 internal + muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + (IOMUX_REMAP5) + 0x28 + 0x20 + read-write + 0x00000000 + + + USART5_GMUX + USART5 muxing + 0 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C3_GMUX + I2C3 muxing + 12 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI3_GMUX + SPI3 muxing + 24 + 4 + + + SPI4_GMUX + SPI4 muxing + 28 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + (IOMUX_REMAP6) + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO2_GMUX + SDIO2 muxing + 12 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART2_GMUX + USART2 muxing + 20 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + (IOMUX_REMAP7) + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + XMC_GMUX + XMC muxing + 24 + 3 + + + XMC_NADV_GMUX + XMC_NADV muxing + 27 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + (IOMUX_REMAP8) + 0x34 + 0x20 + read-write + 0x00000000 + + + EMAC_GMUX + Ethernet MAC muxing + 16 + 2 + + + MII_RMII_SEL_GMUX + MII_RMII select muxing + 18 + 1 + + + PTP_PPS_GMUX + PTP_PPS muxing + 19 + 1 + + + USART6_GMUX + USART6 muxing + 20 + 4 + + + UART7_GMUX + UART7 muxing + 24 + 4 + + + UART8_GMUX + UART8 muxing + 28 + 4 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 80 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x40023400 + + SDIO2 + SDIO2 global interrupt + 60 + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + read-write + 0x00000000 + + + DT5 + BPR data5 + 0 + 16 + + + + + DT6 + DT6 + Battery powered domain data + register (BPR_DTx) + 0x14 + 0x20 + read-write + 0x00000000 + + + DT6 + BPR data6 + 0 + 16 + + + + + DT7 + DT7 + Battery powered domain data + register (BPR_DTx) + 0x18 + 0x20 + read-write + 0x00000000 + + + DT7 + BPR data7 + 0 + 16 + + + + + DT8 + DT8 + Battery powered domain data + register (BPR_DTx) + 0x1C + 0x20 + read-write + 0x00000000 + + + DT8 + BPR data8 + 0 + 16 + + + + + DT9 + DT9 + Battery powered domain data + register (BPR_DTx) + 0x20 + 0x20 + read-write + 0x00000000 + + + DT9 + BPR data9 + 0 + 16 + + + + + DT10 + DT10 + Battery powered domain data + register (BPR_DTx) + 0x24 + 0x20 + read-write + 0x00000000 + + + DT10 + BPR data10 + 0 + 16 + + + + + DT11 + DT11 + Battery powered domain data + register (BPR_DTx) + 0x3C + 0x20 + read-write + 0x00000000 + + + DT11 + BPR data11 + 0 + 16 + + + + + DT12 + DT12 + Battery powered domain data + register (BPR_DTx) + 0x40 + 0x20 + read-write + 0x00000000 + + + DT12 + BPR data12 + 0 + 16 + + + + + DT13 + DT13 + Battery powered domain data + register (BPR_DTx) + 0x44 + 0x20 + read-write + 0x00000000 + + + DT13 + BPR data13 + 0 + 16 + + + + + DT14 + DT14 + Battery powered domain data + register (BPR_DTx) + 0x48 + 0x20 + read-write + 0x00000000 + + + DT14 + BPR data14 + 0 + 16 + + + + + DT15 + DT15 + Battery powered domain data + register (BPR_DTx) + 0x4C + 0x20 + read-write + 0x00000000 + + + DT15 + BPR data15 + 0 + 16 + + + + + DT16 + DT16 + Battery powered domain data + register (BPR_DTx) + 0x50 + 0x20 + read-write + 0x00000000 + + + DT16 + BPR data16 + 0 + 16 + + + + + DT17 + DT17 + Battery powered domain data + register (BPR_DTx) + 0x54 + 0x20 + read-write + 0x00000000 + + + DT17 + BPR data17 + 0 + 16 + + + + + DT18 + DT18 + Battery powered domain data + register (BPR_DTx) + 0x58 + 0x20 + read-write + 0x00000000 + + + DT18 + BPR data18 + 0 + 16 + + + + + DT19 + DT19 + Battery powered domain data + register (BPR_DTx) + 0x5C + 0x20 + read-write + 0x00000000 + + + DT19 + BPR data19 + 0 + 16 + + + + + DT20 + DT20 + Battery powered domain data + register (BPR_DTx) + 0x60 + 0x20 + read-write + 0x00000000 + + + DT20 + BPR data20 + 0 + 16 + + + + + DT21 + DT21 + Battery powered domain data + register (BPR_DTx) + 0x64 + 0x20 + read-write + 0x00000000 + + + DT21 + BPR data21 + 0 + 16 + + + + + DT22 + DT22 + Battery powered domain data + register (BPR_DTx) + 0x68 + 0x20 + read-write + 0x00000000 + + + DT22 + BPR data22 + 0 + 16 + + + + + DT23 + DT23 + Battery powered domain data + register (BPR_DTx) + 0x6C + 0x20 + read-write + 0x00000000 + + + DT23 + BPR data23 + 0 + 16 + + + + + DT24 + DT24 + Battery powered domain data + register (BPR_DTx) + 0x70 + 0x20 + read-write + 0x00000000 + + + DT24 + BPR data24 + 0 + 16 + + + + + DT25 + DT25 + Battery powered domain data + register (BPR_DTx) + 0x74 + 0x20 + read-write + 0x00000000 + + + DT25 + BPR data25 + 0 + 16 + + + + + DT26 + DT26 + Battery powered domain data + register (BPR_DTx) + 0x78 + 0x20 + read-write + 0x00000000 + + + DT26 + BPR data26 + 0 + 16 + + + + + DT27 + DT27 + Battery powered domain data + register (BPR_DTx) + 0x7C + 0x20 + read-write + 0x00000000 + + + DT27 + BPR data27 + 0 + 16 + + + + + DT28 + DT28 + Battery powered domain data + register (BPR_DTx) + 0x80 + 0x20 + read-write + 0x00000000 + + + DT28 + BPR data28 + 0 + 16 + + + + + DT29 + DT29 + Battery powered domain data + register (BPR_DTx) + 0x84 + 0x20 + read-write + 0x00000000 + + + DT29 + BPR data29 + 0 + 16 + + + + + DT30 + DT30 + Battery powered domain data + register (BPR_DTx) + 0x88 + 0x20 + read-write + 0x00000000 + + + DT30 + BPR data30 + 0 + 16 + + + + + DT31 + DT31 + Battery powered domain data + register (BPR_DTx) + 0x8C + 0x20 + read-write + 0x00000000 + + + DT31 + BPR data31 + 0 + 16 + + + + + DT32 + DT32 + Battery powered domain data + register (BPR_DTx) + 0x90 + 0x20 + read-write + 0x00000000 + + + DT32 + BPR data32 + 0 + 16 + + + + + DT33 + DT33 + Battery powered domain data + register (BPR_DTx) + 0x94 + 0x20 + read-write + 0x00000000 + + + DT33 + BPR data33 + 0 + 16 + + + + + DT34 + DT34 + Battery powered domain data + register (BPR_DTx) + 0x98 + 0x20 + read-write + 0x00000000 + + + DT34 + BPR data34 + 0 + 16 + + + + + DT35 + DT35 + Battery powered domain data + register (BPR_DTx) + 0x9C + 0x20 + read-write + 0x00000000 + + + DT35 + BPR data35 + 0 + 16 + + + + + DT36 + DT36 + Battery powered domain data + register (BPR_DTx) + 0xA0 + 0x20 + read-write + 0x00000000 + + + DT36 + BPR data36 + 0 + 16 + + + + + DT37 + DT37 + Battery powered domain data + register (BPR_DTx) + 0xA4 + 0x20 + read-write + 0x00000000 + + + DT37 + BPR data37 + 0 + 16 + + + + + DT38 + DT38 + Battery powered domain data + register (BPR_DTx) + 0xA8 + 0x20 + read-write + 0x00000000 + + + DT38 + BPR data38 + 0 + 16 + + + + + DT39 + DT39 + Battery powered domain data + register (BPR_DTx) + 0xAC + 0x20 + read-write + 0x00000000 + + + DT39 + BPR data39 + 0 + 16 + + + + + DT40 + DT40 + Battery powered domain data + register (BPR_DTx) + 0xB0 + 0x20 + read-write + 0x00000000 + + + DT40 + BPR data40 + 0 + 16 + + + + + DT41 + DT41 + Battery powered domain data + register (BPR_DTx) + 0xB4 + 0x20 + read-write + 0x00000000 + + + DT41 + BPR data41 + 0 + 16 + + + + + DT42 + DT42 + Battery powered domain data + register (BPR_DTx) + 0xB8 + 0x20 + read-write + 0x00000000 + + + DT42 + BPR data42 + 0 + 16 + + + + + RTCCAL + RTCCAL + RTC clock calibration register + (BPR_RTCCAL) + 0x28 + 0x20 + read-write + 0x00000000 + + + CALVAL + Calibration value + 0 + 7 + + + CALOUT + Calibration Clock Output + 7 + 1 + + + OUTEN + Output enable + 8 + 1 + + + OUTSEL + Output selection + 9 + 1 + + + CCOS + Calibration clock output selection + 10 + 1 + + + OUTM + Output mode + 11 + 1 + + + + + CTRL + CTRL + BPR control register + (BPR_CTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TPEN + Tamper pin enable + 0 + 1 + + + TPP + TAMPER pin polarity + 1 + 1 + + + + + CTRLSTS + CTRLSTS + BPR control/status register + (BPR_CTRLSTS) + 0x30 + 0x20 + 0x00000000 + + + TPEFCLR + Tamper event flag clear + 0 + 1 + write-only + + + TPIFCLR + Tamper interrupt flag clear + 1 + 1 + write-only + + + TPIEN + Tamper pin interrupt enable + 2 + 1 + read-write + + + TPEF + Tamper event flag + 8 + 1 + read-write + + + TPIF + Tamper interrupt flag + 9 + 1 + read-write + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + read-write + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-write + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40012C00 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + TMR1_CH + TMR1 channel interrupt + 27 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode + selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C4IOS + Channel 4 idle output state + 14 + 1 + + + C3CIOS + Channel 3 complementary idle output state + 13 + 1 + + + C3IOS + Channel 3 idle output state + 12 + 1 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + C1INSEL + C1IN selection + 7 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + ESP + External signal polarity + 15 + 1 + + + ECMBEN + External clock mode B enable + 14 + 1 + + + ESDIV + External signal divider + 12 + 2 + + + ESF + External signal filter + 8 + 4 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C4DEN + Channel 4 DMA request + enable + 12 + 1 + + + C3DEN + Channel 3 DMA request + enable + 11 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C4IEN + Channel 4 interrupt + enable + 4 + 1 + + + C3IEN + Channel 3 interrupt + enable + 3 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C4RF + Channel 4 recapture flag + 12 + 1 + + + C3RF + Channel 3 recapture flag + 11 + 1 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C3IF + Channel 3 interrupt flag + 3 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM2_OUTPUT + CM2_OUTPUT + Channel output mode register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + C4OSEN + Channel 4 output switch enable + 15 + 1 + + + C4OCTRL + Channel 4 output control + 12 + 3 + + + C4OBEN + Channel 4 output buffer enable + 11 + 1 + + + C4OIEN + Channel 4 output immediately enable + 10 + 1 + + + C4C + Channel 4 configure + 8 + 2 + + + C3OSEN + Channel 3 output switch enable + 7 + 1 + + + C3OCTRL + Channel 3 output control + 4 + 3 + + + C3OBEN + Channel 3 output buffer enable + 3 + 1 + + + C3OIEN + Channel 3 output immediately enable + 2 + 1 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CM2_INPUT + CM2_INPUT + Channel input mode register 2 + CM2_OUTPUT + 0x1C + 0x20 + read-write + 0x00000000 + + + C4DF + Channel 4 digital filter + 12 + 4 + + + C4IDIV + Channel 4 input divider + 10 + 2 + + + C4C + Channel 4 configure + 8 + 2 + + + C3DF + Channel 3 digital filter + 4 + 4 + + + C3IDIV + Channel 3 input divider + 2 + 2 + + + C3C + Channel 3 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C4P + Channel 4 Polarity + 13 + 1 + + + C4EN + Channel 4 enable + 12 + 1 + + + C3CP + Channel 3 complementary polarity + 11 + 1 + + + C3CEN + Channel 3 complementary enable + 10 + 1 + + + C3P + Channel 3 Polarity + 9 + 1 + + + C3EN + Channel 3 enable + 8 + 1 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + C3DT + C3DT + Channel 3 data register + 0x3C + 0x20 + read-write + 0x00000000 + + + C3DT + Channel 3 data register + 0 + 16 + + + + + C4DT + C4DT + Channel 4 data register + 0x40 + 0x20 + read-write + 0x00000000 + + + C4DT + Channel 4 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data 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complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40015400 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + I2C1 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RESET + I2C peripheral reset + 15 + 1 + + + SMBALERT + SMBus alert pin set + 13 + 1 + + + PECTEN + Request PEC transmission enable + 12 + 1 + + + MACKCTRL + Master receiving mode acknowledge control + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + GENSTOP + Stop generation + 9 + 1 + + + GENSTART + Start generation + 8 + 1 + + + STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40015C00 + + I2C3_EVT + I2C3 event interrupt + 61 + + + I2C3_ERR + I2C3 error interrupt + 62 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40004000 + + SPI4 + SPI4 global interrupt + 63 + + + + I2S2_EXT + 0x40016C00 + + + I2S3_EXT + 0x40017000 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40016000 + + USART6 + USART6 global interrupt + 76 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC3 + Analog to digital converter + ADC + 0x40013C00 + + 0x0 + 0x400 + registers + + + ADC3 + ADC3 global interrupt + 47 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB1 + F4FB1 + Filter bank 4 filtrate bit register 1 + 0x260 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F4FB2 + F4FB2 + Filter bank 4 filtrate bit register 2 + 0x264 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F5FB1 + F5FB1 + Filter bank 5 filtrate bit register 1 + 0x268 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F5FB2 + F5FB2 + Filter bank 5 filtrate bit register 2 + 0x26C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data 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data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 68 + + + CAN2_RX0 + CAN2 RX0 interrupt + 69 + + + CAN2_RX1 + CAN2 RX1 interrupt + 70 + + + CAN2_SE + CAN2 SE interrupt + 71 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 17 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 19 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 20 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 21 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 25 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 26 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 27 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 31 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40016400 + + UART7 + UART7 global interrupt + 77 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40016800 + + UART8 + UART8 global interrupt + 78 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + UNLOCK3 + UNLOCK3 + Unlock 3 register + 0x84 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + SELECT + SELECT + Select register + 0x88 + 0x20 + write-only + 0x00000000 + + + SELECT + spim type selection + 0 + 32 + + + + + STS3 + STS3 + Status 3 register + 0x8C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL3 + CTRL3 + Control 3 register + 0x90 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + CHPERS + Chip erase + 2 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR3 + ADDR3 + Address 3 register + 0x94 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + DA + DA + Spim decryption address + 0x98 + 0x20 + write-only + 0x00000000 + + + FDA + Flash decryption address + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + read-only + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + read-only + + + SLIB_ES + sLib end sector + 22 + 10 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting,valid input: 0~511 + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting,valid input: 0~511, 0 means no data area + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting,valid input: 0~511 + 22 + 10 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + PUO + DP pullup off + 1 + 1 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 79 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h new file mode 100644 index 000000000..55d9d05dc --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.h @@ -0,0 +1,61 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk new file mode 100644 index 000000000..58b3fdb11 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld + +CFLAGS += \ + -DAT32F403ACGU7 diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c new file mode 100644 index 000000000..23798526f --- /dev/null +++ b/hw/bsp/at32f403a_407/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f403a_407_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk new file mode 100644 index 000000000..4a1c3949c --- /dev/null +++ b/hw/bsp/at32f403a_407/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 +DEPS_SUBMODULES += $(AT32F403A_407_SDK) + +# AT32 SDK path +AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F403A_407 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_gpio.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_misc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_usart.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_acc.c \ + $(AT32F403A_407_SDK_SRC)/drivers/src/at32f403a_407_crm.c \ + $(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support/system_at32f403a_407.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F403A_407_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f403a_407.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s new file mode 100644 index 000000000..8bb76a062 --- /dev/null +++ b/hw/bsp/at32f403a_407/startup_at32f403a_407.s @@ -0,0 +1,478 @@ +/** + ****************************************************************************** + * @file startup_at32f403a_407.s + * @brief at32f403a_407xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 & I2S2EXT */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word ADC3_IRQHandler /* ADC3 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 & I2S3EXT */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + .word USART6_IRQHandler /* USART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak ADC3_IRQHandler + .thumb_set ADC3_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..599d22ffc --- /dev/null +++ b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f413.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + _spim_init_base = LOADADDR(.spim); + _spim_init_length = SIZEOF(.spim); + + .spim : + { + . = ALIGN(4); + _spim_start = .; /* create a global symbol at spim start */ + *(.spim) /* .spim sections */ + *(.spim*) /* .spim* sections */ + . = ALIGN(4); + _spim_end = .; /* define a global symbols at end of spim */ + } >SPIM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd new file mode 100644 index 000000000..a4a95208e --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd @@ -0,0 +1,23368 @@ + + + + + + + + Keil + ArteryTek + AT32F413xx_v2 + AT32F413 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + PLLRANGE + PLL clock output frequency up 72MHz or not + 31 + 1 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O reset + 0 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + ADC2RST + ADC2 reset + 10 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TMR8RST + Timer8 reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + USBRST + USB reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + BPRRST + Battery powered domain register reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + CAN2RST + CAN2 reset + 31 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + ADC2EN + ADC2 clock enable + 10 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TMR8EN + Timer8 clock enable + 13 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + WWDTEN + Window watchdog timer clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBEN + USB clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + BPREN + Barrery powered domain register clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + CAN2EN + CAN2 clock enable + 31 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register 1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + USBBUFS + USB buffer size selection + 24 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register 2 + 0x50 + 0x20 + 0x00000000 + + + CLK_TO_TMR + Clock output internal connect to timer10 + 16 + 1 + read-write + + + + + MISC3 + MISC3 + Miscellaneous register 3 + 0x54 + 0x20 + 0x00000000 + + + AUTO_STEP_EN + Auto step en + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + INTMAP + INTMAP + Interrupt remap register + 0x5C + 0x20 + 0x00000000 + + + USB_INT_MAP + USBDEV interrupt remap + 0 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted + conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary + conversion muxing + 18 + 1 + read-write + + + ADC2_ETP_MUX + ADC2 external trigger preempted + conversion muxing + 19 + 1 + read-write + + + ADC2_ETO_MUX + ADC2 external trigger ordinary + conversion muxing + 20 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_EN_MUX + SPIM enable + 21 + 1 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR2ITR1_GMUX + TMR2 internal trigger 1 muxing + 7 + 1 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR5CH4_GMUX + TMR5 channel4 internal muxing + 19 + 1 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + CAN2_GMUX + CAN2 muxing + 4 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + EXT_SPIM_GMUX + SPIM muxing + 0 + 3 + + + EXT_SPIM_GEN + SPIM enable + 3 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted + conversion muxing + 4 + 1 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary + conversion muxing + 5 + 1 + + + ADC2_ETP_GMUX + ADC2 external trigger preempted + conversion muxing + 8 + 1 + + + ADC2_ETO_GMUX + ADC2 external trigger ordinary + conversion muxing + 9 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + PD01_GMUX + PortD0/PortD1 mappingon + OSC_IN/OSC_OUT + 20 + 1 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + RTCALARM + RTC Alarm interrupt connect to EXINT line17 + 41 + + + USBFSWakeUp + USB Device FS Wakeup interrupt connect to EXINT line18 + 42 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global interrupt + 75 + + + + SDIO + Secure digital input/output interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC global interrupt + 3 + + + + CTRLH + CTRLH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + TAIEN + Time alarm interrupt enable + 1 + 1 + + + TSIEN + Time second interrupt enable + 2 + 1 + + + + + CTRLL + CTRLL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + TSF + Time second flag + 0 + 1 + read-write + + + TAF + Time alarm flag + 1 + 1 + read-write + + + OVFF + Overflow Flag + 2 + 1 + read-write + + + UPDF + RTC update finish + 3 + 1 + read-write + + + CFGEN + RTC configuration enable + 4 + 1 + read-write + + + CFGF + RTC configuration finish + 5 + 1 + read-only + + + + + DIVH + DIVH + RTC Divider Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + DIV + RTC divider high + 0 + 4 + + + + + DIVL + DIVL + RTC Divider Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + DIV + RTC divider low + 0 + 16 + + + + + DIVCNTH + DIVCNTH + RTC Divider Register High + 0x10 + 0x20 + read-write + 0x00000000 + + + DIVCNT + RTC divider register high + 0 + 4 + + + + + DIVCNTL + DIVCNTL + RTC Divider Register Low + 0x14 + 0x20 + read-write + 0x8000 + + + DIVCNT + RTC divider register low + 0 + 16 + + + + + CNTH + CNTH + RTC Counter Register High + 0x18 + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register high + 0 + 16 + + + + + CNTL + CNTL + RTC Counter Register Low + 0x1C + 0x20 + read-write + 0x00000000 + + + CNT + RTC counter register low + 0 + 16 + + + + + TAH + TAH + RTC Alarm Register High + 0x20 + 0x20 + write-only + 0xFFFF + + + TA + Time alarm register high + 0 + 16 + + + + + TAL + TAL + Time alarm register low + 0x24 + 0x20 + write-only + 0xFFFF + + + TA + RTC alarm register low + 0 + 16 + + + + + + + BPR + Battery powered register + BPR + 0x40006C04 + + 0x0 + 0x3FC + registers + + + + DT1 + DT1 + Battery powered domain data + register (BPR_DTx) + 0x0 + 0x20 + read-write + 0x00000000 + + + DT1 + BPR data1 + 0 + 16 + + + + + DT2 + DT2 + Battery powered domain data + register (BPR_DTx) + 0x4 + 0x20 + read-write + 0x00000000 + + + DT2 + BPR data2 + 0 + 16 + + + + + DT3 + DT3 + Battery powered domain data + register (BPR_DTx) + 0x8 + 0x20 + read-write + 0x00000000 + + + DT3 + BPR data3 + 0 + 16 + + + + + DT4 + DT4 + Battery powered domain data + register (BPR_DTx) + 0xC + 0x20 + read-write + 0x00000000 + + + DT4 + BPR data4 + 0 + 16 + + + + + DT5 + DT5 + Battery powered domain data + register (BPR_DTx) + 0x10 + 0x20 + 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+ DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + MSSEL + Master slave mode select + 16 + 4 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ADC2ODT + ADC2 conversion data of ordinary channel + 16 + 16 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + ADC2 + Analog to digital converter + ADC + 0x40012800 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + USBFS_H_CAN1_TX + CAN1 TX interrupt + 19 + + + USBFS_L_CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit 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SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USBFS + Universal serial bus full-speed device + interface + USBFS + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EPT0 + EPT0 + endpoint 0 register + 0x0 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT1 + EPT1 + endpoint 1 register + 0x4 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT2 + EPT2 + endpoint 2 register + 0x8 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT3 + EPT3 + endpoint 3 register + 0xC + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT4 + EPT4 + endpoint 4 register + 0x10 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT5 + EPT5 + endpoint 5 register + 0x14 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT6 + EPT6 + endpoint 6 register + 0x18 + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + EPT7 + EPT7 + endpoint 7 register + 0x1C + 0x20 + read-write + 0x00000000 + + + EPTADDR + Endpoint address + 0 + 4 + + + TXSTS + Tx status + 4 + 2 + + + TXDTS + Tx data toggle synchronization + 6 + 1 + + + TXTC + Tx transaction completed + 7 + 1 + + + EXF + Endpoint extend function + 8 + 1 + + + TRANS_TYPE + Transfer type + 9 + 2 + + + SETUPTC + Setup transaction + completed + 11 + 1 + + + RXSTS + Rx Status + 12 + 2 + + + RXDTS + Rx data toggle synchronization + 14 + 1 + + + RXTC + Rx transaction completed + 15 + 1 + + + + + CTRL + CTRL + control register + 0x40 + 0x20 + read-write + 0x00000003 + + + CSRST + Core soft reset + 0 + 1 + + + DISUSB + Disable usb phy + 1 + 1 + + + LPM + Low power mode + 2 + 1 + + + SSP + Soft suspend config + 3 + 1 + + + GRESUME + Generate resume request + 4 + 1 + + + LSOFIEN + Lost start of frame interrupt enable + 8 + 1 + + + SOFIEN + Start of frame interrupt + enable + 9 + 1 + + + RSTIEN + Bus reset interrupt enable + 10 + 1 + + + SPIEN + Bus suspend mode interrupt + enable + 11 + 1 + + + WKIEN + Wakeup/Remote wakeup interrupt enable + 12 + 1 + + + BEIEN + Bus error interrupt enable + 13 + 1 + + + UCFORIEN + USB Core fifo overrun + interrupt enable + 14 + 1 + + + TCIEN + transmission completed interrupt + enable + 15 + 1 + + + + + INTSTS + INTSTS + interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EPT_NUM + Endpoint number + 0 + 4 + + + INOUT + In/Out transaction + 4 + 1 + + + LSOF + Lost start of frame + 8 + 1 + + + SOF + start of frame + 9 + 1 + + + RST + Bus reset + 10 + 1 + + + SP + Bus suspend + 11 + 1 + + + WK + Wakeup + 12 + 1 + + + BE + Bus error + 13 + 1 + + + UCFOR + USB core fifo overrun memory + 14 + 1 + + + TC + transaction completed + 15 + 1 + + + + + SOFRNUM + SOFRNUM + frame number register + 0x48 + 0x20 + read-write + 0x0000 + + + SOFNUM + Start of frame number + 0 + 11 + + + LSOFNUM + Lost start of frame number + 11 + 2 + + + CLCK + Connect locked + 13 + 1 + + + DMSTS + DM status + 14 + 1 + + + DPSTS + DP status + 15 + 1 + + + + + DEVADDR + DEVADDR + device address + 0x4C + 0x20 + read-write + 0x0000 + + + ADDR + Host assign device address + 0 + 7 + + + CEN + USB core enable + 7 + 1 + + + + + BUFTBL + BUFTBL + Buffer table address + 0x50 + 0x20 + read-write + 0x0000 + + + BTADDR + Endpoint buffer table start address + 3 + 13 + + + + + CFG + CFG + CFG control register + 0x60 + 0x20 + read-write + 0x0000 + + + SOFOUTEN + SOF output enable + 0 + 1 + + + + + + + diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h new file mode 100644 index 000000000..f0bf0e4ae --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.h @@ -0,0 +1,62 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +static inline void board_vbus_sense_init(void) +{ + +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.mk b/hw/bsp/at32f413/boards/AT_START_F413/board.mk new file mode 100644 index 000000000..28351265d --- /dev/null +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F413xC_FLASH.ld + +CFLAGS += \ + -DAT32F413RCT7 diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c new file mode 100644 index 000000000..a38fe450e --- /dev/null +++ b/hw/bsp/at32f413/family.c @@ -0,0 +1,286 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f413_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void uart_print_init(uint32_t baudrate); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USBFS_H_CAN1_TX_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_L_CAN1_RX0_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPH_IRQHandler(void) { + tud_int_handler(0); +} +void USBFS_MAPL_IRQHandler(void) { + tud_int_handler(0); +} +void USBFSWakeUp_IRQHandler(void) { + tud_int_handler(0); +} + +void board_init(void) +{ + system_clock_config(); + + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HICK); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + + /* enable usb clock */ + crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USBFS_H_CAN1_TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFS_L_CAN1_RX0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + NVIC_SetPriority(USBFSWakeUp_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); + + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + default: + break; + } + } +} + +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void board_led_write(bool state) { + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk new file mode 100644 index 000000000..c56d1064c --- /dev/null +++ b/hw/bsp/at32f413/family.mk @@ -0,0 +1,42 @@ +# Submodules +AT32F413_SDK = hw/mcu/artery/at32f413 +DEPS_SUBMODULES += $(AT32F413_SDK) + +# AT32 SDK path +AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F413 + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_gpio.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_misc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_usart.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_acc.c \ + $(AT32F413_SDK_SRC)/drivers/src/at32f413_crm.c \ + $(AT32F413_SDK_SRC)/cmsis/cm4/device_support/system_at32f413.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F413_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F413_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f413.s + +# For freeRTOS port source +FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s new file mode 100644 index 000000000..4fc1f2a86 --- /dev/null +++ b/hw/bsp/at32f413/startup_at32f413.s @@ -0,0 +1,431 @@ +/** + ****************************************************************************** + * @file startup_at32f413.s + * @brief at32f413xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMPER_IRQHandler /* Tamper */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1 & ADC2 */ + .word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */ + .word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TMR8_BRK_IRQHandler /* TMR8 Brake */ + .word TMR8_OVF_IRQHandler /* TMR8 Overflow */ + .word TMR8_TRG_HALL_IRQHandler /* TMR8 Trigger and hall */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word ACC_IRQHandler /* ACC */ + .word USBFS_MAPH_IRQHandler /* USB Map HP */ + .word USBFS_MAPL_IRQHandler /* USB Map LP */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_2_IRQHandler + .thumb_set ADC1_2_IRQHandler,Default_Handler + + .weak USBFS_H_CAN1_TX_IRQHandler + .thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler + + .weak USBFS_L_CAN1_RX0_IRQHandler + .thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak RTCAlarm_IRQHandler + .thumb_set RTCAlarm_IRQHandler,Default_Handler + + .weak USBFSWakeUp_IRQHandler + .thumb_set USBFSWakeUp_IRQHandler,Default_Handler + + .weak TMR8_BRK_IRQHandler + .thumb_set TMR8_BRK_IRQHandler,Default_Handler + + .weak TMR8_OVF_IRQHandler + .thumb_set TMR8_OVF_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_IRQHandler + .thumb_set TMR8_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak USBFS_MAPH_IRQHandler + .thumb_set USBFS_MAPH_IRQHandler,Default_Handler + + .weak USBFS_MAPL_IRQHandler + .thumb_set USBFS_MAPL_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..73889ebf9 --- /dev/null +++ b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f415.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd new file mode 100644 index 000000000..cd22346c7 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd @@ -0,0 +1,27108 @@ + + + + + + + + Keil + ArteryTek + AT32F415xx_v2 + AT32F415 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 150MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLST) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN + Standby wake-up pin enable + 8 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + IOMUXRST + MUX function I/O + reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + GPIOARST + IO port A reset + 2 + 1 + + + GPIOBRST + IO port B reset + 3 + 1 + + + GPIOCRST + IO port C reset + 4 + 1 + + + GPIODRST + IO port D reset + 5 + 1 + + + GPIOFRST + IO port F reset + 7 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + Timer1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR9RST + Timer9 reset + 19 + 1 + + + TMR10RST + Timer10 reset + 20 + 1 + + + TMR11RST + Timer11 reset + 21 + 1 + + + ACCRST + ACC reset + 22 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR4RST + Timer 4 reset + 2 + 1 + + + TMR5RST + Timer 5 reset + 3 + 1 + + + CMPRST + Comparator reset + 9 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + UART4RST + UART 4 reset + 19 + 1 + + + UART5RST + UART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + SDIO1EN + SDIO1 clock enable + 10 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + IOMUXEN + MUX function I/O clock + enable + 0 + 1 + + + GPIOAEN + I/O port A clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 3 + 1 + + + GPIOCEN + I/O port C clock enable + 4 + 1 + + + GPIODEN + I/O port D clock enable + 5 + 1 + + + GPIOFEN + I/O port F clock enable + 7 + 1 + + + ADC1EN + ADC1 clock + enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 19 + 1 + + + TMR10EN + Timer10 clock enable + 20 + 1 + + + TMR11EN + Timer11 clock enable + 21 + 1 + + + ACCEN + ACC clock enable + 22 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + CMPEN + Comparator clock enable + 9 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + read-write + + + + + PLL + PLL + PLL configuration register + (RCC_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + OTG_EXTCTRL + OTG_EXTCTRL + OTGFS external ctrl register1 + 0x44 + 0x20 + 0x00000000 + + + USBDIV_RST + USB divider reset + 30 + 1 + read-write + + + EP3_RMPEN + OTGFS end-point 3 remap enable + 31 + 1 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + HICK_TO_USB + HICK to usb clock + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose IO + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CFGLR + CFGLR + GPIO function configurate low register + 0x0 + 0x20 + read-write + 0x44444444 + + + IOMC0 + Port n.0 mode configurate bits + 0 + 2 + + + IOFC0 + Port n.0 function configurate + bits + 2 + 2 + + + IOMC1 + Port n.1 mode configurate bits + 4 + 2 + + + IOFC1 + Port n.1 function configurate + bits + 6 + 2 + + + IOMC2 + Port n.2 mode configurate bits + 8 + 2 + + + IOFC2 + Port n.2 function configurate + bits + 10 + 2 + + + IOMC3 + Port n.3 mode configurate bits + 12 + 2 + + + IOFC3 + Port n.3 function configurate + bits + 14 + 2 + + + IOMC4 + Port n.4 mode configurate bits + 16 + 2 + + + IOFC4 + Port n.4 function configurate + bits + 18 + 2 + + + IOMC5 + Port n.5 mode configurate bits + 20 + 2 + + + IOFC5 + Port n.5 function configurate + bits + 22 + 2 + + + IOMC6 + Port n.6 mode configurate bits + 24 + 2 + + + IOFC6 + Port n.6 function configurate + bits + 26 + 2 + + + IOMC7 + Port n.7 mode configurate bits + 28 + 2 + + + IOFC7 + Port n.7 function configurate + bits + 30 + 2 + + + + + CFGHR + CFGHR + GPIO function configurate high register + 0x4 + 0x20 + read-write + 0x44444444 + + + IOMC8 + Port n.8 mode configurate bits + 0 + 2 + + + IOFC8 + Port n.8 function configurate + bits + 2 + 2 + + + IOMC9 + Port n.9 mode configurate bits + 4 + 2 + + + IOFC9 + Port n.9 function configurate + bits + 6 + 2 + + + IOMC10 + Port n.10 mode configurate bits + 8 + 2 + + + IOFC10 + Port n.10 function configurate + bits + 10 + 2 + + + IOMC11 + Port n.11 mode configurate bits + 12 + 2 + + + IOFC11 + Port n.11 function configurate + bits + 14 + 2 + + + IOMC12 + Port n.12 mode configurate bits + 16 + 2 + + + IOFC12 + Port n.12 function configurate + bits + 18 + 2 + + + IOMC13 + Port n.13 mode configurate bits + 20 + 2 + + + IOFC13 + Port n.13 function configurate + bits + 22 + 2 + + + IOMC14 + Port n.14 mode configurate bits + 24 + 2 + + + IOFC14 + Port n.14 function configurate + bits + 26 + 2 + + + IOMC15 + Port n.15 mode configurate bits + 28 + 2 + + + IOFC15 + Port n.15 function configurate + bits + 30 + 2 + + + + + IDT + IDT + Port input data register + 0x8 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + Port output data register + 0xC + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x10 + 0x20 + read-write + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + CLR + CLR + Port bit reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + WPR + WPR + Port write protect + register + 0x18 + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOF + 0x40011C00 + + + IOMUX + IO MUX function + IOMUX + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVTOUT + EVTOUT + Event output register + (IOMUX_EVTOUT) + 0x0 + 0x20 + read-write + 0x00000000 + + + SELPIN + Select pin + 0 + 4 + + + SELPORT + Select port + 4 + 3 + + + EVOEN + Event output enable + 7 + 1 + + + + + REMAP + REMAP + IO MUX remap register + 0x4 + 0x20 + 0x00000000 + + + SPI1_MUX0 + SPI1 muxing bit0 + 0 + 1 + read-write + + + I2C1_MUX + I2C1 muxing + 1 + 1 + read-write + + + USART1_MUX + USART1 muxing + 2 + 1 + read-write + + + USART3_MUX + USART3 muxing + 4 + 2 + read-write + + + TMR1_MUX + TMR1 muxing + 6 + 2 + read-write + + + TMR2_MUX + TMR2 muxing + 8 + 2 + read-write + + + TMR3_MUX + TMR3 muxing + 10 + 2 + read-write + + + CAN_MUX + CAN1 muxing + 13 + 2 + read-write + + + PD01_MUX + PD0/PD1 muxing on OSCIN/OSCOUT + 15 + 1 + read-write + + + TMR5CH4_MUX + TMR5 channel4 internal muxing + 16 + 1 + read-write + + + ADC1_ETP_MUX + ADC1 external trigger preempted conversion muxing + 17 + 1 + read-write + + + ADC1_ETO_MUX + ADC1 external trigger ordinary conversion muxing + 18 + 1 + read-write + + + SWJTAG_MUX + SWD JTAG muxing + 24 + 3 + read-write + + + SPI1_MUX1 + SPI1 muxing bit1 + 31 + 1 + read-write + + + + + EXINTC1 + EXINTC1 + External interrupt configuration register 1 + (IOMUX_EXINTC1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXINT0 + Configure EXINT0 source + 0 + 4 + + + EXINT1 + Configure EXINT1 source + 4 + 4 + + + EXINT2 + Configure EXINT2 source + 8 + 4 + + + EXINT3 + Configure EXINT3 source + 12 + 4 + + + + + EXINTC2 + EXINTC2 + External interrupt configuration register 2 + (IOMUX_EXINTC2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXINT4 + Configure EXINT4 source + 0 + 4 + + + EXINT5 + Configure EXINT5 source + 4 + 4 + + + EXINT6 + Configure EXINT6 source + 8 + 4 + + + EXINT7 + Configure EXINT7 source + 12 + 4 + + + + + EXINTC3 + EXINTC3 + External interrupt configuration register 3 + (IOMUX_EXINTC3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXINT8 + Configure EXINT8 source + 0 + 4 + + + EXINT9 + Configure EXINT9 source + 4 + 4 + + + EXINT10 + Configure EXINT10 source + 8 + 4 + + + EXINT11 + Configure EXINT11 source + 12 + 4 + + + + + EXINTC4 + EXINTC4 + External interrupt configuration register 4 + (IOMUX_EXINTC4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXINT12 + Configure EXINT12 source + 0 + 4 + + + EXINT13 + Configure EXINT13 source + 4 + 4 + + + EXINT14 + Configure EXINT14 source + 8 + 4 + + + EXINT15 + Configure EXINT15 source + 12 + 4 + + + + + REMAP2 + REMAP2 + IO MUX remap register 2 + 0x1C + 0x20 + write-only + 0x00000000 + + + CMP_MUX + CMP internal muxing + 26 + 2 + + + + + REMAP3 + REMAP3 + IO MUX remap register 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR11_GMUX + TMR11 muxing + 8 + 4 + + + TMR10_GMUX + TMR10 muxing + 4 + 4 + + + TMR9_GMUX + TMR9 muxing + 0 + 4 + + + + + REMAP4 + REMAP4 + IO MUX remap register 4 + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR5CH4_GMUX + TMR5CH4 muxing + 19 + 1 + + + TMR5_GMUX + TMR5 muxing + 16 + 3 + + + TMR3_GMUX + TMR3 muxing + 8 + 4 + + + TMR2_GMUX + TMR2 muxing + 4 + 3 + + + TMR1_GMUX + TMR1 muxing + 0 + 4 + + + + + REMAP5 + REMAP5 + IO MUX remap register 5 + 0x28 + 0x20 + read-write + 0x00000000 + + + SPI2_GMUX + SPI2 muxing + 20 + 4 + + + SPI1_GMUX + SPI1 muxing + 16 + 4 + + + I2C2_GMUX + I2C2 muxing + 8 + 4 + + + I2C1_GMUX + I2C1 muxing + 4 + 4 + + + + + REMAP6 + REMAP6 + IO MUX remap register 6 + 0x2C + 0x20 + read-write + 0x00000000 + + + UART4_GMUX + UART4 muxing + 28 + 4 + + + USART3_GMUX + USART3 muxing + 24 + 4 + + + USART1_GMUX + USART1 muxing + 16 + 4 + + + SDIO1_GMUX + SDIO1 muxing + 8 + 4 + + + CAN1_GMUX + CAN1 muxing + 0 + 4 + + + + + REMAP7 + REMAP7 + IO MUX remap register 7 + 0x30 + 0x20 + read-write + 0x00000000 + + + PD01_GMUX + PortD0/PortD1 muxing on OSC_IN/OSC_OUT + 20 + 1 + + + SWJTAG_GMUX + Serial wire JTAG muxing + 16 + 3 + + + ADC1_ETO_GMUX + ADC1 external trigger ordinary conversion muxing + 5 + 1 + + + ADC1_ETP_GMUX + ADC1 external trigger preempted conversion muxing + 4 + 1 + + + + + REMAP8 + REMAP8 + IO MUX remap register 8 + 0x34 + 0x20 + read-write + 0x00000000 + + + TMR3_CH1_CMP_GMUX + TMR3 CH1 CMP muxing + 6 + 2 + + + TMR2_CH4_CMP_GMUX + TMR2 CH4 CMP muxing + 4 + 2 + + + TMR1_CH1_CMP_GMUX + TMR1 CH1 CMP muxing + 2 + 2 + + + TMR1_BK1_CMP_GMUX + TMR1 BK1 CMP muxing + 0 + 2 + + + + + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVD interrupt + 1 + + + ERTC + ERTC interrupt + 3 + + + TAMPER + Tamper interrupt + 2 + + + ERTCAlarm + ERTCAlarm interrupt + 41 + + + CMP1 + CMP1 interrupt + 70 + + + CMP2 + CMP2 interrupt + 71 + + + EXTINT0 + EXTI Line0 interrupt + 6 + + + EXTINT1 + EXTI Line1 interrupt + 7 + + + EXTINT2 + EXTI Line2 interrupt + 8 + + + EXTINT3 + EXTI Line3 interrupt + 9 + + + EXTINT4 + EXTI Line4 interrupt + 10 + + + EXTINT9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTINT15_10 + EXTI Line[15:10] interrupts + 40 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + DMA2 + 0x40020400 + + DMA2_Channel1 + DMA2 Channel1 global interrupt + 56 + + + DMA2_Channel2 + DMA2 Channel2 global interrupt + 57 + + + DMA2_Channel3 + DMA2 Channel3 global interrupt + 58 + + + DMA2_Channel4_5 + DMA2 Channel4 and DMA2 Channel5 global + interrupt + 59 + + + DMA2_Channel6_7 + DMA2 Channel6 and DMA2 Channel7 global + interrupt + 75 + + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + POWER + POWER + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SDI clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKPSC + Clock divide factor + 0 + 8 + + + CLKEN + Clock enable bit + 8 + 1 + + + PWRSVG + Power saving configuration + bit + 9 + 1 + + + BYPS + Clock divider bypass enable + bit + 10 + 1 + + + BUSWIDTH + Wide bus mode enable bit + 11 + 2 + + + CLKEDG + SDIO_CK dephasing selection + bit + 13 + 1 + + + FLWCTRLEN + HW Flow Control enable + 14 + 1 + + + CLKPSC98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARG + ARG + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARG + Command argument + 0 + 32 + + + + + CMD + CMD + SDIO command register + (SDIO_CMD) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + WAITRESP + 6 + 2 + + + INTWT + WAITINT + 8 + 1 + + + PNDWT + WAITPEND + 9 + 1 + + + CMDMEN + CPSMEN + 10 + 1 + + + SDIOSUSP + SDIOSuspend + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS3 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS4 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = DATATIME: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + SDIOEN + SDIOEN + 11 + 1 + + + + + DTCNTR + DTCNTR + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STS) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + CCRCFAIL + 0 + 1 + + + DTFAIL + DCRCFAIL + 1 + 1 + + + CMDTIMEOUT + CTIMEOUT + 2 + 1 + + + DTTIMEOUT + DTIMEOUT + 3 + 1 + + + TXERRU + TXUNDERR + 4 + 1 + + + RXERRO + RXOVERR + 5 + 1 + + + CMDRSPCMPL + CMDREND + 6 + 1 + + + CMDCMPL + CMDSENT + 7 + 1 + + + DTCMPL + DATAEND + 8 + 1 + + + SBITERR + STBITERR + 9 + 1 + + + DTBLKCMPL + DBCKEND + 10 + 1 + + + DOCMD + CMDACT + 11 + 1 + + + DOTX + TXACT + 12 + 1 + + + DORX + RXACT + 13 + 1 + + + TXBUF_H + TXFIFOHE + 14 + 1 + + + RXBUF_H + RXFIFOHF + 15 + 1 + + + TXBUF_F + TXFIFOF + 16 + 1 + + + RXBUF_F + RXFIFOF + 17 + 1 + + + TXBUF_E + TXFIFOE + 18 + 1 + + + RXBUF_E + RXFIFOE + 19 + 1 + + + TXBUF + TXDAVL + 20 + 1 + + + RXBUF + RXDAVL + 21 + 1 + + + SDIOIF + SDIOIT + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILC + 0 + 1 + + + DTFAIL + DCRCFAILC + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTC + 2 + 1 + + + DTTIMEOUT + DTIMEOUTC + 3 + 1 + + + TXERRU + TXUNDERRC + 4 + 1 + + + RXERRU + RXOVERRC + 5 + 1 + + + CMDRSPCMPL + CMDRENDC + 6 + 1 + + + CMDCMPL + CMDSENTC + 7 + 1 + + + DTCMPL + DATAENDC + 8 + 1 + + + SBITERR + STBITERRC + 9 + 1 + + + DTBLKCMPL + DBCKENDC + 10 + 1 + + + SDIOIF + SDIOITC + 22 + 1 + + + + + INTEN + INTEN + SDIO interrupt enable register + (SDIO_INTEN) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAIL + CCRCFAILIE + 0 + 1 + + + DTFAIL + DCRCFAILIE + 1 + 1 + + + CMDTIMEOUT + CTIMEOUTIE + 2 + 1 + + + DTTIMEOUT + DTIMEOUTIE + 3 + 1 + + + TXERRU + TXUNDERRIE + 4 + 1 + + + RXERRU + RXOVERRIE + 5 + 1 + + + CMDRSPCMPL + CMDRENDIE + 6 + 1 + + + CMDCMPL + CMDSENTIE + 7 + 1 + + + DTCMPL + DATAENDIE + 8 + 1 + + + SBITERR + STBITERRIE + 9 + 1 + + + DTBLKCMPL + DBACKENDIE + 10 + 1 + + + DOCMD + CMDACTIE + 11 + 1 + + + DOTX + TXACTIE + 12 + 1 + + + DORX + RXACTIE + 13 + 1 + + + TXBUF_H + TXFIFOHEIE + 14 + 1 + + + RXBUF_H + RXFIFOHFIE + 15 + 1 + + + TXBUF_F + TXFIFOFIE + 16 + 1 + + + RXBUF_F + RXFIFOFIE + 17 + 1 + + + TXBUF_E + TXFIFOEIE + 18 + 1 + + + RXBUF_E + RXFIFOEIE + 19 + 1 + + + TXBUF + TXDAVLIE + 20 + 1 + + + RXBUF + RXDAVLIE + 21 + 1 + + + SDIOIF + SDIOITIE + 22 + 1 + + + + + BUFCNTR + BUFCNTR + Bits 23:0 = FIFOCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = FIFOData: Receive and transmit + FIFO data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + FIFOData + 0 + 32 + + + + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40015800 + + 0x0 + 0x400 + registers + + + ACC + ACC global interrupt + 72 + + + + STS + STS + Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + CALRDY + Internal high-speed clock calibration ready + 0 + 1 + + + RSLOST + Reference Signal Lost + 1 + 1 + + + + + CTRL1 + CTRL1 + Control register 1 + 0x4 + 0x20 + read-write + 0x00000100 + + + CALON + Internal high-speed clock calibration ready + 0 + 1 + + + ENTRIM + Enable trim + 1 + 1 + + + EIEN + RSLOST error interrupt enable + 4 + 1 + + + CALRDYIEN + CALRDY interrupt enable + 5 + 1 + + + STEP + STEP + 8 + 4 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x8 + 0x20 + read-only + 0x00002080 + + + ACC_HSICAL + Internal high-speed auto clock calibration + 0 + 8 + + + ACC_HSITRIM + Internal high-speed auto clock trimming + 8 + 6 + + + + + C1 + C1 + Compare 1 + 0xC + 0x20 + read-write + 0x00001F2C + + + C1 + Compare 1 + 0 + 16 + + + + + C2 + C2 + Compare 2 + 0x10 + 0x20 + read-write + 0x00001F40 + + + C2 + Compare 2 + 0 + 16 + + + + + C3 + C3 + Compare 3 + 0x14 + 0x20 + read-write + 0x00001F54 + + + C3 + Compare 3 + 0 + 16 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens 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1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain 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+ STRETCH + Clock stretching mode + 7 + 1 + + + GCAEN + General call address enable + 6 + 1 + + + PECEN + PEC calculation enable + 5 + 1 + + + ARPEN + SMBus address resolution protocol enable + 4 + 1 + + + SMBMODE + SMBus device mode + 3 + 1 + + + PERMODE + I2C peripheral mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + DMAEND + DMA transfer end indication + 12 + 1 + + + DMAEN + DMA transfer enable + 11 + 1 + + + DATAIEN + Data transmission interrupt enable + 10 + 1 + + + EVTIEN + Event interrupt enable + 9 + 1 + + + ERRIEN + Error interrupt enable + 8 + 1 + + + CLKFREQ + Input clock frequency + 0 + 8 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDR1MODE + Address mode + 15 + 1 + + + ADDR1 + Own address 1 + 0 + 10 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2EN + Own address 2 enable + 0 + 1 + + + + + DT + DT + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DT + data register + 0 + 8 + + + + + STS1 + STS1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + ALERTF + SMBus alert + 15 + 1 + read-write + + + TMOUT + Timeout error + 14 + 1 + read-write + + + PECERR + PEC receive error + 12 + 1 + read-write + + + OUF + Overflow or underflow + 11 + 1 + read-write + + + ACKFAIL + Acknowledge failure + 10 + 1 + read-write + + + ARLOST + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BUSERR + Bus error + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + (transmitters) + 7 + 1 + read-only + + + RDBF + Receive data buffer full + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADDRHF + address header match (Master + mode) + 3 + 1 + read-only + + + TDC + Transmit data complete + 2 + 1 + read-only + + + ADDR7F + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + STARTF + Start bit (Master mode) + 0 + 1 + read-only + + + + + STS2 + STS2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PECVAL + PEC value + 8 + 8 + + + ADDR2F + Received address 2 + 7 + 1 + + + HOSTADDRF + SMBus host address receiving + 6 + 1 + + + DEVADDRF + SMBus device address receiving + 5 + 1 + + + GCADDRF + General call address reception + 4 + 1 + + + DIRF + Transmission direction + 2 + 1 + + + BUSYF + Bus busy + 1 + 1 + + + TRMODE + Transmission mode + 0 + 1 + + + + + CLKCTRL + CLKCTRL + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + SPEEDMODE + Speed mode selection + 15 + 1 + + + DUTYMODE + Fast mode duty cycle + 14 + 1 + + + SPEED + I2C bus speed config + 0 + 12 + + + + + TMRISE + TMRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + I2C bus rise time + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UEN + USART enable + 13 + 1 + + + DBN + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + ADC1 + Analog to digital converter + ADC1 + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 25 + 1 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 24 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN1_RX1 + CAN1 RX1 interrupt + 21 + + + CAN1_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 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Comparator2 inverting selection + 20 + 3 + read-write + + + DCMPEN + Double comparator mode enable + 23 + 1 + read-write + + + CMP2TAG + Comparator2 output target + 24 + 3 + read-write + + + CMP2P + Comparator2 polarity + 27 + 1 + read-write + + + CMP2HYST + Comparator2 hysteresis + 28 + 2 + read-write + + + CMP2VALUE + Comparator2 output value + 30 + 1 + read-only + + + CMP2WP + Comparator2 write protect + 31 + 1 + read-write + + + + + CTRLSTS2 + CTRLSTS2 + CMP control/status register2 + 0x4 + 0x20 + 0x00000000 + + + COMP1NINVSEL + Comparator1 non-inverting input selection + 0 + 2 + read-write + + + COMP2NINVSEL + Comparator2 non-inverting input selection + 16 + 2 + read-write + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + DEBUG_IDCODE + DEBUG_IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + MCUDBG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 13 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 18 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 28 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 29 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 30 + 1 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + FAP_HL_DIS + FAP high level disable + 16 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + read-only + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_DAT_SS + Extension memory sLib data start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + read-only + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_DAT_SS + sLib data start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x00000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_DSS_SET + sLib data start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_DSS_SET + Extension memory sLib data start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG_GLOBAL + USB on the go full speed + USB_OTG + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS + USB On The Go FS global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + AVALIDSESEN + sense Avalid enable + 18 + 1 + + + BVALIDSESEN + sense Bvalid enable + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG_HOST + USB on the go full speed + USB_OTG + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG_DEVICE + USB on the go full speed + USB_OTG + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG_PWRCLK + USB on the go full speed + USB_OTG + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.h b/hw/bsp/at32f415/boards/AT_START_F415/board.h new file mode 100644 index 000000000..8b933f9e9 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.h @@ -0,0 +1,80 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f415/boards/AT_START_F415/board.mk b/hw/bsp/at32f415/boards/AT_START_F415/board.mk new file mode 100644 index 000000000..6c877ec71 --- /dev/null +++ b/hw/bsp/at32f415/boards/AT_START_F415/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F415xC_FLASH.ld + +CFLAGS += \ + -DAT32F415RCT7 diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c new file mode 100644 index 000000000..6c7600783 --- /dev/null +++ b/hw/bsp/at32f415/family.c @@ -0,0 +1,287 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f415_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + (void) clk_s; + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + default: + break; + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk new file mode 100644 index 000000000..d0cca67ab --- /dev/null +++ b/hw/bsp/at32f415/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F415_SDK = hw/mcu/artery/at32f415 +DEPS_SUBMODULES += $(AT32F415_SDK) + +# AT32 SDK path +AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F415 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_gpio.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_misc.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_usart.c \ + $(AT32F415_SDK_SRC)/drivers/src/at32f415_crm.c \ + $(AT32F415_SDK_SRC)/cmsis/cm4/device_support/system_at32f415.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F415_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F415_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f415.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s new file mode 100644 index 000000000..47a913e36 --- /dev/null +++ b/hw/bsp/at32f415/startup_at32f415.s @@ -0,0 +1,407 @@ +/** + ****************************************************************************** + * @file startup_at32f415.s + * @brief at32f415xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* ERTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word 0 /* Reserved */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */ + .word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CMP1_IRQHandler /* CMP1 */ + .word CMP2_IRQHandler /* CMP2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_5_IRQHandler + .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak CMP1_IRQHandler + .thumb_set CMP1_IRQHandler,Default_Handler + + .weak CMP2_IRQHandler + .thumb_set CMP2_IRQHandler,Default_Handler + + .weak DMA2_Channel6_7_IRQHandler + .thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..06afc3860 --- /dev/null +++ b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f423.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd new file mode 100644 index 000000000..4954c417f --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd @@ -0,0 +1,36050 @@ + + + + + + + + Keil + ArteryTek + AT32F423xx_v2 + AT32F423 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + SWPEN6 + Standby wake-up pin 6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin 7 enable + 14 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 2 + read-write + + + VREXLPEN + Voltage regulator extra low power mode enable + 4 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUTDIV1 + Clock output division1 + 27 + 3 + read-write + + + CLKOUT_SEL1 + Clock output selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART4RST + USART4 reset + 19 + 1 + + + USART5RST + USART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + USART7RST + USART7 reset + 30 + 1 + + + USART8RST + USART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + USART5EN + USART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + USART7EN + USART7 clock enable + 30 + 1 + + + USART8EN + USART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADCEN + ADC clock enable + 8 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAMLPEN + SRAM clock enable during sleep mode + 16 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + USART4LPEN + USART4 clock enable during sleep mode + 19 + 1 + + + USART5LPEN + USART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + USART7LPEN + USART7 clock enable during sleep mode + 30 + 1 + + + USART8LPEN + USART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADCLPEN + ADC clock enable during sleep mode + 8 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + PICLKS + PICLKS + Peripheral independent clock register + (CRM_PICLKS) + 0x68 + 0x20 + 0x00000000 + + + USART1SEL + USART1 clock select + 0 + 2 + read-write + + + USART2SEL + USART2 clock select + 2 + 2 + read-write + + + USART3SEL + USART3 clock select + 4 + 2 + read-write + + + I2C1SEL + I2C1 clock select + 12 + 2 + read-write + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + PLLCLK_TO_ADC + ADC clock source select + 15 + 1 + read-write + + + CLKOUT_SEL2 + Clock output select2 + 16 + 4 + read-write + + + CLKOUTDIV2 + Clock output division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + HICK_TO_SCLK_DIV + HICK as system clock frequency division + 16 + 3 + read-write + + + HEXT_TO_SCLK_DIV + HEXT as system clock frequency division + 19 + 3 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 2 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + TOGR + TOGR + GPIO bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + IOTB0 + Toggle bit 0 + 0 + 1 + + + IOTB1 + Toggle bit 1 + 1 + 1 + + + IOTB2 + Toggle bit 2 + 2 + 1 + + + IOTB3 + Toggle bit 3 + 3 + 1 + + + IOTB4 + Toggle bit 4 + 4 + 1 + + + IOTB5 + Toggle bit 5 + 5 + 1 + + + IOTB6 + Toggle bit 6 + 6 + 1 + + + IOTB7 + Toggle bit 7 + 7 + 1 + + + IOTB8 + Toggle bit 8 + 8 + 1 + + + IOTB9 + Toggle bit 9 + 9 + 1 + + + IOTB10 + Toggle bit 10 + 10 + 1 + + + IOTB11 + Toggle bit 11 + 11 + 1 + + + IOTB12 + Toggle bit 12 + 12 + 1 + + + IOTB13 + Toggle bit 13 + 13 + 1 + + + IOTB14 + Toggle bit 14 + 14 + 1 + + + IOTB15 + Toggle bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + I2C1_EVT + I2C1_EVT interrupt connect to EXINT line23 + 31 + + + USART1 + ERTC Global interrupt connect to EXINT line25 + 37 + + + USART2 + ERTC Global interrupt connect to EXINT line26 + 38 + + + USART3 + USART3 Global interrupt connect to EXINT line28 + 39 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + INTEN23 + Interrupt enable or disable on line 23 + 23 + 1 + + + INTEN25 + Interrupt enable or disable on line 25 + 25 + 1 + + + INTEN26 + Interrupt enable or disable on line 26 + 26 + 1 + + + INTEN28 + Interrupt enable or disable on line 28 + 28 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + EVTEN23 + Event enable or disable on line 23 + 23 + 1 + + + EVTEN25 + Event enable or disable on line 25 + 25 + 1 + + + EVTEN26 + Event enable or disable on line 26 + 26 + 1 + + + EVTEN28 + Event enable or disable on line 28 + 28 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + RP23 + Rising polarity configuration bit of line 23 + 23 + 1 + + + RP25 + Rising polarity configuration bit of line 25 + 25 + 1 + + + RP26 + Rising polarity configuration bit of line 26 + 26 + 1 + + + RP28 + Rising polarity configuration bit of line 28 + 28 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + FP23 + Falling polarity event configuration bit of line 23 + 23 + 1 + + + FP25 + Falling polarity event configuration bit of line 25 + 25 + 1 + + + FP26 + Falling polarity event configuration bit of line 26 + 26 + 1 + + + FP28 + Falling polarity event configuration bit of line 28 + 28 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + SWT23 + Software triggle on line 233 + 23 + 1 + + + SWT25 + Software triggle on line 255 + 25 + 1 + + + SWT26 + Software triggle on line 26 + 26 + 1 + + + SWT28 + Software triggle on line 28 + 28 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + LINE23 + Line 23 state bit + 23 + 1 + + + LINE25 + Line 25 state bit + 25 + 1 + + + LINE26 + Line 26 state bit + 26 + 1 + + + LINE28 + Line 28 state bit + 28 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40026000 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 11 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 12 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 13 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 14 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 15 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 16 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 17 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026400 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Window value + 0 + 12 + + + + + + + WWDT + Window watchdog + WWDT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDT + Window Watchdog interrupt + 0 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + CNT + Decrement counter + 0 + 7 + + + WWDTEN + Window watchdog enable + 7 + 1 + + + + + CFG + CFG + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WIN + Window value + 0 + 7 + + + DIV + Clock division value + 7 + 2 + + + RLDIEN + Reload counter interrupt + 9 + 1 + + + + + STS + STS + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + RLDF + Reload counter interrupt flag + 0 + 1 + + + + + + + TMR1 + Advanced timer + TIMER + 0x40010000 + + 0x0 + 0x400 + registers + + + TMR1_BRK_TMR9 + TMR1 brake interrupt and TMR9 global + interrupt + 24 + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts 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30 + + + + TMR9 + General purpose timer + TIMER + 0x40014000 + + 0x0 + 0x400 + registers + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C2CIOS + Channel 2 complementary idle output state + 11 + 1 + + + C2IOS + Channel 2 idle output state + 10 + 1 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + PTOS + Primary TMR output selection + 4 + 3 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + STCTRL + STCTRL + Subordinate TMR control register + 0x8 + 0x20 + read-write + 0x0000 + + + STS + Subordinate TMR synchronization + 7 + 1 + + + STIS + Subordinate TMR input selection + 4 + 3 + + + SMSEL + Subordinate TMR mode selection + 0 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDEN + Trigger DMA request enable + 14 + 1 + + + HALLDE + HALL DMA request enable + 13 + 1 + + + C2DEN + Channel 2 DMA request + enable + 10 + 1 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + TIEN + Trigger interrupt enable + 6 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C2IEN + Channel 2 interrupt + enable + 2 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C2RF + Channel 2 recapture flag + 10 + 1 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C2IF + Channel 2 interrupt flag + 2 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 digital filter + 12 + 4 + + + C2IDIV + Channel 2 input divider + 10 + 2 + + + C2C + Channel 2 configure + 8 + 2 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C2CP + Channel 2 complementary polarity + 7 + 1 + + + C2CEN + Channel 2 complementary enable + 6 + 1 + + + C2P + Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + TWCMSEL + Two-way count mode selection + 5 + 2 + + + OWCDIR + One-way count direction + 4 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + BKF + brake input filter + 16 + 4 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + + TMR14 + 0x40002000 + + + RMP + RMP + TMR14 channel 1 input remap + 0x50 + 0x20 + read-write + 0x00000000 + + + TMR14_CH1_IRMP + TMR14 channel 1 input remap + 6 + 2 + + + + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HICK Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLKP + I2SCLKP + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL + trigger event select for ordinary channels conversion + 24 + 4 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL + trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + SPT3 + SPT3 + sample time register 3 + 0x50 + 0x20 + read-write + 0x00000000 + + + CSPT27 + Selection sample time of channel ADC_IN27 + 21 + 3 + + + CSPT26 + Selection sample time of channel ADC_IN26 + 18 + 3 + + + CSPT25 + Selection sample time of channel ADC_IN25 + 15 + 3 + + + CSPT24 + Selection sample time of channel ADC_IN24 + 12 + 3 + + + CSPT23 + Selection sample time of channel ADC_IN23 + 9 + 3 + + + CSPT22 + Selection sample time of channel ADC_IN22 + 6 + 3 + + + CSPT21 + Selection sample time of channel ADC_IN21 + 3 + 3 + + + CSPT20 + Selection sample time of channel ADC_IN20 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 16 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 16 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 5 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + OSQ4 + OSQ4 + Ordinary sequence register 4 + 0x54 + 0x20 + read-write + 0x00000000 + + + OSN22 + Number of 22th conversion in ordinary sequence + 25 + 5 + + + OSN21 + Number of 21th conversion in ordinary sequence + 20 + 5 + + + OSN20 + Number of 20th conversion in ordinary sequence + 15 + 5 + + + OSN19 + number of 19rd conversion in ordinary sequence + 10 + 5 + + + OSN18 + Number of 18nd conversion in ordinary sequence + 5 + 5 + + + OSN17 + Number of 17st conversion in ordinary sequence + 0 + 5 + + + + + OSQ5 + OSQ5 + Ordinary sequence register 5 + 0x58 + 0x20 + read-write + 0x00000000 + + + OSN28 + Number of 28th conversion in ordinary sequence + 25 + 5 + + + OSN27 + Number of 27th conversion in ordinary sequence + 20 + 5 + + + OSN26 + Number of 26th conversion in ordinary sequence + 15 + 5 + + + OSN25 + number of 25rd conversion in ordinary sequence + 10 + 5 + + + OSN24 + Number of 24nd conversion in ordinary sequence + 5 + 5 + + + OSN23 + Number of 23st conversion in ordinary sequence + 0 + 5 + + + + + OSQ6 + OSQ6 + Ordinary sequence register 6 + 0x5C + 0x20 + read-write + 0x00000000 + + + OSN32 + Number of 32th conversion in ordinary sequence + 15 + 5 + + + OSN31 + number of 31rd conversion in ordinary sequence + 10 + 5 + + + OSN30 + Number of 30nd conversion in ordinary sequence + 5 + 5 + + + OSN29 + Number of 29st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB1 + F2FB1 + Filter bank 2 filtrate bit register 1 + 0x250 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F2FB2 + F2FB2 + Filter bank 2 filtrate bit register 2 + 0x254 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB1 + F3FB1 + Filter bank 3 filtrate bit register 1 + 0x258 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F3FB2 + F3FB2 + Filter bank 3 filtrate bit register 2 + 0x25C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + 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Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB2 + F12FB2 + Filter bank 12 filtrate bit register 2 + 0x2A4 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + D1DMAUDRF + DAC1 DMA underrun flag + 13 + 1 + + + D2DMAUDRF + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTGFS_GLOBAL + USB on-the-go full speed + USB_OTGFS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTGFS_HOST + USB on the go full speed + USB_OTGFS + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTGFS_DEVICE + USB on the go full speed + USB_OTGFS + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTGFS_PWRCLK + USB on the go full speed + USB_OTGFS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + LOCKUP_LK + CM4 LOCKUP bit enable + 0 + 1 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex configuration bit + 30 + 2 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB8_UH + PB8 ultra high sourcing/sinking strength + 3 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.h b/hw/bsp/at32f423/boards/AT_START_F423/board.h new file mode 100644 index 000000000..fc8e2d8a5 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.h @@ -0,0 +1,91 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// UART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_10 + +//Vbus +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk new file mode 100644 index 000000000..95ec21d02 --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld + +CFLAGS += \ + -DAT32F423VCT7 diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c new file mode 100644 index 000000000..f63fb8962 --- /dev/null +++ b/hw/bsp/at32f423/family.c @@ -0,0 +1,294 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f423_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); +void uart_print_init(uint32_t baudrate); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk new file mode 100644 index 000000000..2653842da --- /dev/null +++ b/hw/bsp/at32f423/family.mk @@ -0,0 +1,44 @@ +# Submodules +AT32F423_SDK = hw/mcu/artery/at32f423 +DEPS_SUBMODULES += $(AT32F423_SDK) + +# AT32 SDK path +AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F423 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_gpio.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_misc.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_usart.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_crm.c \ + $(AT32F423_SDK_SRC)/drivers/src/at32f423_acc.c \ + $(AT32F423_SDK_SRC)/cmsis/cm4/device_support/system_at32f423.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F423_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F423_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f423.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s new file mode 100644 index 000000000..764380f0e --- /dev/null +++ b/hw/bsp/at32f423/startup_at32f423.s @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file startup_at32f423.s + * @brief at32f423 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_IRQHandler /* ADC1 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR12_GLOBAL_IRQHandler /* TMR12 */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI3_IRQHandler /* SPI3 */ + .word USART4_IRQHandler /* USART4 */ + .word USART5_IRQHandler /* USART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word USART7_IRQHandler /* USART7 */ + .word USART8_IRQHandler /* USART8 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* DMAMUX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word ACC_IRQHandler /* ACC */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR12_GLOBAL_IRQHandler + .thumb_set TMR12_GLOBAL_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak USART4_IRQHandler + .thumb_set USART4_IRQHandler,Default_Handler + + .weak USART5_IRQHandler + .thumb_set USART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak USART7_IRQHandler + .thumb_set USART7_IRQHandler,Default_Handler + + .weak USART8_IRQHandler + .thumb_set USART8_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..6cc39f727 --- /dev/null +++ b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f425.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd new file mode 100644 index 000000000..d18e75e8e --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd @@ -0,0 +1,30790 @@ + + + + + + + + Keil + ArteryTek + AT32F425xx_v2 + AT32F425 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 120MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + PVM + PVM through EXTI line detection interrupt + 1 + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + read-write + + + LPSEL + Low power mode select when Cortex-M4 sleepdeep + 1 + 1 + read-write + + + CLSWEF + Clear SWEF flag + 2 + 1 + write-only + + + CLSEF + Clear SEF flag + 3 + 1 + write-only + + + PVMEN + Power voltage monitoring enable + 4 + 1 + read-write + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + read-write + + + BPWEN + Battery power domain write enable + 8 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Power control register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin2 enable + 9 + 1 + read-write + + + SWPEN4 + Standby wake-up pin4 enable + 11 + 1 + read-write + + + SWPEN5 + Standby wake-up pin5 enable + 12 + 1 + read-write + + + SWPEN6 + Standby wake-up pin6 enable + 13 + 1 + read-write + + + SWPEN7 + Standby wake-up pin7 enable + 14 + 1 + read-write + + + + + CTRL2 + CTRL2 + Power control register 2 + (PWC_CTRL2) + 0x20 + 0x20 + 0x00000000 + + + VREXLPEN + Voltage regulator extra low power mode enable + 5 + 1 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40021000 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 4 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + CFG + CFG + Clock configuration register + (CRM_CFG) + 0x4 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 8 + 3 + read-write + + + APB2DIV + APB2 division + 11 + 3 + read-write + + + ADCDIV1_0 + ADC division bit1 and bit0 + 14 + 2 + read-write + + + PLLRCS + PLL reference clock select + 16 + 1 + read-write + + + PLLHEXTDIV + HEXT division selection for PLL entry clock + 17 + 1 + read-write + + + PLLMULT3_0 + PLL Multiplication Factor bit3 to bit0 + 18 + 4 + read-write + + + USBDIV1_0 + USB division bit1 and bit0 + 22 + 2 + read-write + + + CLKOUT_SEL + Clock output selection bit2 to bit0 + 24 + 3 + read-write + + + USBDIV2 + USB division bit2 + 27 + 1 + read-write + + + ADCDIV2 + ADC division bit2 + 28 + 1 + read-write + + + PLLMULT5_4 + PLL Multiplication Factor bit5 and bit4 + 29 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0x8 + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0xC + 0x20 + read-write + 0x000000000 + + + SCFGRST + System config reset + 0 + 1 + + + EXINTRST + External interrupt reset + 1 + 1 + + + ADC1RST + ADC1 reset + 9 + 1 + + + TMR1RST + TMR1 reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + TMR15RST + Timer15 reset + 16 + 1 + + + TMR16RST + Timer16 reset + 17 + 1 + + + TMR17RST + Timer17 reset + 18 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer 2 reset + 0 + 1 + + + TMR3RST + Timer 3 reset + 1 + 1 + + + TMR6RST + Timer 6 reset + 4 + 1 + + + TMR7RST + Timer 7 reset + 5 + 1 + + + TMR13RST + Timer 13 reset + 7 + 1 + + + TMR14RST + Timer 14 reset + 8 + 1 + + + WWDTRST + Window watchdog timer reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + ACCRST + ACC reset + 27 + 1 + + + PWCRST + Power controller reset + 28 + 1 + + + + + AHBEN + AHBEN + AHB Peripheral Clock enable register + (CRM_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLASHEN + FLASH clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 12 + 1 + + + GPIOAEN + I/O port A clock enable + 17 + 1 + + + GPIOBEN + I/O port B clock enable + 18 + 1 + + + GPIOCEN + I/O port C clock enable + 19 + 1 + + + GPIODEN + I/O port D clock enable + 20 + 1 + + + GPIOFEN + I/O port F clock enable + 22 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + SCFGEN + System config clock enable + 0 + 1 + + + ADC1EN + ADC1 clock enable + 9 + 1 + + + TMR1EN + Timer1 clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + TMR15EN + Timer15 clock enable + 16 + 1 + + + TMR16EN + Timer16 clock enable + 17 + 1 + + + TMR17EN + Timer17 clock enable + 18 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + Window watchdog timer clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART4EN + USART4 clock enable + 19 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + ACCEN + ACC clock enable + 27 + 1 + + + PWCEN + Power clock enable + 28 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x20 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x24 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + + 0x28 + 0x20 + 0x00000000 + + + OTGFS1RST + OTGFS1 reset + 12 + 1 + + + GPIOARST + IO port A reset + 17 + 1 + + + GPIOBRST + IO port B reset + 18 + 1 + + + GPIOCRST + IO port C reset + 19 + 1 + + + GPIODRST + IO port D reset + 20 + 1 + + + GPIOFRST + IO port F reset + 22 + 1 + + + + + PLL + PLL + PLL configuration register + (CRM_PLL) + 0x2C + 0x20 + 0x00001F10 + + + PLL_FR + PLL_FR + 0 + 3 + read-write + + + PLL_MS + PLL_MS + 4 + 4 + read-write + + + PLL_NS + PLL_NS + 8 + 9 + read-write + + + PLL_FREF + PLL entry clock reference frequency + 24 + 3 + read-write + + + PLLCFGEN + PLL config enable + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0x30 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + CLKOUT_SEL3 + Clock output bit3 + 16 + 1 + read-write + + + HICKDIV + HICK 6 divider selection + 25 + 1 + read-write + + + CLKOUTDIV + Clock output division + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0x54 + 0x20 + 0x0000000D + + + HICK_TO_USB + HICK_TO_USB + 8 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 9 + 1 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x48000400 + + + GPIOC + 0x48000800 + + + GPIOD + 0x48000C00 + + + GPIOF + 0x48001400 + + + EXINT + EXINT + EXINT + 0x40010400 + + 0x0 + 0x400 + registers + + + PVM + PVM interrupt connect to EXTI line16 + 1 + + + ERTC + ERTC interrupt connect to EXTI line17_19_20 + 2 + + + EXTINT1_0 + EXINT Line1_0 interrupt + 5 + + + EXTINT3_2 + EXINT Line3_2 interrupt + 6 + + + EXTINT15_4 + EXINT Line15_4 interrupt + 7 + + + OTGFS + OTGFS interrupt connect to EXTI Line18 + 31 + + + + INTEN + INTEN + Interrupt enable register (EXTINT_INTEN) + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + + + EVTEN + EVTEN + Event enable register (EXTINT_EVTEN) + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register(EXTINT_POLCFG1) + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register(EXTINT_POLCFG2) + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + + + SWTRG + SWTRG + Software triggle register + (EXTINT_SWIE) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + + + INTSTS + INTSTS + Interrupt status register (EXTINT_INTSTS) + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 9 + + + DMA1_Channel3_2 + DMA1 Channel3_2 global interrupt + 10 + + + DMA1_Channel7_4 + DMA1 Channel7_4 global interrupt + 11 + + + + STS + STS + DMA interrupt status register (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Full data transfer interrupt enable + 1 + 1 + + + HDTIEN + Half data transfer interrupt enable + 2 + 1 + + + DTERRIEN + Data transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral address increment mode + 6 + 1 + + + MINCM + Memory address increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_SRC_SEL0 + DMA_SRC_SEL0 + DMA channel source assignment register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CH1_SRC + CH1 SRC select + 0 + 8 + + + CH2_SRC + CH2 SRC select + 8 + 8 + + + CH3_SRC + CH3 SRC select + 16 + 8 + + + CH4_SRC + CH4 SRC select + 24 + 8 + + + + + DMA_SRC_SEL1 + DMA_SRC_SEL1 + DMA channel source assignment register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CH5_SRC + CH5 SRC select + 0 + 8 + + + CH6_SRC + CH6 SRC select + 8 + 8 + + + CH7_SRC + CH7 SRC select + 16 + 8 + + + DMA_FLEX_EN + DMA FLEX Enable + 24 + 1 + + + + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC 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HALLSWTR + HALL event triggered by software + 5 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C2DF + Channel 2 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DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR16 + General-purpose-timers + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR16 + TMR16 global interrupt + 21 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + C1CIOS + Channel 1 complementary idle output state + 9 + 1 + + + C1IOS + Channel 1 idle output state + 8 + 1 + + + DRS + DMA request source + 3 + 1 + + + CCFS + Channel control bit flash select + 2 + 1 + + + CBCTRL + Channel buffer control + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1DEN + Channel 1 DMA request + enable + 9 + 1 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + BRKIE + Brake interrupt enable + 7 + 1 + + + HALLIEN + HALL interrupt enable + 5 + 1 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + BRKIF + Brake interrupt flag + 7 + 1 + + + HALLIF + HALL interrupt flag + 5 + 1 + + + C4IF + Channel 4 interrupt flag + 4 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + BRKSWTR + Brake event triggered by software + 7 + 1 + + + HALLSWTR + HALL event triggered by software + 5 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + RPR + RPR + Repetition of period value + 0x30 + 0x20 + read-write + 0x0000 + + + RPR + Repetition of period value + 0 + 8 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + BRK + BRK + Brake register + 0x44 + 0x20 + read-write + 0x0000 + + + OEN + Output enable + 15 + 1 + + + AOEN + Automatic output enable + 14 + 1 + + + BRKV + Brake input validity + 13 + 1 + + + BRKEN + Brake enable + 12 + 1 + + + FCSOEN + Frozen channel status when + holistic output enable + 11 + 1 + + + FCSODIS + Frozen channel status when + holistic output disable + 10 + 1 + + + WPC + Write protected configuration + 8 + 2 + + + DTC + Dead-time configuration + 0 + 8 + + + + + DMACTRL + DMACTRL + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + + + TMR17 + 0x40014800 + + TMR17 + TMR17 global interrupt + 22 + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 23 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 24 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1 + CAN1 global interrupt + 30 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC + 0x20 + 0x00000000 + + + RF0R + Receive FIFO 0 release + 5 + 1 + read-write + + + RF0OF + Receive FIFO 0 overflow flag + 4 + 1 + read-write + + + RF0FF + Receive FIFO 0 full flag + 3 + 1 + read-write + + + RF0MN + Receive FIFO 0 message num + 0 + 2 + read-only + + + + + RF1 + RF1 + Receive FIFO 1 register + 0x10 + 0x20 + 0x00000000 + + + RF1R + Receive FIFO 1 release + 5 + 1 + read-write + + + RF1OF + Receive FIFO 1 overflow flag + 4 + 1 + read-write + + + RF1FF + Receive FIFO 1 full flag + 3 + 1 + read-write + + + RF1MN + Receive FIFO 1 message num + 0 + 2 + read-only + + + + + INTEN + INTEN + Interrupt enable register + 0x14 + 0x20 + read-write + 0x00000000 + + + EDZIEN + Enter doze mode interrupt enable + 17 + 1 + + + QDZIEN + Quit doze mode interrupt enable + 16 + 1 + + + EOIEN + Error occur interrupt enable + 15 + 1 + + + ETRIEN + Error type record interrupt enable + 11 + 1 + + + BOIEN + Bus-off interrupt enable + 10 + 1 + + + EPIEN + Error passive interrupt enable + 9 + 1 + + + EAIEN + Error active interrupt enable + 8 + 1 + + + RF1OIEN + Receive FIFO 1 overflow interrupt enable + 6 + 1 + + + RF1FIEN + Receive FIFO 1 full interrupt enable + 5 + 1 + + + RF1MIEN + FIFO 1 receive message interrupt enable + 4 + 1 + + + RF0OIEN + Receive FIFO 0 overflow interrupt enable + 3 + 1 + + + RF0FIEN + Receive FIFO 0 full interrupt enable + 2 + 1 + + + RF0MIEN + FIFO 0 receive message interrupt enable + 1 + 1 + + + TCIEN + Transmission complete interrupt enable + 0 + 1 + + + + + ESTS + ESTS + Error status register + 0x18 + 0x20 + 0x00000000 + + + REC + Receive error counter + 24 + 8 + read-only + + + TEC + Transmit error counter + 16 + 8 + read-only + + + ETR + Error type record + 4 + 3 + read-write + + + BOF + Bus-off flag + 2 + 1 + read-only + + + EPF + Error passive flag + 1 + 1 + read-only + + + EAF + Error active flag + 0 + 1 + read-only + + + + + BTMG + BTMG + Bit timing register + 0x1C + 0x20 + read-write + 0x00000000 + + + LOEN + Listen-Only mode + 31 + 1 + + + LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit 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register 2 + 0x28C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB1 + F10FB1 + Filter bank 10 filtrate bit register 1 + 0x290 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F10FB2 + F10FB2 + Filter bank 10 filtrate bit register 2 + 0x294 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit 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data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F11FB2 + F11FB2 + Filter bank 11 filtrate bit register 2 + 0x29C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F12FB1 + F12FB1 + Filter bank 12 filtrate bit filtrate bit register 1 + 0x2A0 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit 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FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB1 + F13FB1 + Filter bank 13 filtrate bit filtrate bit register 1 + 0x2A8 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F13FB2 + F13FB2 + Filter bank 13 filtrate bit filtrate bit register 2 + 0x2AC + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40006C00 + + 0x0 + 0x400 + registers + + + ACC + ACC interrupts + 8 + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + ACC_HSITRIM + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + ACC_HSICAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 25 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency 3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-only + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 26 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 33 + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 27 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + ID + USART identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 28 + + + + USART3 + 0x40004800 + + USART3 + USART4_3 global interrupt + 29 + + + + USART4 + 0x40004C00 + + + ADC + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC1 + ADC1 global interrupt + 12 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + CCE + Channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + CCEIEN + Channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + OCSWTRG + Conversion trigger by software of ordinary channels + 22 + 1 + + + PCSWTRG + Conversion trigger by software of preempted channels + 21 + 1 + + + OCTEN + Trigger mode enable for ordinary channels conversion + 20 + 1 + + + OCTESEL + Low bit of trigger event select for ordinary channels conversion + 17 + 3 + + + PCTEN + Trigger mode enable for preempted channels conversion + 15 + 1 + + + PCTESEL + Low bit of trigger event select for preempted channels conversion + 12 + 3 + + + DTALIGN + Data alignment + 11 + 1 + + + OCDMAEN + DMA transfer enable of ordinary channels + 8 + 1 + + + ADCALINIT + initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + + + SCFG + System configuration controller + SCFG + 0x40010000 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory mapping selection + bits + 0 + 2 + + + PA11_12_RMP + PA11/PA12 pins remapping bit + 4 + 1 + + + IR_POL + Infrared output polarity selection + 5 + 1 + + + IR_SRC_SEL + Infrared modulation envelope signal source selection + 6 + 2 + + + PB14_UH + PB14 Ultra high sourcing/sinking strength + 16 + 1 + + + PB13_UH + PB13 Ultra high sourcing/sinking strength + 17 + 1 + + + PB9_UH + PB9 Ultra high sourcing/sinking strength + 18 + 1 + + + PB8_UH + PB8 Ultra high sourcing/sinking strength + 19 + 1 + + + + + EXTIC1 + EXTIC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTINT3 + EXTINT 3 configuration bits + 12 + 4 + + + EXTINT2 + EXTINT 2 configuration bits + 8 + 4 + + + EXTINT1 + EXTINT 1 configuration bits + 4 + 4 + + + EXTINT0 + EXTINT 0 configuration bits + 0 + 4 + + + + + EXTIC2 + EXTIC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTINT7 + EXTINT 7 configuration bits + 12 + 4 + + + EXTINT6 + EXTINT 6 configuration bits + 8 + 4 + + + EXTINT5 + EXTINT 5 configuration bits + 4 + 4 + + + EXTINT4 + EXTINT 4 configuration bits + 0 + 4 + + + + + EXTIC3 + EXTIC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTINT11 + EXTINT 11 configuration bits + 12 + 4 + + + EXTINT10 + EXTINT 10 configuration bits + 8 + 4 + + + EXTINT9 + EXTINT 9 configuration bits + 4 + 4 + + + EXTINT8 + EXTINT 8 configuration bits + 0 + 4 + + + + + EXTIC4 + EXTIC4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTINT15 + EXTINT 15 configuration bits + 12 + 4 + + + EXTINT14 + EXTINT 14 configuration bits + 8 + 4 + + + EXTINT13 + EXTINT 13 configuration bits + 4 + 4 + + + EXTINT12 + EXTINT 12 configuration bits + 0 + 4 + + + + + CFG2 + CFG2 + configuration register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + PVM_LK + PVM lock enable + 2 + 1 + + + I2S_FD + I2S full duplex + 30 + 2 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + PID + 0 + 32 + + + + + CTRL + CTRL + DEBUG_CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + CAN_PAUSE + CAN_PAUSE + 3 + 1 + + + WDT_PAUSE + WDT_PAUSE + 8 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 9 + 1 + + + TMR1_PAUSE + TMR1_PAUSE + 10 + 1 + + + TMR2_PAUSE + TMR2_PAUSE + 11 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 12 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 14 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 15 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 16 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 19 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 20 + 1 + + + ERTC_512_PAUSE + ERTC_512_PAUSE + 21 + 1 + + + TMR15_PAUSE + TMR15_PAUSE + 22 + 1 + + + TMR16_PAUSE + TMR16_PAUSE + 23 + 1 + + + TMR17_PAUSE + TMR17_PAUSE + 24 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 26 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 27 + 1 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 3 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000030 + + + WTCYC + Wait cycle + 0 + 3 + read-write + + + HFCYC_EN + Half cycle acceleration access enable + 3 + 1 + read-write + + + PFT_EN + Prefetch enable + 4 + 1 + read-write + + + PFT_ENF + Prefetch enabled flag + 5 + 1 + read-only + + + PFT_EN2 + Prefetch enable 2 + 6 + 1 + read-write + + + PFT_ENF2 + Prefetch enabled flag 2 + 7 + 1 + read-only + + + PFT_LAT_DIS + Prefetch latency disable + 8 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00020080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + LPMEN + Low power mode enable + 17 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + nBOOT1 + boot1 + 6 + 1 + + + nDEPSLP_WDT + Deepsleep wdt stop count + 7 + 1 + + + nSTDBY_WDT + Standby wdt stop count + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + FAP_HL + FAP high level + 26 + 1 + + + + + EPPS + EPPS + Erase/program protection status register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0x74 + 0x20 + 0x00000000 + + + BTM_AP_ENF + Boot memory store application code enabled flag + 0 + 1 + + + EM_SLIB_ENF + Extension memory sLib enabled flag + 2 + 1 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + + + EM_SLIB_INST_SS + Extension memory sLib instruction start sector + 16 + 8 + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0x78 + 0x20 + 0x00000000 + + + SLIB_SS + sLib start sector + 0 + 11 + + + SLIB_INST_SS + sLib instruction start sector + 11 + 11 + + + SLIB_ES + sLib end sector + 22 + 10 + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0x7C + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0x80 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + + + CRC_ADDR + CRC_ADDR + Flash CRC data start address register + 0x84 + 0x20 + write-only + 0x00000000 + + + CRC_ADDR + CRC address + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + Flash CRC controll register + 0x88 + 0x20 + 0x00000000 + + + CRC_SN + CRC sector numbler + 0 + 16 + read-write + + + CRC_STRT + CRC start + 16 + 1 + write-only + + + + + CRC_CHKR + CRC_CHKR + FLASH CRC check result register + 0x8C + 0x20 + read-only + 0x00000000 + + + FCRC_OUT + CRC32 verification result of flash user code or SLIB code + 0 + 32 + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0x160 + 0x20 + write-only + 0x00000000 + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE + SLIB_SET_RANGE + Configure sLib range register + 0x164 + 0x20 + write-only + 0x00000000 + + + SLIB_SS_SET + sLib start sector setting + 0 + 11 + + + SLIB_ISS_SET + sLib instruction start sector setting + 11 + 11 + + + SLIB_ES_SET + sLib end sector setting + 22 + 10 + + + + + EM_SLIB_SET + EM_SLIB_SET + Extension momery slib set register + 0x168 + 0x20 + write-only + 0x00000000 + + + EM_SLIB_SET + Extension memory sLib setting + 0 + 16 + + + EM_SLIB_ISS_SET + Extension memory sLib instruction start sector setting + 16 + 8 + + + + + BTM_MODE_SET + BTM_MODE_SET + Boot memory mode setting register + 0x16C + 0x20 + write-only + 0x00000000 + + + BTM_MODE_SET + Boot memory mode setting + 0 + 8 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0x170 + 0x20 + write-only + 0x00000000 + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.h b/hw/bsp/at32f425/boards/AT_START_F425/board.h new file mode 100644 index 000000000..ddfe1f71b --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.h @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define USB_VBUS_IGNORE + +// LED +#define LED_PORT GPIOC +#define LED_PIN GPIO_PINS_2 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// Usart +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_1 + +//USB +#define USB_ID 0 +#define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK +#define OTG_IRQ OTGFS1_IRQn +#define OTG_IRQ_HANDLER OTGFS1_IRQHandler +#define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn +#define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler +#define OTG_WKUP_EXINT_LINE EXINT_LINE_18 +#define OTG_PIN_GPIO GPIOA +#define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_DP GPIO_PINS_12 +#define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 +#define OTG_PIN_DM GPIO_PINS_11 +#define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 +#define OTG_PIN_VBUS GPIO_PINS_9 +#define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 +#define OTG_PIN_ID GPIO_PINS_10 +#define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 +#define OTG_PIN_SOF_GPIO GPIOA +#define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK +#define OTG_PIN_SOF GPIO_PINS_8 +#define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 +#define OTG_PIN_MUX GPIO_MUX_3 + +static inline void board_vbus_sense_init(void) +{ + *(int*)(0x50000038) |= (1<<21); +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f425/boards/AT_START_F425/board.mk b/hw/bsp/at32f425/boards/AT_START_F425/board.mk new file mode 100644 index 000000000..3fa74d95a --- /dev/null +++ b/hw/bsp/at32f425/boards/AT_START_F425/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F425x8_FLASH.ld + +CFLAGS += \ + -DAT32F425R8T7 diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c new file mode 100644 index 000000000..e0b66730a --- /dev/null +++ b/hw/bsp/at32f425/family.c @@ -0,0 +1,298 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f425_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_button_init(void); + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock */ + system_clock_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* vbus ignore */ + board_vbus_sense_init(); + + /* configure systick */ + systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); + SysTick_Config(SystemCoreClock / 1000); + #if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); + #endif + + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif + + /* config led and key */ + led_and_button_init(); + + /* config usart printf */ + uart_print_init(115200); + printf("usart printf config success!\r\n"); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + /* usb divider reset */ + crm_usb_div_reset(); + + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + default: + break; + } + } +} + +void led_and_button_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} + +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + + +#if CFG_TUSB_OS == OPT_OS_NONE + + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + + uint32_t board_millis(void) + { + return system_ticks; + } + + void SVC_Handler(void) + { + } + + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk new file mode 100644 index 000000000..d1bcdfda3 --- /dev/null +++ b/hw/bsp/at32f425/family.mk @@ -0,0 +1,43 @@ +# Submodules +AT32F425_SDK = hw/mcu/artery/at32f425 +DEPS_SUBMODULES += $(AT32F425_SDK) + +# AT32 SDK path +AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m3 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F425 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_gpio.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_misc.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_usart.c \ + $(AT32F425_SDK_SRC)/drivers/src/at32f425_crm.c \ + $(AT32F425_SDK_SRC)/cmsis/cm4/device_support/system_at32f425.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F425_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F425_SDK_SRC)/cmsis/cm4/device_support + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f425.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4 + +flash: flash-atlink diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s new file mode 100644 index 000000000..38127c759 --- /dev/null +++ b/hw/bsp/at32f425/startup_at32f425.s @@ -0,0 +1,309 @@ +/** + ****************************************************************************** + * @file startup_at32f425.s + * @brief at32f425xx devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word ERTC_IRQHandler /* ERTC */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT1_0_IRQHandler /* EXINT Line 1 & 0 */ + .word EXINT3_2_IRQHandler /* EXINT Line 3 & 2 */ + .word EXINT15_4_IRQHandler /* EXINT Line 15 ~ 4 */ + .word ACC_IRQHandler /* ACC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel3_2_IRQHandler /* DMA1 Channel 3 & 2 */ + .word DMA1_Channel7_4_IRQHandler /* DMA1 Channel 7 & 4 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TMR1_BRK_OVF_TRG_HALL_IRQHandler /* TMR1 brake overflow trigger and hall */ + .word TMR1_CH_IRQHandler /* TMR1 channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR6_GLOBAL_IRQHandler /* TMR6 */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word TMR14_GLOBAL_IRQHandler /* TMR14 */ + .word TMR15_GLOBAL_IRQHandler /* TMR15 */ + .word TMR16_GLOBAL_IRQHandler /* TMR16 */ + .word TMR17_GLOBAL_IRQHandler /* TMR17 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART4_3_IRQHandler /* USART3 & USART4 */ + .word CAN1_IRQHandler /* CAN1 */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word SPI3_IRQHandler /* SPI3 */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word TMR13_GLOBAL_IRQHandler /* TMR13 */ +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak ERTC_IRQHandler + .thumb_set ERTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT1_0_IRQHandler + .thumb_set EXINT1_0_IRQHandler,Default_Handler + + .weak EXINT3_2_IRQHandler + .thumb_set EXINT3_2_IRQHandler,Default_Handler + + .weak EXINT15_4_IRQHandler + .thumb_set EXINT15_4_IRQHandler,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel3_2_IRQHandler + .thumb_set DMA1_Channel3_2_IRQHandler,Default_Handler + + .weak DMA1_Channel7_4_IRQHandler + .thumb_set DMA1_Channel7_4_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TMR1_BRK_OVF_TRG_HALL_IRQHandler + .thumb_set TMR1_BRK_OVF_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR6_GLOBAL_IRQHandler + .thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak TMR14_GLOBAL_IRQHandler + .thumb_set TMR14_GLOBAL_IRQHandler,Default_Handler + + .weak TMR15_GLOBAL_IRQHandler + .thumb_set TMR15_GLOBAL_IRQHandler,Default_Handler + + .weak TMR16_GLOBAL_IRQHandler + .thumb_set TMR16_GLOBAL_IRQHandler,Default_Handler + + .weak TMR17_GLOBAL_IRQHandler + .thumb_set TMR17_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART4_3_IRQHandler + .thumb_set USART4_3_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak TMR13_GLOBAL_IRQHandler + .thumb_set TMR13_GLOBAL_IRQHandler,Default_Handler diff --git a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..a42e4d414 --- /dev/null +++ b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// Include MCU header + #include "at32f435_437.h" + +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd new file mode 100644 index 000000000..4f34af9d3 --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd @@ -0,0 +1,58291 @@ + + + + + + + + Keil + ArteryTek + AT32F437xx_v2 + AT32F437 + 1.0 + ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + CM4 + r0p1 + little + false + true + 4 + false + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + + XMC + Flexible static memory controller + XMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + XMC + XMC global interrupt + 48 + + + + BK1CTRL1 + BK1CTRL1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030DB + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG1 + BK1TMG1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL2 + BK1CTRL2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG2 + BK1TMG2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL3 + BK1CTRL3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG3 + BK1TMG3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1CTRL4 + BK1CTRL4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D2 + + + MWMC + Memory write mode control + 19 + 1 + + + CRPGS + CRAM page size + 16 + 3 + + + NWASEN + NWAIT in asynchronous transfer enable + 15 + 1 + + + RWTD + Read-write timing different + 14 + 1 + + + NWSEN + NWAIT in synchronous transfer enable + 13 + 1 + + + WEN + Write enable + 12 + 1 + + + NWTCFG + Wait timing configuration + 11 + 1 + + + WRAPEN + Wrapped enable + 10 + 1 + + + NWPOL + NWAIT polarity + 9 + 1 + + + SYNCBEN + Synchronous burst enable + 8 + 1 + + + NOREN + Nor flash access enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 2 + 2 + + + ADMUXEN + Address and data multiplexing enable + 1 + 1 + + + EN + Memory bank enable + 0 + 1 + + + + + BK1TMG4 + BK1TMG4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + DTLAT + Data latency + 24 + 4 + + + CLKPSC + Clock prescale + 20 + 4 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK2CTRL + BK2CTRL + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK2IS + BK2IS + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK2TMGRG + BK2TMGRG + Regular memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK2TMGSP + BK2TMGSP + special memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK2ECC + BK2ECC + ECC result register 2 + 0x74 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK3CTRL + BK3CTRL + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPGS + ECC page size + 17 + 3 + + + TAR + ALE to RE delay + 13 + 4 + + + TCR + CLE to RE delay + 9 + 4 + + + ECCEN + ECC enable + 6 + 1 + + + EXTMDBW + External memory data bus width + 4 + 2 + + + DEV + Memory device type + 3 + 1 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK3IS + BK3IS + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK3TMGRG + BK3TMGRG + Regular memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + RGDHIZT + Regular memory databus High resistance time + 24 + 8 + + + RGHT + Regular memory hold time + 16 + 8 + + + RGWT + Regular memory wait time + 8 + 8 + + + RGST + Regular memory setup time + 0 + 8 + + + + + BK3TMGSP + BK3TMGSP + special memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + SPDHIZT + special memory databus High resistance time + 24 + 8 + + + SPHT + special memory hold time + 16 + 8 + + + SPWT + special memory wait time + 8 + 8 + + + SPST + special memory setup time + 0 + 8 + + + + + BK3ECC + BK3ECC + ECC result register 3 + 0x94 + 0x20 + read-write + 0x00000000 + + + ECC + ECC result + 0 + 32 + + + + + BK4CTRL + BK4CTRL + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + EN + Memory bank enable + 2 + 1 + + + NWEN + Wait feature enable + 1 + 1 + + + + + BK4IS + BK4IS + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FIFOE + FIFO empty + 6 + 1 + read-only + + + FEIEN + Falling edge interrupt enable + 5 + 1 + read-write + + + HLIEN + High-level interrupt enable + 4 + 1 + read-write + + + REIEN + Rising edge interrupt enable + 3 + 1 + read-write + + + FES + Falling edge status + 2 + 1 + read-write + + + HLS + High-level status + 1 + 1 + read-write + + + RES + Rising edge capture status + 0 + 1 + read-write + + + + + BK4TMGCM + BK4TMGCM + Regular memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + CMDHIZT + Regular memory databus High resistance time + 24 + 8 + + + CMHT + Regular memory hold time + 16 + 8 + + + CMWT + Regular memory wait time + 8 + 8 + + + CMST + Regular memory setup time + 0 + 8 + + + + + BK4TMGAT + BK4TMGAT + special memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATDHIZT + special memory databus High resistance time + 24 + 8 + + + ATHT + special memory hold time + 16 + 8 + + + ATWT + special memory wait time + 8 + 8 + + + ATST + special memory setup time + 0 + 8 + + + + + BK4TMGIO + BK4TMGIO + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IODHIZT + WRSTP + 24 + 8 + + + IOHT + HLD + 16 + 8 + + + IOWT + OP + 8 + 8 + + + IOST + STP + 0 + 8 + + + + + BK1TMGWR1 + BK1TMGWR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR2 + BK1TMGWR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR3 + BK1TMGWR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + BK1TMGWR4 + BK1TMGWR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ASYNCM + Asynchronous mode + 28 + 2 + + + BUSLAT + Bus latency + 16 + 4 + + + DTST + Asynchronous data setup time + 8 + 8 + + + ADDRHT + Address-hold time + 4 + 4 + + + ADDRST + Address setup time + 0 + 4 + + + + + CTRL1 + CTRL1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read delay + 13 + 2 + + + + + CTRL2 + CTRL2 + SDRAM Control Register 2 + 0x144 + 0x20 + read-write + 0x000002D0 + + + CA + Number of column address + bits + 0 + 2 + + + RA + Number of row address bits + 2 + 2 + + + DB + Memory data bus width + 4 + 2 + + + INBK + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WRP + Write protection + 9 + 1 + + + CLKDIV + Clock division configuration + 10 + 2 + + + BSTR + Burst read + 12 + 1 + + + RD + Read pipe + 13 + 2 + + + + + TM1 + TM1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + TM2 + TM2 + SDRAM Timing register 2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Mode register program to active delay + 0 + 4 + + + TXSR + Exit Self-refresh to active delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Refresh to active delay + 12 + 4 + + + TWR + Write Recovery delay + 16 + 4 + + + TRP + Precharge to active delay + 20 + 4 + + + TRCD + Row active to Read/Write delay + 24 + 4 + + + + + CMD + CMD + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + CMD + SDRAM Command + 0 + 3 + write-only + + + BK2 + SDRAM Bank 2 + 3 + 1 + write-only + + + BK1 + SDRAM Bank 1 + 4 + 1 + write-only + + + ART + Auto-refresh times + 5 + 4 + read-write + + + MRD + Mode register data + 9 + 13 + read-write + + + + + RCNT + RCNT + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + ERRC + error flag clear + 0 + 1 + write-only + + + RC + Refresh Count + 1 + 13 + read-write + + + ERIEN + error Interrupt Enable + 14 + 1 + read-write + + + + + STS + STS + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + ERR + error flag + 0 + 1 + + + BK1STS + Bank 1 Status + 1 + 2 + + + BK2STS + Bank 2 Status + 3 + 2 + + + BUSY + Busy status + 5 + 1 + + + + + EXT1 + EXT1 + externl timeing register 1 + 0x220 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT2 + EXT2 + externl timeing register 2 + 0x224 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT3 + EXT3 + externl timeing register 3 + 0x228 + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + EXT4 + EXT4 + externl timeing register 4 + 0x22C + 0x20 + read-write + 0x00000808 + + + BUSLATW2W + Bus turnaround phase for consecutive write duration + 0 + 8 + + + BUSLATR2R + Bus turnaround phase for consecutive read duration + 8 + 8 + + + + + + + PWC + Power control + PWC + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Power control register + (PWC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + VRSEL + Voltage regulator state select when deepsleep mode + 0 + 1 + + + LPSEL + Low power mode select when Cortex-M4F sleepdeep + 1 + 1 + + + CLSWEF + Clear SWEF flag + 2 + 1 + + + CLSEF + Clear SEF flag + 3 + 1 + + + PVMEN + Power voltage monitoring enable + 4 + 1 + + + PVMSEL + Power voltage monitoring boundary select + 5 + 3 + + + BPWEN + Battery powered domain write enable + 8 + 1 + + + + + CTRLSTS + CTRLSTS + Power control and status register + (PWC_CTRLSTS) + 0x4 + 0x20 + 0x00000000 + + + SWEF + Standby wake-up event flag + 0 + 1 + read-only + + + SEF + Standby mode entry flag + 1 + 1 + read-only + + + PVMOF + Power voltage monitoring output flag + 2 + 1 + read-only + + + SWPEN1 + Standby wake-up pin 1 enable + 8 + 1 + read-write + + + SWPEN2 + Standby wake-up pin 2 enable + 9 + 1 + read-write + + + + + LDOOV + LDOOV + LDO output voltage register + 0x10 + 0x20 + 0x00000000 + + + LDOOVSEL + LDO output voltage select + 0 + 3 + read-write + + + + + + + CRM + Clock and reset management + CRM + 0x40023800 + + 0x0 + 0x400 + registers + + + CRM + CRM global interrupt + 5 + + + + CTRL + CTRL + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HICKEN + High speed internal clock enable + 0 + 1 + read-write + + + HICKSTBL + High speed internal clock ready flag + 1 + 1 + read-only + + + HICKTRIM + High speed internal clock trimming + 2 + 6 + read-write + + + HICKCAL + High speed internal clock calibration + 8 + 8 + read-only + + + HEXTEN + High speed exernal crystal enable + 16 + 1 + read-write + + + HEXTSTBL + High speed exernal crystal ready flag + 17 + 1 + read-only + + + HEXTBYPS + High speed exernal crystal bypass + 18 + 1 + read-write + + + CFDEN + Clock failure detection enable + 19 + 1 + read-write + + + PLLEN + PLL enable + 24 + 1 + read-write + + + PLLSTBL + PLL clock ready flag + 25 + 1 + read-only + + + + + PLLCFG + PLLCFG + PLL configuration register + (CRM_PLLCFG) + 0x4 + 0x20 + 0x00033002 + + + PLL_MS + PLL pre-division + 0 + 4 + read-write + + + PLL_NS + PLL frequency multiplication factor + 6 + 9 + read-write + + + PLL_FR + PLL post-division + 16 + 3 + read-write + + + PLLRCS + PLL reference clock select + 22 + 1 + read-write + + + + + CFG + CFG + Clock configuration register(CRM_CFG) + 0x8 + 0x20 + 0x00000000 + + + SCLKSEL + System clock select + 0 + 2 + read-write + + + SCLKSTS + System Clock select Status + 2 + 2 + read-only + + + AHBDIV + AHB division + 4 + 4 + read-write + + + APB1DIV + APB1 division + 10 + 3 + read-write + + + APB2DIV + APB2 division + 13 + 3 + read-write + + + ERTCDIV + HEXT division for ERTC clock + 16 + 5 + read-write + + + CLKOUT1_SEL + Clock output1 selection + 21 + 2 + read-write + + + CLKOUT1DIV1 + Clock output1 division1 + 24 + 3 + read-write + + + CLKOUT2DIV1 + Clock output2 division1 + 27 + 3 + read-write + + + CLKOUT2_SEL1 + Clock output2 selection1 + 30 + 2 + read-write + + + + + CLKINT + CLKINT + Clock interrupt register + (CRM_CLKINT) + 0xC + 0x20 + 0x00000000 + + + LICKSTBLF + LICK ready interrupt flag + 0 + 1 + read-only + + + LEXTSTBLF + LEXT ready interrupt flag + 1 + 1 + read-only + + + HICKSTBLF + HICK ready interrupt flag + 2 + 1 + read-only + + + HEXTSTBLF + HEXT ready interrupt flag + 3 + 1 + read-only + + + PLLSTBLF + PLL ready interrupt flag + 4 + 1 + read-only + + + CFDF + Clock failure detection interrupt flag + 7 + 1 + read-only + + + LICKSTBLIEN + LICK ready interrupt enable + 8 + 1 + read-write + + + LEXTSTBLIEN + LEXT ready interrupt enable + 9 + 1 + read-write + + + HICKSTBLIEN + HICK ready interrupt enable + 10 + 1 + read-write + + + HEXTSTBLIEN + HEXT ready interrupt enable + 11 + 1 + read-write + + + PLLSTBLIEN + PLL ready interrupt enable + 12 + 1 + read-write + + + LICKSTBLFC + LICK ready interrupt clear + 16 + 1 + write-only + + + LEXTSTBLFC + LEXT ready interrupt clear + 17 + 1 + write-only + + + HICKSTBLFC + HICK ready interrupt clear + 18 + 1 + write-only + + + HEXTSTBLFC + HEXT ready interrupt clear + 19 + 1 + write-only + + + PLLSTBLFC + PLL ready interrupt clear + 20 + 1 + write-only + + + CFDFC + Clock failure detection interrupt clear + 23 + 1 + write-only + + + + + AHBRST1 + AHBRST1 + AHB peripheral reset register1 + (CRM_AHBRST1) + 0x10 + 0x20 + read-write + 0x000000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + EDMARST + EDMA reset + 21 + 1 + + + DMA1RST + DMA1 reset + 22 + 1 + + + DMA2RST + DMA2 reset + 24 + 1 + + + EMACRST + EMAC reset + 25 + 1 + + + OTGFS2RST + OTGFS2 interface reset + 29 + 1 + + + + + AHBRST2 + AHBRST2 + AHB peripheral reset register 2 + (CRM_AHBRST2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DVPRST + DVP reset + 0 + 1 + + + OTGFS1RST + OTGFS1 reset + 7 + 1 + + + SDIO1RST + SDIO1 reset + 15 + 1 + + + + + AHBRST3 + AHBRST3 + AHB peripheral reset register 3 + (CRM_AHBRST3) + 0x18 + 0x20 + read-write + 0x00000000 + + + XMCRST + XMC reset + 0 + 1 + + + QSPI1RST + QSPI1 reset + 1 + 1 + + + QSPI2RST + QSPI2 reset + 14 + 1 + + + SDIO2RST + SDIO2 reset + 15 + 1 + + + + + APB1RST + APB1RST + APB1 peripheral reset register + (CRM_APB1RST) + 0x20 + 0x20 + read-write + 0x00000000 + + + TMR2RST + Timer2 reset + 0 + 1 + + + TMR3RST + Timer3 reset + 1 + 1 + + + TMR4RST + Timer4 reset + 2 + 1 + + + TMR5RST + Timer5 reset + 3 + 1 + + + TMR6RST + Timer6 reset + 4 + 1 + + + TMR7RST + Timer7 reset + 5 + 1 + + + TMR12RST + Timer12 reset + 6 + 1 + + + TMR13RST + Timer13 reset + 7 + 1 + + + TMR14RST + Timer14 reset + 8 + 1 + + + WWDTRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWCRST + PWC reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + UART7RST + UART7 reset + 30 + 1 + + + UART8RST + UART8 reset + 31 + 1 + + + + + APB2RST + APB2RST + APB2 peripheral reset register + (CRM_APB2RST) + 0x24 + 0x20 + read-write + 0x00000000 + + + TMR1RST + Timer1 reset + 0 + 1 + + + TMR8RST + Timer8 reset + 1 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC reset + 8 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + SPI4RST + SPI4 reset + 13 + 1 + + + SCFGRST + SCFG reset + 14 + 1 + + + TMR9RST + Timer9 reset + 16 + 1 + + + TMR10RST + Timer10 reset + 17 + 1 + + + TMR11RST + Timer 11 reset + 18 + 1 + + + TMR20RST + Timer20 reset + 20 + 1 + + + ACCRST + ACC reset + 29 + 1 + + + + + AHBEN1 + AHBEN1 + AHB Peripheral Clock enable register 1 + (CRM_AHBEN1) + 0x30 + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO A clock enable + 0 + 1 + + + GPIOBEN + IO B clock enable + 1 + 1 + + + GPIOCEN + IO C clock enable + 2 + 1 + + + GPIODEN + IO D clock enable + 3 + 1 + + + GPIOEEN + IO E clock enable + 4 + 1 + + + GPIOFEN + IO F clock enable + 5 + 1 + + + GPIOGEN + IO G clock enable + 6 + 1 + + + GPIOHEN + IO H clock enable + 7 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + EDMAEN + DMA1 clock enable + 21 + 1 + + + DMA1EN + DMA1 clock enable + 22 + 1 + + + DMA2EN + DMA2 clock enable + 24 + 1 + + + EMACEN + EMAC clock enable + 25 + 1 + + + EMACTXEN + EMAC Tx clock enable + 26 + 1 + + + EMACRXEN + EMAC Rx clock enable + 27 + 1 + + + EMACPTPEN + EMAC PTP clock enable + 28 + 1 + + + OTGFS2EN + OTGFS2 clock enable + 29 + 1 + + + + + AHBEN2 + AHBEN2 + AHB peripheral clock enable register 2 + (CRM_AHBEN2) + 0x34 + 0x20 + read-write + 0x00000000 + + + DVPEN + DVP clock enable + 0 + 1 + + + OTGFS1EN + OTGFS1 clock enable + 7 + 1 + + + SDIO1EN + SDIO1 clock enable + 15 + 1 + + + + + AHBEN3 + AHBEN3 + AHB peripheral clock enable register 3 + (CRM_AHBEN3) + 0x38 + 0x20 + read-write + 0x00000000 + + + XMCEN + XMC clock enable + 0 + 1 + + + QSPI1EN + QSPI1 clock enable + 1 + 1 + + + QSPI2EN + QSPI2 clock enable + 14 + 1 + + + SDIO2EN + SDIO 2 clock enable + 15 + 1 + + + + + APB1EN + APB1EN + APB1 peripheral clock enable register + (CRM_APB1EN) + 0x40 + 0x20 + read-write + 0x00000000 + + + TMR2EN + Timer2 clock enable + 0 + 1 + + + TMR3EN + Timer3 clock enable + 1 + 1 + + + TMR4EN + Timer4 clock enable + 2 + 1 + + + TMR5EN + Timer5 clock enable + 3 + 1 + + + TMR6EN + Timer6 clock enable + 4 + 1 + + + TMR7EN + Timer7 clock enable + 5 + 1 + + + TMR12EN + Timer12 clock enable + 6 + 1 + + + TMR13EN + Timer13 clock enable + 7 + 1 + + + TMR14EN + Timer14 clock enable + 8 + 1 + + + WWDTEN + WWDT clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + PWCEN + PWC clock enable + 28 + 1 + + + DACEN + DAC clock enable + 29 + 1 + + + UART7EN + UART7 clock enable + 30 + 1 + + + UART8EN + UART8 clock enable + 31 + 1 + + + + + APB2EN + APB2EN + APB2 peripheral clock enable register + (CRM_APB2EN) + 0x44 + 0x20 + read-write + 0x00000000 + + + TMR1EN + Timer1 clock enable + 0 + 1 + + + TMR8EN + Timer8 clock enable + 1 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SPI4EN + SPI4 clock enable + 13 + 1 + + + SCFGEN + SCFG clock enable + 14 + 1 + + + TMR9EN + Timer9 clock enable + 16 + 1 + + + TMR10EN + Timer10 clock enable + 17 + 1 + + + TMR11EN + Timer11 clock enable + 18 + 1 + + + TMR20EN + Timer20 clock enable + 20 + 1 + + + ACCEN + ACC clock enable + 29 + 1 + + + + + AHBLPEN1 + AHBLPEN1 + AHB Low-power Peripheral Clock enable + register 1 (CRM_AHBLPEN1) + 0x50 + 0x20 + read-write + 0x3E6390FF + + + GPIOALPEN + IO A clock enable during sleep mode + 0 + 1 + + + GPIOBLPEN + IO B clock enable during sleep mode + 1 + 1 + + + GPIOCLPEN + IO C clock enable during sleep mode + 2 + 1 + + + GPIODLPEN + IO D clock enable during sleep mode + 3 + 1 + + + GPIOELPEN + IO E clock enable during sleep mode + 4 + 1 + + + GPIOFLPEN + IO F clock enable during sleep mode + 5 + 1 + + + GPIOGLPEN + IO G clock enable during sleep mode + 6 + 1 + + + GPIOHLPEN + IO H clock enable during sleep mode + 7 + 1 + + + CRCLPEN + CRC clock enable during sleep mode + 12 + 1 + + + FLASHLPEN + Flash clock enable during sleep mode + 15 + 1 + + + SRAM1LPEN + SRAM1 clock enable during sleep mode + 16 + 1 + + + SRAM2LPEN + SRAM2 clock enable during sleep mode + 17 + 1 + + + EDMALPEN + EDMA clock enable during sleep mode + 21 + 1 + + + DMA1LPEN + DMA1 clock enable during sleep mode + 22 + 1 + + + DMA2LPEN + DMA2 clock enable during sleep mode + 24 + 1 + + + EMACLPEN + EMAC clock enable during sleep mode + 25 + 1 + + + EMACTXLPEN + EMAC Tx clock enable during sleep mode + 26 + 1 + + + EMACRXLPEN + EMAC Rx clock enable during sleep mode + 27 + 1 + + + EMACPTPLPEN + EMAC PTP clock enable during sleep mode + 28 + 1 + + + OTGFS2LPEN + OTGFS2 clock enable during sleep mode + 29 + 1 + + + + + AHBLPEN2 + AHBLPEN2 + AHB peripheral Low-power clock + enable register 2 (CRM_AHBLPEN2) + 0x54 + 0x20 + read-write + 0x00008081 + + + DVPLPEN + DVP clock enable during sleep mode + 0 + 1 + + + OTGFS1LPEN + OTGFS1 clock enable during sleep mode + 7 + 1 + + + SDIO1LPEN + SDIO1 clock enable during sleep mode + 15 + 1 + + + + + AHBLPEN3 + AHBLPEN3 + AHB peripheral Low-power clock + enable register 3 (CRM_AHBLPEN3) + 0x58 + 0x20 + read-write + 0x0000C003 + + + XMCLPEN + XMC clock enable during sleep mode + 0 + 1 + + + QSPI1LPEN + QSPI1 clock enable during sleep mode + 1 + 1 + + + QSPI2LPEN + QSPI2 clock enable during sleep mode + 14 + 1 + + + SDIO2LPEN + SDIO2 clock enable during sleep mode + 15 + 1 + + + + + APB1LPEN + APB1LPEN + APB1 peripheral Low-power clock + enable register (CRM_APB1LPEN) + 0x60 + 0x20 + read-write + 0xF6FEE9FF + + + TMR2LPEN + Timer2 clock enable during sleep mode + 0 + 1 + + + TMR3LPEN + Timer3 clock enable during sleep mode + 1 + 1 + + + TMR4LPEN + Timer4 clock enable during sleep mode + 2 + 1 + + + TMR5LPEN + Timer5 clock enable during sleep mode + 3 + 1 + + + TMR6LPEN + Timer6 clock enable during sleep mode + 4 + 1 + + + TMR7LPEN + Timer7 clock enable during sleep mode + 5 + 1 + + + TMR12LPEN + Timer12 clock enable during sleep mode + 6 + 1 + + + TMR13LPEN + Timer13 clock enable during sleep mode + 7 + 1 + + + TMR14LPEN + Timer14 clock enable during sleep mode + 8 + 1 + + + WWDTLPEN + WWDT clock enable during sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during sleep mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during sleep mode + 15 + 1 + + + USART2LPEN + USART2 clock enable during sleep mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during sleep mode + 18 + 1 + + + UART4LPEN + UART4 clock enable during sleep mode + 19 + 1 + + + UART5LPEN + UART5 clock enable during sleep mode + 20 + 1 + + + I2C1CPEN + I2C1 clock enable during sleep mode + 21 + 1 + + + I2C2CPEN + I2C2 clock enable during sleep mode + 22 + 1 + + + I2C3CPEN + I2C3 clock enable during sleep mode + 23 + 1 + + + CAN1LPEN + CAN1 clock enable during sleep mode + 25 + 1 + + + CAN2LPEN + CAN2 clock enable during sleep mode + 26 + 1 + + + PWCLPEN + PWC clock enable during sleep mode + 28 + 1 + + + DACLPEN + DAC clock enable during sleep mode + 29 + 1 + + + UART7LPEN + UART7 clock enable during sleep mode + 30 + 1 + + + UART8LPEN + UART8 clock enable during sleep mode + 31 + 1 + + + + + APB2LPEN + APB2LPEN + APB2 peripheral Low-power clock + enable register (CRM_APB2LPEN) + 0x64 + 0x20 + read-write + 0x20177733 + + + TMR1LPEN + Timer1 clock enable during sleep mode + 0 + 1 + + + TMR8LPEN + Timer8 clock enable during sleep mode + 1 + 1 + + + USART1LPEN + USART1 clock enable during sleep mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during sleep mode + 5 + 1 + + + ADC1CPEN + ADC1 clock enable during sleep mode + 8 + 1 + + + ADC2CPEN + ADC2 clock enable during sleep mode + 9 + 1 + + + ADC3EN + ADC3 clock enable during sleep mode + 10 + 1 + + + SPI1LPEN + SPI1 clock enable during sleep mode + 12 + 1 + + + SPI4LPEN + SPI4 clock enable during sleep mode + 13 + 1 + + + SCFGLPEN + SCFG clock enable during sleep mode + 14 + 1 + + + TMR9LPEN + Timer9 clock enable during sleep mode + 16 + 1 + + + TMR10LPEN + Timer10 clock enable during sleep mode + 17 + 1 + + + TMR11LPEN + Timer11 clock enable during sleep mode + 18 + 1 + + + TMR20LPEN + Timer20 clock enable during sleep mode + 20 + 1 + + + ACCLPEN + ACC clock enable during sleep mode + 29 + 1 + + + + + BPDC + BPDC + Battery powered domain control register + (CRM_BPDC) + 0x70 + 0x20 + 0x00000000 + + + LEXTEN + Low speed external crystal enable + 0 + 1 + read-write + + + LEXTSTBL + Low speed external crystal ready + 1 + 1 + read-only + + + LEXTBYPS + Low speed external crystal bypass + 2 + 1 + read-write + + + ERTCSEL + ERTC clock source selection + 8 + 2 + read-write + + + ERTCEN + ERTC clock enable + 15 + 1 + read-write + + + BPDRST + Battery powered domain software reset + 16 + 1 + read-write + + + + + CTRLSTS + CTRLSTS + Control/status register + (CRM_CTRLSTS) + 0x74 + 0x20 + 0x0C000000 + + + LICKEN + Low speed internal clock enable + 0 + 1 + read-write + + + LICKSTBL + Low speed internal clock ready + 1 + 1 + read-only + + + RSTFC + Reset reset flag + 24 + 1 + read-write + + + NRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/LVR reset flag + 27 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + WDTRSTF + Watchdog timer reset flag + 29 + 1 + read-write + + + WWDTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + MISC1 + MISC1 + Miscellaneous register1 + 0xA0 + 0x20 + 0x00000000 + + + HICKCAL_KEY + HICKCAL write key value + 0 + 8 + read-write + + + HICKDIV + HICK 6 divider selection + 12 + 1 + read-write + + + HICK_TO_USB + HICK to usb clock + 13 + 1 + read-write + + + HICK_TO_SCLK + HICK to system clock + 14 + 1 + read-write + + + CLKOUT2_SEL2 + Clock output2 select2 + 16 + 4 + read-write + + + CLKOUT1DIV2 + Clock output1 division2 + 24 + 4 + read-write + + + CLKOUT2DIV2 + Clock output2 division2 + 28 + 4 + read-write + + + + + MISC2 + MISC2 + Miscellaneous register2 + 0xA4 + 0x20 + 0x0000000D + + + AUTO_STEP_EN + AUTO_STEP_EN + 4 + 2 + read-write + + + CLK_TO_TMR + Clock output internal connect to timer10 + 8 + 1 + read-write + + + USBDIV + USB division + 12 + 4 + read-write + + + + + + + GPIOA + General purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + CFGR + CFGR + GPIO configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + IOMC15 + GPIOx pin 15 mode configurate + 30 + 2 + + + IOMC14 + GPIOx pin 14 mode configurate + 28 + 2 + + + IOMC13 + GPIOx pin 13 mode configurate + 26 + 2 + + + IOMC12 + GPIOx pin 12 mode configurate + 24 + 2 + + + IOMC11 + GPIOx pin 11 mode configurate + 22 + 2 + + + IOMC10 + GPIOx pin 10 mode configurate + 20 + 2 + + + IOMC9 + GPIOx pin 9 mode configurate + 18 + 2 + + + IOMC8 + GPIOx pin 8 mode configurate + 16 + 2 + + + IOMC7 + GPIOx pin 7 mode configurate + 14 + 2 + + + IOMC6 + GPIOx pin 6 mode configurate + 12 + 2 + + + IOMC5 + GPIOx pin 5 mode configurate + 10 + 2 + + + IOMC4 + GPIOx pin 4 mode configurate + 8 + 2 + + + IOMC3 + GPIOx pin 3 mode configurate + 6 + 2 + + + IOMC2 + GPIOx pin 2 mode configurate + 4 + 2 + + + IOMC1 + GPIOx pin 1 mode configurate + 2 + 2 + + + IOMC0 + GPIOx pin 0 mode configurate + 0 + 2 + + + + + OMODE + OMODE + GPIO output mode register + 0x4 + 0x20 + read-write + 0x00000000 + + + OM15 + GPIOx pin 15 outpu mode configurate + 15 + 1 + + + OM14 + GPIOx pin 14 outpu mode configurate + 14 + 1 + + + OM13 + GPIOx pin 13 outpu mode configurate + 13 + 1 + + + OM12 + GPIOx pin 12 outpu mode configurate + 12 + 1 + + + OM11 + GPIOx pin 11 outpu mode configurate + 11 + 1 + + + OM10 + GPIOx pin 10 outpu mode configurate + 10 + 1 + + + OM9 + GPIOx pin 9 outpu mode configurate + 9 + 1 + + + OM8 + GPIOx pin 8 outpu mode configurate + 8 + 1 + + + OM7 + GPIOx pin 7 outpu mode configurate + 7 + 1 + + + OM6 + GPIOx pin 6 outpu mode configurate + 6 + 1 + + + OM5 + GPIOx pin 5 outpu mode configurate + 5 + 1 + + + OM4 + GPIOx pin 4 outpu mode configurate + 4 + 1 + + + OM3 + GPIOx pin 3 outpu mode configurate + 3 + 1 + + + OM2 + GPIOx pin 2 outpu mode configurate + 2 + 1 + + + OM1 + GPIOx pin 1 outpu mode configurate + 1 + 1 + + + OM0 + GPIOx pin 0 outpu mode configurate + 0 + 1 + + + + + ODRVR + ODRVR + GPIO drive capability register + 0x8 + 0x20 + read-write + 0x00000000 + + + ODRV15 + GPIOx pin 15 output drive capability + 30 + 2 + + + ODRV14 + GPIOx pin 14 output drive capability + 28 + 2 + + + ODRV13 + GPIOx pin 13 output drive capability + 26 + 2 + + + ODRV12 + GPIOx pin 12 output drive capability + 24 + 2 + + + ODRV11 + GPIOx pin 11 output drive capability + 22 + 2 + + + ODRV10 + GPIOx pin 10 output drive capability + 20 + 2 + + + ODRV9 + GPIOx pin 9 output drive capability + 18 + 2 + + + ODRV8 + GPIOx pin 8 output drive capability + 16 + 2 + + + ODRV7 + GPIOx pin 7 output drive capability + 14 + 2 + + + ODRV6 + GPIOx pin 6 output drive capability + 12 + 2 + + + ODRV5 + GPIOx pin 5 output drive capability + 10 + 2 + + + ODRV4 + GPIOx pin 4 output drive capability + 8 + 2 + + + ODRV3 + GPIOx pin 3 output drive capability + 6 + 2 + + + ODRV2 + GPIOx pin 2 output drive capability + 4 + 2 + + + ODRV1 + GPIOx pin 1 output drive capability + 2 + 2 + + + ODRV0 + GPIOx pin 0 output drive capability + 0 + 2 + + + + + PULL + PULL + GPIO pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PULL15 + GPIOx pin 15 pull configuration + 30 + 2 + + + PULL14 + GPIOx pin 14 pull configuration + 28 + 2 + + + PULL13 + GPIOx pin 13 pull configuration + 26 + 2 + + + PULL12 + GPIOx pin 12 pull configuration + 24 + 2 + + + PULL11 + GPIOx pin 11 pull configuration + 22 + 2 + + + PULL10 + GPIOx pin 10 pull configuration + 20 + 2 + + + PULL9 + GPIOx pin 9 pull configuration + 18 + 2 + + + PULL8 + GPIOx pin 8 pull configuration + 16 + 2 + + + PULL7 + GPIOx pin 7 pull configuration + 14 + 2 + + + PULL6 + GPIOx pin 6 pull configuration + 12 + 2 + + + PULL5 + GPIOx pin 5 pull configuration + 10 + 2 + + + PULL4 + GPIOx pin 4 pull configuration + 8 + 2 + + + PULL3 + GPIOx pin 3 pull configuration + 6 + 2 + + + PULL2 + GPIOx pin 2 pull configuration + 4 + 2 + + + PULL1 + GPIOx pin 1 pull configuration + 2 + 2 + + + PULL0 + GPIOx pin 0 pull configuration + 0 + 2 + + + + + IDT + IDT + GPIO input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDT0 + Port input data + 0 + 1 + + + IDT1 + Port input data + 1 + 1 + + + IDT2 + Port input data + 2 + 1 + + + IDT3 + Port input data + 3 + 1 + + + IDT4 + Port input data + 4 + 1 + + + IDT5 + Port input data + 5 + 1 + + + IDT6 + Port input data + 6 + 1 + + + IDT7 + Port input data + 7 + 1 + + + IDT8 + Port input data + 8 + 1 + + + IDT9 + Port input data + 9 + 1 + + + IDT10 + Port input data + 10 + 1 + + + IDT11 + Port input data + 11 + 1 + + + IDT12 + Port input data + 12 + 1 + + + IDT13 + Port input data + 13 + 1 + + + IDT14 + Port input data + 14 + 1 + + + IDT15 + Port input data + 15 + 1 + + + + + ODT + ODT + GPIO output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODT0 + Port output data + 0 + 1 + + + ODT1 + Port output data + 1 + 1 + + + ODT2 + Port output data + 2 + 1 + + + ODT3 + Port output data + 3 + 1 + + + ODT4 + Port output data + 4 + 1 + + + ODT5 + Port output data + 5 + 1 + + + ODT6 + Port output data + 6 + 1 + + + ODT7 + Port output data + 7 + 1 + + + ODT8 + Port output data + 8 + 1 + + + ODT9 + Port output data + 9 + 1 + + + ODT10 + Port output data + 10 + 1 + + + ODT11 + Port output data + 11 + 1 + + + ODT12 + Port output data + 12 + 1 + + + ODT13 + Port output data + 13 + 1 + + + ODT14 + Port output data + 14 + 1 + + + ODT15 + Port output data + 15 + 1 + + + + + SCR + SCR + Port bit set/clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + IOSB0 + Set bit 0 + 0 + 1 + + + IOSB1 + Set bit 1 + 1 + 1 + + + IOSB2 + Set bit 1 + 2 + 1 + + + IOSB3 + Set bit 3 + 3 + 1 + + + IOSB4 + Set bit 4 + 4 + 1 + + + IOSB5 + Set bit 5 + 5 + 1 + + + IOSB6 + Set bit 6 + 6 + 1 + + + IOSB7 + Set bit 7 + 7 + 1 + + + IOSB8 + Set bit 8 + 8 + 1 + + + IOSB9 + Set bit 9 + 9 + 1 + + + IOSB10 + Set bit 10 + 10 + 1 + + + IOSB11 + Set bit 11 + 11 + 1 + + + IOSB12 + Set bit 12 + 12 + 1 + + + IOSB13 + Set bit 13 + 13 + 1 + + + IOSB14 + Set bit 14 + 14 + 1 + + + IOSB15 + Set bit 15 + 15 + 1 + + + IOCB0 + Clear bit 0 + 16 + 1 + + + IOCB1 + Clear bit 1 + 17 + 1 + + + IOCB2 + Clear bit 2 + 18 + 1 + + + IOCB3 + Clear bit 3 + 19 + 1 + + + IOCB4 + Clear bit 4 + 20 + 1 + + + IOCB5 + Clear bit 5 + 21 + 1 + + + IOCB6 + Clear bit 6 + 22 + 1 + + + IOCB7 + Clear bit 7 + 23 + 1 + + + IOCB8 + Clear bit 8 + 24 + 1 + + + IOCB9 + Clear bit 9 + 25 + 1 + + + IOCB10 + Clear bit 10 + 26 + 1 + + + IOCB11 + Clear bit 11 + 27 + 1 + + + IOCB12 + Clear bit 12 + 28 + 1 + + + IOCB13 + Clear bit 13 + 29 + 1 + + + IOCB14 + Clear bit 14 + 30 + 1 + + + IOCB15 + Clear bit 15 + 31 + 1 + + + + + WPR + WPR + Port write protect + register + 0x1C + 0x20 + read-write + 0x00000000 + + + WPEN0 + Write protect enable 0 + 0 + 1 + + + WPEN1 + Write protect enable 1 + 1 + 1 + + + WPEN2 + Write protect enable 2 + 2 + 1 + + + WPEN3 + Write protect enable 3 + 3 + 1 + + + WPEN4 + Write protect enable 4 + 4 + 1 + + + WPEN5 + Write protect enable 5 + 5 + 1 + + + WPEN6 + Write protect enable 6 + 6 + 1 + + + WPEN7 + Write protect enable 7 + 7 + 1 + + + WPEN8 + Write protect enable 8 + 8 + 1 + + + WPEN9 + Write protect enable 9 + 9 + 1 + + + WPEN10 + Write protect enable 10 + 10 + 1 + + + WPEN11 + Write protect enable 11 + 11 + 1 + + + WPEN12 + Write protect enable 12 + 12 + 1 + + + WPEN13 + Write protect enable 13 + 13 + 1 + + + WPEN14 + Write protect enable 14 + 14 + 1 + + + WPEN15 + Write protect enable 15 + 15 + 1 + + + WPSEQ + Write protect sequence + 16 + 1 + + + + + MUXL + MUXL + GPIO muxing function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + MUXL7 + GPIOx pin 7 muxing + 28 + 4 + + + MUXL6 + GPIOx pin 6 muxing + 24 + 4 + + + MUXL5 + GPIOx pin 5 muxing + 20 + 4 + + + MUXL4 + GPIOx pin 4 muxing + 16 + 4 + + + MUXL3 + GPIOx pin 3 muxing + 12 + 4 + + + MUXL2 + GPIOx pin 2 muxing + 8 + 4 + + + MUXL1 + GPIOx pin 1 muxing + 4 + 4 + + + MUXL0 + GPIOx pin 0 muxing + 0 + 4 + + + + + MUXH + MUXH + GPIO muxing function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + MUXH15 + GPIOx pin 15 muxing + 28 + 4 + + + MUXH14 + GPIOx pin 14 muxing + 24 + 4 + + + MUXH13 + GPIOx pin 13 muxing + 20 + 4 + + + MUXH12 + GPIOx pin 12 muxing + 16 + 4 + + + MUXH11 + GPIOx pin 11 muxing + 12 + 4 + + + MUXH10 + GPIOx pin 10 muxing + 8 + 4 + + + MUXH9 + GPIOx pin 9 muxing + 4 + 4 + + + MUXH8 + GPIOx pin 8 muxing + 0 + 4 + + + + + CLR + CLR + GPIO bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + IOCB0 + Clear bit 0 + 0 + 1 + + + IOCB1 + Clear bit 1 + 1 + 1 + + + IOCB2 + Clear bit 1 + 2 + 1 + + + IOCB3 + Clear bit 3 + 3 + 1 + + + IOCB4 + Clear bit 4 + 4 + 1 + + + IOCB5 + Clear bit 5 + 5 + 1 + + + IOCB6 + Clear bit 6 + 6 + 1 + + + IOCB7 + Clear bit 7 + 7 + 1 + + + IOCB8 + Clear bit 8 + 8 + 1 + + + IOCB9 + Clear bit 9 + 9 + 1 + + + IOCB10 + Clear bit 10 + 10 + 1 + + + IOCB11 + Clear bit 11 + 11 + 1 + + + IOCB12 + Clear bit 12 + 12 + 1 + + + IOCB13 + Clear bit 13 + 13 + 1 + + + IOCB14 + Clear bit 14 + 14 + 1 + + + IOCB15 + Clear bit 15 + 15 + 1 + + + + + HDRV + HDRV + Huge current driver + 0x3C + 0x20 + read-write + 0x00000000 + + + HDRV0 + Port x driver bit y + 0 + 1 + + + HDRV1 + Port x driver bit y + 1 + 1 + + + HDRV2 + Port x driver bit y + 2 + 1 + + + HDRV3 + Port x driver bit y + 3 + 1 + + + HDRV4 + Port x driver bit y + 4 + 1 + + + HDRV5 + Port x driver bit y + 5 + 1 + + + HDRV6 + Port x driver bit y + 6 + 1 + + + HDRV7 + Port x driver bit y + 7 + 1 + + + HDRV8 + Port x driver bit y + 8 + 1 + + + HDRV9 + Port x driver bit y + 9 + 1 + + + HDRV10 + Port x driver bit y + 10 + 1 + + + HDRV11 + Port x driver bit y + 11 + 1 + + + HDRV12 + Port x driver bit y + 12 + 1 + + + HDRV13 + Port x driver bit y + 13 + 1 + + + HDRV14 + Port x driver bit y + 14 + 1 + + + HDRV15 + Port x driver bit y + 15 + 1 + + + + + + + GPIOB + 0x40020400 + + + GPIOC + 0x40020800 + + + GPIOD + 0x40020C00 + + + GPIOE + 0x40021000 + + + GPIOF + 0x40021400 + + + GPIOG + 0x40021800 + + + GPIOH + 0x40021C00 + + + EXINT + EXINT + EXINT + 0x40013C00 + + 0x0 + 0x400 + registers + + + EXINT0 + EXINT Line0 interrupt + 6 + + + EXINT1 + EXINT Line1 interrupt + 7 + + + EXINT2 + EXINT Line2 interrupt + 8 + + + EXINT3 + EXINT Line3 interrupt + 9 + + + EXINT4 + EXINT Line4 interrupt + 10 + + + EXINT9_5 + EXINT Line[9:5] interrupts + 23 + + + EXINT15_10 + EXINT Line[15:10] interrupts + 40 + + + PVM + PVM interrupt connect to EXINT line16 + 1 + + + ERTCALARM + ERTC Alarm interrupt connect to EXINT line17 + 41 + + + OTGFS1_WKUP + OTGFS1_WKUP interrupt connect to EXINT line18 + 42 + + + EMAC_WKUP + EMAC_WKUP interrupt connect to EXINT line19 + 62 + + + OTGFS2_WKUP + OTGFS2_WKUP interrupt connect to EXINT line20 + 76 + + + TAMPER + Tamper interrupt connect to EXINT line21 + 2 + + + ERTC_WKUP + ERTC Global interrupt connect to EXINT line22 + 3 + + + + INTEN + INTEN + Interrupt enable register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTEN0 + Interrupt enable or disable on line 0 + 0 + 1 + + + INTEN1 + Interrupt enable or disable on line 1 + 1 + 1 + + + INTEN2 + Interrupt enable or disable on line 2 + 2 + 1 + + + INTEN3 + Interrupt enable or disable on line 3 + 3 + 1 + + + INTEN4 + Interrupt enable or disable on line 4 + 4 + 1 + + + INTEN5 + Interrupt enable or disable on line 5 + 5 + 1 + + + INTEN6 + Interrupt enable or disable on line 6 + 6 + 1 + + + INTEN7 + Interrupt enable or disable on line 7 + 7 + 1 + + + INTEN8 + Interrupt enable or disable on line 8 + 8 + 1 + + + INTEN9 + Interrupt enable or disable on line 9 + 9 + 1 + + + INTEN10 + Interrupt enable or disable on line 10 + 10 + 1 + + + INTEN11 + Interrupt enable or disable on line 11 + 11 + 1 + + + INTEN12 + Interrupt enable or disable on line 12 + 12 + 1 + + + INTEN13 + Interrupt enable or disable on line 13 + 13 + 1 + + + INTEN14 + Interrupt enable or disable on line 14 + 14 + 1 + + + INTEN15 + Interrupt enable or disable on line 15 + 15 + 1 + + + INTEN16 + Interrupt enable or disable on line 16 + 16 + 1 + + + INTEN17 + Interrupt enable or disable on line 17 + 17 + 1 + + + INTEN18 + Interrupt enable or disable on line 18 + 18 + 1 + + + INTEN19 + Interrupt enable or disable on line 19 + 19 + 1 + + + INTEN20 + Interrupt enable or disable on line 20 + 20 + 1 + + + INTEN21 + Interrupt enable or disable on line 21 + 21 + 1 + + + INTEN22 + Interrupt enable or disable on line 22 + 22 + 1 + + + + + EVTEN + EVTEN + Event enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + EVTEN0 + Event enable or disable on line 0 + 0 + 1 + + + EVTEN1 + Event enable or disable on line 1 + 1 + 1 + + + EVTEN2 + Event enable or disable on line 2 + 2 + 1 + + + EVTEN3 + Event enable or disable on line 3 + 3 + 1 + + + EVTEN4 + Event enable or disable on line 4 + 4 + 1 + + + EVTEN5 + Event enable or disable on line 5 + 5 + 1 + + + EVTEN6 + Event enable or disable on line 6 + 6 + 1 + + + EVTEN7 + Event enable or disable on line 7 + 7 + 1 + + + EVTEN8 + Event enable or disable on line 8 + 8 + 1 + + + EVTEN9 + Event enable or disable on line 9 + 9 + 1 + + + EVTEN10 + Event enable or disable on line 10 + 10 + 1 + + + EVTEN11 + Event enable or disable on line 11 + 11 + 1 + + + EVTEN12 + Event enable or disable on line 12 + 12 + 1 + + + EVTEN13 + Event enable or disable on line 13 + 13 + 1 + + + EVTEN14 + Event enable or disable on line 14 + 14 + 1 + + + EVTEN15 + Event enable or disable on line 15 + 15 + 1 + + + EVTEN16 + Event enable or disable on line 16 + 16 + 1 + + + EVTEN17 + Event enable or disable on line 17 + 17 + 1 + + + EVTEN18 + Event enable or disable on line 18 + 18 + 1 + + + EVTEN19 + Event enable or disable on line 19 + 19 + 1 + + + EVTEN20 + Event enable or disable on line 20 + 20 + 1 + + + EVTEN21 + Event enable or disable on line 21 + 21 + 1 + + + EVTEN22 + Event enable or disable on line 22 + 22 + 1 + + + + + POLCFG1 + POLCFG1 + Rising polarity configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + RP0 + Rising polarity configuration bit of line 0 + 0 + 1 + + + RP1 + Rising polarity configuration bit of line 1 + 1 + 1 + + + RP2 + Rising polarity configuration bit of line 2 + 2 + 1 + + + RP3 + Rising polarity configuration bit of line 3 + 3 + 1 + + + RP4 + Rising polarity configuration bit of line 4 + 4 + 1 + + + RP5 + Rising polarity configuration bit of line 5 + 5 + 1 + + + RP6 + Rising polarity configuration bit of linee 6 + 6 + 1 + + + RP7 + Rising polarity configuration bit of line 7 + 7 + 1 + + + RP8 + Rising polarity configuration bit of line 8 + 8 + 1 + + + RP9 + Rising polarity configuration bit of line 9 + 9 + 1 + + + RP10 + Rising polarity configuration bit of line 10 + 10 + 1 + + + RP11 + Rising polarity configuration bit of line 11 + 11 + 1 + + + RP12 + Rising polarity configuration bit of line 12 + 12 + 1 + + + RP13 + Rising polarity configuration bit of line 13 + 13 + 1 + + + RP14 + Rising polarity configuration bit of line 14 + 14 + 1 + + + RP15 + Rising polarity configuration bit of line 15 + 15 + 1 + + + RP16 + Rising polarity configuration bit of line 16 + 16 + 1 + + + RP17 + Rising polarity configuration bit of line 17 + 17 + 1 + + + RP18 + Rising polarity configuration bit of line 18 + 18 + 1 + + + RP19 + Rising polarity configuration bit of line 19 + 19 + 1 + + + RP20 + Rising polarity configuration bit of line 20 + 20 + 1 + + + RP21 + Rising polarity configuration bit of line 21 + 21 + 1 + + + RP22 + Rising polarity configuration bit of line 22 + 22 + 1 + + + + + POLCFG2 + POLCFG2 + Falling polarity configuration register + 0xC + 0x20 + read-write + 0x00000000 + + + FP0 + Falling polarity event configuration bit of line 0 + 0 + 1 + + + FP1 + Falling polarity event configuration bit of line 1 + 1 + 1 + + + FP2 + Falling polarity event configuration bit of line 2 + 2 + 1 + + + FP3 + Falling polarity event configuration bit of line 3 + 3 + 1 + + + FP4 + Falling polarity event configuration bit of line 4 + 4 + 1 + + + FP5 + Falling polarity event configuration bit of line 5 + 5 + 1 + + + FP6 + Falling polarity event configuration bit of line 6 + 6 + 1 + + + FP7 + Falling polarity event configuration bit of line 7 + 7 + 1 + + + FP8 + Falling polarity event configuration bit of line 8 + 8 + 1 + + + FP9 + Falling polarity event configuration bit of line 9 + 9 + 1 + + + FP10 + Falling polarity event configuration bit of line 10 + 10 + 1 + + + FP11 + Falling polarity event configuration bit of line 11 + 11 + 1 + + + FP12 + Falling polarity event configuration bit of line 12 + 12 + 1 + + + FP13 + Falling polarity event configuration bit of line 13 + 13 + 1 + + + FP14 + Falling polarity event configuration bit of line 14 + 14 + 1 + + + FP15 + Falling polarity event configuration bit of line 15 + 15 + 1 + + + FP16 + Falling polarity event configuration bit of line 16 + 16 + 1 + + + FP17 + Falling polarity event configuration bit of line 17 + 17 + 1 + + + FP18 + Falling polarity event configuration bit of line 18 + 18 + 1 + + + FP19 + Falling polarity event configuration bit of line 19 + 19 + 1 + + + FP20 + Falling polarity event configuration bit of line 20 + 20 + 1 + + + FP21 + Falling polarity event configuration bit of line 21 + 21 + 1 + + + FP22 + Falling polarity event configuration bit of line 22 + 22 + 1 + + + + + SWTRG + SWTRG + Software triggle register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWT0 + Software triggle on line 0 + 0 + 1 + + + SWT1 + Software triggle on line 1 + 1 + 1 + + + SWT2 + Software triggle on line 2 + 2 + 1 + + + SWT3 + Software triggle on line 3 + 3 + 1 + + + SWT4 + Software triggle on line 4 + 4 + 1 + + + SWT5 + Software triggle on line 5 + 5 + 1 + + + SWT6 + Software triggle on line 6 + 6 + 1 + + + SWT7 + Software triggle on line 7 + 7 + 1 + + + SWT8 + Software triggle on line 8 + 8 + 1 + + + SWT9 + Software triggle on line 9 + 9 + 1 + + + SWT10 + Software triggle on line 10 + 10 + 1 + + + SWT11 + Software triggle on line 11 + 11 + 1 + + + SWT12 + Software triggle on line 12 + 12 + 1 + + + SWT13 + Software triggle on line 13 + 13 + 1 + + + SWT14 + Software triggle on line 14 + 14 + 1 + + + SWT15 + Software triggle on line 15 + 15 + 1 + + + SWT16 + Software triggle on line 16 + 16 + 1 + + + SWT17 + Software triggle on line 17 + 17 + 1 + + + SWT18 + Software triggle on line 18 + 18 + 1 + + + SWT19 + Software triggle on line 19 + 19 + 1 + + + SWT20 + Software triggle on line 20 + 20 + 1 + + + SWT21 + Software triggle on line 21 + 21 + 1 + + + SWT22 + Software triggle on line 22 + 22 + 1 + + + + + INTSTS + INTSTS + Interrupt status register + 0x14 + 0x20 + read-write + 0x00000000 + + + LINE0 + Line 0 state bit + 0 + 1 + + + LINE1 + Line 1 state bit + 1 + 1 + + + LINE2 + Line 2 state bit + 2 + 1 + + + LINE3 + Line 3 state bit + 3 + 1 + + + LINE4 + Line 4 state bit + 4 + 1 + + + LINE5 + Line 5 state bit + 5 + 1 + + + LINE6 + Line 6 state bit + 6 + 1 + + + LINE7 + Line 7 state bit + 7 + 1 + + + LINE8 + Line 8 state bit + 8 + 1 + + + LINE9 + Line 9 state bit + 9 + 1 + + + LINE10 + Line 10 state bit + 10 + 1 + + + LINE11 + Line 11 state bit + 11 + 1 + + + LINE12 + Line 12 state bit + 12 + 1 + + + LINE13 + Line 13 state bit + 13 + 1 + + + LINE14 + Line 14 state bit + 14 + 1 + + + LINE15 + Line 15 state bit + 15 + 1 + + + LINE16 + Line 16 state bit + 16 + 1 + + + LINE17 + Line 17 state bit + 17 + 1 + + + LINE18 + Line 18 state bit + 18 + 1 + + + LINE19 + Line 19 state bit + 19 + 1 + + + LINE20 + Line 20 state bit + 20 + 1 + + + LINE21 + Line 21 state bit + 21 + 1 + + + LINE22 + Line 22 state bit + 22 + 1 + + + + + + + EDMA + EDMA controller + EDMA + 0x40026000 + + 0x0 + 0x400 + registers + + + EDMA_Stream1 + EDMA Stream1 global interrupt + 11 + + + EDMA_Stream2 + EDMA Stream2 global interrupt + 12 + + + EDMA_Stream3 + EDMA Stream3 global interrupt + 13 + + + EDMA_Stream4 + EDMA Stream4 global interrupt + 14 + + + EDMA_Stream5 + EDMA Stream5 global interrupt + 15 + + + EDMA_Stream6 + EDMA Stream6 global interrupt + 16 + + + EDMA_Stream7 + EDMA Stream7 global interrupt + 17 + + + EDMA_Stream8 + EDMA Stream8 global interrupt + 47 + + + + STS1 + STS1 + Interrupt status register1 + 0x0 + 0x20 + read-only + 0x00000000 + + + FDTF4 + Stream 4 Full data transfer interrupt flag + + 27 + 1 + + + HDTF4 + Stream 4 half data transfer interrupt flag + + 26 + 1 + + + DTERRF4 + Stream 4 transfer error interrupt flag + + 25 + 1 + + + DMERRF4 + Stream 4 direct mode error interrupt flag + + 24 + 1 + + + FERRF4 + Stream 4 FIFO error interrupt flag + + 22 + 1 + + + FDTF3 + Stream 3 Full data transfer interrupt flag + + 21 + 1 + + + HDTF3 + Stream 3 half data transfer interrupt flag + + 20 + 1 + + + DTERRF3 + Stream 3 transfer error interrupt flag + + 19 + 1 + + + DMERRF3 + Stream 3 direct mode error interrupt flag + + 18 + 1 + + + FERRF3 + Stream 3 FIFO error interrupt flag + + 16 + 1 + + + FDTF2 + Stream 2 Full data transfer interrupt flag + + 11 + 1 + + + HDTF2 + Stream 2 half data transfer interrupt flag + + 10 + 1 + + + DTERRF2 + Stream 2 transfer error interrupt flag + + 9 + 1 + + + DMERRF2 + Stream 2 direct mode error interrupt flag + + 8 + 1 + + + FERRF2 + Stream 2 FIFO error interrupt flag + + 6 + 1 + + + FDTF1 + Stream 1 Full data transfer interrupt flag + + 5 + 1 + + + HDTF1 + Stream 1 half data transfer interrupt flag + + 4 + 1 + + + DTERRF1 + Stream 1 transfer error interrupt flag + + 3 + 1 + + + DMERRF1 + Stream 1 direct mode error interrupt flag + + 2 + 1 + + + FERRF1 + Stream 1 FIFO error interrupt flag + + 0 + 1 + + + + + STS2 + STS2 + Interrupt status register2 + 0x4 + 0x20 + read-only + 0x00000000 + + + FDTF8 + Stream 8 full data transfer interrupt flag + + 27 + 1 + + + HDTF8 + Stream 8 half data transfer interrupt flag + + 26 + 1 + + + DTERRF8 + Stream 8 transfer error interrupt flag + + 25 + 1 + + + DMERRF8 + Stream 8 direct mode error interrupt flag + + 24 + 1 + + + FERRF8 + Stream 8 FIFO error interrupt flag + + 22 + 1 + + + FDTF7 + Stream 7 full data transfer interrupt flag + + 21 + 1 + + + HDTF7 + Stream 7 half data transfer interrupt flag + + 20 + 1 + + + DTERRF7 + Stream 7 transfer error interrupt flag + + 19 + 1 + + + DMERRF7 + Stream 7 direct mode error interrupt flag + + 18 + 1 + + + FERRF7 + Stream 7 FIFO error interrupt flag + + 16 + 1 + + + FDTF6 + Stream 6 full data transfer interrupt flag + + 11 + 1 + + + HDTF6 + Stream 6 half data transfer interrupt flag + + 10 + 1 + + + DTERRF6 + Stream 6 transfer error interrupt flag + + 9 + 1 + + + DMERRF6 + Stream 6 direct mode error interrupt flag + + 8 + 1 + + + FERRF6 + Stream 6 FIFO error interrupt flag + + 6 + 1 + + + FDTF5 + Stream 5 full data transfer interrupt flag + + 5 + 1 + + + HDTF5 + Stream 5 half data transfer interrupt flag + + 4 + 1 + + + DTERRF5 + Stream 5 transfer error interrupt flag + + 3 + 1 + + + DMERRF5 + Stream 5 direct mode error interrupt flag + + 2 + 1 + + + FERRF5 + Stream 5 FIFO error interrupt flag + + 0 + 1 + + + + + CLR1 + CLR1 + Interrupt flag clear register1 + + 0x8 + 0x20 + read-write + 0x00000000 + + + FDTFC4 + Stream 4 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC4 + Stream 4 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC4 + Stream 4 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC4 + Stream 4 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC4 + Stream 4 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC3 + Stream 3 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC3 + Stream 3 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC3 + Stream 3 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC3 + Stream 3 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC3 + Stream 3 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC2 + Stream 2 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC2 + Stream 2 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC2 + Stream 2 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC2 + Stream 2 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC2 + Stream 2 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC1 + Stream 1 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC1 + Stream 1 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC1 + Stream 1 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC1 + Stream 1 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC1 + Stream 1 clear FIFO error interrupt flag + + 0 + 1 + + + + + CLR2 + CLR2 + Interrupt flag clear register2 + + 0xC + 0x20 + read-write + 0x00000000 + + + FDTFC8 + Stream 8 clear full data transfer complete interrupt flag + + 27 + 1 + + + HDTFC8 + Stream 8 clear half data transfer interrupt flag + + 26 + 1 + + + DTERRFC8 + Stream 8 clear transfer error interrupt flag + + 25 + 1 + + + DMERRFC8 + Stream 8 clear direct mode error interrupt flag + + 24 + 1 + + + FERRFC8 + Stream 8 clear FIFO error interrupt flag + + 22 + 1 + + + FDTFC7 + Stream 7 clear full data transfer complete interrupt flag + + 21 + 1 + + + HDTFC7 + Stream 7 clear half data transfer interrupt flag + + 20 + 1 + + + DTERRFC7 + Stream 7 clear transfer error interrupt flag + + 19 + 1 + + + DMERRFC7 + Stream 7 clear direct mode error interrupt flag + + 18 + 1 + + + FERRFC7 + Stream 7 clear FIFO error interrupt flag + + 16 + 1 + + + FDTFC6 + Stream 6 clear full data transfer complete interrupt flag + + 11 + 1 + + + HDTFC6 + Stream 6 clear half data transfer interrupt flag + + 10 + 1 + + + DTERRFC6 + Stream 6 clear transfer error interrupt flag + + 9 + 1 + + + DMERRFC6 + Stream 6 clear direct mode error interrupt flag + + 8 + 1 + + + FERRFC6 + Stream 6 clear FIFO error interrupt flag + + 6 + 1 + + + FDTFC5 + Stream 5 clear full data transfer complete interrupt flag + + 5 + 1 + + + HDTFC5 + Stream 5 clear half data transfer interrupt flag + + 4 + 1 + + + DTERRFC5 + Stream 5 clear transfer error interrupt flag + + 3 + 1 + + + DMERRFC5 + Stream 5 clear direct mode error interrupt flag + + 2 + 1 + + + FERRFC5 + Stream 5 clear FIFO error interrupt flag + + 0 + 1 + + + + + S1CTRL + S1CTRL + stream 1 control + register + 0x10 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S1DTCNT + S1DTCNT + stream 1 number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S1PADDR + S1PADDR + stream 1 peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S1M0ADDR + S1M0ADDR + stream 1 memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S1M1ADDR + S1M1ADDR + stream 1 memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S1FCTRL + S1FCTRL + stream 1 FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S2CTRL + S2CTRL + stream 2 control + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S2DTCNT + S2DTCNT + stream 2 number of data + register + 0x2C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S2PADDR + S2PADDR + stream 2 peripheral address + register + 0x30 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S2M0ADDR + S2M0ADDR + stream 2 memory 0 address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S2M1ADDR + S2M1ADDR + stream 2 memory 1 address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S2FCTRL + S2FCTRL + stream 2 FIFO control register + 0x3C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S3CTRL + S3CTRL + stream 3 control + register + 0x40 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S3DTCNT + S3DTCNT + stream 3 number of data + register + 0x44 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S3PADDR + S3PADDR + stream 3 peripheral address + register + 0x48 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S3M0ADDR + S3M0ADDR + stream 3 memory 0 address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S3M1ADDR + S3M1ADDR + stream 3 memory 1 address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S3FCTRL + S3FCTRL + stream 3 FIFO control register + 0x54 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S4CTRL + S4CTRL + stream 4 control + register + 0x58 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S4DTCNT + S4DTCNT + stream 4 number of data + register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S4PADDR + S4PADDR + stream 4 peripheral address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S4M0ADDR + S4M0ADDR + stream 4 memory 0 address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S4M1ADDR + S4M1ADDR + stream 4 memory 1 address + register + 0x68 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S4FCTRL + S4FCTRL + stream 4 FIFO control register + 0x6C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S5CTRL + S5CTRL + stream 5 control + register + 0x70 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S5DTCNT + S5DTCNT + stream 5 number of data + register + 0x74 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S5PADDR + S5PADDR + stream 5 peripheral address + register + 0x78 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S5M0ADDR + S5M0ADDR + stream 5 memory 0 address + register + 0x7C + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S5M1ADDR + S5M1ADDR + stream 5 memory 1 address + register + 0x80 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S5FCTRL + S5FCTRL + stream 5 FIFO control register + 0x84 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S6CTRL + S6CTRL + stream 6 control + register + 0x88 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S6DTCNT + S6DTCNT + stream 6 number of data + register + 0x8C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S6PADDR + S6PADDR + stream 6 peripheral address + register + 0x90 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S6M0ADDR + S6M0ADDR + stream 6 memory 0 address + register + 0x94 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S6M1ADDR + S6M1ADDR + stream 6 memory 1 address + register + 0x98 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S6FCTRL + S6FCTRL + stream 6 FIFO control register + 0x9C + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S7CTRL + S7CTRL + stream 7 control + register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S7DTCNT + S7DTCNT + stream 7 number of data + register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S7PADDR + S7PADDR + stream 7 peripheral address + register + 0xA8 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S7M0ADDR + S7M0ADDR + stream 7 memory 0 address + register + 0xAC + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S7M1ADDR + S7M1ADDR + stream 7 memory 1 address + register + 0xB0 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S7FCTRL + S7FCTRL + stream 7 FIFO control register + 0xB4 + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + S8CTRL + S8CTRL + stream 8 control + register + 0xB8 + 0x20 + read-write + 0x00000000 + + + MBURST + Memory burst transmission + + 23 + 2 + + + PBURST + Peripheral burst transmission + + 21 + 2 + + + CM + Current memory (only in double buffer + mode) + 19 + 1 + + + DMM + Double memory mode + 18 + 1 + + + SPL + Stream priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MWIDTH + Memory data width + 13 + 2 + + + PWIDTH + Peripheral data width + 11 + 2 + + + MINCM + Memory increment mode + 10 + 1 + + + PINCM + Peripheral increment mode + 9 + 1 + + + LM + Loop mode + 8 + 1 + + + DTD + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + FDTIEN + Full data transfer complete interrupt + enable + 4 + 1 + + + HDTIEN + Half data transfer interrupt + enable + 3 + 1 + + + DTERRIEN + Transfer error interrupt + enable + 2 + 1 + + + DMERRIEN + Direct mode error interrupt + enable + 1 + 1 + + + SEN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S8DTCNT + S8DTCNT + stream 8 number of data + register + 0xBC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data items to + transfer + 0 + 16 + + + + + S8PADDR + S8PADDR + stream 8 peripheral address + register + 0xC0 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + S8M0ADDR + S8M0ADDR + stream 8 memory 0 address + register + 0xC4 + 0x20 + read-write + 0x00000000 + + + M0ADDR + Memory 0 address + 0 + 32 + + + + + S8M1ADDR + S8M1ADDR + stream 8 memory 1 address + register + 0xC8 + 0x20 + read-write + 0x00000000 + + + M1ADDR + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S8FCTRL + S8FCTRL + stream 8 FIFO control register + 0xCC + 0x20 + 0x00000021 + + + FERRIEN + FIFO error interrupt + enable + 7 + 1 + read-write + + + FSTS + FIFO status + 3 + 3 + read-only + + + FEN + FIFO mode enable + 2 + 1 + read-write + + + FTHSEL + FIFO threshold selection + 0 + 2 + read-write + + + + + LLCTRL + LLCTRL + DMA Link List Control Register + 0xD0 + 0x20 + 0x00000000 + + + S1LLEN + Stream 1 link list enable + 0 + 1 + read-write + + + S2LLEN + Stream 2 link list enable + 1 + 1 + read-write + + + S3LLEN + Stream 3 link list enable + 2 + 1 + read-write + + + S4LLEN + Stream 4 link list enable + 3 + 1 + read-write + + + S5LLEN + Stream 5 link list enable + 4 + 1 + read-write + + + S6LLEN + Stream 6 link list enable + 5 + 1 + read-write + + + S7LLEN + Stream 7 link list enable + 6 + 1 + read-write + + + S8LLEN + Stream 8 link list enable + 7 + 1 + read-write + + + + + S1LLP + S1LLP + Stream 1 Link List Pointer + 0xD4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2LLP + S2LLP + Stream 2 Link List Pointer + 0xD8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S3LLP + S3LLP + Stream 3 Link List Pointer + 0xDC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S4LLP + S4LLP + Stream 4 Link List Pointer + 0xE0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S5LLP + S5LLP + Stream 5 Link List Pointer + 0xE4 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S6LLP + S6LLP + Stream 6 Link List Pointer + 0xE8 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S7LLP + S7LLP + Stream 7 Link List Pointer + 0xEC + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S8LLP + S8LLP + Stream 8 Link List Pointer + 0xF0 + 0x20 + 0x00000000 + + + LLP + Link list pointer + 0 + 32 + read-write + + + + + S2DCTRL + S2DCTRL + EDMA 2D Transfer Control Register + 0xF4 + 0x20 + 0x00000000 + + + S1_2DEN + Stream 1 2D transfer enable + 0 + 1 + read-write + + + S2_2DEN + Stream 2 2D transfer enable + 1 + 1 + read-write + + + S3_2DEN + Stream 3 2D transfer enable + 2 + 1 + read-write + + + S4_2DEN + Stream 4 2D transfer enable + 3 + 1 + read-write + + + S5_2DEN + Stream 5 2D transfer enable + 4 + 1 + read-write + + + S6_2DEN + Stream 6 2D transfer enable + 5 + 1 + read-write + + + S7_2DEN + Stream 7 2D transfer enable + 6 + 1 + read-write + + + S8_2DEN + Stream 8 2D transfer enable + 7 + 1 + read-write + + + + + S1_2DCNT + S1_2DCNT + Stream 1 2D Transfer Count + 0xF8 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S1_STRIDE + S1_STRIDE + Stream 1 2D Transfer Stride + 0xFC + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S2_2DCNT + S2_2DCNT + Stream 2 2D Transfer Count + 0x100 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S2_STRIDE + S2_STRIDE + Stream 2 2D Transfer Stride + 0x104 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S3_2DCNT + S3_2DCNT + Stream 3 2D Transfer Count + 0x108 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S3_STRIDE + S3_STRIDE + Stream 3 2D Transfer Stride + 0x10C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S4_2DCNT + S4_2DCNT + Stream 4 2D Transfer Count + 0x110 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S4_STRIDE + S4_STRIDE + Stream 4 2D Transfer Stride + 0x114 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S5_2DCNT + S5_2DCNT + Stream 5 2D Transfer Count + 0x118 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S5_STRIDE + S5_STRIDE + Stream 5 2D Transfer Stride + 0x11C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S6_2DCNT + S6_2DCNT + Stream 6 2D Transfer Count + 0x120 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S6_STRIDE + S6_STRIDE + Stream 6 2D Transfer Stride + 0x124 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S7_2DCNT + S7_2DCNT + Stream 7 2D Transfer Count + 0x128 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S7_STRIDE + S7_STRIDE + Stream 7 2D Transfer Stride + 0x12C + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + S8_2DCNT + S8_2DCNT + Stream 8 2D Transfer Count + 0x130 + 0x20 + 0x00000000 + + + XCONUT + X dimension transfer count + 0 + 16 + read-write + + + YCONUT + Y dimension transfer count + 16 + 16 + read-write + + + + + S8_STRIDE + S8_STRIDE + Stream 8 2D Transfer Stride + 0x134 + 0x20 + 0x00000000 + + + SRCSTD + Source stride + 0 + 16 + read-write + + + DSTSTD + Destination stride + 16 + 16 + read-write + + + + + SYNCEN + SYNCEN + Sync Enable + 0x138 + 0x20 + 0x00000000 + + + S1SYNC + Stream 1 sync enable + 0 + 1 + read-write + + + S2SYNC + Stream 2 sync enable + 1 + 1 + read-write + + + S3SYNC + Stream 3 sync enable + 2 + 1 + read-write + + + S4SYNC + Stream 4 sync enable + 3 + 1 + read-write + + + S5SYNC + Stream 5 sync enable + 4 + 1 + read-write + + + S6SYNC + Stream 6 sync enable + 5 + 1 + read-write + + + S7SYNC + Stream 7 sync enable + 6 + 1 + read-write + + + S8SYNC + Stream 8 sync enable + 7 + 1 + read-write + + + + + MUXSEL + MUXSEL + EDMA MUX Table Selection + 0x13C + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXS1CTRL + MUXS1CTRL + Stream 1 Configuration Register + 0x140 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS2CTRL + MUXS2CTRL + Stream 2 Configuration Register + 0x144 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS3CTRL + MUXS3CTRL + Stream 3 Configuration Register + 0x148 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS4CTRL + MUXS4CTRL + Stream 4 Configuration Register + 0x14C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS5CTRL + MUXS5CTRL + Stream x Configuration Register + 0x150 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS6CTRL + MUXS6CTRL + Stream 6 Configuration Register + 0x154 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS7CTRL + MUXS7CTRL + Stream 7 Configuration Register + 0x158 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXS8CTRL + MUXS8CTRL + Stream 8 Configuration Register + 0x15C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization select + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x160 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x164 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x168 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x16C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x170 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + SYNCOVF8 + Synchronizaton overrun interrupt flag + 7 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x174 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + SYNCOVFC8 + Clear synchronizaton overrun interrupt flag + 7 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x178 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x17C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA1 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x200 + registers + + + DMA1_Channel1 + DMA1 Channel1 global interrupt + 56 + + + DMA1_Channel2 + DMA1 Channel2 global interrupt + 57 + + + DMA1_Channel3 + DMA1 Channel3 global interrupt + 58 + + + DMA1_Channel4 + DMA1 Channel4 global interrupt + 59 + + + DMA1_Channel5 + DMA1 Channel5 global interrupt + 60 + + + DMA1_Channel6 + DMA1 Channel6 global interrupt + 68 + + + DMA1_Channel7 + DMA1 Channel7 global interrupt + 69 + + + + STS + STS + DMA interrupt status register + (DMA_STS) + 0x0 + 0x20 + read-only + 0x00000000 + + + GF1 + Channel 1 Global event flag + 0 + 1 + + + FDTF1 + Channel 1 full data transfer event flag + 1 + 1 + + + HDTF1 + Channel 1 half data transfer event flag + 2 + 1 + + + DTERRF1 + Channel 1 data transfer error event flag + 3 + 1 + + + GF2 + Channel 2 Global event flag + 4 + 1 + + + FDTF2 + Channel 2 full data transfer event flag + 5 + 1 + + + HDTF2 + Channel 2 half data transfer event flag + 6 + 1 + + + DTERRF2 + Channel 2 data transfer error event flag + 7 + 1 + + + GF3 + Channel 3 Global event flag + 8 + 1 + + + FDTF3 + Channel 3 full data transfer event flag + 9 + 1 + + + HDTF3 + Channel 3 half data transfer event flag + 10 + 1 + + + DTERRF3 + Channel 3 data transfer error event flag + 11 + 1 + + + GF4 + Channel 4 Global event flag + 12 + 1 + + + FDTF4 + Channel 4 full data transfer event flag + 13 + 1 + + + HDTF4 + Channel 4 half data transfer event flag + 14 + 1 + + + DTERRF4 + Channel 4 data transfer error event flag + 15 + 1 + + + GF5 + Channel 5 Global event flag + 16 + 1 + + + FDTF5 + Channel 5 full data transfer event flag + 17 + 1 + + + HDTF5 + Channel 5 half data transfer event flag + 18 + 1 + + + DTERRF5 + Channel 5 data transfer error event flag + 19 + 1 + + + GF6 + Channel 6 Global event flag + 20 + 1 + + + FDTF6 + Channel 6 full data transfer event flag + 21 + 1 + + + HDTF6 + Channel 6 half data transfer event flag + 22 + 1 + + + DTERRF6 + Channel 6 data transfer error event flag + 23 + 1 + + + GF7 + Channel 7 Global event flag + 24 + 1 + + + FDTF7 + Channel 7 full data transfer event flag + 25 + 1 + + + HDTF7 + Channel 7 half data transfer event flag + 26 + 1 + + + DTERRF7 + Channel 7 data transfer error event flag + 27 + 1 + + + + + CLR + CLR + DMA interrupt flag clear register + (DMA_CLR) + 0x4 + 0x20 + read-write + 0x00000000 + + + GFC1 + Channel 1 Global flag clear + 0 + 1 + + + GFC2 + Channel 2 Global flag clear + 4 + 1 + + + GFC3 + Channel 3 Global flag clear + 8 + 1 + + + GFC4 + Channel 4 Global flag clear + 12 + 1 + + + GFC5 + Channel 5 Global flag clear + 16 + 1 + + + GFC6 + Channel 6 Global flag clear + 20 + 1 + + + GFC7 + Channel 7 Global flag clear + 24 + 1 + + + FDTFC1 + Channel 1 full data transfer flag clear + 1 + 1 + + + FDTFC2 + Channel 2 full data transfer flag clear + 5 + 1 + + + FDTFC3 + Channel 3 full data transfer flag clear + 9 + 1 + + + FDTFC4 + Channel 4 full data transfer flag clear + 13 + 1 + + + FDTFC5 + Channel 5 full data transfer flag clear + 17 + 1 + + + FDTFC6 + Channel 6 full data transfer flag clear + 21 + 1 + + + FDTFC7 + Channel 7 full data transfer flag clear + 25 + 1 + + + HDTFC1 + Channel 1 half data transfer flag clear + 2 + 1 + + + HDTFC2 + Channel 2 half data transfer flag clear + 6 + 1 + + + HDTFC3 + Channel 3 half data transfer flag clear + 10 + 1 + + + HDTFC4 + Channel 4 half data transfer flag clear + 14 + 1 + + + HDTFC5 + Channel 5 half data transfer flag clear + 18 + 1 + + + HDTFC6 + Channel 6 half data transfer flag clear + 22 + 1 + + + HDTFC7 + Channel 7 half data transfer flag clear + 26 + 1 + + + DTERRFC1 + Channel 1 data transfer error flag clear + 3 + 1 + + + DTERRFC2 + Channel 2 data transfer error flag clear + 7 + 1 + + + DTERRFC3 + Channel 3 data transfer error flag clear + 11 + 1 + + + DTERRFC4 + Channel 4 data transfer error flag clear + 15 + 1 + + + DTERRFC5 + Channel 5 data transfer error flag clear + 19 + 1 + + + DTERRFC6 + Channel 6 data transfer error flag clear + 23 + 1 + + + DTERRFC7 + Channel 7 data transfer error flag clear + 27 + 1 + + + + + C1CTRL + C1CTRL + DMA channel configuration register(DMA_C1CTRL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C1DTCNT + C1DTCNT + DMA channel 1 number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C1PADDR + C1PADDR + DMA channel 1 peripheral base address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C1MADDR + C1MADDR + DMA channel 1 memory base address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C2CTRL + C2CTRL + DMA channel configuration register (DMA_C2CTRL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C2DTCNT + C2DTCNT + DMA channel 2 number of data to transferregister + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C2PADDR + C2PADDR + DMA channel 2 peripheral base address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C2MADDR + C2MADDR + DMA channel 2 memory base address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C3CTRL + C3CTRL + DMA channel configuration register (DMA_C3CTRL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C3DTCNT + C3DTCNT + DMA channel 3 number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C3PADDR + C3PADDR + DMA channel 3 peripheral base address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C3MADDR + C3MADDR + DMA channel 3 memory base address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C4CTRL + C4CTRL + DMA channel configuration register (DMA_C4CTRL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C4DTCNT + C4DTCNT + DMA channel 4 number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C4PADDR + C4PADDR + DMA channel 4 peripheral base address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C4MADDR + C4MADDR + DMA channel 4 memory base address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C5CTRL + C5CTRL + DMA channel configuration register (DMA_C5CTRL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C5DTCNT + C5DTCNT + DMA channel 5 number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C5PADDR + C5PADDR + DMA channel 5 peripheral base address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C5MADDR + C5MADDR + DMA channel 5 memory base address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C6CTRL + C6CTRL + DMA channel configuration register(DMA_C6CTRL) + 0x6C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C6DTCNT + C6DTCNT + DMA channel 6 number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C6PADDR + C6PADDR + DMA channel 6 peripheral address base register + 0x74 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C6MADDR + C6MADDR + DMA channel 6 memory address base register + 0x78 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + C7CTRL + C7CTRL + DMA channel configuration register(DMA_C7CTRL) + 0x80 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FDTIEN + Transfer complete interrupt enable + 1 + 1 + + + HDTIEN + Half transfer interrupt enable + 2 + 1 + + + DTERRIEN + Transfer error interrupt enable + 3 + 1 + + + DTD + Data transfer direction + 4 + 1 + + + LM + Loop mode + 5 + 1 + + + PINCM + Peripheral increment mode + 6 + 1 + + + MINCM + Memory increment mode + 7 + 1 + + + PWIDTH + Peripheral data bit width + 8 + 2 + + + MWIDTH + Memory data bit width + 10 + 2 + + + CHPL + Channel Priority level + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + C7DTCNT + C7DTCNT + DMA channel 7 number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + CNT + Number of data to transfer + 0 + 16 + + + + + C7PADDR + C7PADDR + DMA channel 7 peripheral base address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral address + 0 + 32 + + + + + C7MADDR + C7MADDR + DMA channel 7 memory base address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + DMA_MUXSEL + DMA_MUXSEL + DMAMUX Table Selection + 0x100 + 0x20 + 0x00000000 + + + TBL_SEL + Multiplexer Table Select + 0 + 1 + read-write + + + + + MUXC1CTRL + MUXC1CTRL + Channel 1 Configuration Register + 0x104 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC2CTRL + MUXC2CTRL + Channel 2 Configuration Register + 0x108 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC3CTRL + MUXC3CTRL + Channel 3 Configuration Register + 0x10C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC4CTRL + MUXC4CTRL + Channel 4 Configuration Register + 0x110 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC5CTRL + MUXC5CTRL + Channel 5 Configuration Register + 0x114 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC6CTRL + MUXC6CTRL + Channel 6 Configuration Register + 0x118 + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXC7CTRL + MUXC7CTRL + Channel 7 Configuration Register + 0x11C + 0x20 + 0x00000000 + + + REQSEL + DMA request select + 0 + 7 + read-write + + + SYNCOVIEN + Synchronization overrun interrupt enable + 8 + 1 + read-write + + + EVTGEN + Event generation enable + 9 + 1 + read-write + + + SYNCEN + Synchroniztion enable + 16 + 1 + read-write + + + SYNCPOL + Synchronization polarity + 17 + 2 + read-write + + + REQCNT + Number of DMA requests + 19 + 5 + read-write + + + SYNCSEL + Synchronization Identification + 24 + 5 + read-write + + + + + MUXG1CTRL + MUXG1CTRL + Generator 1 Configuration Register + 0x120 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG2CTRL + MUXG2CTRL + Generator 2 Configuration Register + 0x124 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG3CTRL + MUXG3CTRL + Generator 3 Configuration Register + 0x128 + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXG4CTRL + MUXG4CTRL + Generator 4 Configuration Register + 0x12C + 0x20 + 0x00000000 + + + SIGSEL + Signal select + 0 + 5 + read-write + + + TRGOVIEN + Trigger overrun interrupt enable + 8 + 1 + read-write + + + GEN + DMA request generator enable + 16 + 1 + read-write + + + GPOL + DMA request generator trigger polarity + 17 + 2 + read-write + + + GREQCNT + Number of DMA requests to be generated + 19 + 5 + read-write + + + + + MUXSYNCSTS + MUXSYNCSTS + Channel Interrupt Status Register + 0x130 + 0x20 + 0x00000000 + + + SYNCOVF1 + Synchronizaton overrun interrupt flag + 0 + 1 + read-only + + + SYNCOVF2 + Synchronizaton overrun interrupt flag + 1 + 1 + read-only + + + SYNCOVF3 + Synchronizaton overrun interrupt flag + 2 + 1 + read-only + + + SYNCOVF4 + Synchronizaton overrun interrupt flag + 3 + 1 + read-only + + + SYNCOVF5 + Synchronizaton overrun interrupt flag + 4 + 1 + read-only + + + SYNCOVF6 + Synchronizaton overrun interrupt flag + 5 + 1 + read-only + + + SYNCOVF7 + Synchronizaton overrun interrupt flag + 6 + 1 + read-only + + + + + MUXSYNCCLR + MUXSYNCCLR + Channel Interrupt Clear Flag Register + 0x134 + 0x20 + 0x00000000 + + + SYNCOVFC1 + Clear synchronizaton overrun interrupt flag + 0 + 1 + read-write + + + SYNCOVFC2 + Clear synchronizaton overrun interrupt flag + 1 + 1 + read-write + + + SYNCOVFC3 + Clear synchronizaton overrun interrupt flag + 2 + 1 + read-write + + + SYNCOVFC4 + Clear synchronizaton overrun interrupt flag + 3 + 1 + read-write + + + SYNCOVFC5 + Clear synchronizaton overrun interrupt flag + 4 + 1 + read-write + + + SYNCOVFC6 + Clear synchronizaton overrun interrupt flag + 5 + 1 + read-write + + + SYNCOVFC7 + Clear synchronizaton overrun interrupt flag + 6 + 1 + read-write + + + + + MUXGSTS + MUXGSTS + Generator Interrupt Status Register + 0x138 + 0x20 + 0x00000000 + + + TRGOVF1 + Trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVF2 + Trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVF3 + Trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVF4 + Trigger overrun interrupt flag + 3 + 1 + read-write + + + + + MUXGCLR + MUXGCLR + Generator Interrupt Clear Flag Register + 0x13C + 0x20 + 0x00000000 + + + TRGOVFC1 + Clear trigger overrun interrupt flag + 0 + 1 + read-write + + + TRGOVFC2 + Clear trigger overrun interrupt flag + 1 + 1 + read-write + + + TRGOVFC3 + Clear trigger overrun interrupt flag + 2 + 1 + read-write + + + TRGOVFC4 + Clear trigger overrun interrupt flag + 3 + 1 + read-write + + + + + + + DMA2 + 0x40026600 + + + SDIO1 + Secure digital input/output + interface + SDIO + 0x4002C400 + + 0x0 + 0x400 + registers + + + SDIO1 + SDIO1 global interrupt + 49 + + + + PWRCTRL + PWRCTRL + Bits 1:0 = PWRCTRL: Power supply control + bits + 0x0 + 0x20 + read-write + 0x00000000 + + + PS + Power switch + 0 + 2 + + + + + CLKCTRL + CLKCTRL + SD clock control register + (SDIO_CLKCTRL) + 0x4 + 0x20 + read-write + 0x00000000 + + + CLKDIV + Clock division + 0 + 8 + + + CLKOEN + Clock output enable + 8 + 1 + + + PWRSVEN + Power saving mode enable + 9 + 1 + + + BYPSEN + Clock divider bypass enable + bit + 10 + 1 + + + BUSWS + Bus width selection + 11 + 2 + + + CLKEDS + SDIO_CK edge selection bit + 13 + 1 + + + HFCEN + Hardware flow control enable + 14 + 1 + + + CLKDIV98 + Clock divide factor bit9 and bit8 + 15 + 2 + + + + + ARGU + ARGU + Bits 31:0 = : Command argument + 0x8 + 0x20 + read-write + 0x00000000 + + + ARGU + Command argument + 0 + 32 + + + + + CMDCTRL + CMDCTRL + SDIO command control register + (SDIO_CMDCTRL) + 0xC + 0x20 + read-write + 0x00000000 + + + CMDIDX + CMDIDX + 0 + 6 + + + RSPWT + Wait for response + 6 + 2 + + + INTWT + CCSM wait for interrupt + 8 + 1 + + + PNDWT + CCSM wait for end of transfer + 9 + 1 + + + CCSMEN + Command channel state machine + 10 + 1 + + + IOSUSP + SD I/O suspend command + 11 + 1 + + + + + RSPCMD + RSPCMD + SDIO command register + 0x10 + 0x20 + read-only + 0x00000000 + + + RSPCMD + RSPCMD + 0 + 6 + + + + + RSP1 + RSP1 + Bits 31:0 = CARDSTATUS1 + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTS1 + CARDSTATUS1 + 0 + 32 + + + + + RSP2 + RSP2 + Bits 31:0 = CARDSTATUS2 + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS2 + 0 + 32 + + + + + RSP3 + RSP3 + Bits 31:0 = CARDSTATUS3 + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS3 + 0 + 32 + + + + + RSP4 + RSP4 + Bits 31:0 = CARDSTATUS4 + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTS2 + CARDSTATUS4 + 0 + 32 + + + + + DTTMR + DTTMR + Bits 31:0 = TIMEOUT: Data timeout + period + 0x24 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Data timeout period + 0 + 32 + + + + + DTLEN + DTLEN + Bits 24:0 = DATALENGTH: Data length + value + 0x28 + 0x20 + read-write + 0x00000000 + + + DTLEN + Data length value + 0 + 25 + + + + + DTCTRL + DTCTRL + SDIO data control register + (SDIO_DCTRL) + 0x2C + 0x20 + read-write + 0x00000000 + + + TFREN + DTEN + 0 + 1 + + + TFRDIR + DTDIR + 1 + 1 + + + TFRMODE + DTMODE + 2 + 1 + + + DMAEN + DMAEN + 3 + 1 + + + BLKSIZE + DBLOCKSIZE + 4 + 4 + + + RDWTSTART + PWSTART + 8 + 1 + + + RDWTSTOP + PWSTOP + 9 + 1 + + + RDWTMODE + RWMOD + 10 + 1 + + + IOEN + SD I/O function enable + 11 + 1 + + + + + DTCNT + DTCNT + Bits 24:0 = DATACOUNT: Data count + value + 0x30 + 0x20 + read-only + 0x00000000 + + + CNT + Data count value + 0 + 25 + + + + + STS + STS + SDIO status register + (SDIO_STA) + 0x34 + 0x20 + read-only + 0x00000000 + + + CMDFAIL + Command crc fail + 0 + 1 + + + DTFAIL + Data crc fail + 1 + 1 + + + CMDTIMEOUT + Command timeout + 2 + 1 + + + DTTIMEOUT + Data timeout + 3 + 1 + + + TXERRU + Tx under run error + 4 + 1 + + + RXERRO + Rx over run error + 5 + 1 + + + CMDRSPCMPL + Command response complete + 6 + 1 + + + CMDCMPL + Command sent + 7 + 1 + + + DTCMPL + Data sent + 8 + 1 + + + SBITERR + Start bit error + 9 + 1 + + + DTBLKCMPL + Data block sent + 10 + 1 + + + DOCMD + Command transfer in progress + 11 + 1 + + + DOTX + Data transmit in progress + 12 + 1 + + + DORX + Data receive in progress + 13 + 1 + + + TXBUFH + Tx buffer half empty + 14 + 1 + + + RXBUFH + Rx buffer half empty + 15 + 1 + + + TXBUFF + Tx buffer full + 16 + 1 + + + RXBUFF + Rx buffer full + 17 + 1 + + + TXBUFE + Tx buffer empty + 18 + 1 + + + RXBUFE + Rx buffer empty + 19 + 1 + + + TXBUF + Tx data vaild + 20 + 1 + + + RXBUF + Rx data vaild + 21 + 1 + + + IOIF + SD I/O interrupt + 22 + 1 + + + + + INTCLR + INTCLR + SDIO interrupt clear register + (SDIO_INTCLR) + 0x38 + 0x20 + read-write + 0x00000000 + + + CMDFAIL + Command crc fail flag clear + 0 + 1 + + + DTFAIL + Data crc fail flag clear + 1 + 1 + + + CMDTIMEOUT + Command timeout flag clear + 2 + 1 + + + DTTIMEOUT + Data timeout flag clear + 3 + 1 + + + TXERRU + Tx under run error flag clear + 4 + 1 + + + RXERRU + Rx over run error flag clear + 5 + 1 + + + CMDRSPCMPL + Command response complete flag clear + 6 + 1 + + + CMDCMPL + Command sent flag clear + 7 + 1 + + + DTCMPL + Data sent flag clear + 8 + 1 + + + SBITERR + Start bit error flag clear + 9 + 1 + + + DTBLKCMPL + Data block sent clear + 10 + 1 + + + IOIF + SD I/O interrupt flag clear + 22 + 1 + + + + + INTEN + INTEN + SDIO mask register (SDIO_MASK) + 0x3C + 0x20 + read-write + 0x00000000 + + + CMDFAILIEN + Command crc fail interrupt enable + 0 + 1 + + + DTFAILIEN + Data crc fail interrupt enable + 1 + 1 + + + CMDTIMEOUTIEN + Command timeout interrupt enable + 2 + 1 + + + DTTIMEOUTIEN + Data timeout interrupt enable + 3 + 1 + + + TXERRUIEN + Tx under run interrupt enable + 4 + 1 + + + RXERRUIEN + Rx over run interrupt enable + 5 + 1 + + + CMDRSPCMPLIEN + Command response complete interrupt enable + 6 + 1 + + + CMDCMPLIEN + Command sent complete interrupt enable + 7 + 1 + + + DTCMPLIEN + Data sent complete interrupt enable + 8 + 1 + + + SBITERRIEN + Start bit error interrupt enable + 9 + 1 + + + DTBLKCMPLIEN + Data block sent complete interrupt enable + 10 + 1 + + + DOCMDIEN + Command acting interrupt enable + 11 + 1 + + + DOTXIEN + Data transmit acting interrupt enable + 12 + 1 + + + DORXIEN + Data receive acting interrupt enable + 13 + 1 + + + TXBUFHIEN + Tx buffer half empty interrupt enable + 14 + 1 + + + RXBUFHIEN + Rx buffer half empty interrupt enable + 15 + 1 + + + TXBUFFIEN + Tx buffer full interrupt enable + 16 + 1 + + + RXBUFFIEN + Rx buffer full interrupt enable + 17 + 1 + + + TXBUFEIEN + Tx buffer empty interrupt enable + 18 + 1 + + + RXBUFEIEN + Rx buffer empty interrupt enable + 19 + 1 + + + TXBUFIEN + Tx buffer data vaild interrupt enable + 20 + 1 + + + RXBUFIEN + Rx buffer data vaild interrupt enable + 21 + 1 + + + IOIFIEN + SD I/O interrupt enable + 22 + 1 + + + + + BUFCNT + BUFCNT + Bits 23:0 = BUFCOUNT: Remaining number of + words to be written to or read from the + FIFO + 0x48 + 0x20 + read-only + 0x00000000 + + + CNT + FIF0COUNT + 0 + 24 + + + + + BUF + BUF + bits 31:0 = Buffer Data: Receive and transmit + buffer data + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Buffer data + 0 + 32 + + + + + + + SDIO2 + 0x50061000 + + SDIO2 + SDIO2 global interrupt + 102 + + + + ERTC + Real-time clock + ERTC + 0x40002800 + + 0x0 + 0x400 + registers + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + AMPM + AM/PM notation + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens + 20 + 4 + + + YU + Year units + 16 + 4 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + CTRL + CTRL + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + CALOEN + Calibration output enable + 23 + 1 + + + OUTSEL + Output source selection + 21 + 2 + + + OUTP + Output polarity + 20 + 1 + + + CALOSEL + Calibration output selection + 19 + 1 + + + BPR + Battery power domain data register + 18 + 1 + + + DEC1H + Decrease 1 hour + 17 + 1 + + + ADD1H + Add 1 hour + 16 + 1 + + + TSIEN + Timestamp interrupt enable + 15 + 1 + + + WATIEN + Wakeup timer interrupt enable + 14 + 1 + + + ALBIEN + Alarm B interrupt enable + 13 + 1 + + + ALAIEN + Alarm A interrupt enable + 12 + 1 + + + TSEN + Timestamp enable + 11 + 1 + + + WATEN + Wakeup timer enable + 10 + 1 + + + ALBEN + Alarm B enable + 9 + 1 + + + ALAEN + Alarm A enable + 8 + 1 + + + CCALEN + Coarse calibration enable + 7 + 1 + + + HM + Hour mode + 6 + 1 + + + DREN + Date/time register direct read enable + 5 + 1 + + + RCDEN + Reference clock detection enable + 4 + 1 + + + TSEDG + Timestamp trigger edge + 3 + 1 + + + WATCLK + Wakeup timer clock selection + 0 + 3 + + + + + STS + STS + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALAWF + Alarm A register allows write flag + 0 + 1 + read-only + + + ALBWF + Alarm B register allows write flag + 1 + 1 + read-only + + + WATWF + Wakeup timer register allows write flag + 2 + 1 + read-only + + + TADJF + Time adjustment flag + 3 + 1 + read-write + + + INITF + Calendar initialization flag + 4 + 1 + read-only + + + UPDF + Calendar update flag + 5 + 1 + read-write + + + IMF + Enter initialization mode flag + 6 + 1 + read-only + + + IMEN + Initialization mode enable + 7 + 1 + read-write + + + ALAF + Alarm A flag + 8 + 1 + read-write + + + ALBF + Alarm B flag + 9 + 1 + read-write + + + WATF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Timestamp flag + 11 + 1 + read-write + + + TSOF + Timestamp overflow flag + 12 + 1 + read-write + + + TP1F + Tamper detection 1 flag + 13 + 1 + read-write + + + TP2F + Tamper detection 2 flag + 14 + 1 + read-write + + + CALUPDF + Calibration value update completed flag + 16 + 1 + read-only + + + + + DIV + DIV + Diveder register + 0x10 + 0x20 + read-write + 0x007F00FF + + + DIVA + Diveder A + 16 + 7 + + + DIVB + Diveder B + 0 + 15 + + + + + WAT + WAT + Wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + VAL + Wakeup timer reload value + 0 + 16 + + + + + CCAL + CCAL + Calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + CALDIR + Calibration direction + 7 + 1 + + + CALVAL + Calibration value + 0 + 5 + + + + + ALA + ALA + Alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + ALB + ALB + Alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MASK4 + Date/week mask + 31 + 1 + + + WKSEL + Date/week mode select + 30 + 1 + + + DT + Date tens + 28 + 2 + + + DU + Date units + 24 + 4 + + + MASK3 + Hours mask + 23 + 1 + + + AMPM + AM/PM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MASK2 + Minutes mask + 15 + 1 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + MASK1 + Seconds mask + 7 + 1 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + WP + WP + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 8 + + + + + SBS + SBS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + TADJ + TADJ + time adjust register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add 1 second + 31 + 1 + + + DECSBS + Decrease sub-second value + 0 + 15 + + + + + TSTM + TSTM + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + AMPM + AMPM + 22 + 1 + + + HT + Hour tens + 20 + 2 + + + HU + Hour units + 16 + 4 + + + MT + Minute tens + 12 + 3 + + + MU + Minute units + 8 + 4 + + + ST + Second tens + 4 + 3 + + + SU + Second units + 0 + 4 + + + + + TSDT + TSDT + timestamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WK + Week + 13 + 3 + + + MT + Month tens + 12 + 1 + + + MU + Month units + 8 + 4 + + + DT + Date tens + 4 + 2 + + + DU + Date units + 0 + 4 + + + + + TSSBS + TSSBS + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SBS + Sub second value + 0 + 16 + + + + + SCAL + SCAL + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + ADD + Add ERTC clock + 15 + 1 + + + CAL8 + 8-second calibration period + 14 + 1 + + + CAL16 + 16 second calibration period + 13 + 1 + + + DEC + Decrease ERTC clock + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + OUTTYPE + Output type + 18 + 1 + + + TSPIN + Time stamp detection pin selection + 17 + 1 + + + TP1PIN + Tamper detection pin selection + 16 + 1 + + + TPPU + Tamper detection pull-up + 15 + 1 + + + TPPR + Tamper detection pre-charge time + 13 + 2 + + + TPFLT + Tamper detection filter time + 11 + 2 + + + TPFREQ + Tamper detection frequency + 8 + 3 + + + TPTSEN + Tamper detection timestamp enable + 7 + 1 + + + TP2EDG + Tamper detection 2 valid edge + 4 + 1 + + + TP2EN + Tamper detection 2 enable + 3 + 1 + + + TPIEN + Tamper detection interrupt enable + 2 + 1 + + + TP1EDG + Tamper detection 1 valid edge + 1 + 1 + + + TP1EN + Tamper detection 1 enable + 0 + 1 + + + + + ALASBS + ALASBS + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + ALBSBS + ALBSBS + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + SBSMSK + Sub-second mask + 24 + 4 + + + SBS + Sub-seconds value + 0 + 15 + + + + + BPR1DT + BPR1DT + Battery powered domain register + 0x50 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR2DT + BPR2DT + Battery powered domain register + 0x54 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR3DT + BPR3DT + Battery powered domain register + 0x58 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR4DT + BPR4DT + Battery powered domain register + 0x5C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR5DT + BPR5DT + Battery powered domain register + 0x60 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR6DT + BPR6DT + Battery powered domain register + 0x64 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR7DT + BPR7DT + Battery powered domain register + 0x68 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR8DT + BPR8DT + Battery powered domain register + 0x6C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR9DT + BPR9DT + Battery powered domain register + 0x70 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR10DT + BPR10DT + Battery powered domain register + 0x74 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR11DT + BPR11DT + Battery powered domain register + 0x78 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR12DT + BPR12DT + Battery powered domain register + 0x7C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR13DT + BPR13DT + Battery powered domain register + 0x80 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR14DT + BPR14DT + Battery powered domain register + 0x84 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR15DT + BPR15DT + Battery powered domain register + 0x88 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR16DT + BPR16DT + Battery powered domain register + 0x8C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR17DT + BPR17DT + Battery powered domain register + 0x90 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR18DT + BPR18DT + Battery powered domain register + 0x94 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR19DT + BPR19DT + Battery powered domain register + 0x98 + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + BPR20DT + BPR20DT + Battery powered domain register + 0x9C + 0x20 + read-write + 0x00000000 + + + DT + Battery powered domain data + 0 + 32 + + + + + + + WDT + Watchdog + WDT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CMD + CMD + Command register + 0x0 + 0x20 + write-only + 0x00000000 + + + CMD + Command register + 0 + 16 + + + + + DIV + DIV + Division register + 0x4 + 0x20 + read-write + 0x00000000 + + + DIV + Division divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RLD + Reload value + 0 + 12 + + + + + STS + STS + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + DIVF + Division value update complete flag + 0 + 1 + + + RLDF + Reload value update complete flag + 1 + 1 + + + WINF + Window value update complete flag + 2 + 1 + + + + + WIN + WIN + Window register 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control register + 0x48 + 0x20 + read-write + 0x0000 + + + DTB + DMA transfer bytes + 8 + 5 + + + ADDR + DMA transfer address offset + 0 + 5 + + + + + DMADT + DMADT + DMA data register + 0x4C + 0x20 + read-write + 0x0000 + + + DMADT + DMA data register + 0 + 16 + + + + + CM3_OUTPUT + CM3_OUTPUT + Channel output mode register + 0x70 + 0x20 + read-write + 0x00000000 + + + C5OSEN + Channel 5 output switch enable + 7 + 1 + + + C5OCTRL + Channel 5 output control + 4 + 3 + + + C5OBEN + Channel 5 output buffer enable + 3 + 1 + + + C5OIEN + Channel 5 output immediately enable + 2 + 1 + + + + + C5DT + C5DT + Channel 5 data register + 0x74 + 0x20 + read-write + 0x00000000 + + + C5DT + Channel 5 data register + 0 + 16 + + + + + + + TMR8 + 0x40010400 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 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Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + TRGSWTR + Trigger event triggered by software + 6 + 1 + + + C4SWTR + Channel 4 event triggered by software + 4 + 1 + + + C3SWTR + Channel 3 event triggered by software + 3 + 1 + + + C2SWTR + Channel 2 event triggered by software + 2 + 1 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C2OSEN + Channel 2 output switch enable + 15 + 1 + + + C2OCTRL + Channel 2 output control + 12 + 3 + + + C2OBEN + Channel 2 output buffer enable + 11 + 1 + + + C2OIEN + Channel 2 output immediately enable + 10 + 1 + + + C2C + Channel 2 configure + 8 + 2 + + + C1OSEN + Channel 1 output switch enable + 7 + 1 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 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Channel 2 Polarity + 5 + 1 + + + C2EN + Channel 2 enable + 4 + 1 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1CEN + Channel 1 complementary enable + 2 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + C2DT + C2DT + Channel 2 data register + 0x38 + 0x20 + read-write + 0x00000000 + + + C2DT + Channel 2 data register + 0 + 16 + + + + + + + TMR12 + 0x40001800 + + TMR8_BRK_TMR12 + TMR8 brake interrupt and TMR12 global + interrupt + 43 + + + + TMR10 + General purpose timer + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TMR1_OVF_TMR10 + TMR1 overflow interrupt and TMR10 global + interrupt + 25 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CLKDIV + Clock divider + 8 + 2 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + C1IEN + Channel 1 interrupt + enable + 1 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + C1RF + Channel 1 recapture flag + 9 + 1 + + + C1IF + Channel 1 interrupt flag + 1 + 1 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + C1SWTR + Channel 1 event triggered by software + 1 + 1 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CM1_OUTPUT + CM1_OUTPUT + Channel output mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + C1OCTRL + Channel 1 output control + 4 + 3 + + + C1OBEN + Channel 1 output buffer enable + 3 + 1 + + + C1OIEN + Channel 1 output immediately enable + 2 + 1 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CM1_INPUT + CM1_INPUT + Channel input mode register 1 + CM1_OUTPUT + 0x18 + 0x20 + read-write + 0x00000000 + + + C1DF + Channel 1 digital filter + 4 + 4 + + + C1IDIV + Channel 1 input divider + 2 + 2 + + + C1C + Channel 1 configure + 0 + 2 + + + + + CCTRL + CCTRL + Channel control + register + 0x20 + 0x20 + read-write + 0x0000 + + + C1CP + Channel 1 complementary polarity + 3 + 1 + + + C1P + Channel 1 Polarity + 1 + 1 + + + C1EN + Channel 1 enable + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + C1DT + C1DT + Channel 1 data register + 0x34 + 0x20 + read-write + 0x00000000 + + + C1DT + Channel 1 data register + 0 + 16 + + + + + + + TMR11 + 0x40014800 + + TMR1_TRG_HALL_TMR11 + TMR1 trigger and HALL interrupts and + TMR11 global interrupt + 26 + + + + TMR13 + 0x40001C00 + + TMR8_OVF_TMR13 + TMR8 overflow interrupt and TMR13 global + interrupt + 44 + + + + TMR14 + 0x40002000 + + TMR8_TRG_HALL_TMR14 + TMR8 trigger and HALL interrupts and + TMR14 global interrupt + 45 + + + + TMR6 + Basic timer + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TMR6 + TMR6 global interrupt + 54 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + PRBEN + Period buffer enable + 7 + 1 + + + OCMEN + One cycle mode enable + 3 + 1 + + + OVFS + Overflow event source + 2 + 1 + + + OVFEN + Overflow event enable + 1 + 1 + + + TMREN + TMR enable + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + PTOS + Primary TMR output selection + 4 + 3 + + + + + IDEN + IDEN + Interrupt/DMA enable register + 0xC + 0x20 + read-write + 0x0000 + + + OVFDEN + Overflow DMA request enable + 8 + 1 + + + OVFIEN + Overflow interrupt enable + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-write + 0x0000 + + + OVFIF + Overflow interrupt flag + 0 + 1 + + + + + SWEVT + SWEVT + Software event register + 0x14 + 0x20 + read-write + 0x0000 + + + OVFSWTR + Overflow event triggered by software + 0 + 1 + + + + + CVAL + CVAL + Counter value + 0x24 + 0x20 + read-write + 0x00000000 + + + CVAL + Counter value + 0 + 16 + + + + + DIV + DIV + Divider value + 0x28 + 0x20 + read-write + 0x0000 + + + DIV + Divider value + 0 + 16 + + + + + PR + PR + Period value + 0x2C + 0x20 + read-write + 0x00000000 + + + PR + Period value + 0 + 16 + + + + + + + TMR7 + 0x40001400 + + TMR7 + TMR7 global interrupt + 55 + + + + ACC + HSI Auto Clock Calibration + ACC + 0x40017400 + + 0x0 + 0x400 + registers + + + + STS + STS + status register + 0x0 + 0x20 + 0x0000 + + + RSLOST + Reference Signal Lost + read-write + 1 + 1 + + + CALRDY + Internal high-speed clock calibration ready + read-write + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x04 + 0x20 + 0x0100 + + + STEP + STEP + read-write + 8 + 4 + + + CALRDYIEN + CALRDY interrupt enable + read-write + 5 + 1 + + + EIEN + RSLOST error interrupt enable + read-write + 4 + 1 + + + SOFSEL + SOF Select + read-write + 2 + 1 + + + ENTRIM + Enable trim + read-write + 1 + 1 + + + CALON + Calibration on + read-write + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x08 + 0x20 + 0x2080 + + + HICKTWK + Internal high-speed auto clock trimming + read-only + 8 + 6 + + + HICKCAL + Internal high-speed auto clock calibration + read-only + 0 + 8 + + + + + C1 + C1 + compare value 1 + 0x0C + 0x20 + 0x1F2C + + + C1 + Compare 1 + read-write + 0 + 16 + + + + + C2 + C2 + compare value 2 + 0x10 + 0x20 + 0x1F40 + + + C2 + Compare 2 + read-write + 0 + 16 + + + + + C3 + C3 + compare value 3 + 0x14 + 0x20 + 0x1F54 + + + C3 + Compare 3 + read-write + 0 + 16 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EVT + I2C1 event interrupt + 31 + + + I2C1_ERR + I2C1 error interrupt + 32 + + + + CTRL1 + CTRL1 + Control register 1 + 0x0 + 0x20 + 0x00000000 + + + I2CEN + I2C peripheral enable + 0 + 1 + read-write + + + TDIEN + Transmit data interrupt enable + 1 + 1 + read-write + + + RDIEN + Receive data interrupt enable + 2 + 1 + read-write + + + ADDRIEN + Address match interrupt enable + 3 + 1 + read-write + + + ACKFAILIEN + Acknowledge fail interrupt enable + 4 + 1 + read-write + + + STOPIEN + Stop generation complete interrupt enable + 5 + 1 + read-write + + + TDCIEN + Transfer data complete interrupt enable + 6 + 1 + read-write + + + ERRIEN + Error interrupts enable + 7 + 1 + read-write + + + DFLT + Digital filter value + 8 + 4 + read-write + + + DMATEN + DMA Transmit data request enable + 14 + 1 + read-write + + + DMAREN + DMA receive data request enable + 15 + 1 + read-write + + + SCTRL + Slave receiving data control + 16 + 1 + read-write + + + STRETCH + Clock stretching mode + 17 + 1 + read-write + + + GCAEN + General call address enable + 19 + 1 + read-write + + + HADDREN + SMBus host address enable + 20 + 1 + read-write + + + DEVADDREN + SMBus device default address enable + 21 + 1 + read-write + + + SMBALERT + SMBus alert enable / pin set + 22 + 1 + read-write + + + PECEN + PEC calculation enable + 23 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECTEN + Request PEC transmission enable + 26 + 1 + + + ASTOPEN + Automatically send stop condition enable + 25 + 1 + + + RLDEN + Send data reload mode enable + 24 + 1 + + + CNT + Transmit data counter + 16 + 8 + + + NACKEN + Not acknowledge enable + 15 + 1 + + + GENSTOP + Generate stop condition + 14 + 1 + + + GENSTART + Generate start condition + 13 + 1 + + + READH10 + 10-bit address header read enable + 12 + 1 + + + ADDR10 + Host send 10-bit address mode enable + 11 + 1 + + + DIR + Master data transmission direction + 10 + 1 + + + SADDR + Slave address + 0 + 10 + + + + + OADDR1 + OADDR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + ADDR1 + Interface address + 0 + 10 + + + ADDR1MODE + Own Address mode + 10 + 1 + + + ADDR1EN + Own address 1 enable + 15 + 1 + + + + + OADDR2 + OADDR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + ADDR2 + Own address 2 + 1 + 7 + + + ADDR2MASK + Own address 2-bit mask + 8 + 3 + + + ADDR2EN + Own address 2 enable + 15 + 1 + + + + + CLKCTRL + CLKCTRL + Clock contorl register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low level + 0 + 8 + + + SCLH + SCL high level + 8 + 8 + + + SDAD + SDA output delay + 16 + 4 + + + SCLD + SCL output delay + 20 + 4 + + + DIVH + High 4 bits of clock divider value + 24 + 4 + + + DIVL + Low 4 bits of clock divider value + 28 + 4 + + + + + TIMEOUT + TIMEOUT + Timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + TOTIME + Clock timeout detection time + 0 + 12 + + + TOMOED + Clock timeout detection mode + 12 + 1 + + + TOEN + Detect clock low/high timeout enable + 15 + 1 + + + EXTTIME + Cumulative clock low extend timeout value + 16 + 12 + + + EXTEN + Cumulative clock low extend timeout enable + 31 + 1 + + + + + STS + STS + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDR + Slave address matching value + 17 + 7 + read-only + + + SDIR + Slave data transmit direction + 16 + 1 + read-only + + + BUSYF + Bus busy + 15 + 1 + read-only + + + ALERTF + SMBus alert flag + 13 + 1 + read-only + + + TMOUT + SMBus timeout flag + 12 + 1 + read-only + + + PECERR + PEC receive error flag + 11 + 1 + read-only + + + OUF + Overflow or underflow flag + 10 + 1 + read-only + + + ARLOST + Arbitration lost flag + 9 + 1 + read-only + + + BUSERR + Bus error flag + 8 + 1 + read-only + + + TCRLD + Transmission is complete, waiting to load data + 7 + 1 + read-only + + + TDC + Transmit data complete flag + 6 + 1 + read-only + + + STOPF + Stop condition generation complete flag + 5 + 1 + read-only + + + ACKFAIL + Acknowledge failure flag + 4 + 1 + read-only + + + ADDRF + 0~7 bit address match flag + 3 + 1 + read-only + + + RDBF + Receive data buffer full flag + 2 + 1 + read-only + + + TDIS + Send interrupt status + 1 + 1 + read-write + + + TDBE + Transmit data buffer empty flag + 0 + 1 + read-write + + + + + CLR + CLR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTC + Clear SMBus alert flag + 13 + 1 + + + TMOUTC + Clear SMBus timeout flag + 12 + 1 + + + PECERRC + Clear PEC receive error flag + 11 + 1 + + + OUFC + Clear overload / underload flag + 10 + 1 + + + ARLOSTC + Clear arbitration lost flag + 9 + 1 + + + BUSERRC + Clear bus error flag + 8 + 1 + + + STOPC + Clear stop condition generation complete flag + 5 + 1 + + + ACKFAILC + Clear acknowledge failure flag + 4 + 1 + + + ADDRC + Clear 0~7 bit address match flag + 3 + 1 + + + + + PEC + PEC + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PECVAL + PEC value + 0 + 8 + + + + + RXDT + RXDT + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + DT + Receive data register + 0 + 8 + + + + + TXDT + TXDT + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + DT + Transmit data register + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + I2C2_EVT + I2C2 event interrupt + 33 + + + I2C2_ERR + I2C2 error interrupt + 34 + + + + I2C3 + 0x40005C00 + + I2C3_EVT + I2C3 event interrupt + 72 + + + I2C3_ERR + I2C3 error interrupt + 73 + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CTRL1 + CTRL1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SLBEN + Single line bidirectional half-duplex enable + 15 + 1 + + + SLBTD + Single line bidirectional half-duplex transmission direction + 14 + 1 + + + CCEN + CRC calculation enable + 13 + 1 + + + NTC + Next transmission CRC + 12 + 1 + + + FBN + frame bit num + 11 + 1 + + + ORA + Only receive active + 10 + 1 + + + SWCSEN + Software CS enable + 9 + 1 + + + SWCSIL + Software CS internal level + 8 + 1 + + + LTF + LSB transmit first + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + MDIV2_0 + Master clock frequency division bit2-0 + 3 + 3 + + + MSTEN + Master enable + 2 + 1 + + + CLKPOL + Clock polarity + 1 + 1 + + + CLKPHA + Clock phase + 0 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MDIV3EN + Master clock frequency3 division enable + 9 + 1 + + + MDIV3 + Master clock frequency division bit3 + 8 + 1 + + + TDBEIE + Transmit data buffer empty interrupt enable + 7 + 1 + + + RDBFIE + Receive data buffer full interrupt enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TIEN + TI mode enable + 4 + 1 + + + HWCSOE + Hardware CS output enable + 2 + 1 + + + DMATEN + DMA transmit enable + 1 + 1 + + + DMAREN + DMA receive enable + 0 + 1 + + + + + STS + STS + status register + 0x8 + 0x20 + 0x0002 + + + CSPAS + CS pulse abnormal setting fiag + 8 + 1 + read-write + + + BF + Busy flag + 7 + 1 + read-only + + + ROERR + Receiver overflow error + 6 + 1 + read-only + + + MMERR + Master mode error + 5 + 1 + read-only + + + CCERR + CRC calculation error + 4 + 1 + read-write + + + TUERR + Transmitter underload error + 3 + 1 + read-only + + + ACS + Audio channel state + 2 + 1 + read-only + + + TDBE + Transmit data buffer empty + 1 + 1 + read-only + + + RDBF + Receive data buffer full + 0 + 1 + read-only + + + + + DT + DT + data register + 0xC + 0x20 + read-write + 0x0000 + + + DT + Data value + 0 + 16 + + + + + CPOLY + CPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CPOLY + CRC polynomial + 0 + 16 + + + + + RCRC + RCRC + Receive CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + Receive CRC + 0 + 16 + + + + + TCRC + TCRC + Transmit CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Transmit CRC + 0 + 16 + + + + + I2SCTRL + I2SCTRL + I2S control register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMSEL + I2S mode select + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + OPERSEL + I2S operation select + 8 + 2 + + + PCMFSSEL + PCM frame synchronization select + 7 + 1 + + + STDSEL + I2S standard select + 4 + 2 + + + I2SCLKPOL + I2S clock polarity + 3 + 1 + + + I2SDBN + I2S data bit num + 1 + 2 + + + I2SCBN + I2S channel bit num + 0 + 1 + + + + + I2SCLK + I2SCLK + I2S clock register + 0x20 + 0x20 + read-write + 00000010 + + + I2SDIV9_8 + I2S division bit9 and bit8 + 10 + 2 + + + I2SMCLKOE + I2S master clock output enable + 9 + 1 + + + I2SODD + Odd result for I2S division + 8 + 1 + + + I2SDIV7_0 + I2S division bit7 to bit0 + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI4 global interrupt + 84 + + + + I2S2_EXT + 0x40017800 + + + I2S3_EXT + 0x40017C00 + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011000 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global interrupt + 37 + + + + STS + STS + Status register + 0x0 + 0x20 + 0x00C0 + + + CTSCF + CTS change flag + 9 + 1 + read-write + + + BFF + Break frame flag + 8 + 1 + read-write + + + TDBE + Transmit data buffer empty + 7 + 1 + read-only + + + TDC + Transmit data complete + 6 + 1 + read-write + + + RDBF + Receive data buffer full + 5 + 1 + read-write + + + IDLEF + IDLE flag + 4 + 1 + read-only + + + ROERR + Receiver overflow error + 3 + 1 + read-only + + + NERR + Noise error + 2 + 1 + read-only + + + FERR + Framing error + 1 + 1 + read-only + + + PERR + Parity error + 0 + 1 + read-only + + + + + DT + DT + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DT + Data value + 0 + 9 + + + + + BAUDR + BAUDR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV + Division + 0 + 16 + + + + + CTRL1 + CTRL1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + DBN1 + high bit for Data bit num + 28 + 1 + + + TSDT + transmit start delay time + 21 + 5 + + + TCDT + transmit complete delay time + 16 + 5 + + + UEN + USART enable + 13 + 1 + + + DBN0 + low bit for Data bit num + 12 + 1 + + + WUM + Wake up mode + 11 + 1 + + + PEN + Parity enable + 10 + 1 + + + PSEL + Parity selection + 9 + 1 + + + PERRIEN + PERR interrupt enable + 8 + 1 + + + TDBEIEN + TDBE interrupt enable + 7 + 1 + + + TDCIEN + TDC interrupt enable + 6 + 1 + + + RDBFIEN + RDBF interrupt enable + 5 + 1 + + + IDLEIEN + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + RM + Receiver mute + 1 + 1 + + + SBF + Send break frame + 0 + 1 + + + + + CTRL2 + CTRL2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + ID7_4 + bit 7-4 for usart identification + 28 + 4 + + + TRPSWAP + Transmit receive pin swap + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOPBN + STOP bit num + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CLKPOL + Clock polarity + 10 + 1 + + + CLKPHA + Clock phase + 9 + 1 + + + LBCP + Last bit clock pulse + 8 + 1 + + + BFIEN + Break frame interrupt enable + 6 + 1 + + + BFBN + Break frame bit num + 5 + 1 + + + IDBN + Identification bit num + 4 + 1 + + + ID3_0 + bit 3-0 for usart identification + 0 + 4 + + + + + CTRL3 + CTRL3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + DEP + DE polarity selection + 15 + 1 + + + RS485EN + RS485 enable + 14 + 1 + + + CTSCFIEN + CTSCF interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DMATEN + DMA transmitter enable + 7 + 1 + + + DMAREN + DMA receiver enable + 6 + 1 + + + SCMEN + Smartcard mode enable + 5 + 1 + + + SCNACKEN + Smartcard NACK enable + 4 + 1 + + + SLBEN + Single line bidirectional half-duplex enable + 3 + 1 + + + IRDALP + IrDA low-power mode + 2 + 1 + + + IRDAEN + IrDA enable + 1 + 1 + + + ERRIEN + Error interrupt enable + 0 + 1 + + + + + GDIV + GDIV + Guard time and division register + 0x18 + 0x20 + read-write + 0x0000 + + + SCGT + Smart card guard time value + 8 + 8 + + + ISDIV + IrDA/smartcard division value + 0 + 8 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + USART6 + 0x40011400 + + USART6 + USART6 global interrupt + 71 + + + + ADC1 + Analog to digital converter + ADC + 0x40012000 + + 0x0 + 0x100 + registers + + + ADC + ADC1 global interrupt + 18 + + + + STS + STS + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + RDY + ADC ready to conversion flag + 6 + 1 + read-only + + + OCCO + Ordinary channel conversion overflow flag + 5 + 1 + + + OCCS + Ordinary channel conversion start flag + 4 + 1 + + + PCCS + Preempted channel conversion start flag + 3 + 1 + + + PCCE + Preempted channels conversion end flag + 2 + 1 + + + OCCE + Ordinary channels conversion end flag + 1 + 1 + + + VMOR + Voltage monitoring out of range flag + 0 + 1 + + + + + CTRL1 + CTRL1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OCCOIEN + Ordinary channel conversion overflow interrupt enable + 26 + 1 + + + CRSEL + Conversion resolution select + 24 + 2 + + + OCVMEN + Voltage monitoring enable on ordinary channels + 23 + 1 + + + PCVMEN + Voltage monitoring enable on preempted channels + 22 + 1 + + + OCPCNT + Partitioned mode conversion count of ordinary channels + 13 + 3 + + + PCPEN + Partitioned mode enable on preempted channels + 12 + 1 + + + OCPEN + Partitioned mode enable on ordinary channels + 11 + 1 + + + PCAUTOEN + Preempted group automatic conversion enable after ordinary group + 10 + 1 + + + VMSGEN + Voltage monitoring enable on a single channel + 9 + 1 + + + SQEN + Sequence mode enable + 8 + 1 + + + PCCEIEN + Conversion end interrupt enable for preempted channels + 7 + 1 + + + VMORIEN + Voltage monitoring out of range interrupt enable + 6 + 1 + + + OCCEIEN + Ordinary channel conversion end interrupt enable + 5 + 1 + + + VMCSEL + Voltage monitoring channel select + 0 + 5 + + + + + CTRL2 + CTRL2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + OCTESEL_H + High bit of trigger event select for ordinary channels conversion + 31 + 1 + + + OCSWTRG + Ordinary channel software conversion trigger + 30 + 1 + + + OCETE + Ordinary channel external trigger edge select + 28 + 2 + + + OCTESEL_L + Low bit of trigger event select for ordinary channels conversion + 24 + 4 + + + PCTESEL_H + High bit of trigger event select for preempted channels conversion + 23 + 1 + + + PCSWTRG + Preempted channel software conversion trigger + 22 + 1 + + + PCETE + Preempted channel external trigger edge select + 20 + 2 + + + PCTESEL_L + Low bit of trigger event select for preempted channels conversion + 16 + 4 + + + DTALIGN + Data alignment + 11 + 1 + + + EOCSFEN + Each ordinary channel conversion set OCCE flag enable + 10 + 1 + + + OCDRCEN + Ordinary channel DMA request continuation enable for independent mode + 9 + 1 + + + OCDMAEN + Ordinary channel DMA transfer enable for independent mode + 8 + 1 + + + ADABRT + ADC conversion abort + 4 + 1 + + + ADCALINIT + Initialize A/D calibration + 3 + 1 + + + ADCAL + A/D Calibration + 2 + 1 + + + RPEN + Repeat mode enable + 1 + 1 + + + ADCEN + A/D converter enable + 0 + 1 + + + + + SPT1 + SPT1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + CSPT18 + Selection sample time of channel ADC_IN18 + 24 + 3 + + + CSPT17 + Selection sample time of channel ADC_IN17 + 21 + 3 + + + CSPT16 + Selection sample time of channel ADC_IN16 + 18 + 3 + + + CSPT15 + Selection sample time of channel ADC_IN15 + 15 + 3 + + + CSPT14 + Selection sample time of channel ADC_IN14 + 12 + 3 + + + CSPT13 + Selection sample time of channel ADC_IN13 + 9 + 3 + + + CSPT12 + Selection sample time of channel ADC_IN12 + 6 + 3 + + + CSPT11 + Selection sample time of channel ADC_IN11 + 3 + 3 + + + CSPT10 + Selection sample time of channel ADC_IN10 + 0 + 3 + + + + + SPT2 + SPT2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CSPT9 + Selection sample time of channel ADC_IN9 + 27 + 3 + + + CSPT8 + Selection sample time of channel ADC_IN8 + 24 + 3 + + + CSPT7 + Selection sample time of channel ADC_IN7 + 21 + 3 + + + CSPT6 + Selection sample time of channel ADC_IN6 + 18 + 3 + + + CSPT5 + Selection sample time of channel ADC_IN5 + 15 + 3 + + + CSPT4 + Selection sample time of channel ADC_IN4 + 12 + 3 + + + CSPT3 + Selection sample time of channel ADC_IN3 + 9 + 3 + + + CSPT2 + Selection sample time of channel ADC_IN2 + 6 + 3 + + + CSPT1 + Selection sample time of channel ADC_IN1 + 3 + 3 + + + CSPT0 + Selection sample time of channel ADC_IN0 + 0 + 3 + + + + + PCDTO1 + PCDTO1 + Preempted channel 1 data offset register + 0x14 + 0x20 + read-write + 0x00000000 + + + PCDTO1 + Data offset for Preempted channel 1 + 0 + 12 + + + + + PCDTO2 + PCDTO2 + Preempted channel 2 data offset register + 0x18 + 0x20 + read-write + 0x00000000 + + + PCDTO2 + Data offset for Preempted channel 2 + 0 + 12 + + + + + PCDTO3 + PCDTO3 + Preempted channel 3 data offset register + 0x1C + 0x20 + read-write + 0x00000000 + + + PCDTO3 + Data offset for Preempted channel 3 + 0 + 12 + + + + + PCDTO4 + PCDTO4 + Preempted channel 4 data offset register + 0x20 + 0x20 + read-write + 0x00000000 + + + PCDTO4 + Data offset for Preempted channel 4 + 0 + 12 + + + + + VMHB + VMHB + Voltage monitoring high boundary register + 0x24 + 0x20 + read-write + 0x00000FFF + + + VMHB + Voltage monitoring high boundary + 0 + 12 + + + + + VMLB + VMLB + Voltage monitoring low boundary register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMLB + Voltage monitoring low boundary + 0 + 12 + + + + + OSQ1 + OSQ1 + Ordinary sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + OCLEN + Ordinary conversion sequence length + 20 + 4 + + + OSN16 + Number of 16th conversion in ordinary sequence + 15 + 5 + + + OSN15 + Number of 15th conversion in ordinary sequence + 10 + 5 + + + OSN14 + Number of 14th conversion in ordinary sequence + 5 + 5 + + + OSN13 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ2 + OSQ2 + Ordinary sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + OSN12 + Number of 12th conversion in ordinary sequence + 25 + 5 + + + OSN11 + Number of 11th conversion in ordinary sequence + 20 + 5 + + + OSN10 + Number of 10th conversion in ordinary sequence + 15 + 5 + + + OSN9 + Number of 8th conversion in ordinary sequence + 10 + 5 + + + OSN8 + Number of 7th conversion in ordinary sequence + 5 + 5 + + + OSN7 + Number of 13th conversion in ordinary sequence + 0 + 5 + + + + + OSQ3 + OSQ3 + Ordinary sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + OSN6 + Number of 6th conversion in ordinary sequence + 25 + 5 + + + OSN5 + Number of 5th conversion in ordinary sequence + 20 + 5 + + + OSN4 + Number of 4th conversion in ordinary sequence + 15 + 5 + + + OSN3 + number of 3rd conversion in ordinary sequence + 10 + 5 + + + OSN2 + Number of 2nd conversion in ordinary sequence + 5 + 5 + + + OSN1 + Number of 1st conversion in ordinary sequence + 0 + 5 + + + + + PSQ + PSQ + Preempted sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + PCLEN + Preempted conversion sequence length + 20 + 2 + + + PSN4 + Number of 4th conversion in Preempted sequence + 15 + 5 + + + PSN3 + Number of 3rd conversion in Preempted sequence + 10 + 5 + + + PSN2 + Number of 2nd conversion in Preempted sequence + 5 + 5 + + + PSN1 + Number of 1st conversion in Preempted sequence + 0 + 5 + + + + + PDT1 + PDT1 + Preempted data register 1 + 0x3C + 0x20 + read-only + 0x00000000 + + + PDT1 + Preempted data + 0 + 16 + + + + + PDT2 + PDT2 + Preempted data register 2 + 0x40 + 0x20 + read-only + 0x00000000 + + + PDT2 + Preempted data + 0 + 16 + + + + + PDT3 + PDT3 + Preempted data register 3 + 0x44 + 0x20 + read-only + 0x00000000 + + + PDT3 + Preempted data + 0 + 16 + + + + + PDT4 + PDT4 + Preempted data register 4 + 0x48 + 0x20 + read-only + 0x00000000 + + + PDT4 + Preempted data + 0 + 16 + + + + + ODT + ODT + Ordinary data register + 0x4C + 0x20 + read-only + 0x00000000 + + + ODT + Conversion data of ordinary channel + 0 + 16 + + + + + OVSP + OVSP + oversampling register + 0x80 + 0x20 + read-write + 0x00000000 + + + OOSRSEL + Ordinary oversampling recovery mode select + 10 + 1 + + + OOSTREN + Ordinary oversampling trigger mode enable + 9 + 1 + + + OSSSEL + Oversampling shift select + 5 + 4 + + + OSRSEL + Oversampling ratio select + 2 + 3 + + + POSEN + Preempted oversampling enable + 1 + 1 + + + OOSEN + Ordinary oversampling enable + 0 + 1 + + + + + CALVAL + CALVAL + Calibration value register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALVAL + A/D Calibration value + 0 + 7 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + ADCCOM + ADC common area + ADC + 0x40012300 + + 0x0 + 0x100 + registers + + + + CSTS + CSTS + Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + RDY3 + ADC ready to conversion flag of ADC3 + 22 + 1 + + + OCCO3 + Ordinary channel conversion overflow flag of ADC3 + 21 + 1 + + + OCCS3 + Ordinary channel conversion start flag of ADC3 + 20 + 1 + + + PCCS3 + Preempted channel conversion start flag of ADC3 + 19 + 1 + + + PCCE3 + Preempted channels conversion end flag of ADC3 + 18 + 1 + + + OCCE3 + Ordinary channels conversion end flag of ADC3 + 17 + 1 + + + VMOR3 + Voltage monitoring out of range flag of ADC3 + 16 + 1 + + + RDY2 + ADC ready to conversion flag of ADC2 + 14 + 1 + + + OCCO2 + Ordinary channel conversion overflow flag of ADC2 + 13 + 1 + + + OCCS2 + Ordinary channel conversion start flag of ADC2 + 12 + 1 + + + PCCS2 + Preempted channel conversion start flag of ADC2 + 11 + 1 + + + PCCE2 + Preempted channels conversion end flag of ADC2 + 10 + 1 + + + OCCE2 + Ordinary channels conversion end flag of ADC2 + 9 + 1 + + + VMOR2 + Voltage monitoring out of range flag of ADC2 + 8 + 1 + + + RDY1 + ADC ready to conversion flag of ADC1 + 6 + 1 + + + OCCO1 + Ordinary channel conversion overflow flag of ADC1 + 5 + 1 + + + OCCS1 + Ordinary channel conversion start flag of ADC1 + 4 + 1 + + + PCCS1 + Preempted channel conversion start flag of ADC1 + 3 + 1 + + + PCCE1 + Preempted channels conversion end flag of ADC1 + 2 + 1 + + + OCCE1 + Ordinary channels conversion end flag of ADC1 + 1 + 1 + + + VMOR1 + Voltage monitoring out of range flag of ADC1 + 0 + 1 + + + + + CCTRL + CCTRL + Common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + MSDMASEL_H + High bit of ordinary channel DMA transfer mode select for master slave mode + 28 + 1 + + + ITSRVEN + Internal temperature sensor and VINTRV enable + 23 + 1 + + + VBATEN + VBAT enable + 22 + 1 + + + ADCDIV + ADC division + 16 + 4 + + + MSDMASEL_L + Low bit of ordinary channel DMA transfer mode select for master slave mode + 14 + 2 + + + MSDRCEN + Ordinary channel DMA request continuation enable for master slave mode + 13 + 1 + + + ASISEL + Adjacent ADC sampling interval select for ordinary shifting mode + 8 + 4 + + + MSSEL + Master slave mode select + 0 + 5 + + + + + CODT + CODT + Common Ordinary data register + 0x8 + 0x20 + read-only + 0x00000000 + + + CODTH + Ordinary conversion high halfword data for master slave mode + 16 + 16 + + + CODTL + Ordinary conversion low halfword data for master slave mode + 0 + 16 + + + + + + + CAN1 + Can controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupt + 19 + + + CAN1_RX0 + CAN1 RX0 interrupt + 20 + + + CAN_RX1 + CAN1 RX1 interrupt + 21 + + + CAN_SE + CAN1 SE interrupt + 22 + + + + MCTRL + MCTRL + Main control register + 0x0 + 0x20 + read-write + 0x00010002 + + + PTD + Prohibit transmission when debug + 16 + 1 + + + SPRST + Software partial reset + 15 + 1 + + + TTCEN + Time triggered communication mode enable + 7 + 1 + + + AEBOEN + Automatic exit bus-off enable + 6 + 1 + + + AEDEN + Automatic exit doze mode enable + 5 + 1 + + + PRSFEN + Prohibit retransmission when sending fails enable + 4 + 1 + + + MDRSEL + Message discarding rule select when overflow + 3 + 1 + + + MMSSR + Multiple message sending sequence rule + 2 + 1 + + + DZEN + Doze mode enable + 1 + 1 + + + FZEN + Freeze mode enable + 0 + 1 + + + + + MSTS + MSTS + Main status register + 0x4 + 0x20 + 0x00000C02 + + + REALRX + Real time level of RX pin + 11 + 1 + read-only + + + LSAMPRX + Last sample level of RX pin + 10 + 1 + read-only + + + CURS + Currently receiving status + 9 + 1 + read-only + + + CUSS + Currently sending status + 8 + 1 + read-only + + + EDZIF + Enter doze mode interrupt flag + 4 + 1 + read-write + + + QDZIF + Quit doze mode interrupt flag + 3 + 1 + read-write + + + EOIF + Error occur Interrupt flag + 2 + 1 + read-write + + + DZC + Doze mode confirm + 1 + 1 + read-only + + + FZC + Freeze mode confirm + 0 + 1 + read-only + + + + + TSTS + TSTS + Transmit status register + 0x8 + 0x20 + 0x1C000000 + + + TM2LPF + Transmit mailbox 2 lowest priority flag + 31 + 1 + read-only + + + TM1LPF + Transmit mailbox 1 lowest priority flag + 30 + 1 + read-only + + + TM0LPF + Transmit mailbox 0 lowest priority flag + 29 + 1 + read-only + + + TM2EF + Transmit mailbox 2 empty flag + 28 + 1 + read-only + + + TM1EF + Transmit mailbox 1 empty flag + 27 + 1 + read-only + + + TM0EF + Transmit mailbox 0 empty flag + 26 + 1 + read-only + + + TMNR + Transmit Mailbox number record + 24 + 2 + read-only + + + TM2CT + Transmit mailbox 2 cancel transmission + 23 + 1 + read-write + + + TM2TEF + Transmit mailbox 2 transmission error flag + 19 + 1 + read-write + + + TM2ALF + Transmit mailbox 2 arbitration lost flag + 18 + 1 + read-write + + + TM2TSF + Transmit mailbox 2 transmission success flag + 17 + 1 + read-write + + + TM2TCF + transmit mailbox 2 transmission complete flag + 16 + 1 + read-write + + + TM1CT + Transmit mailbox 1 cancel transmission + 15 + 1 + read-write + + + TM1TEF + Transmit mailbox 1 transmission error flag + 11 + 1 + read-write + + + TM1ALF + Transmit mailbox 1 arbitration lost flag + 10 + 1 + read-write + + + TM1TSF + Transmit mailbox 1 transmission success flag + 9 + 1 + read-write + + + TM1TCF + Transmit mailbox 1 transmission complete flag + 8 + 1 + read-write + + + TM0CT + Transmit mailbox 0 cancel transmission + 7 + 1 + read-write + + + TM0TEF + Transmit mailbox 0 transmission error flag + 3 + 1 + read-write + + + TM0ALF + Transmit mailbox 0 arbitration lost flag + 2 + 1 + read-write + + + TM0TSF + Transmit mailbox 0 transmission success flag + 1 + 1 + read-write + + + TM0TCF + Transmit mailbox 0 transmission complete flag + 0 + 1 + read-write + + + + + RF0 + RF0 + Receive FIFO 0 register + 0xC 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LBEN + Loop back mode + 30 + 1 + + + RSAW + Resynchronization adjust width + 24 + 2 + + + BTS2 + Bit time segment 2 + 20 + 3 + + + BTS1 + Bit time segment 1 + 16 + 4 + + + BRDIV + Baud rate division + 0 + 12 + + + + + TMI0 + TMI0 + Transmit mailbox 0 identifier register + 0x180 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC0 + TMC0 + Transmit mailbox 0 data length and time stamp register + 0x184 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL0 + TMDTL0 + Transmit mailbox 0 low byte data register + 0x188 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH0 + TMDTH0 + Transmit mailbox 0 high byte data register + 0x18C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI1 + TMI1 + Transmit mailbox 1 identifier register + 0x190 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC1 + TMC1 + Transmit mailbox 1 data length and time stamp register + 0x194 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL1 + TMDTL1 + Transmit mailbox 1 low byte data register + 0x198 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH1 + TMDTH1 + Transmit mailbox 1 high byte data register + 0x19C + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + TMI2 + TMI2 + Transmit mailbox 2 identifier register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + TMSID + Transmit mailbox standard identifier or extended identifier high bytes + 21 + 11 + + + TMEID + Ttransmit mailbox extended identifier + 3 + 18 + + + TMIDSEL + Transmit mailbox identifier type select + 2 + 1 + + + TMFRSEL + Transmit mailbox frame type select + 1 + 1 + + + TMSR + Transmit mailbox send request + 0 + 1 + + + + + TMC2 + TMC2 + Transmit mailbox 2 data length and time stamp register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + TMTS + Transmit mailbox time stamp + 16 + 16 + + + TMTSTEN + Transmit mailbox time stamp transmit enable + 8 + 1 + + + TMDTBL + Transmit mailbox data byte length + 0 + 4 + + + + + TMDTL2 + TMDTL2 + Transmit mailbox 2 low byte data register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + TMDT3 + Transmit mailbox data byte 3 + 24 + 8 + + + TMDT2 + Transmit mailbox data byte 2 + 16 + 8 + + + TMDT1 + Transmit mailbox data byte 1 + 8 + 8 + + + TMDT0 + Transmit mailbox data byte 0 + 0 + 8 + + + + + TMDTH2 + TMDTH2 + Transmit mailbox 2 high byte data register + 0x1AC + 0x20 + read-write + 0x00000000 + + + TMDT7 + Transmit mailbox data byte 7 + 24 + 8 + + + TMDT6 + Transmit mailbox data byte 6 + 16 + 8 + + + TMDT5 + Transmit mailbox data byte 5 + 8 + 8 + + + TMDT4 + Transmit mailbox data byte 4 + 0 + 8 + + + + + RFI0 + RFI0 + Receive FIFO 0 register + 0x1B0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC0 + RFC0 + Receive FIFO 0 data length and time stamp register + 0x1B4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL0 + RFDTL0 + Receive FIFO 0 low byte data register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH0 + RFDTH0 + Receive FIFO 0 high byte data register + 0x1BC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + RFI1 + RFI1 + Receive FIFO 1 register + 0x1C0 + 0x20 + read-only + 0x00000000 + + + RFSID + Receive FIFO standard identifier or receive FIFO extended identifier + 21 + 11 + + + RFEID + Receive FIFO extended identifier + 3 + 18 + + + RFIDI + Receive FIFO identifier type indication + 2 + 1 + + + RFFRI + Receive FIFO frame type indication + 1 + 1 + + + + + RFC1 + RFC1 + Receive FIFO 1 data length and time stamp register + 0x1C4 + 0x20 + read-only + 0x00000000 + + + RFTS + Receive FIFO time stamp + 16 + 16 + + + RFFMN + Receive FIFO filter match number + 8 + 8 + + + RFDTL + Receive FIFO data length + 0 + 4 + + + + + RFDTL1 + RFDTL1 + Receive FIFO 1 low byte data register + 0x1C8 + 0x20 + read-only + 0x00000000 + + + RFDT3 + Receive FIFO data byte 3 + 24 + 8 + + + RFDT2 + Receive FIFO data byte 2 + 16 + 8 + + + RFDT1 + Receive FIFO data byte 1 + 8 + 8 + + + RFDT0 + Receive FIFO data byte 0 + 0 + 8 + + + + + RFDTH1 + RFDTH1 + Receive FIFO 1 high byte data register + 0x1CC + 0x20 + read-only + 0x00000000 + + + RFDT7 + Receive FIFO data byte 7 + 24 + 8 + + + RFDT6 + Receive FIFO data byte 6 + 16 + 8 + + + RFDT5 + Receive FIFO data byte 5 + 8 + 8 + + + RFDT4 + Receive FIFO data byte 4 + 0 + 8 + + + + + FCTRL + FCTRL + Filter control register + 0x200 + 0x20 + read-write + 0x00000000 + + + FCS + Filters configure switch + 0 + 1 + + + + + FMCFG + FMCFG + Filter mode config register + 0x204 + 0x20 + read-write + 0x00000000 + + + FMSEL0 + Filter mode select + 0 + 1 + + + FMSEL1 + Filter mode select + 1 + 1 + + + FMSEL2 + Filter mode select + 2 + 1 + + + FMSEL3 + Filter mode select + 3 + 1 + + + FMSEL4 + Filter mode select + 4 + 1 + + + FMSEL5 + Filter mode select + 5 + 1 + + + FMSEL6 + Filter mode select + 6 + 1 + + + FMSEL7 + Filter mode select + 7 + 1 + + + FMSEL8 + Filter mode select + 8 + 1 + + + FMSEL9 + Filter mode select + 9 + 1 + + + FMSEL10 + Filter mode select + 10 + 1 + + + FMSEL11 + Filter mode select + 11 + 1 + + + FMSEL12 + Filter mode select + 12 + 1 + + + FMSEL13 + Filter mode select + 13 + 1 + + + FMSEL14 + Filter mode select + 14 + 1 + + + FMSEL15 + Filter mode select + 15 + 1 + + + FMSEL16 + Filter mode select + 16 + 1 + + + FMSEL17 + Filter mode select + 17 + 1 + + + FMSEL18 + Filter mode select + 18 + 1 + + + FMSEL19 + Filter mode select + 19 + 1 + + + FMSEL20 + Filter mode select + 20 + 1 + + + FMSEL21 + Filter mode select + 21 + 1 + + + FMSEL22 + Filter mode select + 22 + 1 + + + FMSEL23 + Filter mode select + 23 + 1 + + + FMSEL24 + Filter mode select + 24 + 1 + + + FMSEL25 + Filter mode select + 25 + 1 + + + FMSEL26 + Filter mode select + 26 + 1 + + + FMSEL27 + Filter mode select + 27 + 1 + + + + + FBWCFG + FBWCFG + Filter bit width config register + 0x20C + 0x20 + read-write + 0x00000000 + + + FBWSEL0 + Filter bit width select + 0 + 1 + + + FBWSEL1 + Filter bit width select + 1 + 1 + + + FBWSEL2 + Filter bit width select + 2 + 1 + + + FBWSEL3 + Filter bit width select + 3 + 1 + + + FBWSEL4 + Filter bit width select + 4 + 1 + + + FBWSEL5 + Filter bit width select + 5 + 1 + + + FBWSEL6 + Filter bit width select + 6 + 1 + + + FBWSEL7 + Filter bit width select + 7 + 1 + + + FBWSEL8 + Filter bit width select + 8 + 1 + + + FBWSEL9 + Filter bit width select + 9 + 1 + + + FBWSEL10 + Filter bit width select + 10 + 1 + + + FBWSEL11 + Filter bit width select + 11 + 1 + + + FBWSEL12 + Filter bit width select + 12 + 1 + + + FBWSEL13 + Filter bit width select + 13 + 1 + + + FBWSEL14 + Filter bit width select + 14 + 1 + + + FBWSEL15 + Filter bit width select + 15 + 1 + + + FBWSEL16 + Filter bit width select + 16 + 1 + + + FBWSEL17 + Filter bit width select + 17 + 1 + + + FBWSEL18 + Filter bit width select + 18 + 1 + + + FBWSEL19 + Filter bit width select + 19 + 1 + + + FBWSEL20 + Filter bit width select + 20 + 1 + + + FBWSEL21 + Filter bit width select + 21 + 1 + + + FBWSEL22 + Filter bit width select + 22 + 1 + + + FBWSEL23 + Filter bit width select + 23 + 1 + + + FBWSEL24 + Filter bit width select + 24 + 1 + + + FBWSEL25 + Filter bit width select + 25 + 1 + + + FBWSEL26 + Filter bit width select + 26 + 1 + + + FBWSEL27 + Filter bit width select + 27 + 1 + + + + + FRF + FRF + Filter related FIFO register + 0x214 + 0x20 + read-write + 0x00000000 + + + FRFSEL0 + Filter relation FIFO select + 0 + 1 + + + FRFSEL1 + Filter relation FIFO select + 1 + 1 + + + FRFSEL2 + Filter relation FIFO select + 2 + 1 + + + FRFSEL3 + Filter relation FIFO select + 3 + 1 + + + FRFSEL4 + Filter relation FIFO select + 4 + 1 + + + FRFSEL5 + Filter relation FIFO select + 5 + 1 + + + FRFSEL6 + Filter relation FIFO select + 6 + 1 + + + FRFSEL7 + Filter relation FIFO select + 7 + 1 + + + FRFSEL8 + Filter relation FIFO select + 8 + 1 + + + FRFSEL9 + Filter relation FIFO select + 9 + 1 + + + FRFSEL10 + Filter relation FIFO select + 10 + 1 + + + FRFSEL11 + Filter relation FIFO select + 11 + 1 + + + FRFSEL12 + Filter relation FIFO select + 12 + 1 + + + FRFSEL13 + Filter relation FIFO select + 13 + 1 + + + FRFSEL14 + Filter relation FIFO select + 14 + 1 + + + FRFSEL15 + Filter relation FIFO select + 15 + 1 + + + FRFSEL16 + Filter relation FIFO select + 16 + 1 + + FRFSEL17 + Filter relation FIFO select + 17 + 1 + + + FRFSEL18 + Filter relation FIFO select + 18 + 1 + + + FRFSEL19 + Filter relation FIFO select + 19 + 1 + + + FRFSEL20 + Filter relation FIFO select + 20 + 1 + + + FRFSEL21 + Filter relation FIFO select + 21 + 1 + + + FRFSEL22 + Filter relation FIFO select + 22 + 1 + + + FRFSEL23 + Filter relation FIFO select + 23 + 1 + + + FRFSEL24 + Filter relation FIFO select + 24 + 1 + + + FRFSEL25 + Filter relation FIFO select + 25 + 1 + + + FRFSEL26 + Filter relation FIFO select + 26 + 1 + + + FRFSEL27 + Filter relation FIFO select + 27 + 1 + + + + + FACFG + FACFG + Filter activate configuration register + 0x21C + 0x20 + read-write + 0x00000000 + + + FAEN0 + Filter activate enable + 0 + 1 + + + FAEN1 + Filter activate enable + 1 + 1 + + + FAEN2 + Filter activate enable + 2 + 1 + + + FAEN3 + Filter activate enable + 3 + 1 + + + FAEN4 + Filter activate enable + 4 + 1 + + + FAEN5 + Filter activate enable + 5 + 1 + + + FAEN6 + Filter activate enable + 6 + 1 + + + FAEN7 + Filter activate enable + 7 + 1 + + + FAEN8 + Filter activate enable + 8 + 1 + + + FAEN9 + Filter activate enable + 9 + 1 + + + FAEN10 + Filter activate enable + 10 + 1 + + + FAEN11 + Filter activate enable + 11 + 1 + + + FAEN12 + Filter activate enable + 12 + 1 + + + FAEN13 + Filter activate enable + 13 + 1 + + + FAEN14 + Filter activate enable + 14 + 1 + + FAEN15 + Filter activate enable + 15 + 1 + + + FAEN16 + Filter activate enable + 16 + 1 + + + FAEN17 + Filter activate enable + 17 + 1 + + + FAEN18 + Filter activate enable + 18 + 1 + + + FAEN19 + Filter activate enable + 19 + 1 + + + FAEN20 + Filter activate enable + 20 + 1 + + + FAEN21 + Filter activate enable + 21 + 1 + + + FAEN22 + Filter activate enable + 22 + 1 + + + FAEN23 + Filter activate enable + 23 + 1 + + + FAEN24 + Filter activate enable + 24 + 1 + + + FAEN25 + Filter activate enable + 25 + 1 + + + FAEN26 + Filter activate enable + 26 + 1 + + + FAEN27 + Filter activate enable + 27 + 1 + + + + + F0FB1 + F0FB1 + Filter bank 0 filtrate bit register 1 + 0x240 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F0FB2 + F0FB2 + Filter bank 0 filtrate bit register 2 + 0x244 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB1 + F1FB1 + Filter bank 1 filtrate bit register 1 + 0x248 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F1FB2 + F1FB2 + Filter bank 1 filtrate bit register 2 + 0x24C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data 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bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F24FB2 + F24FB2 + Filter bank 24 filtrate bit register 2 + 0x304 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB1 + F25FB1 + Filter bank 25 filtrate bit register 1 + 0x308 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F25FB2 + F25FB2 + Filter bank 25 filtrate bit register 2 + 0x30C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB1 + F26FB1 + Filter bank 26 filtrate bit register 1 + 0x310 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F26FB2 + F26FB2 + Filter bank 26 filtrate bit register 2 + 0x314 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB1 + F27FB1 + Filter bank 27 filtrate bit register 1 + 0x318 + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + F27FB2 + F27FB2 + Filter bank 27 filtrate bit register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FFDB0 + Filter data bit + 0 + 1 + + + FFDB1 + Filter data bit + 1 + 1 + + + FFDB2 + Filter data bit + 2 + 1 + + + FFDB3 + Filter data bit + 3 + 1 + + + FFDB4 + Filter data bit + 4 + 1 + + + FFDB5 + Filter data bit + 5 + 1 + + + FFDB6 + Filter data bit + 6 + 1 + + + FFDB7 + Filter data bit + 7 + 1 + + + FFDB8 + Filter data bit + 8 + 1 + + + FFDB9 + Filter data bit + 9 + 1 + + + FFDB10 + Filter data bit + 10 + 1 + + + FFDB11 + Filter data bit + 11 + 1 + + + FFDB12 + Filter data bit + 12 + 1 + + + FFDB13 + Filter data bit + 13 + 1 + + + FFDB14 + Filter data bit + 14 + 1 + + + FFDB15 + Filter data bit + 15 + 1 + + + FFDB16 + Filter data bit + 16 + 1 + + + FFDB17 + Filter data bit + 17 + 1 + + + FFDB18 + Filter data bit + 18 + 1 + + + FFDB19 + Filter data bit + 19 + 1 + + + FFDB20 + Filter data bit + 20 + 1 + + + FFDB21 + Filter data bit + 21 + 1 + + + FFDB22 + Filter data bit + 22 + 1 + + + FFDB23 + Filter data bit + 23 + 1 + + + FFDB24 + Filter data bit + 24 + 1 + + + FFDB25 + Filter data bit + 25 + 1 + + + FFDB26 + Filter data bit + 26 + 1 + + + FFDB27 + Filter data bit + 27 + 1 + + + FFDB28 + Filter data bit + 28 + 1 + + + FFDB29 + Filter data bit + 29 + 1 + + + FFDB30 + Filter data bit + 30 + 1 + + + FFDB31 + Filter data bit + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupt + 63 + + + CAN2_RX0 + CAN2 RX0 interrupt + 64 + + + CAN2_RX1 + CAN2 RX1 interrupt + 65 + + + CAN2_SE + CAN2 SE interrupt + 66 + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CTRL + CTRL + Control register (DAC_CTRL) + 0x0 + 0x20 + read-write + 0x00000000 + + + D1EN + DAC1 enable + 0 + 1 + + + D1OBDIS + DAC1 output buffer disable + 1 + 1 + + + D1TRGEN + DAC1 trigger enable + 2 + 1 + + + D1TRGSEL + DAC1 trigger selection + 3 + 3 + + + D1NM + DAC1 noise/triangle wave generation enable + 6 + 2 + + + D1NBSEL + DAC1 mask/amplitude selector + 8 + 4 + + + D1DMAEN + DAC1 DMA enable + 12 + 1 + + + D1DMAUDRIEN + DAC1 DMA underrun interrupt enable + 13 + 1 + + + D2EN + DAC2 enable + 16 + 1 + + + D2OBDIS + DAC2 output buffer disable + 17 + 1 + + + D2TRGEN + DAC2 trigger enable + 18 + 1 + + + D2TRGSEL + DAC2 trigger selection + 19 + 3 + + + D2NM + DAC2 noise/triangle wave generation enable + 22 + 2 + + + D2NBSEL + DAC2 mask/amplitude selector + 24 + 4 + + + D2DMAEN + DAC2 DMA enable + 28 + 1 + + + D2DMAUDRIEN + DAC2 DMA underrun interrupt enable + 29 + 1 + + + + + SWTRG + SWTRG + DAC software trigger register(DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + D1SWTRG + DAC1 software trigger + 0 + 1 + + + D2SWTRG + DAC2 software trigger + 1 + 1 + + + + + D1DTH12R + D1DTH12R + DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) + 0x8 + 0x20 + read-write + 0x00000000 + + + D1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + + + D1DTH12L + D1DTH12L + DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) + 0xC + 0x20 + read-write + 0x00000000 + + + D1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + + + D1DTH8R + D1DTH8R + DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) + 0x10 + 0x20 + read-write + 0x00000000 + + + D1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + + + D2DTH12R + D2DTH12R + DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) + 0x14 + 0x20 + read-write + 0x00000000 + + + D2DT12R + DAC2 12-bit right-aligned + data + 0 + 12 + + + + + D2DTH12L + D2DTH12L + DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) + 0x18 + 0x20 + read-write + 0x00000000 + + + D2DT12L + DAC2 12-bit left-aligned data + 4 + 12 + + + + + D2DTH8R + D2DTH8R + DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) + 0x1C + 0x20 + read-write + 0x00000000 + + + D2DT8R + DAC2 8-bit right-aligned + data + 0 + 8 + + + + + DDTH12R + DDTH12R + Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DD1DT12R + DAC1 12-bit right-aligned data + 0 + 12 + + + DD2DT12R + DAC2 12-bit right-aligned data + 16 + 12 + + + + + DDTH12L + DDTH12L + DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DD1DT12L + DAC1 12-bit left-aligned data + 4 + 12 + + + DD2DT12L + DAC2 12-bit right-aligned data + 20 + 12 + + + + + DDTH8R + DDTH8R + DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DD1DT8R + DAC1 8-bit right-aligned data + 0 + 8 + + + DD2DT8R + DAC2 8-bit right-aligned data + 8 + 8 + + + + + D1ODT + D1ODT + DAC1 data output register (DAC_D1ODT) + 0x2C + 0x20 + read-only + 0x00000000 + + + D1ODT + DAC1 data output + 0 + 12 + + + + + D2ODT + D2ODT + DAC2 data output register (DAC_D2ODT) + 0x30 + 0x20 + read-only + 0x00000000 + + + D2ODT + DAC2 data output + 0 + 12 + + + + + STS + STS + DAC2 status register + (DAC_STS) + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR1 + DAC1 DMA underrun flag + 13 + 1 + + + DMAUDR2 + DAC2 DMA underrun flag + 29 + 1 + + + + + + + DEBUG + Debug support + DEBUG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DEBUG IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + PID + Product ID + 0 + 32 + + + + + CTRL + CTRL + DEBUG CTRL + 0x4 + 0x20 + read-write + 0x0 + + + SLEEP_DEBUG + SLEEP_DEBUG + 0 + 1 + + + DEEPSLEEP_DEBUG + DEEPSLEEP_DEBUG + 1 + 1 + + + STANDBY_DEBUG + STANDBY_DEBUG + 2 + 1 + + + + + APB1_PAUSE + APB1_PAUSE + DEBUG APB1 PAUSE + 0x8 + 0x20 + read-write + 0x0 + + + TMR2_PAUSE + TMR2_PAUSE + 0 + 1 + + + TMR3_PAUSE + TMR3_PAUSE + 1 + 1 + + + TMR4_PAUSE + TMR4_PAUSE + 2 + 1 + + + TMR5_PAUSE + TMR5_PAUSE + 3 + 1 + + + TMR6_PAUSE + TMR6_PAUSE + 4 + 1 + + + TMR7_PAUSE + TMR7_PAUSE + 5 + 1 + + + TMR12_PAUSE + TMR12_PAUSE + 6 + 1 + + + TMR13_PAUSE + TMR13_PAUSE + 7 + 1 + + + TMR14_PAUSE + TMR14_PAUSE + 8 + 1 + + + ERTC_PAUSE + ERTC_PAUSE + 10 + 1 + + + WWDT_PAUSE + WWDT_PAUSE + 11 + 1 + + + WDT_PAUSE + WDT_PAUSE + 12 + 1 + + + ERTC512_PAUSE + ERTC512_PAUSE + 15 + 1 + + + I2C1_SMBUS_TIMEOUT + I2C1_SMBUS_TIMEOUT + 24 + 1 + + + CAN1_PAUSE + CAN1_PAUSE + 25 + 1 + + + CAN2_PAUSE + CAN2_PAUSE + 26 + 1 + + + I2C2_SMBUS_TIMEOUT + I2C2_SMBUS_TIMEOUT + 27 + 1 + + + I2C3_SMBUS_TIMEOUT + I2C3_SMBUS_TIMEOUT + 28 + 1 + + + + + APB2_PAUSE + APB2_PAUSE + DEBUG APB2 PAUSE + 0xC + 0x20 + read-write + 0x0 + + + TMR1_PAUSE + TMR1_PAUSE + 0 + 1 + + + TMR8_PAUSE + TMR8_PAUSE + 1 + 1 + + + TMR20_PAUSE + TIM20_PAUSE + 6 + 1 + + + TMR9_PAUSE + TMR9_PAUSE + 16 + 1 + + + TMR10_PAUSE + TMR10_PAUSE + 17 + 1 + + + TMR11_PAUSE + TMR11_PAUSE + 18 + 1 + + + + + SER_ID + SER_ID + SERIES ID + 0x20 + 0x20 + read-only + 0x0 + + + REV_ID + version ID + 0 + 3 + + + SER_ID + series ID + 8 + 8 + + + + + + + UART4 + Universal asynchronous receiver transmitter + 0x40004C00 + + UART4 + UART4 global interrupt + 52 + + + + UART5 + Universal asynchronous receiver transmitter + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + Universal asynchronous receiver transmitter + 0x40007800 + + UART7 + UART7 global interrupt + 82 + + + + UART8 + Universal asynchronous receiver transmitter + 0x40007C00 + + UART8 + UART8 global interrupt + 83 + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DT + DT + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DT + Data Register + 0 + 32 + + + + + CDT + CDT + Common data register + 0x4 + 0x20 + read-write + 0x00000000 + + + CDT + Common Data + 0 + 1 + + + + + CTRL + CTRL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + Reset bit + 0 + 1 + + + REVID + Reverse input data + 5 + 2 + + + REVOD + Reverse output data + 7 + 1 + + + + + IDT + IDT + Initial data register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDT + Initial Data + 0 + 32 + + + + + + + FLASH + Flash memory controler + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + PSR + PSR + Performance selection register + 0x0 + 0x20 + 0x00000330 + + + NZW_BST_STS + Flash non-zero wait area boost status + 13 + 1 + read-only + + + NZW_BST + Flash non-zero wait area boost + 12 + 1 + read-write + + + + + UNLOCK + UNLOCK + Unlock register + 0x4 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + USD_UNLOCK + USD_UNLOCK + USD unlock register + 0x8 + 0x20 + write-only + 0x00000000 + + + USD_UKVAL + User system data Unlock key value + 0 + 32 + + + + + STS + STS + Status register + 0xC + 0x20 + 0x00000000 + + + ODF + Operate done flag + 5 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + PRGMERR + program error + 2 + 1 + read-write + + + OBF + Operate busy flag + 0 + 1 + read-only + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + USDPRGM + User system data program + 4 + 1 + + + USDERS + User system data erase + 5 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + USDULKS + User system data unlock success + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + USD + USD + User system data register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + USDERR + User system data error + 0 + 1 + + + FAP + FLASH access protection + 1 + 1 + + + nWDT_ATO_EN + WDT auto enable + 2 + 1 + + + nDEPSLP_RST + Deepsleep reset + 3 + 1 + + + nSTDBY_RST + Standby reset + 4 + 1 + + + BTOPT + boot option + 5 + 1 + + + nWDT_DEPSLP + WDT deep sleep + 7 + 1 + + + nWDT_STDBY + WDT standby + 8 + 1 + + + USER_D0 + User data 0 + 10 + 8 + + + USER_D1 + User data 1 + 18 + 8 + + + + + EPPS0 + EPPS0 + Erase/program protection status register 0 + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + EPPS1 + EPPS1 + Erase/program protection status register 1 + 0x2C + 0x20 + read-only + 0xFFFFFFFF + + + EPPS + Erase/program protection status + 0 + 32 + + + + + UNLOCK2 + UNLOCK2 + Unlock 2 register + 0x44 + 0x20 + write-only + 0x00000000 + + + UKVAL + Unlock key value + 0 + 32 + + + + + STS2 + STS2 + Status 2 register + 0x4C + 0x20 + 0x00000000 + + + OBF + Operate busy flag + 0 + 1 + read-only + + + PRGMERR + program error + 2 + 1 + read-write + + + EPPERR + Erase/program protection error + 4 + 1 + read-write + + + ODF + Operate done flag + 5 + 1 + read-write + + + + + CTRL2 + CTRL2 + Control 2 register + 0x50 + 0x20 + read-write + 0x00000080 + + + FPRGM + Flash program + 0 + 1 + + + SECERS + Sector erase + 1 + 1 + + + BANKERS + Bank erase + 2 + 1 + + + BLKERS + Block erase + 3 + 1 + + + ERSTR + Erasing start + 6 + 1 + + + OPLK + Operation lock + 7 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + ODFIE + Operation done flag interrupt enable + 12 + 1 + + + + + ADDR2 + ADDR2 + Address 2 register + 0x54 + 0x20 + write-only + 0x00000000 + + + FA + Flash Address + 0 + 32 + + + + + CONTR + CONTR + Flash continue read register + 0x58 + 0x20 + read-write + 0x00000080 + + + FCONTR_EN + Flash continue read enable + 31 + 1 + + + + + DIVR + DIVR + Flash divider register + 0x60 + 0x20 + 0x00000022 + + + FDIV + Flash divider + 0 + 2 + read-write + + + FDIV_STS + Flash divider status + 4 + 2 + read-only + + + + + SLIB_STS2 + SLIB_STS2 + sLib status 2 register + 0xC8 + 0x20 + 0x0000FFFF + + + SLIB_INST_SS + sLib instruction start sector + 0 + 16 + read-only + + + + + SLIB_STS0 + SLIB_STS0 + sLib status 0 register + 0xCC + 0x20 + 0x00000000 + + + SLIB_ENF + sLib enabled flag + 3 + 1 + read-only + + + + + SLIB_STS1 + SLIB_STS1 + sLib status 1 register + 0xD0 + 0x20 + 0xFFFFFFFF + + + SLIB_SS + sLib start sector + 0 + 16 + read-only + + + SLIB_ES + sLib end sector + 16 + 16 + read-only + + + + + SLIB_PWD_CLR + SLIB_PWD_CLR + SLIB password clear register + 0xD4 + 0x20 + 0x00000000 + write-only + + + SLIB_PCLR_VAL + sLib password clear value + 0 + 32 + + + + + SLIB_MISC_STS + SLIB_MISC_STS + sLib misc status register + 0xD8 + 0x20 + 0x01000000 + + + SLIB_PWD_ERR + sLib password error + 0 + 1 + read-only + + + SLIB_PWD_OK + sLib password ok + 1 + 1 + read-only + + + SLIB_ULKF + sLib unlock flag + 2 + 1 + read-only + + + SLIB_RCNT + sLib remaining count + 16 + 9 + read-only + + + + + SLIB_SET_PWD + SLIB_SET_PWD + sLib password setting register + 0xDC + 0x20 + 0x00000000 + write-only + + + SLIB_PSET_VAL + sLib password setting val + 0 + 32 + + + + + SLIB_SET_RANGE0 + SLIB_SET_RANGE0 + Configure sLib range register 0 + 0xE0 + 0x20 + 0x00000000 + write-only + + + SLIB_SS_SET + sLib start sector setting + 0 + 16 + + + SLIB_ES_SET + sLib end sector setting + 16 + 16 + + + + + SLIB_SET_RANGE1 + SLIB_SET_RANGE1 + Configure sLib range register 1 + 0xE4 + 0x20 + 0x00000000 + write-only + + + SLIB_ISS_SET + sLib instruction start sector setting + 0 + 16 + + + SET_SLIB_STRT + sLib start setting + 31 + 1 + + + + + SLIB_UNLOCK + SLIB_UNLOCK + sLib unlock register + 0xF0 + 0x20 + 0x00000000 + write-only + + + SLIB_UKVAL + sLib unlock key value + 0 + 32 + + + + + CRC_CTRL + CRC_CTRL + CRC controler register + 0xF4 + 0x20 + 0x00000000 + write-only + + + CRC_SS + CRC start sector + 0 + 12 + + + CRC_SN + CRC sector numbler + 12 + 12 + + + CRC_STRT + CRC start + 31 + 1 + + + + + CRC_CHKR + CRC_CHKR + CRC check result register + 0xF8 + 0x20 + 0x00000000 + read-only + + + CRC_CHKR + CRC check result + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E000 + + 0x0 + 0x1001 + registers + + + + ICTR + ICTR + Interrupt Controller Type + Register + 0x4 + 0x20 + read-only + 0x00000000 + + + INTLINESNUM + Total number of interrupt lines in + groups + 0 + 4 + + + + + STIR + STIR + Software Triggered Interrupt + Register + 0xF00 + 0x20 + write-only + 0x00000000 + + + INTID + interrupt to be triggered + 0 + 9 + + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x200 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x204 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x300 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x304 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x400 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x404 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x408 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x40C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x410 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x414 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x418 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x41C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x420 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x424 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x428 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x42C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x430 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x434 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x438 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + DVP + Digital video parallel interface + DVP + 0x50050000 + + 0x0 + 0x400 + registers + + + DVP + DVP global interrupt + 78 + + + + CTRL + CTRL + Control register + 0x0 + 0x20 + 0x0000 + + + LCDS + Line capture/drop selection + 20 + 1 + read-write + + + LCDC + Line capture/drop control + + 19 + 1 + read-write + + + PCDS + Pixel capture/drop selection + + 18 + 1 + read-write + + + PCDC + Basic pixel capture/drop control + + 16 + 2 + read-write + + + ENA + DVP enable + 14 + 1 + read-write + + + PDL + Pixel data length + 10 + 2 + read-write + + + BFRC + Basic frame rate control + 8 + 2 + read-write + + + VSP + Vertical synchronization + polarity + 7 + 1 + read-write + + + HSP + Horizontal synchronization polarity + + 6 + 1 + read-write + + + CKP + Pixel clock polarity + 5 + 1 + read-write + + + SM + synchronization mode + 4 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + CRP + Cropping function enable + 2 + 1 + read-write + + + CFM + Capture fire mode + 1 + 1 + read-write + + + CAP + Capture function enable + 0 + 1 + read-write + + + + + STS + STS + status register + 0x4 + 0x20 + read-only + 0x0000 + + + OFNE + Output FIFO Non-empty + 2 + 1 + + + VSYN + Vertical synchronization status + 1 + 1 + + + HSYN + Horizontal synchronization status + 0 + 1 + + + + + ESTS + ESTS + Event status register + 0x8 + 0x20 + read-only + 0x0000 + + + HSES + Horizontal synchronization event status + 4 + 1 + + + VSES + Vertical synchronization event status + 3 + 1 + + + ESEES + Embedded synchronization error event status + + 2 + 1 + + + OVRES + Data FIFO overrun event status + + 1 + 1 + + + CFDES + Capture frame done event status + + 0 + 1 + + + + + IENA + IENA + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + HSIE + Horizontal synchronization interrupt enable + + 4 + 1 + + + VSIE + Vertical synchronization interrupt enablee + + 3 + 1 + + + ESEIE + Embedded synchronization error interrupt + enable + 2 + 1 + + + OVRIE + Data FIFO overrun interrupt enable + + 1 + 1 + + + CFDIE + Capture frame done interrupt enable + + 0 + 1 + + + + + ISTS + ISTS + Interrupt status register + 0x10 + 0x20 + read-only + 0x0000 + + + HSIS + Horizontal synchronization interrupt + status + 4 + 1 + + + VSIS + Vertical synchronization interrupt + status + 3 + 1 + + + ESEIS + Embedded synchronization error + interrupt status + 2 + 1 + + + OVRIS + Data FIFO overrun interrupt + status + 1 + 1 + + + CFDIS + Capture frame done interrupt + status + 0 + 1 + + + + + ICLR + ICLR + Interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + HSIC + Horizontal synchronization + interrupt clear + 4 + 1 + + + VSIC + Vertical synchronization + interrupt clear + 3 + 1 + + + ESEIC + Embedded synchronization + error interrupt clear + 2 + 1 + + + OVRIC + Data FIFO overrun + interrupt clear + 1 + 1 + + + CFDIC + Capture frame done + interrupt clear + 0 + 1 + + + + + SCR + SCR + Synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FMEC + Frame end code + 24 + 8 + + + LNEC + Line end code + 16 + 8 + + + LNSC + Line start code + 8 + 8 + + + FMSC + Frame start code + 0 + 8 + + + + + SUR + SUR + Synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FMEU + Frame end unmask + 24 + 8 + + + LNEU + Line end unmask + 16 + 8 + + + LNSU + Line start unmask + + 8 + 8 + + + FMSU + Frame start unmask + + 0 + 8 + + + + + CWST + CWST + Crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + CVSTR + Cropping window vertical start line + + 16 + 13 + + + CHSTR + Cropping window horizontal start pixel + + 0 + 14 + + + + + CWSZ + CWSZ + Crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + CVNUM + Cropping window vertical line number + + 16 + 14 + + + CHNUM + Cropping window horizontal pixel number + + 0 + 14 + + + + + DT + DT + Data register + 0x28 + 0x20 + read-only + 0x0000 + + + DT + Data Port + 0 + 32 + + + + + ACTRL + ACTRL + Advanced Control register + + 0x40 + 0x20 + read-write + 0x0000 + + + VSEID + Vertical synchonization event and interrupt + definition + 17 + 1 + + + HSEID + Horizontal synchonization event and interrupt + definition + 16 + 1 + + + DMABT + DMA burst transfer configuration + + 12 + 1 + + + IDUS + Input data un-used setting + + 10 + 1 + + + IDUN + Input data un-used number + + 8 + 2 + + + EFDM + Enhanced function data format management + + 6 + 1 + + + EFDF + Enhanced function data format + + 4 + 2 + + + PCDES + Basic pixel capture/drop extended + selection + 3 + 1 + + + MIBE + Monochrome image binarization + enable + 2 + 1 + + + EFRCE + Enhanced frame rate control + enable + 1 + 1 + + + EISRE + Enhanced image scaling resize + enable + 0 + 1 + + + + + HSCF + HSCF + Horizontal scaling control flow + + 0x48 + 0x20 + read-write + 0x0000 + + + HSRTF + Horizontal scaling resize target factor + + 16 + 13 + + + HSRSF + Horizontal scaling resize source factor + + 0 + 13 + + + + + VSCF + VSCF + Vertical scaling control flow + + 0x4C + 0x20 + read-write + 0x0000 + + + VSRTF + Vertical scaling resize target factor + + 16 + 13 + + + VSRSF + Vertical scaling resize source factor + + 0 + 13 + + + + + FRF + FRF + Frame rate flow + + 0x50 + 0x20 + read-write + 0x0000 + + + EFRCTF + Enhanced frame rate control target factor + + 8 + 5 + + + EFRCSF + Enhanced frame rate contorl source factor + + 0 + 5 + + + + + BTH + BTH + Binarization threshold + + 0x54 + 0x20 + read-write + 0x0000 + + + MIBTHD + Monochrome image binarization threshold + + 0 + 8 + + + + + + + USB_OTG1_GLOBAL + USB on-the-go full speed + USB_OTG1 + 0x50000000 + + 0x0 + 0x400 + registers + + + OTGFS1 + USB On The Go FS global + interrupt + 67 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-write + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG1_HOST + USB on the go full speed + USB_OTG1 + 0x50000400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG1_DEVICE + USB on the go full speed + USB_OTG1 + 0x50000800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG1_PWRCLK + USB on the go full speed + USB_OTG1 + 0x50000E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + USB_OTG2_GLOBAL + USB on the go full speed + USB_OTG2 + 0x40040000 + + 0x0 + 0x400 + registers + + + OTGFS2 + USB On The Go FS2 global + interrupt + 77 + + + + GOTGCTL + GOTGCTL + OTGFS control and status register + (OTGFS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + CONIDSTS + Connector ID status + 16 + 1 + read-only + + + CURMOD + Current Mode of Operation + 21 + 1 + read-only + + + + + GOTGINT + GOTGINT + OTGFS interrupt register + (OTGFS_GOTGINT) + 0x4 + 0x20 + 0x00000000 + + + SESENDDET + VBUS is deasserted + 2 + 1 + read-write + + + + + GAHBCFG + GAHBCFG + OTGFS AHB configuration register + (OTGFS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GLBINTMSK + Global interrupt mask + 0 + 1 + + + NPTXFEMPLVL + Non-Periodic TxFIFO empty level + 7 + 1 + + + PTXFEMPLVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + GUSBCFG + GUSBCFG + USB configuration register + (OTGFS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOUTCAL + FS timeout calibration + 0 + 3 + read-write + + + USBTRDTIM + USB turnaround time + 10 + 4 + read-write + + + FHSTMODE + Force host mode + 29 + 1 + read-write + + + FDEVMODE + Force device mode + 30 + 1 + read-write + + + COTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + GRSTCTL + GRSTCTL + OTGFS reset register + (OTGFS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSFTRST + Core soft reset + 0 + 1 + read-write + + + PIUSFTRST + PIU FS Dedicated Controller Soft Reset + 1 + 1 + read-write + + + FRMCNTRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDLE + AHB master idle + 31 + 1 + read-only + + + + + GINTSTS + GINTSTS + OTGFS core interrupt register + (OTGFS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CURMOD + Current mode of operation + 0 + 1 + read-only + + + MODEMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFEMP + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINNAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ERLYSUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDONE + Enumeration done + 13 + 1 + read-write + + + ISOOUTDROP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPTINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPTINT + OUT endpoint interrupt + 19 + 1 + read-only + + + INCOMPISOIN + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + PRTINT + Host port interrupt + 24 + 1 + read-only + + + HCHINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFEMP + Periodic TxFIFO empty + 26 + 1 + read-only + + + CONIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCONINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + GINTMSK + GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MODEMISMSK + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINTMSK + OTG interrupt mask + 2 + 1 + read-write + + + SOFMSK + Start of frame mask + 3 + 1 + read-write + + + RXFLVLMSK + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEMPMSK + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINNAKEFFMSK + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GOUTNAKEFFMSK + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ERLYSUSPMSK + Early suspend mask + 10 + 1 + read-write + + + USBSUSPMSK + USB suspend mask + 11 + 1 + read-write + + + USBRSTMSK + USB reset mask + 12 + 1 + read-write + + + ENUMDONEMSK + Enumeration done mask + 13 + 1 + read-write + + + ISOOUTDROPMSK + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFMSK + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + IEPTINTMSK + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPTINTMSK + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + INCOMISOINMSK + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + INCOMPIP_INCOMPISOOUTMSK + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTINTMSK + Host port interrupt mask + 24 + 1 + read-only + + + HCHINTMSK + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEMPMSK + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CONIDSCHGMSK + Connector ID status change + mask + 28 + 1 + read-write + + + DISCONINTMSK + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + WKUPINTMSK + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + GRXSTSR_Device + GRXSTSR_Device + OTGFS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPTNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FN + Frame number + 21 + 4 + + + + + GRXSTSR_Host + GRXSTSR_Host + OTGFS Receive status debug read(Host + mode) + GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + GRXFSIZ + GRXFSIZ + OTGFS Receive FIFO size register + (OTGFS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFDEP + RxFIFO depth + 0 + 16 + + + + + DIEPTXF0 + DIEPTXF0 + IN Endpoint TxFIFO 0 transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + INEPT0TXSTADDR + Endpoint 0 transmit RAM start + address + 0 + 16 + + + INEPT0TXDEP + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + GNPTXFSIZ + GNPTXFSIZ + OTGFS non-periodic transmit FIFO size + register (Host mode) + DIEPTXF0 + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSTADDR + Non-periodic Transmit RAM Start + address + 0 + 16 + + + NPTXFDEP + Non-periodic TxFIFO depth + 16 + 16 + + + + + GNPTXSTS + GNPTXSTS + OTGFS non-periodic transmit FIFO/queue + status register (OTGFS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSPCAVAIL + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTXQSPCAVAIL + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + GCCFG + GCCFG + OTGFS general core configuration register + (OTGFS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDOWN + Power down + 16 + 1 + + + LP_MODE + Low power mode + 17 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + VBUSIG + VBUS Ignored + 21 + 1 + + + + + GUID + GUID + Product ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + USERID + Product ID field + 0 + 32 + + + + + HPTXFSIZ + HPTXFSIZ + OTGFS Host periodic transmit FIFO size + register (OTGFS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXFSTADDR + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZE + Host periodic TxFIFO depth + 16 + 16 + + + + + DIEPTXF1 + DIEPTXF1 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF1) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO1 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF2 + DIEPTXF2 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF2) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF3 + DIEPTXF3 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF3) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF4 + DIEPTXF4 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF4) + 0x110 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF5 + DIEPTXF5 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF5) + 0x114 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO5 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF6 + DIEPTXF6 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF6) + 0x118 + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO6 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + DIEPTXF7 + DIEPTXF7 + OTGFS device IN endpoint transmit FIFO size + register (OTGFS_DIEPTXF7) + 0x11C + 0x20 + read-write + 0x02000400 + + + INEPTXFSTADDR + IN endpoint FIFO7 transmit RAM start + address + 0 + 16 + + + INEPTXFDEP + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG2_HOST + USB on the go full speed + USB_OTG2 + 0x40040400 + + 0x0 + 0x400 + registers + + + + HCFG + HCFG + OTGFS host configuration register + (OTGFS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCLKSEL + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSSUPP + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTGFS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRINT + Frame interval + 0 + 16 + + + + + HFNUM + HFNUM + OTGFS host frame number/frame time + remaining register (OTGFS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + HPTXSTS + HPTXSTS + OTGFS_Host periodic transmit FIFO/queue + status register (OTGFS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSPCAVAIL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSPCAVAIL + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTGFS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTGFS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTMSK + Channel interrupt mask + 0 + 16 + + + + + HPRT + HPRT + OTGFS host port control and status register + (OTGFS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PRTCONSTS + Port connect status + 0 + 1 + read-only + + + PRTCONDET + Port connect detected + 1 + 1 + read-write + + + PRTENA + Port enable + 2 + 1 + read-write + + + PRTENCHNG + Port enable/disable change + 3 + 1 + read-write + + + PRTOVRCACT + Port overcurrent active + 4 + 1 + read-only + + + PRTOVRCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRTRES + Port resume + 6 + 1 + read-write + + + PRTSUSP + Port suspend + 7 + 1 + read-write + + + PRTRST + Port reset + 8 + 1 + read-write + + + PRTLNSTS + Port line status + 10 + 2 + read-only + + + PRTPWR + Port power + 12 + 1 + read-write + + + PRTTSTCTL + Port test control + 13 + 4 + read-write + + + PRTSPD + Port speed + 17 + 2 + read-only + + + + + HCCHAR0 + HCCHAR0 + OTGFS host channel-0 characteristics + register (OTGFS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR1 + HCCHAR1 + OTGFS host channel-1 characteristics + register (OTGFS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR2 + HCCHAR2 + OTGFS host channel-2 characteristics + register (OTGFS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR3 + HCCHAR3 + OTGFS host channel-3 characteristics + register (OTGFS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR4 + HCCHAR4 + OTGFS host channel-4 characteristics + register (OTGFS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR5 + HCCHAR5 + OTGFS host channel-5 characteristics + register (OTGFS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR6 + HCCHAR6 + OTGFS host channel-6 characteristics + register (OTGFS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR7 + HCCHAR7 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR8 + HCCHAR8 + OTGFS host channel-8 characteristics + register (OTGFS_HCCHAR8) + 0x200 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR9 + HCCHAR9 + OTGFS host channel-9 characteristics + register (OTGFS_HCCHAR9) + 0x220 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR10 + HCCHAR10 + OTGFS host channel-10 characteristics + register (OTGFS_HCCHAR10) + 0x240 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR11 + HCCHAR11 + OTGFS host channel-7 characteristics + register (OTGFS_HCCHAR11) + 0x260 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR12 + HCCHAR12 + OTGFS host channel-12 characteristics + register (OTGFS_HCCHAR12) + 0x280 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR13 + HCCHAR13 + OTGFS host channel-13 characteristics + register (OTGFS_HCCHAR13) + 0x2A0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR14 + HCCHAR14 + OTGFS host channel-14 characteristics + register (OTGFS_HCCHAR14) + 0x2C0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCCHAR15 + HCCHAR15 + OTGFS host channel-15 characteristics + register (OTGFS_HCCHAR15) + 0x2E0 + 0x20 + read-write + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + + + EPTNUM + Endpoint number + 11 + 4 + + + EPTDIR + Endpoint direction + 15 + 1 + + + LSPDDEV + Low-speed device + 17 + 1 + + + EPTYPE + Endpoint type + 18 + 2 + + + MC + Multicount + 20 + 2 + + + DEVADDR + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + HCINT0 + HCINT0 + OTGFS host channel-0 interrupt register + (OTGFS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT1 + HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT2 + HCINT2 + OTGFS host channel-2 interrupt register + (OTGFS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT3 + HCINT3 + OTGFS host channel-3 interrupt register + (OTGFS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT4 + HCINT4 + OTGFS host channel-4 interrupt register + (OTGFS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT5 + HCINT5 + OTGFS host channel-5 interrupt register + (OTGFS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT6 + HCINT6 + OTGFS host channel-6 interrupt register + (OTGFS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT7 + HCINT7 + OTGFS host channel-7 interrupt register + (OTGFS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT8 + HCINT8 + OTGFS host channel-8 interrupt register + (OTGFS_HCINT8) + 0x208 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT9 + HCINT9 + OTGFS host channel-9 interrupt register + (OTGFS_HCINT9) + 0x228 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT10 + HCINT10 + OTGFS host channel-10 interrupt register + (OTGFS_HCINT10) + 0x248 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT11 + HCINT11 + OTGFS host channel-11 interrupt register + (OTGFS_HCINT11) + 0x268 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT12 + HCINT12 + OTGFS host channel-12 interrupt register + (OTGFS_HCINT12) + 0x288 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT13 + HCINT13 + OTGFS host channel-13 interrupt register + (OTGFS_HCINT13) + 0x2A8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT14 + HCINT14 + OTGFS host channel-14 interrupt register + (OTGFS_HCINT14) + 0x2C8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINT15 + HCINT15 + OTGFS host channel-15 interrupt register + (OTGFS_HCINT15) + 0x2E8 + 0x20 + read-write + 0x00000000 + + + XFERC + Transfer completed + 0 + 1 + + + CHHLTD + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + XACTERR + Transaction error + 7 + 1 + + + BBLERR + Babble error + 8 + 1 + + + FRMOVRUN + Frame overrun + 9 + 1 + + + DTGLERR + Data toggle error + 10 + 1 + + + + + HCINTMSK0 + HCINTMSK0 + OTGFS host channel-0 mask register + (OTGFS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK1 + HCINTMSK1 + OTGFS host channel-1 mask register + (OTGFS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK2 + HCINTMSK2 + OTGFS host channel-2 mask register + (OTGFS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK3 + HCINTMSK3 + OTGFS host channel-3 mask register + (OTGFS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK4 + HCINTMSK4 + OTGFS host channel-4 mask register + (OTGFS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK5 + HCINTMSK5 + OTGFS host channel-5 mask register + (OTGFS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK6 + HCINTMSK6 + OTGFS host channel-6 mask register + (OTGFS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK7 + HCINTMSK7 + OTGFS host channel-7 mask register + (OTGFS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK8 + HCINTMSK8 + OTGFS host channel-8 mask register + (OTGFS_HCINTMSK8) + 0x20C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK9 + HCINTMSK9 + OTGFS host channel-9 mask register + (OTGFS_HCINTMSK9) + 0x22C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK10 + HCINTMSK10 + OTGFS host channel-10 mask register + (OTGFS_HCINTMSK10) + 0x24C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK11 + HCINTMSK11 + OTGFS host channel-11 mask register + (OTGFS_HCINTMSK11) + 0x26C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK12 + HCINTMSK12 + OTGFS host channel-12 mask register + (OTGFS_HCINTMSK12) + 0x28C + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK13 + HCINTMSK13 + OTGFS host channel-13 mask register + (OTGFS_HCINTMSK13) + 0x2AC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK14 + HCINTMSK14 + OTGFS host channel-14 mask register + (OTGFS_HCINTMSK14) + 0x2CC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCINTMSK15 + HCINTMSK15 + OTGFS host channel-15 mask register + (OTGFS_HCINTMSK15) + 0x2EC + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed mask + 0 + 1 + + + CHHLTDMSK + Channel halted mask + 1 + 1 + + + STALLMSK + STALL response received interrupt + mask + 3 + 1 + + + NAKMSK + NAK response received interrupt + mask + 4 + 1 + + + ACKMSK + ACK response received/transmitted + interrupt mask + 5 + 1 + + + XACTERRMSK + Transaction error mask + 7 + 1 + + + BBLERRMSK + Babble error mask + 8 + 1 + + + FRMOVRUNMSK + Frame overrun mask + 9 + 1 + + + DTGLERRMSK + Data toggle error mask + 10 + 1 + + + + + HCTSIZ0 + HCTSIZ0 + OTGFS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ1 + HCTSIZ1 + OTGFS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ2 + HCTSIZ2 + OTGFS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ3 + HCTSIZ3 + OTGFS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ4 + HCTSIZ4 + OTGFS host channel-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ5 + HCTSIZ5 + OTGFS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ6 + HCTSIZ6 + OTGFS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ7 + HCTSIZ7 + OTGFS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ8 + HCTSIZ8 + OTGFS host channel-8 transfer size + register + 0x210 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ9 + HCTSIZ9 + OTGFS host channel-9 transfer size + register + 0x230 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ10 + HCTSIZ10 + OTGFS host channel-10 transfer size + register + 0x250 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ11 + HCTSIZ11 + OTGFS host channel-11 transfer size + register + 0x270 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ12 + HCTSIZ12 + OTGFS host channel-12 transfer size + register + 0x290 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ13 + HCTSIZ13 + OTGFS host channel-13 transfer size + register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ14 + HCTSIZ14 + OTGFS host channel-14 transfer size + register + 0x2D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + HCTSIZ15 + HCTSIZ15 + OTGFS host channel-15 transfer size + register + 0x2F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + PID + PID + 29 + 2 + + + + + + + USB_OTG2_DEVICE + USB on the go full speed + USB_OTG2 + 0x40040800 + + 0x0 + 0x400 + registers + + + + DCFG + DCFG + OTGFS device configuration register + (OTGFS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DEVSPD + Device speed + 0 + 2 + + + NZSTSOUTHSHK + Non-zero-length status OUT + handshake + 2 + 1 + + + DEVADDR + Device address + 4 + 7 + + + PERFRINT + Periodic frame interval + 11 + 2 + + + + + DCTL + DCTL + OTGFS device control register + (OTGFS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWKUPSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SFTDISCON + Soft disconnect + 1 + 1 + read-write + + + GNPINNAKSTS + Global IN NAK status + 2 + 1 + read-only + + + GOUTNAKSTS + Global OUT NAK status + 3 + 1 + read-only + + + TSTCTL + Test control + 4 + 3 + read-write + + + SGNPINNAK + Set global IN NAK + 7 + 1 + read-write + + + CGNPINNAK + Clear global IN NAK + 8 + 1 + read-write + + + SGOUTNAK + Set global OUT NAK + 9 + 1 + read-write + + + CGOUTNAK + Clear global OUT NAK + 10 + 1 + read-write + + + PWROPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + DSTS + DSTS + OTGFS device status register + (OTGFS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + ETICERR + Erratic error + 3 + 1 + + + SOFFN + Frame number of the received + SOF + 8 + 14 + + + + + DIEPMSK + DIEPMSK + OTGFS device IN endpoint common interrupt + mask register (OTGFS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + TIMEOUTMSK + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + INTKNTXFEMPMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INTKNEPTMISMSK + IN token received with EP mismatch + mask + 5 + 1 + + + INEPTNAKMSK + IN endpoint NAK effective + mask + 6 + 1 + + + TXFIFOUDRMSK + FIFO underrun + mask + 8 + 1 + + + BNAINMSK + BNA interrupt + mask + 9 + 1 + + + + + DOEPMSK + DOEPMSK + OTGFS device OUT endpoint common interrupt + mask register (OTGFS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFERCMSK + Transfer completed interrupt + mask + 0 + 1 + + + EPTDISMSK + Endpoint disabled interrupt + mask + 1 + 1 + + + SETUPMSK + SETUP phase done mask + 3 + 1 + + + OUTTEPDMSK + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSETUPMSK + Back-to-back SETUP packets + received mask + 6 + 1 + + + OUTPERRMSK + OUT packet error + mask + 8 + 1 + + + BNAOUTMSK + BNA interrupt + mask + 9 + 1 + + + + + DAINT + DAINT + OTGFS device all endpoints interrupt + register (OTGFS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + INEPTINT + IN endpoint interrupt bits + 0 + 16 + + + OUTEPTINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DAINTMSK + DAINTMSK + OTGFS all endpoints interrupt mask register + (OTGFS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + INEPTMSK + IN EP interrupt mask bits + 0 + 16 + + + OUTEPTMSK + OUT endpoint interrupt + bits + 16 + 16 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTGFS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEMSK + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + DIEPCTL0 + DIEPCTL0 + OTGFS device control IN endpoint 0 control + register (OTGFS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 2 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-only + + + EPTENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTGFS device IN endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTGFS device IN endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTGFS device IN endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL4 + DIEPCTL4 + OTGFS device IN endpoint-4 control + register + 0x180 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL5 + DIEPCTL5 + OTGFS device IN endpoint-5 control + register + 0x1A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL6 + DIEPCTL6 + OTGFS device IN endpoint-6 control + register + 0x1C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPCTL7 + DIEPCTL7 + OTGFS device IN endpoint-7 control + register + 0x1E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-write + + + DPID + Endpoint Data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SETD0PID + Set DATA0 PID + 28 + 1 + write-only + + + SETD1PID + Set DATA1 PID + 29 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + OTGFS device OUT endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + MPS + Maximum packet size + 0 + 2 + read-only + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL1 + DOEPCTL1 + OTGFS device OUT endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + OTGFS device OUT endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + OTGFS device OUT endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL4 + DOEPCTL4 + OTGFS device OUT endpoint-4 control + register + 0x380 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL5 + DOEPCTL5 + OTGFS device OUT endpoint-5 control + register + 0x3A0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL6 + DOEPCTL6 + OTGFS device OUT endpoint-6 control + register + 0x3C0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DOEPCTL7 + DOEPCTL7 + OTGFS device OUT endpoint-7 control + register + 0x3E0 + 0x20 + 0x00000000 + + + MPS + Maximum packet size + 0 + 11 + read-write + + + USBACEPT + USB active endpoint + 15 + 1 + read-only + + + DPID + Endpoint data PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYPE + Endpoint type + 18 + 2 + read-only + + + SNP + Snoop mode + 20 + 1 + read-write + + + STALL + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPTDIS + Endpoint disable + 30 + 1 + read-write + + + EPTENA + Endpoint enable + 31 + 1 + read-write + + + + + DIEPINT0 + DIEPINT0 + OTGFS device IN endpoint-0 interrupt + register + 0x108 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT1 + DIEPINT1 + OTGFS device IN endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT2 + DIEPINT2 + OTGFS device IN endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT3 + DIEPINT3 + OTGFS device IN endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT4 + DIEPINT4 + OTGFS device IN endpoint-4 interrupt + register + 0x188 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT5 + DIEPINT5 + OTGFS device IN endpoint-5 interrupt + register + 0x1A8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT6 + DIEPINT6 + OTGFS device IN endpoint-6 interrupt + register + 0x1C8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DIEPINT7 + DIEPINT7 + OTGFS device IN endpoint-7 interrupt + register + 0x1E8 + 0x20 + 0x00000080 + + + XFERC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPTDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TIMEOUT + Timeout condition + 3 + 1 + read-write + + + INTKNTXFEMP + IN token received when + TxFIFO is empty + 4 + 1 + read-write + + + INEPTNAK + IN endpoint NAK + effective + 6 + 1 + read-write + + + TXFEMP + Transmit FIFO + empty + 7 + 1 + read-only + + + + + DOEPINT0 + DOEPINT0 + OTGFS device OUT endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT1 + DOEPINT1 + OTGFS device OUT endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT2 + DOEPINT2 + OTGFS device OUT endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT3 + DOEPINT3 + OTGFS device OUT endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT4 + DOEPINT4 + OTGFS device OUT endpoint-4 interrupt + register + 0x388 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT5 + DOEPINT5 + OTGFS device OUT endpoint-5 interrupt + register + 0x3A8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT6 + DOEPINT6 + OTGFS device OUT endpoint-6 interrupt + register + 0x3C8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DOEPINT7 + DOEPINT7 + OTGFS device OUT endpoint-7 interrupt + register + 0x3E8 + 0x20 + read-write + 0x00000080 + + + XFERC + Transfer completed interrupt + 0 + 1 + + + EPTDISD + Endpoint disabled interrupt + 1 + 1 + + + SETUP + SETUP phase done + 3 + 1 + + + OUTTEPD + OUT token received when + endpoint disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP + packets received + 6 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + OTGFS device IN endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + OTGFS device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + SETUPCNT + SETUP packet count + 29 + 2 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + OTGFS device IN endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + OTGFS device IN endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + OTG device IN endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ4 + DIEPTSIZ4 + OTG device IN endpoint-4 transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ5 + DIEPTSIZ5 + OTG device IN endpoint-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ6 + DIEPTSIZ6 + OTG device IN endpoint-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DIEPTSIZ7 + DIEPTSIZ7 + OTG device IN endpoint-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MC + Multi count + 29 + 2 + + + + + DTXFSTS0 + DTXFSTS0 + OTGFS device IN endpoint-0 transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTGFS device IN endpoint-1 transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTGFS device IN endpoint-2 transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTGFS device IN endpoint-3 transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS4 + DTXFSTS4 + OTGFS device IN endpoint-4 transmit FIFO + status register + 0x198 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS5 + DTXFSTS5 + OTGFS device IN endpoint-5 transmit FIFO + status register + 0x1B8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS6 + DTXFSTS6 + OTGFS device IN endpoint-6 transmit FIFO + status register + 0x1D8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS7 + DTXFSTS7 + OTGFS device IN endpoint-7 transmit FIFO + status register + 0x1F8 + 0x20 + read-only + 0x00000000 + + + INEPTXFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + OTGFS device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + OTGFS device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + OTGFS device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ4 + DOEPTSIZ4 + OTGFS device OUT endpoint-4 transfer size + register + 0x390 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ5 + DOEPTSIZ5 + OTGFS device OUT endpoint-5 transfer size + register + 0x3B0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ6 + DOEPTSIZ6 + OTGFS device OUT endpoint-6 transfer size + register + 0x3D0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + DOEPTSIZ7 + DOEPTSIZ7 + OTGFS device OUT endpoint-7 transfer size + register + 0x3F0 + 0x20 + read-write + 0x00000000 + + + XFERSIZE + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID + Received data PID + 29 + 2 + + + + + + + USB_OTG2_PWRCLK + USB on the go full speed + USB_OTG2 + 0x40040E00 + + 0x0 + 0x400 + registers + + + + PCGCCTL + PCGCCTL + OTGFS power and clock gating control + register (OTGFS_PCGCCTL) + 0x0 + 0x20 + 0x00000000 + + + STOPPCLK + Stop PHY clock + 0 + 1 + read-write + + + SUSPENDM + PHY Suspended + 4 + 1 + read-only + + + + + + + SCFG + System configuration controller + SCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + CFG1 + CFG1 + configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MAP_SEL + Memory address mapping selection bits + 0 + 3 + + + IR_POL + IR output polarity selection + 5 + 1 + + + IR_SRC_SEL + IR signal source selection + 6 + 2 + + + SWAP_XMC + XMC address mapping swap + 10 + 2 + + + + + CFG2 + CFG2 + configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + MII or RMII selection + bits + 23 + 1 + + + + + EXINTC1 + EXINTC1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXINT3 + EXINT 3 configuration bits + 12 + 4 + + + EXINT2 + EXINT 2 configuration bits + 8 + 4 + + + EXINT1 + EXINT 1 configuration bits + 4 + 4 + + + EXINT0 + EXINT 0 configuration bits + 0 + 4 + + + + + EXINTC2 + EXINTC2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXINT7 + EXINT 7 configuration bits + 12 + 4 + + + EXINT6 + EXINT 6 configuration bits + 8 + 4 + + + EXINT5 + EXINT 5 configuration bits + 4 + 4 + + + EXINT4 + EXINT 4 configuration bits + 0 + 4 + + + + + EXINTC3 + EXINTC3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXINT11 + EXINT 11 configuration bits + 12 + 4 + + + EXINT10 + EXINT 10 configuration bits + 8 + 4 + + + EXINT9 + EXINT 9 configuration bits + 4 + 4 + + + EXINT8 + EXINT 8 configuration bits + 0 + 4 + + + + + EXINTC4 + EXINTC4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXINT15 + EXINT 15 configuration bits + 12 + 4 + + + EXINT14 + EXINT 14 configuration bits + 8 + 4 + + + EXINT13 + EXINT 13 configuration bits + 4 + 4 + + + EXINT12 + EXINT 12 configuration bits + 0 + 4 + + + + + UHDRV + UHDRV + Ultra high drive register + 0x2C + 0x20 + read-write + 0x0000 + + + PF15_UH + PF15 ultra high sourcing/sinking strength + 10 + 1 + + + PF14_UH + PF14 ultra high sourcing/sinking strength + 9 + 1 + + + PD15_UH + PD15 ultra high sourcing/sinking strength + 8 + 1 + + + PD14_UH + PD14 ultra high sourcing/sinking strength + 7 + 1 + + + PD13_UH + PD13 ultra high sourcing/sinking strength + 6 + 1 + + + PD12_UH + PD12 ultra high sourcing/sinking strength + 5 + 1 + + + PB10_UH + PB10 ultra high sourcing/sinking strength + 2 + 1 + + + PB9_UH + PB9 ultra high sourcing/sinking strength + 1 + 1 + + + PB3_UH + PB3 ultra high sourcing/sinking strength + 0 + 1 + + + + + + + QSPI1 + Quad SPI Controller + QSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QSPI1 + QSPI1 global interrupt + 92 + + + + CMD_W0 + CMD_W0 + Command word 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + SPIADR + SPI flash address + 0 + 32 + + + + + CMD_W1 + CMD_W1 + Command word 1 + 0x4 + 0x20 + read-write + 0x01000003 + + + ADRLEN + SPI address length + 0 + 3 + + + DUM2 + Second dummy state cycle + 16 + 8 + + + INSLEN + Instruction code length + 24 + 2 + + + PEMEN + Perfrmance enhance mode enable + 28 + 1 + + + + + CMD_W2 + CMD_W2 + Command word 2 + 0x8 + 0x20 + read-write + 0x01000003 + + + DCNT + Read write data counter + 0 + 32 + + + + + CMD_W3 + CMD_W3 + Command word 3 + 0xC + 0x20 + read-write + 0x00000000 + + + WEN + Write data enable + 1 + 1 + + + RSTSEN + Read spi status enable + 2 + 1 + + + RSTSC + Read spi status configure + 3 + 1 + + + OPMODE + SPI operate mode + 5 + 3 + + + PEMOPC + Performance enhance mode operate code + 16 + 8 + + + INSC + Instruction code + 24 + 8 + + + + + CTRL + CTRL + Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + CLKDIV + SPI clock divider + 0 + 3 + + + SCKMODE + Sckout mode + 4 + 1 + + + XIPIDLE + XIP port idle status + 7 + 1 + + + ABORT + Abort instruction + 8 + 1 + + + BUSY + Busy bit of spi status + 16 + 3 + + + XIPRCMDF + XIP read command flush + 19 + 1 + + + XIPSEL + XIP port selection + 20 + 1 + + + KEYEN + encryption key enable + 21 + 1 + + + + + ACTR + ACTR + AC timing control register + 0x14 + 0x20 + read-write + 0x0000000F + + + CSDLY + CS delay + 0 + 4 + + + + + FIFOSTS + FIFOSTS + FIFO Status register + 0x18 + 0x20 + read-only + 0x00000001 + + + TXFIFORDY + TxFIFO ready status + 0 + 1 + + + RXFIFORDY + RxFIFO ready status + 1 + 1 + + + + + CTRL2 + CTRL2 + control register 2 + 0x20 + 0x20 + read-write + 0x00000001 + + + DMAEN + DMA handshake enable + 0 + 1 + + + CMDIE + Command complete interrupt enable + 1 + 1 + + + TXFIFOTHOD + TxFIFO thod + 8 + 2 + + + RXFIFOTHOD + RxFIFO thod + 12 + 2 + + + + + CMDSTS + CMDSTS + CMD status register + 0x24 + 0x20 + read-only + 0x00000000 + + + CMDSTS + Command complete status + 0 + 1 + + + + + RSTS + RSTS + SPI read status register + 0x28 + 0x20 + read-only + 0x00000000 + + + SPISTS + SPI read status + 0 + 8 + + + + + FSIZE + FSIZE + SPI flash size + 0x2C + 0x20 + read-write + 0x00000000 + + + SPIFSIZE + SPI flash size + 0 + 32 + + + + + XIP_CMD_W0 + XIP_CMD_W0 + XIP command word 0 + 0x30 + 0x20 + read-write + 0x00000000 + + + XIPR_DUM2 + XIP read second dummy cycle + 0 + 8 + + + XIPR_OPMODE + XIP read operate mode + 8 + 3 + + + XIPR_ADRLEN + XIP read address length + 11 + 1 + + + XIPR_INSC + XIP read instruction code + 12 + 8 + + + + + XIP_CMD_W1 + XIP_CMD_W1 + XIP command word 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + XIPW_DUM2 + XIP write second dummy cycle + 0 + 8 + + + XIPW_OPMODE + XIP write operate mode + 8 + 3 + + + XIPW_ADRLEN + XIP write address length + 11 + 1 + + + XIPW_INSC + XIP write instruction code + 12 + 8 + + + + + XIP_CMD_W2 + XIP_CMD_W2 + XIP command word 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + XIPR_DCNT + XIP read data counter + 0 + 6 + + + XIPR_TCNT + XIP continue read cycle counter + 8 + 7 + + + XIPR_SEL + XIP read continue mode select + 15 + 1 + + + XIPW_DCNT + XIP write data counter + 16 + 6 + + + XIPW_TCNT + XIP continue write cycle counter + 24 + 7 + + + XIPW_SEL + XIP write continue mode select + 31 + 1 + + + + + XIP_CMD_W3 + XIP_CMD_W3 + XIP command word 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + BYPASSC + Bypass cache function + 0 + 1 + + + CSTS + Cache status + 3 + 1 + + + + + REV + REV + Revision + 0x50 + 0x20 + read-write + 0x00010500 + + + REVISION + Revision number + 0 + 31 + + + + + DT + DT + 32/16/8 bit data port register + 0x100 + 0x20 + read-write + 0x00000000 + + + + + QSPI2 + 0xA0002000 + + QSPI2 + QSPI2 global interrupt + 91 + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x100 + registers + + + EMAC + Ethernet mac global interrupt + 61 + + + + MACCTRL + MACCTRL + Ethernet MAC configuration register + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + ACS + Automatic pad/CRC + stripping + 7 + 1 + + + DR + Disable retry + 9 + 1 + + + IPC + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + DRO + Disable receive own + 13 + 1 + + + FES + Fast EMAC speed + 14 + 1 + + + DCS + Disable carrier sense + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFRMF + MACFRMF + Ethernet MAC frame filter register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Promiscuous mode + 0 + 1 + + + HUC + Hash unicast + 1 + 1 + + + HMC + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PMC + Pass multicast + 4 + 1 + + + DBF + Disable broadcast frames + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTH + MACHTH + Ethernet MAC hash table high register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTL + MACHTL + Ethernet MAC hash table low register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIADDR + MACMIIADDR + Ethernet MAC MII address register + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MII + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDT + MACMIIDT + Ethernet MAC MII data register + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCTRL + MACFCTRL + Ethernet MAC flow control register + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + ETF + Enable transmit flow control + + 1 + 1 + + + ERF + Enable receive flow control + + 2 + 1 + + + DUP + Detect unicast pause frame + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + DZQP + Disable zero-quanta pause + 7 + 1 + + + PT + Pass time + 16 + 16 + + + + + MACVLT + MACVLT + Ethernet MAC VLAN tag register + 0x1C + 0x20 + read-write + 0x00000000 + + + VTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + ETV + Enable 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWFF + MACRWFF + Ethernet MAC remote wakeup frame filter register + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCTRLSTS + MACPMTCTRLSTS + Ethernet MAC PMT control and status register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + EMP + Enable magic packet + 1 + 1 + + + ERWF + Enable remote wakeup frame + 2 + 1 + + + RMP + Received magic packet + 5 + 1 + + + RRWF + Recevied remote wakeup frame + 6 + 1 + + + GUC + Global unicast + 9 + 1 + + + RWFFPR + Remote wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACISTS + MACISTS + Ethernet MAC interrupt status register + 0x38 + 0x20 + read-write + 0x00000000 + + + PIS + PMT interrupt status + 3 + 1 + + + MIS + MMC interrupt status + 4 + 1 + + + MRIS + MMC receive interrupt status + 5 + 1 + + + MTIS + MMC transmit interrupt status + 6 + 1 + + + TIS + Timestamp interrupt status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + PIM + PMT interrupt mask + 3 + 1 + + + TIM + Timestamp interrupt mask + 9 + 1 + + + + + MACA0H + MACA0H + Ethernet MAC address 0 high register + 0x40 + 0x20 + 0x0010FFFF + + + MA0H + MAC address0 high + 0 + 16 + read-write + + + AE + Address enable + 31 + 1 + read-only + + + + + MACA0L + MACA0L + Ethernet MAC address 0 low register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MA0L + MAC address0 low + 0 + 32 + + + + + MACA1H + MACA1H + Ethernet MAC address 1 high register + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1L + MACA1L + Ethernet MAC address1 low register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MA1L + MAC address1 low + 0 + 32 + + + + + MACA2H + MACA2H + Ethernet MAC address 2 high register + 0x50 + 0x20 + read-write + 0x0050 + + + MA2H + MAC address 2 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2L + MACA2L + Ethernet MAC address 2 low register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MA2L + MAC address2 low + 0 + 31 + + + + + MACA3H + MACA3H + Ethernet MAC address 3 high register + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3L + MACA3L + Ethernet MAC address 3 low register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x100 + registers + + + + MMCCTRL + MMCCTRL + Ethernet MMC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + RC + Reset counter + 0 + 1 + + + SCR + Stop counter rollover + 1 + 1 + + + RR + Reset on read + 2 + 1 + + + FMC + Freeze MMC counter + 31 + 1 + + + + + MMCRI + MMCRI + Ethernet MMC receive interrupt register + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCE + Received frames CRC error + 5 + 1 + + + RFAE + Received frames alignment error + 6 + 1 + + + RGUF + Received good unicast frames + 17 + 1 + + + + + MMCTI + MMCTI + Ethernet MMC transmit interrupt register + 0x8 + 0x20 + read-write + 0x00000000 + + + TSCGFCI + Transmit single collision good frame + counter interrupt + 14 + 1 + + + TGFMSC + Transmit good frames more single + collision + 15 + 1 + + + TGF + Transmitted good frames + 21 + 1 + + + + + MMCRIM + MMCRIM + Ethernet MMC receive interrupt mask register + 0xC + 0x20 + read-write + 0x00000000 + + + RCEFCIM + Received CRC error frame counter interrupt + mask + 5 + 1 + + + RAEFACIM + Received alignment error frame alignment + counter interrupt mask + 6 + 1 + + + RUGFCIM + Received unicast good frame counter + interrupt mask + 17 + 1 + + + + + MMCTIM + MMCTIM + Ethernet MMC transmit interrupt mask register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSCGFCIM + Transmit single collision good frame + counter interrupt mask + 14 + 1 + + + TMCGFCIM + Transmit multiple collision good frame + counter interrupt mask + 15 + 1 + + + TGFCIM + Transmitted good frame counter interrupt + mask + 21 + 1 + + + + + MMCTFSCC + MMCTFSCC + Ethernet MMC transmitted good frames after a single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames single + collision counter + 0 + 32 + + + + + MMCTFMSCC + MMCTFMSCC + Ethernet MMC transmitted good frames after more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frame more single + collision counter + 0 + 32 + + + + + MMCTFCNT + MMCTFCNT + Ethernet MMC transmitted good frames counter register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECNT + MMCRFCECNT + Ethernet MMC received frames with CRC error counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCEC + Received frames CRC error counter + 0 + 32 + + + + + MMCRFAECNT + MMCRFAECNT + Ethernet MMC received frames with alignment error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames alignment error counter + 0 + 32 + + + + + MMCRGUFCNT + MMCRGUFCNT + MMC received good unicast frames counter register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x100 + registers + + + + PTPTSCTRL + PTPTSCTRL + Ethernet PTP time stamp control register + 0x0 + 0x20 + read-write + 0x2000 + + + TE + Timestamp enable + 0 + 1 + + + TFCU + Timestamp fine or coarse + update + 1 + 1 + + + TI + Timestamp initialize + 2 + 1 + + + TU + Timestamp update + 3 + 1 + + + TITE + Timestamp interrupt trigger + enable + 4 + 1 + + + ARU + Addend register update + 5 + 1 + + + ETAF + Enable timestamp for all frames + 8 + 1 + + + TDBRC + Timestamp digital or binary + rollover control + 9 + 1 + + + EPPV2F + Enable PTP packet processing for + version2 format + 10 + 1 + + + EPPEF + Enable processing of PTP + over EMAC frames + 11 + 1 + + + EPPFSIP6U + Enable processing of PTP frames + sent over IPv6-UDP + 12 + 1 + + + EPPFSIP4U + Enable processing of PTP frames + sent over IPv4-UDP + 13 + 1 + + + ETSFEM + Enable timestamp snapshot for + event message + 14 + 1 + + + ESFMRTM + Enable snapshot for message + relevant to master + 15 + 1 + + + SPPFTS + Select PTP packet for taking snapshot + 16 + 2 + + + EMAFPFF + Enable MAC address for PTP frame filtering + 18 + 1 + + + + + PTPSSINC + PTPSSINC + Ethernet PTP subsecond increment register + 0x4 + 0x20 + read-write + 0x00000000 + + + SSIV + Sub-second increment value + 0 + 8 + + + + + PTPTSH + PTPTSH + Ethernet PTP time stamp high register + 0x8 + 0x20 + read-only + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSL + PTPTSL + Ethernet PTP time stamp low register + 0xC + 0x20 + read-only + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSHUD + PTPTSHUD + Ethernet PTP time stamp high update register + 0x10 + 0x20 + read-write + 0x00000000 + + + TS + Timestamp second + 0 + 32 + + + + + PTPTSLUD + PTPTSLUD + Ethernet PTP time stamp low update register + 0x14 + 0x20 + read-write + 0x00000000 + + + TSS + Timestamp subseconds + 0 + 31 + + + AST + Add or subtract time + 31 + 1 + + + + + PTPTSAD + PTPTSAD + Ethernet PTP time stamp addend register + 0x18 + 0x20 + read-write + 0x00000000 + + + TAR + Timestamp addend register + 0 + 32 + + + + + PTPTTH + PTPTTH + Ethernet PTP target time high register + 0x1C + 0x20 + read-write + 0x00000000 + + + TTSR + Target time seconds register + 0 + 32 + + + + + PTPTTL + PTPTTL + Ethernet PTP target time low register + 0x20 + 0x20 + read-write + 0x00000000 + + + TTLR + Target timestamp low register + 0 + 32 + + + + + PTPTSSR + PTPTSSR + Ethernet PTP time stamp status register + 0x28 + 0x20 + read-only + 0x00000000 + + + TSO + Timestamp second overflow + 0 + 1 + + + TTTR + Timestamp target time reached + 1 + 1 + + + + + PTPPPSCR + PTPPPSCR + Ethernet PTP PPS control register + 0x2C + 0x20 + read-only + 0x00000000 + + + POFC + PPS Output frequency control + 0 + 4 + + + + + + + ETHERNET_DMA + Ethernet: DMA controller operation + ETHERNET + 0x40029000 + + 0x0 + 0x100 + registers + + + + DMABM + DMABM + Ethernet DMA bus mode register + 0x0 + 0x20 + read-write + 0x20101 + + + SWR + Software reset + 0 + 1 + + + DA + DMA Arbitration + 1 + 1 + + + DSL + Descriptor skip length + 2 + 5 + + + PBL + Programmable burst length + 8 + 6 + + + PR + Priority ratio + 14 + 2 + + + FB + Fixed burst + 16 + 1 + + + RDP + Rx DMA PBL + 17 + 6 + + + USP + Use separate PBL + 23 + 1 + + + PBLx8 + PNLx8 mode + 24 + 1 + + + AAB + Address-aligned beats + 25 + 1 + + + + + DMATPD + DMATPD + Ethernet DMA transmit poll demand register + 0x4 + 0x20 + read-write + 0x00000000 + + + TPD + Transmit poll demand + 0 + 32 + + + + + DMARPD + DMARPD + EHERNET DMA receive poll demand register + 0x8 + 0x20 + read-write + 0x00000000 + + + RPD + Receive poll demand + 0 + 32 + + + + + DMARDLADDR + DMARDLADDR + Ethernet DMA receive descriptor list address register + 0xC + 0x20 + read-write + 0x00000000 + + + SRL + Start of receive list + 0 + 32 + + + + + DMATDLADDR + DMATDLADDR + Ethernet DMA transmit descriptor list address register + 0x10 + 0x20 + read-write + 0x00000000 + + + STL + Start of transmit list + 0 + 32 + + + + + DMASTS + DMASTS + Ethernet DMA status register + 0x14 + 0x20 + 0x00000000 + + + TI + Transmit interrupt + 0 + 1 + read-write + + + TPS + Transmit process stopped + 1 + 1 + read-write + + + TBU + Transmit buffer unavailable + 2 + 1 + read-write + + + TJT + Transmit jabber timeout + 3 + 1 + read-write + + + OVF + Receive overflow + 4 + 1 + read-write + + + UNF + Transmit underflow + 5 + 1 + read-write + + + RI + Receive interrupt + 6 + 1 + read-write + + + RBU + Receive buffer unavailable + 7 + 1 + read-write + + + RPS + Receive process stopped + 8 + 1 + read-write + + + RWT + Receive watchdog timeout + 9 + 1 + read-write + + + ETI + Early transmit interrupt + 10 + 1 + read-write + + + FBEI + Fatal bus error interrupt + 13 + 1 + read-write + + + ERI + Early receive interrupt + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RS + Receive process state + 17 + 3 + read-only + + + TS + Transmit process state + 20 + 3 + read-only + + + EB + Error bits + 23 + 3 + read-only + + + MMI + MAC MMC interrupt + 27 + 1 + read-only + + + MPI + MAC PMT interrupt + 28 + 1 + read-only + + + TTI + Timestamp trigger interrupt + 29 + 1 + read-only + + + + + DMAOPM + DMAOPM + Ethernet DMA operation mode register + 0x18 + 0x20 + read-write + 0x00000000 + + + SSR + Start or stop receive + 1 + 1 + + + OSF + Operate on second frame + 2 + 1 + + + RTC + Receive threshold control + 3 + 2 + + + FUGF + Forward undersized good frames + 6 + 1 + + + FEF + Forward error frames + 7 + 1 + + + SSTC + Start of stop transmission command + 13 + 1 + + + TTC + Transmit threshold control + 14 + 3 + + + FTF + Flush transmit FIFO + 20 + 1 + + + TSF + Transmit store and forward + 21 + 1 + + + DFRF + Disable flushing of received + frames + 24 + 1 + + + RSF + Receive store and forward + 25 + 1 + + + DT + Disable dropping of TCP/IP + checksum error frames + 26 + 1 + + + + + DMAIE + DMAIE + Ethernet DMA interrupt enable register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TSE + Transmit stopped enable + 1 + 1 + + + TUE + Transmit buffer unavailable enable + 2 + 1 + + + TJE + Transmit jabber timeout enable + 3 + 1 + + + OVE + Overflow interrupt enable + 4 + 1 + + + UNE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUE + Receive buffer unavailable enable + 7 + 1 + + + RSE + Receive stopped enable + 8 + 1 + + + RWTE + receive watchdog timeout enable + 9 + 1 + + + EIE + Early transmit interrupt enable + 10 + 1 + + + FBEE + Fatal bus error enable + 13 + 1 + + + ERE + Early receive interrupt + enable + 14 + 1 + + + AIE + Abnormal interrupt enable + 15 + 1 + + + NIE + Normal interrupt enable + 16 + 1 + + + + + DMAMFBOCNT + DMAMFBOCNT + Ethernet DMA missed frame and buffer overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames control + 0 + 16 + + + OBMFC + Overflow bit for missed frame + counter + 16 + 1 + + + OFC + Overflow frame counter + 17 + 11 + + + OBFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACTD + DMACTD + Ethernet DMA current host transmit descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address pointer + 0 + 32 + + + + + DMACRD + DMACRD + Ethernet DMA current host receive descriptor register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address pointer + 0 + 32 + + + + + DMACTBADDR + DMACTBADDR + Ethernet DMA current host transmit buffer address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address pointer + 0 + 32 + + + + + DMACRBADDR + DMACRBADDR + Ethernet DMA current host receive buffer address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address pointer + 0 + 32 + + + + + + + diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h new file mode 100644 index 000000000..ef4ec6dcf --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.h @@ -0,0 +1,182 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//#define USB_VBUS_IGNORE +//#define USB_SOF_OUTPUT_ENABLE + +// LED +#define LED_PORT GPIOD +#define LED_PIN GPIO_PINS_13 +#define LED_STATE_ON 0 // Active Low +#define LED_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOD_PERIPH_CLOCK, TRUE) + +// Button +#define BUTTON_PORT GPIOA +#define BUTTON_PIN GPIO_PINS_0 +#define BUTTON_STATE_ACTIVE 1 +#define BUTTON_GPIO_CLK_EN() crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE) + +// USART +#define PRINT_UART USART1 +#define PRINT_UART_CRM_CLK CRM_USART1_PERIPH_CLOCK +#define PRINT_UART_TX_PIN GPIO_PINS_9 +#define PRINT_UART_TX_GPIO GPIOA +#define PRINT_UART_TX_GPIO_CRM_CLK CRM_GPIOA_PERIPH_CLOCK +#define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 +#define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 + +// USB +#ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUD_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +#ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + #define USB_ID 0 + #define OTG_CLOCK CRM_OTGFS1_PERIPH_CLOCK + #define OTG_IRQ OTGFS1_IRQn + #define OTG_IRQ_HANDLER OTGFS1_IRQHandler + #define OTG_WKUP_IRQ OTGFS1_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS1_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_18 + #define OTG_PIN_GPIO GPIOA + #define OTG_PIN_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_12 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_DM GPIO_PINS_11 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE11 + #define OTG_PIN_VBUS GPIO_PINS_9 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE9 + #define OTG_PIN_ID GPIO_PINS_10 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE12 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_8 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE8 + #define OTG_PIN_MUX GPIO_MUX_10 + #elif BOARD_TUH_RHPORT == 1 + #define USB_ID 1 + #define OTG_CLOCK CRM_OTGFS2_PERIPH_CLOCK + #define OTG_IRQ OTGFS2_IRQn + #define OTG_IRQ_HANDLER OTGFS2_IRQHandler + #define OTG_WKUP_IRQ OTGFS2_WKUP_IRQn + #define OTG_WKUP_HANDLER OTGFS2_WKUP_IRQHandler + #define OTG_WKUP_EXINT_LINE EXINT_LINE_20 + #define OTG_PIN_GPIO GPIOB + #define OTG_PIN_GPIO_CLOCK CRM_GPIOB_PERIPH_CLOCK + #define OTG_PIN_DP GPIO_PINS_15 + #define OTG_PIN_DP_SOURCE GPIO_PINS_SOURCE15 + #define OTG_PIN_DM GPIO_PINS_14 + #define OTG_PIN_DM_SOURCE GPIO_PINS_SOURCE14 + #define OTG_PIN_VBUS GPIO_PINS_13 + #define OTG_PIN_VBUS_SOURCE GPIO_PINS_SOURCE13 + #define OTG_PIN_ID GPIO_PINS_12 + #define OTG_PIN_ID_SOURCE GPIO_PINS_SOURCE10 + #define OTG_PIN_SOF_GPIO GPIOA + #define OTG_PIN_SOF_GPIO_CLOCK CRM_GPIOA_PERIPH_CLOCK + #define OTG_PIN_SOF GPIO_PINS_4 + #define OTG_PIN_SOF_SOURCE GPIO_PINS_SOURCE4 + #define OTG_PIN_MUX GPIO_MUX_12 + #endif +#endif + +// VBUS +static inline void board_vbus_sense_init(void) +{ + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUD_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif + #ifdef BOARD_TUH_RHPORT + #if BOARD_TUH_RHPORT == 0 + *(int*)(0x50000038) |= (1<<21); + #elif BOARD_TUH_RHPORT == 1 + *(int*)(0x40040038) |= (1<<21); + #endif + #endif +} + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk new file mode 100644 index 000000000..823ae677d --- /dev/null +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/board.mk @@ -0,0 +1,4 @@ +LD_FILE = $(BOARD_PATH)/AT32F437xM_FLASH.ld + +CFLAGS += \ + -DAT32F437ZMT7 diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c new file mode 100644 index 000000000..c238fff32 --- /dev/null +++ b/hw/bsp/at32f435_437/family.c @@ -0,0 +1,370 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "at32f435_437_clock.h" +#include "bsp/board_api.h" +#include "board.h" + +void usb_gpio_config(void); +void uart_print_init(uint32_t baudrate); +void usb_clock48m_select(usb_clk48_s clk_s); +void led_and_botton_init(void); +int inHandlerMode(void); +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void OTGFS1_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_IRQHandler(void) +{ + tusb_int_handler(1, true); +} +void OTGFS1_WKUP_IRQHandler(void) +{ + tusb_int_handler(0, true); +} +void OTGFS2_WKUP_IRQHandler(void) +{ + tusb_int_handler(1, true); +} + +void board_init(void) +{ + /* config nvic priority group */ + nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); + + /* config system clock to 288Mhz */ + system_clock_config(); + + /* config usb io */ + usb_gpio_config(); + + /* enable usb clock */ + crm_periph_clock_enable(OTG_CLOCK, TRUE); + + /* select usb 48m clcok source */ + usb_clock48m_select(USB_CLK_HEXT); + + /* enable otgfs irq */ + //nvic_irq_enable(OTG_IRQ, 0, 0); + + /* vbus ignore */ + board_vbus_sense_init(); + + SysTick_Config(SystemCoreClock / 1000); +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + /* config led and key */ + led_and_botton_init(); + + /* config usart printf */ + uart_print_init(115200); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ +/** + * @brief usb 48M clock select + * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT + * @retval none + */ +void usb_clock48m_select(usb_clk48_s clk_s) +{ + if(clk_s == USB_CLK_HICK) + { + crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); + + /* enable the acc calibration ready interrupt */ + crm_periph_clock_enable(CRM_ACC_PERIPH_CLOCK, TRUE); + + /* update the c1\c2\c3 value */ + acc_write_c1(7980); + acc_write_c2(8000); + acc_write_c3(8020); + #ifdef BOARD_TUD_RHPORT + #if BOARD_TUD_RHPORT == 0 + acc_sof_select(ACC_SOF_OTG1); + #else + acc_sof_select(ACC_SOF_OTG2); + #endif + #endif + /* open acc calibration */ + acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); + } + else + { + switch(system_core_clock) + { + /* 48MHz */ + case 48000000: + crm_usb_clock_div_set(CRM_USB_DIV_1); + break; + + /* 72MHz */ + case 72000000: + crm_usb_clock_div_set(CRM_USB_DIV_1_5); + break; + + /* 96MHz */ + case 96000000: + crm_usb_clock_div_set(CRM_USB_DIV_2); + break; + + /* 120MHz */ + case 120000000: + crm_usb_clock_div_set(CRM_USB_DIV_2_5); + break; + + /* 144MHz */ + case 144000000: + crm_usb_clock_div_set(CRM_USB_DIV_3); + break; + + /* 168MHz */ + case 168000000: + crm_usb_clock_div_set(CRM_USB_DIV_3_5); + break; + + /* 192MHz */ + case 192000000: + crm_usb_clock_div_set(CRM_USB_DIV_4); + break; + + /* 216MHz */ + case 216000000: + crm_usb_clock_div_set(CRM_USB_DIV_4_5); + break; + + /* 240MHz */ + case 240000000: + crm_usb_clock_div_set(CRM_USB_DIV_5); + break; + + /* 264MHz */ + case 264000000: + crm_usb_clock_div_set(CRM_USB_DIV_5_5); + break; + + /* 288MHz */ + case 288000000: + crm_usb_clock_div_set(CRM_USB_DIV_6); + break; + + default: + break; + } + } +} + +void led_and_botton_init(void) +{ + /* LED */ + gpio_init_type gpio_led_init_struct; + /* enable the led clock */ + LED_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_led_init_struct); + /* configure the led gpio */ + gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; + gpio_led_init_struct.gpio_pins = LED_PIN; + gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(LED_PORT, &gpio_led_init_struct); + gpio_bits_set(LED_PORT, LED_PIN); + gpio_bits_set(LED_PORT, GPIO_PINS_14); + gpio_bits_set(LED_PORT, GPIO_PINS_15); + /* Button */ + gpio_init_type gpio_button_init_struct; + /* enable the button clock */ + BUTTON_GPIO_CLK_EN(); + /* set default parameter */ + gpio_default_para_init(&gpio_button_init_struct); + /* configure the button gpio */ + gpio_button_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_button_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_button_init_struct.gpio_mode = GPIO_MODE_INPUT; + gpio_button_init_struct.gpio_pins = BUTTON_PIN; + gpio_button_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_init(BUTTON_PORT, &gpio_button_init_struct); +} + +/** + * @brief initialize uart + * @param baudrate: uart baudrate + * @retval none + */ +void uart_print_init(uint32_t baudrate) +{ + gpio_init_type gpio_init_struct; + /* enable the uart and gpio clock */ + crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); + crm_periph_clock_enable(PRINT_UART_TX_GPIO_CRM_CLK, TRUE); + gpio_default_para_init(&gpio_init_struct); + /* configure the uart tx pin */ + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + gpio_init(PRINT_UART_TX_GPIO, &gpio_init_struct); + gpio_pin_mux_config(PRINT_UART_TX_GPIO, PRINT_UART_TX_PIN_SOURCE, PRINT_UART_TX_PIN_MUX_NUM); + /* configure uart param */ + usart_init(PRINT_UART, baudrate, USART_DATA_8BITS, USART_STOP_1_BIT); + usart_transmitter_enable(PRINT_UART, TRUE); + usart_enable(PRINT_UART, TRUE); +} + +// Get characters from UART. Return number of read bytes +int board_uart_read(uint8_t *buf, int len) +{ + (void) buf; + (void) len; + return 0; +} +// Send characters to UART. Return number of sent bytes +int board_uart_write(void const *buf, int len) +{ + #if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) + { + while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) + { + timeout--; + if(timeout == 0) + { + return 0; + } + } + PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); + buf++; + } + return len; + #else + (void) buf; + (void) len; + return 0; + #endif +} + +int inHandlerMode(void) +{ + return __get_IPSR(); +} + +void usb_gpio_config(void) +{ + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pull = GPIO_PULL_NONE; + /* dp and dm */ + gpio_init_struct.gpio_pins = OTG_PIN_DP | OTG_PIN_DM; + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DP_SOURCE, OTG_PIN_MUX); + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_DM_SOURCE, OTG_PIN_MUX); + #ifdef USB_SOF_OUTPUT_ENABLE + crm_periph_clock_enable(OTG_PIN_SOF_GPIO_CLOCK, TRUE); + gpio_init_struct.gpio_pins = OTG_PIN_SOF; + gpio_init(OTG_PIN_SOF_GPIO, &gpio_init_struct); + gpio_pin_mux_config(OTG_PIN_SOF_GPIO, OTG_PIN_SOF_SOURCE, OTG_PIN_MUX); + #endif + /* otgfs use vbus pin */ + #ifndef USB_VBUS_IGNORE + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); + #endif +} + +void board_led_write(bool state) +{ + gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); +} + +uint32_t board_button_read(void) +{ + return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) +{ + (void) max_len; + volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = at32_uuid[0]; + id32[1] = at32_uuid[1]; + id32[2] = at32_uuid[2]; + + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE + volatile uint32_t system_ticks = 0; + void SysTick_Handler(void) + { + system_ticks++; + } + uint32_t board_millis(void) + { + return system_ticks; + } + void SVC_Handler(void) + { + } + void PendSV_Handler(void) + { + } +#endif + +void HardFault_Handler(void) +{ + __asm("BKPT #0\n"); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk new file mode 100644 index 000000000..47731b621 --- /dev/null +++ b/hw/bsp/at32f435_437/family.mk @@ -0,0 +1,45 @@ +# Submodules +AT32F435_437_SDK = hw/mcu/artery/at32f435_437 +DEPS_SUBMODULES += $(AT32F435_437_SDK) + +# AT32 SDK path +AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries + +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 + +CFLAGS_GCC += \ + -flto + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_AT32F435_437 \ + +LDFLAGS_GCC += \ + -flto --specs=nosys.specs + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_gpio.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_misc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_usart.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_crm.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_acc.c \ + $(AT32F435_437_SDK_SRC)/drivers/src/at32f435_437_exint.c \ + $(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support/system_at32f435_437.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(AT32F435_437_SDK_SRC)/drivers/inc \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/core_support \ + $(TOP)/$(AT32F435_437_SDK_SRC)/cmsis/cm4/device_support \ + +SRC_S += \ + $(FAMILY_PATH)/startup_at32f435_437.s + +# For freeRTOS port source +#FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/ARM_CM4F + +flash: flash-atlink diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s new file mode 100644 index 000000000..aa1aa3f4a --- /dev/null +++ b/hw/bsp/at32f435_437/startup_at32f435_437.s @@ -0,0 +1,569 @@ +/** + ****************************************************************************** + * @file startup_at32f435_437.s + * @brief at32f435_437 devices vector table for gcc toolchain. + * this module performs: + * - set the initial sp + * - set the initial pc == reset_handler, + * - set the vector table entries with the exceptions isr address + * - configure the clock system and the external sram to + * be used as data memory (optional, to be enabled by user) + * - branches to main in the c library (which eventually + * calls main()). + * after reset the cortex-m4 processor is in thread mode, + * priority is privileged, and the stack is set to main. + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDT_IRQHandler /* Window Watchdog Timer */ + .word PVM_IRQHandler /* PVM through EXINT Line detect */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXINT line */ + .word ERTC_WKUP_IRQHandler /* ERTC Wakeup through the EXINT line */ + .word FLASH_IRQHandler /* Flash */ + .word CRM_IRQHandler /* CRM */ + .word EXINT0_IRQHandler /* EXINT Line 0 */ + .word EXINT1_IRQHandler /* EXINT Line 1 */ + .word EXINT2_IRQHandler /* EXINT Line 2 */ + .word EXINT3_IRQHandler /* EXINT Line 3 */ + .word EXINT4_IRQHandler /* EXINT Line 4 */ + .word EDMA_Stream1_IRQHandler /* EDMA Stream 1 */ + .word EDMA_Stream2_IRQHandler /* EDMA Stream 2 */ + .word EDMA_Stream3_IRQHandler /* EDMA Stream 3 */ + .word EDMA_Stream4_IRQHandler /* EDMA Stream 4 */ + .word EDMA_Stream5_IRQHandler /* EDMA Stream 5 */ + .word EDMA_Stream6_IRQHandler /* EDMA Stream 6 */ + .word EDMA_Stream7_IRQHandler /* EDMA Stream 7 */ + .word ADC1_2_3_IRQHandler /* ADC1 & ADC2 & ADC3 */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SE_IRQHandler /* CAN1 SE */ + .word EXINT9_5_IRQHandler /* EXINT Line [9:5] */ + .word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */ + .word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */ + .word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */ + .word TMR1_CH_IRQHandler /* TMR1 Channel */ + .word TMR2_GLOBAL_IRQHandler /* TMR2 */ + .word TMR3_GLOBAL_IRQHandler /* TMR3 */ + .word TMR4_GLOBAL_IRQHandler /* TMR4 */ + .word I2C1_EVT_IRQHandler /* I2C1 Event */ + .word I2C1_ERR_IRQHandler /* I2C1 Error */ + .word I2C2_EVT_IRQHandler /* I2C2 Event */ + .word I2C2_ERR_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_I2S2EXT_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXINT15_10_IRQHandler /* EXINT Line [15:10] */ + .word ERTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */ + .word OTGFS1_WKUP_IRQHandler /* OTGFS1 Wakeup from suspend */ + .word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */ + .word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */ + .word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */ + .word TMR8_CH_IRQHandler /* TMR8 Channel */ + .word EDMA_Stream8_IRQHandler /* EDMA Stream 8 */ + .word XMC_IRQHandler /* XMC */ + .word SDIO1_IRQHandler /* SDIO1 */ + .word TMR5_GLOBAL_IRQHandler /* TMR5 */ + .word SPI3_I2S3EXT_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TMR6_DAC_GLOBAL_IRQHandler /* TMR6 & DAC */ + .word TMR7_GLOBAL_IRQHandler /* TMR7 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word EMAC_IRQHandler /* EMAC */ + .word EMAC_WKUP_IRQHandler /* EMAC Wakeup */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SE_IRQHandler /* CAN2 SE */ + .word OTGFS1_IRQHandler /* OTGFS1 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word 0 /* Reserved */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EVT_IRQHandler /* I2C3 Event */ + .word I2C3_ERR_IRQHandler /* I2C3 Error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word OTGFS2_WKUP_IRQHandler /* OTGFS2 Wakeup from suspend */ + .word OTGFS2_IRQHandler /* OTGFS2 */ + .word DVP_IRQHandler /* DVP */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QSPI2_IRQHandler /* QSPI2 */ + .word QSPI1_IRQHandler /* QSPI1 */ + .word 0 /* Reserved */ + .word DMAMUX_IRQHandler /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SDIO2_IRQHandler /* SDIO2 */ + .word ACC_IRQHandler /* ACC */ + .word TMR20_BRK_IRQHandler /* TMR20 Brake */ + .word TMR20_OVF_IRQHandler /* TMR20 Overflow */ + .word TMR20_TRG_HALL_IRQHandler /* TMR20 Trigger and hall */ + .word TMR20_CH_IRQHandler /* TMR20 Channel */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDT_IRQHandler + .thumb_set WWDT_IRQHandler,Default_Handler + + .weak PVM_IRQHandler + .thumb_set PVM_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak ERTC_WKUP_IRQHandler + .thumb_set ERTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak CRM_IRQHandler + .thumb_set CRM_IRQHandler,Default_Handler + + .weak EXINT0_IRQHandler + .thumb_set EXINT0_IRQHandler,Default_Handler + + .weak EXINT1_IRQHandler + .thumb_set EXINT1_IRQHandler,Default_Handler + + .weak EXINT2_IRQHandler + .thumb_set EXINT2_IRQHandler,Default_Handler + + .weak EXINT3_IRQHandler + .thumb_set EXINT3_IRQHandler,Default_Handler + + .weak EXINT4_IRQHandler + .thumb_set EXINT4_IRQHandler,Default_Handler + + .weak EDMA_Stream1_IRQHandler + .thumb_set EDMA_Stream1_IRQHandler,Default_Handler + + .weak EDMA_Stream2_IRQHandler + .thumb_set EDMA_Stream2_IRQHandler,Default_Handler + + .weak EDMA_Stream3_IRQHandler + .thumb_set EDMA_Stream3_IRQHandler,Default_Handler + + .weak EDMA_Stream4_IRQHandler + .thumb_set EDMA_Stream4_IRQHandler,Default_Handler + + .weak EDMA_Stream5_IRQHandler + .thumb_set EDMA_Stream5_IRQHandler,Default_Handler + + .weak EDMA_Stream6_IRQHandler + .thumb_set EDMA_Stream6_IRQHandler,Default_Handler + + .weak EDMA_Stream7_IRQHandler + .thumb_set EDMA_Stream7_IRQHandler,Default_Handler + + .weak ADC1_2_3_IRQHandler + .thumb_set ADC1_2_3_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SE_IRQHandler + .thumb_set CAN1_SE_IRQHandler,Default_Handler + + .weak EXINT9_5_IRQHandler + .thumb_set EXINT9_5_IRQHandler,Default_Handler + + .weak TMR1_BRK_TMR9_IRQHandler + .thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler + + .weak TMR1_OVF_TMR10_IRQHandler + .thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler + + .weak TMR1_TRG_HALL_TMR11_IRQHandler + .thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler + + .weak TMR1_CH_IRQHandler + .thumb_set TMR1_CH_IRQHandler,Default_Handler + + .weak TMR2_GLOBAL_IRQHandler + .thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler + + .weak TMR3_GLOBAL_IRQHandler + .thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler + + .weak TMR4_GLOBAL_IRQHandler + .thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler + + .weak I2C1_EVT_IRQHandler + .thumb_set I2C1_EVT_IRQHandler,Default_Handler + + .weak I2C1_ERR_IRQHandler + .thumb_set I2C1_ERR_IRQHandler,Default_Handler + + .weak I2C2_EVT_IRQHandler + .thumb_set I2C2_EVT_IRQHandler,Default_Handler + + .weak I2C2_ERR_IRQHandler + .thumb_set I2C2_ERR_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_I2S2EXT_IRQHandler + .thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXINT15_10_IRQHandler + .thumb_set EXINT15_10_IRQHandler,Default_Handler + + .weak ERTCAlarm_IRQHandler + .thumb_set ERTCAlarm_IRQHandler,Default_Handler + + .weak OTGFS1_WKUP_IRQHandler + .thumb_set OTGFS1_WKUP_IRQHandler,Default_Handler + + .weak TMR8_BRK_TMR12_IRQHandler + .thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler + + .weak TMR8_OVF_TMR13_IRQHandler + .thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler + + .weak TMR8_TRG_HALL_TMR14_IRQHandler + .thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler + + .weak TMR8_CH_IRQHandler + .thumb_set TMR8_CH_IRQHandler,Default_Handler + + .weak EDMA_Stream8_IRQHandler + .thumb_set EDMA_Stream8_IRQHandler,Default_Handler + + .weak XMC_IRQHandler + .thumb_set XMC_IRQHandler,Default_Handler + + .weak SDIO1_IRQHandler + .thumb_set SDIO1_IRQHandler,Default_Handler + + .weak TMR5_GLOBAL_IRQHandler + .thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler + + .weak SPI3_I2S3EXT_IRQHandler + .thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TMR6_DAC_GLOBAL_IRQHandler + .thumb_set TMR6_DAC_GLOBAL_IRQHandler,Default_Handler + + .weak TMR7_GLOBAL_IRQHandler + .thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak EMAC_IRQHandler + .thumb_set EMAC_IRQHandler,Default_Handler + + .weak EMAC_WKUP_IRQHandler + .thumb_set EMAC_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler ,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler ,Default_Handler + + .weak CAN2_SE_IRQHandler + .thumb_set CAN2_SE_IRQHandler,Default_Handler + + .weak OTGFS1_IRQHandler + .thumb_set OTGFS1_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EVT_IRQHandler + .thumb_set I2C3_EVT_IRQHandler,Default_Handler + + .weak I2C3_ERR_IRQHandler + .thumb_set I2C3_ERR_IRQHandler,Default_Handler + + .weak OTGFS2_WKUP_IRQHandler + .thumb_set OTGFS2_WKUP_IRQHandler,Default_Handler + + .weak OTGFS2_IRQHandler + .thumb_set OTGFS2_IRQHandler,Default_Handler + + .weak DVP_IRQHandler + .thumb_set DVP_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak QSPI2_IRQHandler + .thumb_set QSPI2_IRQHandler,Default_Handler + + .weak QSPI1_IRQHandler + .thumb_set QSPI1_IRQHandler,Default_Handler + + .weak DMAMUX_IRQHandler + .thumb_set DMAMUX_IRQHandler ,Default_Handler + + .weak SDIO2_IRQHandler + .thumb_set SDIO2_IRQHandler ,Default_Handler + + .weak ACC_IRQHandler + .thumb_set ACC_IRQHandler,Default_Handler + + .weak TMR20_BRK_IRQHandler + .thumb_set TMR20_BRK_IRQHandler,Default_Handler + + .weak TMR20_OVF_IRQHandler + .thumb_set TMR20_OVF_IRQHandler,Default_Handler + + .weak TMR20_TRG_HALL_IRQHandler + .thumb_set TMR20_TRG_HALL_IRQHandler,Default_Handler + + .weak TMR20_CH_IRQHandler + .thumb_set TMR20_CH_IRQHandler,Default_Handler + + .weak DMA2_Channel1_IRQHandler + .thumb_set DMA2_Channel1_IRQHandler,Default_Handler + + .weak DMA2_Channel2_IRQHandler + .thumb_set DMA2_Channel2_IRQHandler,Default_Handler + + .weak DMA2_Channel3_IRQHandler + .thumb_set DMA2_Channel3_IRQHandler,Default_Handler + + .weak DMA2_Channel4_IRQHandler + .thumb_set DMA2_Channel4_IRQHandler,Default_Handler + + .weak DMA2_Channel5_IRQHandler + .thumb_set DMA2_Channel5_IRQHandler,Default_Handler + + .weak DMA2_Channel6_IRQHandler + .thumb_set DMA2_Channel6_IRQHandler,Default_Handler + + .weak DMA2_Channel7_IRQHandler + .thumb_set DMA2_Channel7_IRQHandler,Default_Handler diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a08ed79c8..41c291600 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -550,6 +550,44 @@ #define TUP_RHPORT_HIGHSPEED 1 #define TUD_ENDPOINT_ONE_DIRECTION_ONLY +//--------------------------------------------------------------------+ +// ArteryTek +//--------------------------------------------------------------------+ +#elif TU_CHECK_MCU(OPT_MCU_AT32F403A_407) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F413) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F415) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 4 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F435_437) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F423) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F402_405) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + +#elif TU_CHECK_MCU(OPT_MCU_AT32F425) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_AT32 + #define TUP_DCD_ENDPOINT_MAX 8 + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index ef58957bb..5d6033a66 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -117,6 +117,8 @@ #include "fsdev_stm32.h" #elif defined(TUP_USBIP_FSDEV_CH32) #include "fsdev_ch32.h" +#elif defined(TUP_USBIP_FSDEV_AT32) + #include "fsdev_at32.h" #else #error "Unknown USB IP" #endif diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h new file mode 100644 index 000000000..5f2ce4ba2 --- /dev/null +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -0,0 +1,224 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2024, hathach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ +#ifndef TUSB_FSDEV_AT32_H +#define TUSB_FSDEV_AT32_H + +#include "common/tusb_compiler.h" + +#if CFG_TUSB_MCU == OPT_MCU_AT32F403A_407 + #include "at32f403a_407.h" + +#elif CFG_TUSB_MCU == OPT_MCU_AT32F413 + #include "at32f413.h" + +#endif + +//#include "fsdev_common.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) +static const IRQn_Type fsdev_irq[] = { + USBFS_H_CAN1_TX_IRQn, + USBFS_L_CAN1_RX0_IRQn, + USBFSWakeUp_IRQn +}; +enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; + +#else + #error "Unsupported MCU" +#endif + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_EnableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_DisableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_disconnect(uint8_t rhport) { + (void) rhport; + /* disable usb phy */ + //USB->ctrl_bit.disusb = TRUE; + *(int *)(0x40000000+0x5C00+0x40) |= (1<<1); + *(int *)(0x40000000+0x5C00+0x60) |= (1<<1); + /* D+ 1.5k pull-up disable */ + //USB->cfg_bit.puo = TRUE; +} + +void dcd_connect(uint8_t rhport) { + (void) rhport; + /* enable usb phy */ + //USB->ctrl_bit.disusb = 0; + *(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1); + *(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1); + /* Dp 1.5k pull-up enable */ + //USB->cfg_bit.puo = 0; +} + +#define FSDEV_PMA_SIZE (512u) +#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) +#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) + +/**************************** ISTR interrupt events *************************/ +#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ +#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ +#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */ +#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */ +#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */ +#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */ +#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */ +#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */ +#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */ +#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */ + +/* Legacy defines */ +#define USB_ISTR_PMAOVRM USB_ISTR_PMAOVR + +#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */ +#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/ +#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */ +#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */ +#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */ +#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */ +#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */ +#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */ + +/* Legacy defines */ +#define USB_CLR_PMAOVRM USB_CLR_PMAOVR + +/************************* CNTR control register bits definitions ***********/ +#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */ +#define USB_CNTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */ +#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */ +#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */ +#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */ +#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */ +#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */ +#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */ +#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */ +#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */ +#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */ +#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */ +#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */ + +/* Legacy defines */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVR +#define USB_CNTR_LP_MODE USB_CNTR_LPMODE + +/******************** FNR Frame Number Register bit definitions ************/ +#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */ +#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */ +#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */ +#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */ +#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */ + +/******************** DADDR Device ADDRess bit definitions ****************/ +#define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */ +#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */ + +/****************************** Endpoint register *************************/ +#define USB_EP0R USB_BASE /*!< endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x04U) /*!< endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x08U) /*!< endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0CU) /*!< endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x10U) /*!< endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x14U) /*!< endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x18U) /*!< endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x1CU) /*!< endpoint 7 register address */ +/* bit positions */ +#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */ +#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */ +#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */ +#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK ((uint16_t) ~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h new file mode 100644 index 000000000..10832a702 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -0,0 +1,135 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + + +#ifndef DWC2_AT32_H_ +#define DWC2_AT32_H_ + +#define DWC2_EP_MAX TUP_DCD_ENDPOINT_MAX + +#if CFG_TUSB_MCU == OPT_MCU_AT32F415 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F435_437 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGFS2_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F423 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#elif CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG2_FIFO_SIZE 4096 + #define OTG1_IRQn OTGFS1_IRQn + #define OTG2_IRQn OTGHS_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL + #define DWC2_OTG2_REG_BASE 0x40040000UL //OTGHS +#elif CFG_TUSB_MCU == OPT_MCU_AT32F425 + #include + #define OTG1_FIFO_SIZE 1280 + #define OTG1_IRQn OTGFS1_IRQn + #define DWC2_OTG1_REG_BASE 0x50000000UL +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +static const dwc2_controller_t _dwc2_controller[] = +{ + { .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE }, + #if defined DWC2_OTG2_REG_BASE + { .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE } + #endif +}; + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); +} + +TU_ATTR_ALWAYS_INLINE +static inline void dwc2_dcd_int_disable (uint8_t rhport) +{ + NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); +} + +static inline void dwc2_remote_wakeup_delay(void) +{ + // try to delay for 1 ms + uint32_t count = system_core_clock / 1000; + while ( count-- ) __asm volatile ("nop"); +} + +// MCU specific PHY init, called BEFORE core reset +static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + // Enable on-chip HS PHY + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) + { + + } + else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) + { + + } +} + +// MCU specific PHY update, it is called AFTER init() and core reset +static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) +{ + (void) dwc2; + (void) hs_phy_type; + + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; +} + +#ifdef __cplusplus +} +#endif + +#endif /* DWC2_GD32_H_ */ diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index e1e7d5c1a..56326d5a7 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -121,6 +121,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (ghwcfg4.phy_data_width) { gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + #endif + } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } @@ -139,7 +145,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (ghwcfg4.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + + /* at32f402_405 does not actually support 16-bit */ + #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos; + #endif + dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 18b93894f..33219f786 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -49,6 +49,8 @@ #include "dwc2_efm32.h" #elif TU_CHECK_MCU(OPT_MCU_XMC4000) #include "dwc2_xmc.h" +#elif defined(TUP_USBIP_DWC2_AT32) + #include "dwc2_at32.h" #else #error "Unsupported MCUs" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 867babc33..ebd8d9add 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -201,6 +201,15 @@ #define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 #define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 +// ArteryTek +#define OPT_MCU_AT32F403A_407 2500 ///< ArteryTek AT32F403A_AT32F407 +#define OPT_MCU_AT32F415 2501 ///< ArteryTek AT32F415 +#define OPT_MCU_AT32F435_437 2502 ///< ArteryTek AT32F435_AT32F437 +#define OPT_MCU_AT32F423 2503 ///< ArteryTek AT32F423 +#define OPT_MCU_AT32F402_405 2504 ///< ArteryTek AT32F402_405 +#define OPT_MCU_AT32F425 2505 ///< ArteryTek AT32F425 +#define OPT_MCU_AT32F413 2506 ///< ArteryTek AT32F413 + // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) diff --git a/tools/get_deps.py b/tools/get_deps.py index 6a36ef35d..9a5fa37d9 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -208,6 +208,27 @@ deps_optional = { 'hw/mcu/wch/ch32f20x': ['https://github.com/openwch/ch32f20x.git', '77c4095087e5ed2c548ec9058e655d0b8757663b', 'ch32f20x'], + 'hw/mcu/artery/at32f403a_407': ['https://github.com/ArteryTek/AT32F403A_407_Firmware_Library.git', + 'f2cb360c3d28fada76b374308b8c4c61d37a090b', + 'at32f403a_407'], + 'hw/mcu/artery/at32f415': ['https://github.com/ArteryTek/AT32F415_Firmware_Library.git', + '716f545aa1290ff144ccf023a8e797b951e1bc8e', + 'at32f415'], + 'hw/mcu/artery/at32f435_437': ['https://github.com/ArteryTek/AT32F435_437_Firmware_Library.git', + '25439cc6650a8ae0345934e8707a5f38c7ae41f8', + 'at32f435_437'], + 'hw/mcu/artery/at32f423': ['https://github.com/ArteryTek/AT32F423_Firmware_Library.git', + '2afa7f12852e57a9e8aab3a892c641e1a8635a18', + 'at32f423'], + 'hw/mcu/artery/at32f402_405': ['https://github.com/ArteryTek/AT32F402_405_Firmware_Library.git', + '4424515c2663e82438654e0947695295df2abdfe', + 'at32f402_405'], + 'hw/mcu/artery/at32f425': ['https://github.com/ArteryTek/AT32F425_Firmware_Library.git', + '620233e1357d5c1b7e2bde6b9dd5196822b91817', + 'at32f425'], + 'hw/mcu/artery/at32f413': ['https://github.com/ArteryTek/AT32F413_Firmware_Library.git', + 'f6fe62dfec9fd40c5b63d92fc5ef2c2b5e77a450', + 'at32f413'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' -- cgit v1.3.1 From 7b995267d6c5fb59719e9c652ab53186fa42c8b4 Mon Sep 17 00:00:00 2001 From: YixingShen Date: Mon, 7 Jul 2025 15:46:37 +0800 Subject: update --- src/class/vendor/vendor_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index df1518111..6f109c321 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -202,7 +202,7 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin // Find available interface vendord_interface_t* p_vendor = NULL; uint8_t itf; - for(itf=0; i Date: Mon, 7 Jul 2025 12:33:14 +0700 Subject: change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1 use stock iar linker --- hw/bsp/stm32h7rs/family.cmake | 2 +- hw/bsp/stm32h7rs/family.mk | 2 +- hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf | 55 --------------------------- src/common/tusb_mcu.h | 30 +++++++-------- src/portable/synopsys/dwc2/dwc2_stm32.h | 10 ++--- src/tusb_option.h | 4 +- 6 files changed, 23 insertions(+), 80 deletions(-) delete mode 100644 hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf (limited to 'src') diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake index 6b7915c93..40230ef12 100644 --- a/hw/bsp/stm32h7rs/family.cmake +++ b/hw/bsp/stm32h7rs/family.cmake @@ -58,7 +58,7 @@ function(add_board_target BOARD_TARGET) endif() set(LD_FILE_Clang ${LD_FILE_GNU}) if(NOT DEFINED LD_FILE_IAR) - set(LD_FILE_IAR ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.icf) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) endif() add_library(${BOARD_TARGET} STATIC diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk index 45d4da0cf..fba38448d 100644 --- a/hw/bsp/stm32h7rs/family.mk +++ b/hw/bsp/stm32h7rs/family.mk @@ -92,4 +92,4 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s # Linker LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld -LD_FILE_IAR ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.icf +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf diff --git a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf deleted file mode 100644 index 786be3560..000000000 --- a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf +++ /dev/null @@ -1,55 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x08000000; -/*-Memory Regions-*/ -define symbol NONCACHEABLEBUFFER_size = 0x400; -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x24000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2404FFFF - NONCACHEABLEBUFFER_size; -define symbol NONCACHEABLEBUFFER_start = __ICFEDIT_region_RAM_end__ + 1; -define symbol NONCACHEABLEBUFFER_end = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size; - - -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0x200; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __region_ITCM_start__ = 0x00000000; -define symbol __region_ITCM_end__ = 0x0000FFFF; -define symbol __region_DTCM_start__ = 0x20000000; -define symbol __region_DTCM_end__ = 0x2000FFFF; -define symbol __region_SRAMAHB_start__ = 0x30000000; -define symbol __region_SRAMAHB_end__ = 0x30007FFF; -define symbol __region_BKPSRAM_start__ = 0x38800000; -define symbol __region_BKPSRAM_end__ = 0x38800FFF; - -export symbol NONCACHEABLEBUFFER_start; -export symbol NONCACHEABLEBUFFER_size; - -export symbol __ICFEDIT_region_ROM_start__; -export symbol __ICFEDIT_region_ROM_end__; -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region NONCACHEABLE_region = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end]; -define region ITCM_region = mem:[from __region_ITCM_start__ to __region_ITCM_end__]; -define region DTCM_region = mem:[from __region_DTCM_start__ to __region_DTCM_end__]; -define region SRAMAHB_region = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__]; -define region BKPSRAM_region = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite }; -place in DTCM_region { block CSTACK, block HEAP }; -place in NONCACHEABLE_region { section noncacheable_buffer }; diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 4205239f1..94eeb1294 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -117,9 +117,9 @@ #define TUP_RHPORT_HIGHSPEED 1 #if __CORTEX_M == 7 - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #endif #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) @@ -221,9 +221,9 @@ #endif // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #elif TU_CHECK_MCU(OPT_MCU_STM32H7) #include "stm32h7xx.h" @@ -233,10 +233,10 @@ #define TUP_DCD_ENDPOINT_MAX 9 #if __CORTEX_M == 7 - // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + // Enable dcache if DMA is enabled + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 #endif #elif TU_CHECK_MCU(OPT_MCU_STM32H5) @@ -336,9 +336,9 @@ #define TUP_RHPORT_HIGHSPEED 1 // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 //--------------------------------------------------------------------+ // Sony @@ -410,8 +410,8 @@ #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE // Enable dcache if DMA is enabled - #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index f9aa5301b..5f2b8419c 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -282,8 +282,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { //------------- DCache -------------// #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE -typedef struct -{ +typedef struct { uintptr_t start; uintptr_t end; } mem_region_t; @@ -310,16 +309,15 @@ static mem_region_t uncached_regions[] = { }; TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { - if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) { - size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE; + if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) { + size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT; } return size; } TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) { for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) { - if (addr >= uncached_regions[i].start && addr <= uncached_regions[i].end) - return false; + if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; } } return true; } diff --git a/src/tusb_option.h b/src/tusb_option.h index 867babc33..e6f5004b6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -420,7 +420,7 @@ #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT - #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1 #endif #define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT @@ -428,7 +428,7 @@ // OS selection #ifndef CFG_TUSB_OS - #define CFG_TUSB_OS OPT_OS_NONE + #define CFG_TUSB_OS OPT_OS_NONE #endif #ifndef CFG_TUSB_OS_INC_PATH -- cgit v1.3.1 From 1a41445b17e11db9ab58a39488e4b0d9d85f0fd1 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Tue, 8 Jul 2025 09:51:02 +0700 Subject: Fix HID descriptor parser size handling --- src/class/hid/hid_host.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 57e437196..b2b68e108 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -662,9 +662,9 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t const tag = header.tag; uint8_t const type = header.type; - uint8_t const size = header.size; + uint8_t const size = (header.size == 3) ? 4 : header.size; - uint8_t const data8 = desc_report[0]; + uint8_t const data8 = (size > 0) ? desc_report[0] : 0; TU_LOG(3, "tag = %d, type = %d, size = %d, data = ", tag, type, size); for (uint32_t i = 0; i < size; i++) { -- cgit v1.3.1 From 2908995c4c0a1221247c9d5aed7a5c9817dcb52e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Jul 2025 11:05:16 +0700 Subject: minor reformat code --- src/class/audio/audio_device.c | 16 +++++---- src/class/audio/audio_device.h | 79 ++++++++++++++++-------------------------- src/device/usbd.c | 5 ++- src/device/usbd_pvt.h | 2 +- 4 files changed, 41 insertions(+), 61 deletions(-) (limited to 'src') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index f440a63ef..278c4514a 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -522,7 +522,9 @@ bool tud_audio_n_clear_ep_out_ff(uint8_t func_id) { } tu_fifo_t *tud_audio_n_get_ep_out_ff(uint8_t func_id) { - if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_out_ff; + if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) { + return &_audiod_fct[func_id].ep_out_ff; + } return NULL; } @@ -569,14 +571,15 @@ uint16_t tud_audio_n_write(uint8_t func_id, const void *data, uint16_t len) { return tu_fifo_write_n(&_audiod_fct[func_id].ep_in_ff, data, len); } -bool tud_audio_n_clear_ep_in_ff(uint8_t func_id)// Delete all content in the EP IN FIFO -{ +bool tud_audio_n_clear_ep_in_ff(uint8_t func_id) { TU_VERIFY(func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL); return tu_fifo_clear(&_audiod_fct[func_id].ep_in_ff); } tu_fifo_t *tud_audio_n_get_ep_in_ff(uint8_t func_id) { - if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) return &_audiod_fct[func_id].ep_in_ff; + if (func_id < CFG_TUD_AUDIO && _audiod_fct[func_id].p_desc != NULL) { + return &_audiod_fct[func_id].ep_in_ff; + } return NULL; } @@ -588,7 +591,7 @@ static bool audiod_tx_xfer_isr(uint8_t rhport, audiod_function_t * audio, uint16 TU_VERIFY(audiod_get_AS_interface_index(audio->ep_in_as_intf_num, audio, &idxItf, &dummy2)); // Only send something if current alternate interface is not 0 as in this case nothing is to be sent due to UAC2 specifications - if (audio->alt_setting[idxItf] == 0) return false; + if (audio->alt_setting[idxItf] == 0) { return false; } // Send everything in ISO EP FIFO uint16_t n_bytes_tx; @@ -1459,8 +1462,7 @@ bool audiod_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint3 return false; } -bool audiod_xfer_isr(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) -{ +bool audiod_xfer_isr(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) { (void) result; (void) xferred_bytes; diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index e5724fc6a..307389418 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -26,8 +26,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_AUDIO_DEVICE_H_ -#define _TUSB_AUDIO_DEVICE_H_ +#ifndef TUSB_AUDIO_DEVICE_H_ +#define TUSB_AUDIO_DEVICE_H_ #include "audio.h" @@ -219,19 +219,19 @@ extern "C" { // Application API (Multiple Interfaces) // CFG_TUD_AUDIO > 1 //--------------------------------------------------------------------+ -bool tud_audio_n_mounted (uint8_t func_id); +bool tud_audio_n_mounted(uint8_t func_id); #if CFG_TUD_AUDIO_ENABLE_EP_OUT -uint16_t tud_audio_n_available (uint8_t func_id); -uint16_t tud_audio_n_read (uint8_t func_id, void* buffer, uint16_t bufsize); -bool tud_audio_n_clear_ep_out_ff (uint8_t func_id); // Delete all content in the EP OUT FIFO -tu_fifo_t* tud_audio_n_get_ep_out_ff (uint8_t func_id); +uint16_t tud_audio_n_available (uint8_t func_id); +uint16_t tud_audio_n_read (uint8_t func_id, void* buffer, uint16_t bufsize); +bool tud_audio_n_clear_ep_out_ff (uint8_t func_id); +tu_fifo_t* tud_audio_n_get_ep_out_ff (uint8_t func_id); #endif #if CFG_TUD_AUDIO_ENABLE_EP_IN -uint16_t tud_audio_n_write (uint8_t func_id, const void * data, uint16_t len); -bool tud_audio_n_clear_ep_in_ff (uint8_t func_id); // Delete all content in the EP IN FIFO -tu_fifo_t* tud_audio_n_get_ep_in_ff (uint8_t func_id); +uint16_t tud_audio_n_write (uint8_t func_id, const void * data, uint16_t len); +bool tud_audio_n_clear_ep_in_ff (uint8_t func_id); +tu_fifo_t* tud_audio_n_get_ep_in_ff (uint8_t func_id); #endif #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP @@ -241,24 +241,19 @@ bool tud_audio_int_n_write (uint8_t func_id, const audio_ //--------------------------------------------------------------------+ // Application API (Interface0) //--------------------------------------------------------------------+ - static inline bool tud_audio_mounted (void); -// RX API - #if CFG_TUD_AUDIO_ENABLE_EP_OUT -static inline uint16_t tud_audio_available (void); -static inline bool tud_audio_clear_ep_out_ff (void); // Delete all content in the EP OUT FIFO -static inline uint16_t tud_audio_read (void* buffer, uint16_t bufsize); -static inline tu_fifo_t* tud_audio_get_ep_out_ff (void); +static inline uint16_t tud_audio_available (void); +static inline bool tud_audio_clear_ep_out_ff (void); +static inline uint16_t tud_audio_read (void* buffer, uint16_t bufsize); +static inline tu_fifo_t* tud_audio_get_ep_out_ff (void); #endif -// TX API - #if CFG_TUD_AUDIO_ENABLE_EP_IN -static inline uint16_t tud_audio_write (const void * data, uint16_t len); -static inline bool tud_audio_clear_ep_in_ff (void); -static inline tu_fifo_t* tud_audio_get_ep_in_ff (void); +static inline uint16_t tud_audio_write (const void * data, uint16_t len); +static inline bool tud_audio_clear_ep_in_ff (void); +static inline tu_fifo_t* tud_audio_get_ep_in_ff (void); #endif // INT CTR API @@ -280,13 +275,13 @@ bool tud_audio_buffer_and_schedule_control_xfer(uint8_t rhport, tusb_control_req //--------------------------------------------------------------------+ #if CFG_TUD_AUDIO_ENABLE_EP_IN -// Callback in ISR context, this function is called once a transmit of an audio packet was successfully completed. +// Invoked in ISR context once an audio packet was sent successfully. // Normally this function is not needed, since the data transfer should be driven by audio clock (i.e. I2S clock), call tud_audio_write() in I2S receive callback. bool tud_audio_tx_done_isr(uint8_t rhport, uint16_t n_bytes_sent, uint8_t func_id, uint8_t ep_in, uint8_t cur_alt_setting); #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT -// Callback in ISR context, this function is called once a receive of an audio packet was successfully completed. +// Invoked in ISR context once an audio packet was received successfully. // Normally this function is not needed, since the data transfer should be driven by audio clock (i.e. I2S clock), call tud_audio_read() in I2S transmit callback. bool tud_audio_rx_done_isr(uint8_t rhport, uint16_t n_bytes_received, uint8_t func_id, uint8_t ep_out, uint8_t cur_alt_setting); #endif @@ -410,72 +405,56 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const * // Inline Functions //--------------------------------------------------------------------+ -static inline bool tud_audio_mounted(void) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tud_audio_mounted(void) { return tud_audio_n_mounted(0); } -// RX API - #if CFG_TUD_AUDIO_ENABLE_EP_OUT -static inline uint16_t tud_audio_available(void) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t tud_audio_available(void) { return tud_audio_n_available(0); } -static inline uint16_t tud_audio_read(void* buffer, uint16_t bufsize) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t tud_audio_read(void* buffer, uint16_t bufsize) { return tud_audio_n_read(0, buffer, bufsize); } -static inline bool tud_audio_clear_ep_out_ff(void) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tud_audio_clear_ep_out_ff(void) { return tud_audio_n_clear_ep_out_ff(0); } -static inline tu_fifo_t* tud_audio_get_ep_out_ff(void) -{ +TU_ATTR_ALWAYS_INLINE static inline tu_fifo_t* tud_audio_get_ep_out_ff(void) { return tud_audio_n_get_ep_out_ff(0); } #endif -// TX API - #if CFG_TUD_AUDIO_ENABLE_EP_IN -static inline uint16_t tud_audio_write(const void * data, uint16_t len) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t tud_audio_write(const void * data, uint16_t len) { return tud_audio_n_write(0, data, len); } -static inline bool tud_audio_clear_ep_in_ff(void) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tud_audio_clear_ep_in_ff(void) { return tud_audio_n_clear_ep_in_ff(0); } -static inline tu_fifo_t* tud_audio_get_ep_in_ff(void) -{ +TU_ATTR_ALWAYS_INLINE static inline tu_fifo_t* tud_audio_get_ep_in_ff(void) { return tud_audio_n_get_ep_in_ff(0); } #endif #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP -static inline bool tud_audio_int_write(const audio_interrupt_data_t * data) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tud_audio_int_write(const audio_interrupt_data_t * data) { return tud_audio_int_n_write(0, data); } #endif #if CFG_TUD_AUDIO_ENABLE_EP_OUT && CFG_TUD_AUDIO_ENABLE_FEEDBACK_EP - -static inline bool tud_audio_fb_set(uint32_t feedback) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tud_audio_fb_set(uint32_t feedback) { return tud_audio_n_fb_set(0, feedback); } - #endif //--------------------------------------------------------------------+ diff --git a/src/device/usbd.c b/src/device/usbd.c index b8c9d1b9e..a803301e3 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1260,14 +1260,13 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) send = true; break; - case DCD_EVENT_XFER_COMPLETE: - { - send = true; + case DCD_EVENT_XFER_COMPLETE: { // Invoke the class callback associated with the endpoint address uint8_t const ep_addr = event->xfer_complete.ep_addr; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const ep_dir = tu_edpt_dir(ep_addr); + send = true; if(epnum > 0) { usbd_class_driver_t const* driver = get_driver(_usbd_dev.ep2drv[epnum][ep_dir]); diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 40622be66..f1797bf0d 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -57,7 +57,7 @@ typedef struct { uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len); bool (* control_xfer_cb ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request); bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); - bool (* xfer_isr ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); // optional + bool (* xfer_isr ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); // optional, return false to defer to xfer_cb() void (* sof ) (uint8_t rhport, uint32_t frame_count); // optional } usbd_class_driver_t; -- cgit v1.3.1 From 961ea73e55a54d77882ebc3a40fbacc3bd1899e3 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Jul 2025 12:13:22 +0700 Subject: revert edpt busy/claim status if xfer_isr() defer to xfer_cb() --- src/device/usbd.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/device/usbd.c b/src/device/usbd.c index a803301e3..1e16034a8 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1275,6 +1275,12 @@ TU_ATTR_FAST_FUNC void dcd_event_handler(dcd_event_t const* event, bool in_isr) _usbd_dev.ep_status[epnum][ep_dir].claimed = 0; send = !driver->xfer_isr(event->rhport, ep_addr, (xfer_result_t) event->xfer_complete.result, event->xfer_complete.len); + + // xfer_isr() is deferred to xfer_cb(), revert busy/claimed status + if (send) { + _usbd_dev.ep_status[epnum][ep_dir].busy = 1; + _usbd_dev.ep_status[epnum][ep_dir].claimed = 1; + } } } break; -- cgit v1.3.1 From 59b55898d9f40e7a436836c95c0885e5fc5a0c7c Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 9 Jul 2025 11:27:06 +0700 Subject: fix HID parser variable size handling --- src/class/hid/hid_host.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index b2b68e108..0fbb97c53 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -662,7 +662,10 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t const tag = header.tag; uint8_t const type = header.type; - uint8_t const size = (header.size == 3) ? 4 : header.size; + uint8_t size = header.size; + if (size == 3) { + size = 4; + } uint8_t const data8 = (size > 0) ? desc_report[0] : 0; -- cgit v1.3.1 From 5eb68a3c8777b9085d1fea8e0bba1ac8fb5a26d6 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 9 Jul 2025 11:27:23 +0700 Subject: Add spec reference for 4-byte HID item size --- src/class/hid/hid_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 0fbb97c53..56fccdd22 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -664,7 +664,7 @@ uint8_t tuh_hid_parse_report_descriptor(tuh_hid_report_info_t* report_info_arr, uint8_t const type = header.type; uint8_t size = header.size; if (size == 3) { - size = 4; + size = 4; // HID 1.11 6.2.2.2 3 is 4 bytes } uint8_t const data8 = (size > 0) ? desc_report[0] : 0; -- cgit v1.3.1 From e598972438a698e00bbf38a21bbe3744741be98d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 9 Jul 2025 15:06:26 +0700 Subject: add board_vbus_set() for samd21/d51 to enable usb host vbus enable host example build for samd21/d51 --- .idea/cmake.xml | 6 +- examples/host/bare_api/only.txt | 2 + examples/host/cdc_msc_hid/only.txt | 2 + examples/host/cdc_msc_hid_freertos/only.txt | 2 + examples/host/device_info/only.txt | 2 + examples/host/hid_controller/only.txt | 2 + examples/host/midi_rx/only.txt | 2 + examples/host/msc_file_explorer/only.txt | 2 + hw/bsp/samd21/boards/atsamd21_xpro/board.h | 5 + .../boards/circuitplayground_express/board.h | 4 + hw/bsp/samd21/boards/curiosity_nano/board.h | 4 + hw/bsp/samd21/boards/cynthion_d21/board.h | 4 + hw/bsp/samd21/boards/feather_m0_express/board.h | 4 + hw/bsp/samd21/boards/itsybitsy_m0/board.h | 4 + hw/bsp/samd21/boards/metro_m0_express/board.h | 3 + hw/bsp/samd21/boards/qtpy/board.h | 4 + hw/bsp/samd21/boards/seeeduino_xiao/board.h | 4 + .../samd21/boards/sparkfun_samd21_mini_usb/board.h | 14 +- hw/bsp/samd21/boards/trinket_m0/board.h | 4 + hw/bsp/samd21/family.c | 15 +-- hw/bsp/samd5x_e5x/boards/d5035_01/board.h | 150 +-------------------- .../samd5x_e5x/boards/feather_m4_express/board.h | 4 + hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h | 4 + hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h | 3 + hw/bsp/samd5x_e5x/boards/pybadge/board.h | 4 + hw/bsp/samd5x_e5x/boards/pyportal/board.h | 4 + hw/bsp/samd5x_e5x/boards/same54_xplained/board.h | 4 + hw/bsp/samd5x_e5x/family.c | 15 +-- src/portable/microchip/samd/hcd_samd.c | 10 +- 29 files changed, 109 insertions(+), 178 deletions(-) (limited to 'src') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index dd219bc77..7e0a9be92 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -78,11 +78,13 @@ - + + - + + diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index 31dcb108c..cba58f8e8 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -18,3 +18,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 31dcb108c..cba58f8e8 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -18,3 +18,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index d939d4e7b..576271aff 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -15,3 +15,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index 94ddc73c3..133a7c9a0 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -21,3 +21,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index 31dcb108c..cba58f8e8 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -18,3 +18,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/midi_rx/only.txt b/examples/host/midi_rx/only.txt index 94ddc73c3..133a7c9a0 100644 --- a/examples/host/midi_rx/only.txt +++ b/examples/host/midi_rx/only.txt @@ -21,3 +21,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 31dcb108c..cba58f8e8 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -18,3 +18,5 @@ mcu:STM32F7 mcu:STM32H7 mcu:STM32H7RS mcu:STM32N6 +family:samd21 +family:samd5x_e5x diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h index 6d2e40c56..82ab321cf 100644 --- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h +++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h @@ -48,6 +48,11 @@ #define UART_RX_PIN 4 #define UART_TX_PIN 5 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h index 6a4ec32a9..bfe2d9951 100644 --- a/hw/bsp/samd21/boards/circuitplayground_express/board.h +++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h @@ -48,6 +48,10 @@ #define UART_RX_PIN 4 #define UART_TX_PIN 5 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h index 78d701ec9..a2a7385a4 100644 --- a/hw/bsp/samd21/boards/curiosity_nano/board.h +++ b/hw/bsp/samd21/boards/curiosity_nano/board.h @@ -48,6 +48,10 @@ #define UART_RX_PIN 31 // CDC5_RX #define UART_TX_PIN 37 // CDC5_TX +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.h b/hw/bsp/samd21/boards/cynthion_d21/board.h index 6a2b8c5c6..83782bc65 100644 --- a/hw/bsp/samd21/boards/cynthion_d21/board.h +++ b/hw/bsp/samd21/boards/cynthion_d21/board.h @@ -44,6 +44,10 @@ #define BUTTON_PIN PIN_PB22 #define BUTTON_STATE_ACTIVE 0 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h index a7f9122ee..6fe13eb30 100644 --- a/hw/bsp/samd21/boards/feather_m0_express/board.h +++ b/hw/bsp/samd21/boards/feather_m0_express/board.h @@ -63,6 +63,10 @@ #define MAX3421_INTR_PIN 7 // D10 #define MAX3421_INTR_EIC_ID 7 // EIC7 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h index 15a0afb15..d901b2ea4 100644 --- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h +++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h @@ -48,6 +48,10 @@ #define UART_RX_PIN 4 #define UART_TX_PIN 5 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h index 405c92b02..726de3259 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.h +++ b/hw/bsp/samd21/boards/metro_m0_express/board.h @@ -63,6 +63,9 @@ #define MAX3421_INTR_PIN 7 // D9 #define MAX3421_INTR_EIC_ID 7 // EIC7 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} #ifdef __cplusplus } diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h index 29a9f727f..b1cf338e4 100644 --- a/hw/bsp/samd21/boards/qtpy/board.h +++ b/hw/bsp/samd21/boards/qtpy/board.h @@ -44,6 +44,10 @@ #define UART_RX_PIN 8 #define UART_TX_PIN 7 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h index 0a6d1fc7d..1c434c68c 100644 --- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h +++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h @@ -48,6 +48,10 @@ #define UART_RX_PIN 4 #define UART_TX_PIN 5 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h index 85be34008..a05cf5e4e 100644 --- a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h +++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h @@ -37,17 +37,23 @@ #endif // LED -#define LED_PIN /*PA*/17 /*(D13)*/ +#define LED_PIN 17 // PA17 (D13) #define LED_STATE_ON 1 // Button -#define BUTTON_PIN /*PA*/14 /*(D2)*/ +#define BUTTON_PIN 14 // PA14 (D2) #define BUTTON_STATE_ACTIVE 0 // UART #define UART_SERCOM 0 -#define UART_RX_PIN /*PA*/11 /*(D0)*/ -#define UART_TX_PIN /*PA*/10 /*(D1)*/ +#define UART_RX_PIN 11 // PA11 D0 +#define UART_TX_PIN 10 // PA10 D1 + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; + gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA28, state); +} #ifdef __cplusplus } diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h index 22e7cb77f..01ad83089 100644 --- a/hw/bsp/samd21/boards/trinket_m0/board.h +++ b/hw/bsp/samd21/boards/trinket_m0/board.h @@ -38,3 +38,7 @@ #define UART_SERCOM 0 #define UART_RX_PIN 7 #define UART_TX_PIN 6 + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index dd76509ae..14e60e917 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -30,7 +30,6 @@ #include "sam.h" #include "bsp/board_api.h" -#include "board.h" // Suppress warning caused by mcu driver #ifdef __GNUC__ @@ -50,6 +49,9 @@ #pragma GCC diagnostic pop #endif +static inline void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_UNUSED; +#include "board.h" + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -68,7 +70,7 @@ void USB_Handler(void) { tud_int_handler(0); #endif -#if CFG_TUH_ENABLED && !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) +#if CFG_TUH_ENABLED && !CFG_TUH_MAX3421 tuh_int_handler(0); #endif } @@ -78,11 +80,9 @@ void USB_Handler(void) { //--------------------------------------------------------------------+ static void uart_init(void); -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID) - static void max3421_init(void); - #endif void board_init(void) { @@ -151,12 +151,11 @@ void board_init(void) { _gclk_enable_channel(TCC0_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); #if CFG_TUH_ENABLED - #if defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 + #if CFG_TUH_MAX3421 max3421_init(); #else // VBUS Power - gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA28, true); + board_vbus_set(0, true); #endif #endif } diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h index 4eb4a4ebe..caa79f2dd 100644 --- a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h +++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h @@ -45,156 +45,10 @@ // UART: HWREV < 3: SERCOM5 on PB02, otherwise SERCOM0 on PA08 // XTAL configure is also different for HWREV as well -#if 0 -static inline void init_clock(void) { - /* AUTOWS is enabled by default in REG_NVMCTRL_CTRLA - no need to change the number of wait states when changing the core clock */ -#if HWREV == 1 - /* configure XOSC1 for a 16MHz crystal connected to XIN1/XOUT1 */ - OSCCTRL->XOSCCTRL[1].reg = - OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms - OSCCTRL_XOSCCTRL_RUNSTDBY | - OSCCTRL_XOSCCTRL_ENALC | - OSCCTRL_XOSCCTRL_IMULT(4) | - OSCCTRL_XOSCCTRL_IPTAT(3) | - OSCCTRL_XOSCCTRL_XTALEN | - OSCCTRL_XOSCCTRL_ENABLE; - while(0 == OSCCTRL->STATUS.bit.XOSCRDY1); - - OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 8, input = XOSC1 */ - OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */ - OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; - while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */ - - OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK(OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val); /* pre-scaler = 16, input = XOSC1 */ - OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */ - OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; - while(0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */ -#else // HWREV >= 1 - /* configure XOSC0 for a 16MHz crystal connected to XIN0/XOUT0 */ - OSCCTRL->XOSCCTRL[0].reg = - OSCCTRL_XOSCCTRL_STARTUP(6) | // 1,953 ms - OSCCTRL_XOSCCTRL_RUNSTDBY | - OSCCTRL_XOSCCTRL_ENALC | - OSCCTRL_XOSCCTRL_IMULT(4) | - OSCCTRL_XOSCCTRL_IPTAT(3) | - OSCCTRL_XOSCCTRL_XTALEN | - OSCCTRL_XOSCCTRL_ENABLE; - while (0 == OSCCTRL->STATUS.bit.XOSCRDY0); - - OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(3) | OSCCTRL_DPLLCTRLB_REFCLK( - OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 8, input = XOSC1 */ - OSCCTRL->Dpll[0].DPLLRATIO.reg = - OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(39); /* multiply by 40 -> 80 MHz */ - OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; - while (0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL0 to be ready */ - - OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_DIV(7) | OSCCTRL_DPLLCTRLB_REFCLK( - OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val); /* pre-scaler = 16, input = XOSC1 */ - OSCCTRL->Dpll[1].DPLLRATIO.reg = - OSCCTRL_DPLLRATIO_LDRFRAC(0x0) | OSCCTRL_DPLLRATIO_LDR(47); /* multiply by 48 -> 48 MHz */ - OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_RUNSTDBY | OSCCTRL_DPLLCTRLA_ENABLE; - while (0 == OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY); /* wait for the PLL1 to be ready */ -#endif // HWREV - - /* configure clock-generator 0 to use DPLL0 as source -> GCLK0 is used for the core */ - GCLK->GENCTRL[0].reg = - GCLK_GENCTRL_DIV(0) | - GCLK_GENCTRL_RUNSTDBY | - GCLK_GENCTRL_GENEN | - GCLK_GENCTRL_SRC_DPLL0 | /* DPLL0 */ - GCLK_GENCTRL_IDC; - while (1 == GCLK->SYNCBUSY.bit.GENCTRL0); /* wait for the synchronization between clock domains to be complete */ - - /* configure clock-generator 1 to use DPLL1 as source -> for use with some peripheral */ - GCLK->GENCTRL[1].reg = - GCLK_GENCTRL_DIV(0) | - GCLK_GENCTRL_RUNSTDBY | - GCLK_GENCTRL_GENEN | - GCLK_GENCTRL_SRC_DPLL1 | - GCLK_GENCTRL_IDC; - while (1 == GCLK->SYNCBUSY.bit.GENCTRL1); /* wait for the synchronization between clock domains to be complete */ - - /* configure clock-generator 2 to use DPLL0 as source -> for use with SERCOM */ - GCLK->GENCTRL[2].reg = - GCLK_GENCTRL_DIV(1) | /* 80MHz */ - GCLK_GENCTRL_RUNSTDBY | - GCLK_GENCTRL_GENEN | - GCLK_GENCTRL_SRC_DPLL0 | - GCLK_GENCTRL_IDC; - while (1 == GCLK->SYNCBUSY.bit.GENCTRL2); /* wait for the synchronization between clock domains to be complete */ +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } -static inline void uart_init(void) { -#if HWREV < 3 - /* configure SERCOM5 on PB02 */ - PORT->Group[1].WRCONFIG.reg = - PORT_WRCONFIG_WRPINCFG | - PORT_WRCONFIG_WRPMUX | - PORT_WRCONFIG_PMUX(3) | /* function D */ - PORT_WRCONFIG_DRVSTR | - PORT_WRCONFIG_PINMASK(0x0004) | /* PB02 */ - PORT_WRCONFIG_PMUXEN; - - MCLK->APBDMASK.bit.SERCOM5_ = 1; - GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg = - GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */ - - SERCOM5->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */ - while (SERCOM5->USART.SYNCBUSY.bit.ENABLE); - - SERCOM5->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */ - SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */ - // SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */ - SERCOM_USART_CTRLA_DORD | /* LSB first */ - SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */ - SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */ - SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */ - - SERCOM5->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */ - SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */ - SERCOM5->USART.CTRLC.reg = 0x00; - // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E - SERCOM5->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21); - -// SERCOM5->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - SERCOM5->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */ - while (SERCOM5->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */ -#else - /* configure SERCOM0 on PA08 */ - PORT->Group[0].WRCONFIG.reg = - PORT_WRCONFIG_WRPINCFG | - PORT_WRCONFIG_WRPMUX | - PORT_WRCONFIG_PMUX(2) | /* function C */ - PORT_WRCONFIG_DRVSTR | - PORT_WRCONFIG_PINMASK(0x0100) | /* PA08 */ - PORT_WRCONFIG_PMUXEN; - - MCLK->APBAMASK.bit.SERCOM0_ = 1; - GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK2 | GCLK_PCHCTRL_CHEN; /* setup SERCOM to use GLCK2 -> 80MHz */ - - SERCOM0->USART.CTRLA.reg = 0x00; /* disable SERCOM -> enable config */ - while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); - - SERCOM0->USART.CTRLA.reg = /* CMODE = 0 -> async, SAMPA = 0, FORM = 0 -> USART frame, SMPR = 0 -> arithmetic baud rate */ - SERCOM_USART_CTRLA_SAMPR(1) | /* 0 = 16x / arithmetic baud rate, 1 = 16x / fractional baud rate */ - // SERCOM_USART_CTRLA_FORM(0) | /* 0 = USART Frame, 2 = LIN Master */ - SERCOM_USART_CTRLA_DORD | /* LSB first */ - SERCOM_USART_CTRLA_MODE(1) | /* 0 = Asynchronous, 1 = USART with internal clock */ - SERCOM_USART_CTRLA_RXPO(1) | /* SERCOM PAD[1] is used for data reception */ - SERCOM_USART_CTRLA_TXPO(0); /* SERCOM PAD[0] is used for data transmission */ - - SERCOM0->USART.CTRLB.reg = /* RXEM = 0 -> receiver disabled, LINCMD = 0 -> normal USART transmission, SFDE = 0 -> start-of-frame detection disabled, SBMODE = 0 -> one stop bit, CHSIZE = 0 -> 8 bits */ - SERCOM_USART_CTRLB_TXEN; /* transmitter enabled */ - SERCOM0->USART.CTRLC.reg = 0x00; - // 21.701388889 @ baud rate of 230400 bit/s, table 33-2, p 918 of DS60001507E - SERCOM0->USART.BAUD.reg = SERCOM_USART_BAUD_FRAC_FP(7) | SERCOM_USART_BAUD_FRAC_BAUD(21); - - // SERCOM0->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - SERCOM0->SPI.CTRLA.bit.ENABLE = 1; /* activate SERCOM */ - while(SERCOM0->USART.SYNCBUSY.bit.ENABLE); /* wait for SERCOM to be ready */ -#endif -} -#endif #ifdef __cplusplus } diff --git a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h index edb965c9d..a6882e427 100644 --- a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h @@ -65,6 +65,10 @@ #define MAX3421_INTR_PIN 19 // D9 #define MAX3421_INTR_EIC_ID 3 // EIC3 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h index d41ca4ac3..4e1a6f9dd 100644 --- a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h +++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h @@ -48,6 +48,10 @@ #define UART_TX_PIN 16 #define UART_RX_PIN 17 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h index b2eaaa54d..b76e317a5 100644 --- a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h @@ -63,6 +63,9 @@ #define MAX3421_INTR_PIN 20 // D9 #define MAX3421_INTR_EIC_ID 4 // EIC4 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} #ifdef __cplusplus } diff --git a/hw/bsp/samd5x_e5x/boards/pybadge/board.h b/hw/bsp/samd5x_e5x/boards/pybadge/board.h index a5d447db6..598d8cc88 100644 --- a/hw/bsp/samd5x_e5x/boards/pybadge/board.h +++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.h @@ -48,6 +48,10 @@ #define UART_TX_PIN (32 + 17) #define UART_RX_PIN (32 + 16) +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd5x_e5x/boards/pyportal/board.h b/hw/bsp/samd5x_e5x/boards/pyportal/board.h index e635e1375..7e7370681 100644 --- a/hw/bsp/samd5x_e5x/boards/pyportal/board.h +++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.h @@ -48,6 +48,10 @@ #define UART_TX_PIN (32 + 13) #define UART_RX_PIN (32 + 12) +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h index 6c252f9d0..868c02a66 100644 --- a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h +++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h @@ -48,6 +48,10 @@ //#define UART_TX_PIN 23 //#define UART_RX_PIN 22 +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index a5d094149..d53aa00d6 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -30,7 +30,6 @@ #include "sam.h" #include "bsp/board_api.h" -#include "board.h" // Suppress warning caused by mcu driver #ifdef __GNUC__ @@ -47,6 +46,9 @@ #pragma GCC diagnostic pop #endif +static inline void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_UNUSED; +#include "board.h" + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM DECLARATION //--------------------------------------------------------------------+ @@ -60,8 +62,7 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE inline void USB_Any_Handler(void) -{ +TU_ATTR_ALWAYS_INLINE static inline void USB_Any_Handler(void) { #if CFG_TUD_ENABLED tud_int_handler(0); #endif @@ -72,11 +73,8 @@ TU_ATTR_ALWAYS_INLINE inline void USB_Any_Handler(void) } void USB_0_Handler(void) { USB_Any_Handler(); } - void USB_1_Handler(void) { USB_Any_Handler(); } - void USB_2_Handler(void) { USB_Any_Handler(); } - void USB_3_Handler(void) { USB_Any_Handler(); } //--------------------------------------------------------------------+ @@ -84,10 +82,8 @@ void USB_3_Handler(void) { USB_Any_Handler(); } //--------------------------------------------------------------------+ #if CFG_TUH_ENABLED && CFG_TUH_MAX3421 - #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID) #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler) - static void max3421_init(void); #endif @@ -150,8 +146,7 @@ void board_init(void) { max3421_init(); #else // VBUS Power - gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_OUT); - gpio_set_pin_level(PIN_PA28, true); + board_vbus_set(0, true); #endif #endif } diff --git a/src/portable/microchip/samd/hcd_samd.c b/src/portable/microchip/samd/hcd_samd.c index cecaee0b0..1f4b2b233 100644 --- a/src/portable/microchip/samd/hcd_samd.c +++ b/src/portable/microchip/samd/hcd_samd.c @@ -171,7 +171,7 @@ static void samd_free_pipe(uint8_t pipe) USB->HOST.HostPipe[pipe].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; USB->HOST.HostPipe[pipe].PCFG.reg &= ~USB_HOST_PCFG_PTYPE_Msk; USB->HOST.HostPipe[pipe].PINTENCLR.reg = USB_HOST_PINTENCLR_MASK; - memset((uint8_t*) &usb_pipe_table[pipe], 0, sizeof(usb_pipe_table[pipe])); + memset((uint8_t*)(uintptr_t) &usb_pipe_table[pipe], 0, sizeof(usb_pipe_table[pipe])); } static void samd_free_all_pipes(void) @@ -197,8 +197,7 @@ static bool samd_on_xfer(uint8_t pipe, xfer_result_t xfer_result) xfer_delta = 0; } - TU_LOG3( - "samd_on_xfer(%d, result=%d, xdelta=%d, rem=%d)\r\n", xfer_result, pipe, xfer_delta, pipe_status->xfer_remaining); + TU_LOG3("samd_on_xfer(%d, result=%d, xdelta=%d, rem=%d)\r\n", xfer_result, pipe, xfer_delta, pipe_status->xfer_remaining); // update pipe status if (xfer_delta > pipe_status->xfer_remaining) { @@ -390,10 +389,9 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) } // Initialize controller to host mode -bool hcd_init(uint8_t rhport) -{ +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { TU_ASSERT(rhport == 0); - + (void) rh_init; fake_fnum = 0; // reset to get in a clean state. -- cgit v1.3.1 From 1d2735fb54b4ef9a154e10500e7d70e989f3bcc3 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 10 Nov 2024 12:33:20 +0100 Subject: FIx recurrent suspend ISR. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 5f86d6b76..f10f0bdc3 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -431,7 +431,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { #endif // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; + dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // TX FIFO empty level for interrupt is complete empty uint32_t gahbcfg = dwc2->gahbcfg; @@ -1032,16 +1032,19 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected dwc2->gintsts = GINTSTS_ENUMDNE; + dwc2->gintmsk |= GINTMSK_USBSUSPM; handle_enum_done(rhport); } if (gintsts & GINTSTS_USBSUSP) { dwc2->gintsts = GINTSTS_USBSUSP; + dwc2->gintmsk &= ~GINTMSK_USBSUSPM; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } if (gintsts & GINTSTS_WKUINT) { dwc2->gintsts = GINTSTS_WKUINT; + dwc2->gintmsk |= GINTMSK_USBSUSPM; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -1061,6 +1064,7 @@ void dcd_int_handler(uint8_t rhport) { if(gintsts & GINTSTS_SOF) { dwc2->gintsts = GINTSTS_SOF; + dwc2->gintmsk |= GINTMSK_USBSUSPM; const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos; // Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection -- cgit v1.3.1 From f14fcaa84d44855ac3718eb2a786114385b53657 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 10 Jul 2025 17:36:45 +0700 Subject: rename to tusb_deinit() to match other namingg --- src/tusb.c | 39 ++++++++++++++------------------------- src/tusb.h | 17 ++++------------- 2 files changed, 18 insertions(+), 38 deletions(-) (limited to 'src') diff --git a/src/tusb.c b/src/tusb.c index 5d366aeda..5a3ea356b 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -136,38 +136,27 @@ void tusb_int_handler(uint8_t rhport, bool in_isr) { #endif } -bool tusb_rhport_teardown(uint8_t rhport) { - // backward compatible call with tusb_init(void) - #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) - #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) - // deinit device stack, CFG_TUSB_RHPORTx_MODE must be defined - TU_ASSERT( tud_deinit(TUD_OPT_RHPORT) ); - _tusb_rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_INVALID; - #endif - - #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) - // deinit host stack CFG_TUSB_RHPORTx_MODE must be defined - TU_ASSERT( tuh_deinit(TUH_OPT_RHPORT) ); - _tusb_rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_INVALID; - #endif - - return true; - #endif - - // new API with explicit rhport and role - TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM); +bool tusb_deinit(uint8_t rhport) { + TU_VERIFY(rhport < TUP_USBIP_CONTROLLER_NUM); + bool ret = false; #if CFG_TUD_ENABLED - TU_ASSERT( tud_deinit(rhport) ); - _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + if (_tusb_rhport_role[rhport] == TUSB_ROLE_DEVICE) { + TU_ASSERT(tud_deinit(rhport)); + _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + ret = true; + } #endif #if CFG_TUH_ENABLED - TU_ASSERT( tuh_deinit(rhport) ); - _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + if (_tusb_rhport_role[rhport] == TUSB_ROLE_HOST) { + TU_ASSERT(tuh_deinit(rhport)); + _tusb_rhport_role[rhport] = TUSB_ROLE_INVALID; + ret = true; + } #endif - return true; + return ret; } //--------------------------------------------------------------------+ diff --git a/src/tusb.h b/src/tusb.h index 83f5993d0..e794a8b0b 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -140,7 +140,7 @@ bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Initialize roothub port with device/host role // Note: when using with RTOS, this should be called after scheduler/kernel is started. -// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. +// Since USB IRQ handler does use RTOS queue API. // Note2: defined as macro for backward compatible with tusb_init(void), can be changed to function in the future. #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) #define _tusb_init_arg0() tusb_rhport_init(0, NULL) @@ -158,24 +158,15 @@ bool tusb_inited(void); // Called to handle usb interrupt/event. tusb_init(rhport, role) must be called before void tusb_int_handler(uint8_t rhport, bool in_isr); -// Internal helper for backward compatibility with tusb_init(void) -bool tusb_rhport_teardown(uint8_t rhport); - -#if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) - #define _tusb_teardown_arg0() tusb_rhport_teardown(0) -#else - #define _tusb_teardown_arg0() TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined") -#endif - -#define _tusb_teardown_arg1(_rhport) tusb_rhport_teardown(_rhport) -#define tusb_teardown(...) TU_FUNC_OPTIONAL_ARG(_tusb_teardown, __VA_ARGS__) +// Deinit usb stack on roothub port +bool tusb_deinit(uint8_t rhport); #else #define tusb_init(...) (false) #define tusb_int_handler(...) do {}while(0) #define tusb_inited() (false) -#define tusb_teardown(...) (false) +#define tusb_deinit(...) (false) #endif -- cgit v1.3.1 From e9a78c52d00aa1cad8a9f80bbb2db5df70f1d8ad Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 11 Jul 2025 15:15:14 +0700 Subject: add tud_msc_inquiry2_cb() for full inquiry response --- examples/device/cdc_msc/src/msc_disk.c | 16 +++++---- examples/device/cdc_msc_freertos/src/msc_disk.c | 16 +++++---- .../device/dynamic_configuration/src/msc_disk.c | 17 ++++----- examples/device/msc_dual_lun/src/msc_disk_dual.c | 18 +++++----- src/class/msc/msc.h | 27 ++++++++++++--- src/class/msc/msc_device.c | 40 +++++++++++++--------- src/class/msc/msc_device.h | 7 +++- test/unit-test/test/device/msc/test_msc_device.c | 17 ++++----- 8 files changed, 100 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index 458681f58..6fd42dd80 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -116,18 +116,20 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = { README_CONTENTS }; -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { (void) lun; - const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id, vid, strlen(vid)); - memcpy(product_id, pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); + memcpy(inquiry_resp->vendor_id, vid, strlen(vid)); + memcpy(inquiry_resp->product_id, pid, strlen(pid)); + memcpy(inquiry_resp->product_rev, rev, strlen(rev)); + + return sizeof(scsi_inquiry_resp_t); // 36 bytes } // Invoked when received Test Unit Ready command. diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index d1ff2f71b..3a652103f 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -188,16 +188,20 @@ static void io_task(void *params) { void msc_disk_init() {} #endif -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { (void) lun; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id , vid, strlen(vid)); - memcpy(product_id , pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); + + memcpy(inquiry_resp->vendor_id, vid, strlen(vid)); + memcpy(inquiry_resp->product_id, pid, strlen(pid)); + memcpy(inquiry_resp->product_rev, rev, strlen(rev)); + + return sizeof(scsi_inquiry_resp_t); // 36 bytes } // Invoked when received Test Unit Ready command. diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index 10c3ac6fe..8987c06be 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -116,19 +116,20 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = README_CONTENTS }; -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) -{ +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { (void) lun; - const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id , vid, strlen(vid)); - memcpy(product_id , pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); + memcpy(inquiry_resp->vendor_id, vid, strlen(vid)); + memcpy(inquiry_resp->product_id, pid, strlen(pid)); + memcpy(inquiry_resp->product_rev, rev, strlen(rev)); + + return sizeof(scsi_inquiry_resp_t); // 36 bytes } // Invoked when received Test Unit Ready command. diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index 1f7fb98c7..a1ad220b3 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -207,18 +207,20 @@ uint8_t tud_msc_get_maxlun_cb(void) { return 2; // dual LUN } -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { - (void) lun; // use same ID for both LUNs - +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { + (void) lun; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id , vid, strlen(vid)); - memcpy(product_id , pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); + memcpy(inquiry_resp->vendor_id, vid, strlen(vid)); + memcpy(inquiry_resp->product_id, pid, strlen(pid)); + memcpy(inquiry_resp->product_rev, rev, strlen(rev)); + + return sizeof(scsi_inquiry_resp_t); // 36 bytes } // Invoked when received Test Unit Ready command. diff --git a/src/class/msc/msc.h b/src/class/msc/msc.h index bbfd35a43..b2b44eac4 100644 --- a/src/class/msc/msc.h +++ b/src/class/msc/msc.h @@ -108,8 +108,7 @@ TU_VERIFY_STATIC(sizeof(msc_csw_t) == 13, "size is not correct"); //--------------------------------------------------------------------+ /// SCSI Command Operation Code -typedef enum -{ +typedef enum { SCSI_CMD_TEST_UNIT_READY = 0x00, ///< The SCSI Test Unit Ready command is used to determine if a device is ready to transfer data (read/write), i.e. if a disk has spun up, if a tape is loaded and ready etc. The device does not perform a self-test operation. SCSI_CMD_INQUIRY = 0x12, ///< The SCSI Inquiry command is used to obtain basic information from a target device. SCSI_CMD_MODE_SELECT_6 = 0x15, ///< provides a means for the application client to specify medium, logical unit, or peripheral device parameters to the device server. Device servers that implement the MODE SELECT(6) command shall also implement the MODE SENSE(6) command. Application clients should issue MODE SENSE(6) prior to each MODE SELECT(6) to determine supported mode pages, page lengths, and other parameters. @@ -124,8 +123,7 @@ typedef enum }scsi_cmd_type_t; /// SCSI Sense Key -typedef enum -{ +typedef enum { SCSI_SENSE_NONE = 0x00, ///< no specific Sense Key. This would be the case for a successful command SCSI_SENSE_RECOVERED_ERROR = 0x01, ///< Indicates the last command completed successfully with some recovery action performed by the disc drive. SCSI_SENSE_NOT_READY = 0x02, ///< Indicates the logical unit addressed cannot be accessed. @@ -141,6 +139,27 @@ typedef enum SCSI_SENSE_MISCOMPARE = 0x0e ///< Indicates that the source data did not match the data read from the medium. }scsi_sense_key_type_t; + +typedef enum { + SCSI_PDT_DIRECT_ACCESS = 0x0, + SCSI_PDT_SEQUENTIAL_ACCESS = 0x1, + SCSI_PDT_PRINTER = 0x2, + SCSI_PDT_PROCESSOR = 0x3, + SCSI_PDT_WRITE_ONCE = 0x4, + SCSI_PDT_CD_DVD = 0x5, + SCSI_PDT_SCANNER = 0x6, + SCSI_PDT_OPTICAL_DEVICE = 0x7, + SCSI_PDT_MEDIUM_CHANGER = 0x8, + SCSI_PDT_COMMUNICATIONS = 0x9, // obsolete + SCSI_PDT_RAID = 0x0c, + SCSI_PDT_ENCLOSURE_SERVICES = 0x0d, + SCSI_PDT_SIMPLIFIED_DIRECT_ACCESS = 0x0e, + SCSI_PDT_OPTICAL_CARD_READER = 0x0f, + SCSI_PDT_BRIDGE = 0x10, ///< Bridge device, e.g. USB to SCSI bridge + SCSI_PDT_OBJECT_BASED_STORAGE = 0x11, ///< Object-based storage device + SCSI_PDT_AUTOMATION_DRIVE_INTERFACE = 0x12, ///< Automation/Drive Interface (ADI) device +} scsi_peripheral_device_type_t; + //--------------------------------------------------------------------+ // SCSI Primary Command (SPC-4) //--------------------------------------------------------------------+ diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 747ad03ed..3a4b34e7e 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -41,6 +41,17 @@ #define TU_LOG_DRV(...) TU_LOG(CFG_TUD_MSC_LOG_LEVEL, __VA_ARGS__) +//--------------------------------------------------------------------+ +// Weak stubs: invoked if no strong implementation is available +//--------------------------------------------------------------------+ +TU_ATTR_WEAK void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { + (void) lun; (void) vendor_id; (void) product_id; (void) product_rev; +} +TU_ATTR_WEAK uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { + (void) lun; (void) inquiry_resp; + return 0; +} + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -731,22 +742,19 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ break; case SCSI_CMD_INQUIRY: { - scsi_inquiry_resp_t inquiry_rsp = { - .is_removable = 1, - .version = 2, - .response_data_format = 2, - .additional_length = sizeof(scsi_inquiry_resp_t) - 5, - }; - - // vendor_id, product_id, product_rev is space padded string - memset(inquiry_rsp.vendor_id , ' ', sizeof(inquiry_rsp.vendor_id)); - memset(inquiry_rsp.product_id , ' ', sizeof(inquiry_rsp.product_id)); - memset(inquiry_rsp.product_rev, ' ', sizeof(inquiry_rsp.product_rev)); - - tud_msc_inquiry_cb(lun, inquiry_rsp.vendor_id, inquiry_rsp.product_id, inquiry_rsp.product_rev); - - resplen = sizeof(inquiry_rsp); - TU_VERIFY(0 == tu_memcpy_s(buffer, bufsize, &inquiry_rsp, (size_t) resplen)); + scsi_inquiry_resp_t *inquiry_rsp = (scsi_inquiry_resp_t *) buffer; + tu_memclr(inquiry_rsp, sizeof(scsi_inquiry_resp_t)); + inquiry_rsp->is_removable = 1; + inquiry_rsp->version = 2; + inquiry_rsp->response_data_format = 2; + inquiry_rsp->additional_length = sizeof(scsi_inquiry_resp_t) - 5; + + resplen = (int32_t) tud_msc_inquiry2_cb(lun, inquiry_rsp); + if (resplen == 0) { + // stub callback with no response, use v1 callback + tud_msc_inquiry_cb(lun, inquiry_rsp->vendor_id, inquiry_rsp->product_id, inquiry_rsp->product_rev); + resplen = sizeof(scsi_inquiry_resp_t); + } } break; diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index f2ea256b4..195c6fa87 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -90,10 +90,15 @@ bool tud_msc_async_io_done(int32_t bytes_io, bool in_isr); int32_t tud_msc_read10_cb (uint8_t lun, uint32_t lba, uint32_t offset, void* buffer, uint32_t bufsize); int32_t tud_msc_write10_cb (uint8_t lun, uint32_t lba, uint32_t offset, uint8_t* buffer, uint32_t bufsize); -// Invoked when received SCSI_CMD_INQUIRY +// Invoked when received SCSI_CMD_INQUIRY, v1, application should use v2 if possible // Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]); +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp); + // Invoked when received Test Unit Ready command. // return true allowing host to read/write this LUN e.g SD card inserted bool tud_msc_test_unit_ready_cb(uint8_t lun); diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 3ab46b0f9..e05e9c8b0 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -94,19 +94,20 @@ enum uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE]; -// Invoked when received SCSI_CMD_INQUIRY -// Application fill vendor id, product id and revision with string up to 8, 16, 4 characters respectively -void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) -{ +// Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response +// Some inquiry_resp's fields are already filled with default values, application can update them +// Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { (void) lun; - const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; - memcpy(vendor_id , vid, strlen(vid)); - memcpy(product_id , pid, strlen(pid)); - memcpy(product_rev, rev, strlen(rev)); + memcpy(inquiry_resp->vendor_id, vid, strlen(vid)); + memcpy(inquiry_resp->product_id, pid, strlen(pid)); + memcpy(inquiry_resp->product_rev, rev, strlen(rev)); + + return sizeof(scsi_inquiry_resp_t); // 36 bytes } // Invoked when received Test Unit Ready command. -- cgit v1.3.1 From 48327625904b280295ded0af496b4f388c903646 Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Fri, 11 Jul 2025 17:48:10 +0200 Subject: typo fix Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- src/class/usbtmc/usbtmc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index b79c3369c..544da16b5 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -45,7 +45,7 @@ */ //Limitations: -// "vendor-specific" commands are handled similar to normal massages, except that the MsgID is changed to "vendor-specific". +// "vendor-specific" commands are handled similar to normal messages, except that the MsgID is changed to "vendor-specific". // Dealing with "termchar" must be handled by the application layer, // though additional error checking is does in this module. // talkOnly and listenOnly are NOT supported. They're not permitted -- cgit v1.3.1 From a365cf6e3cb13cd615f169053360385b165ca706 Mon Sep 17 00:00:00 2001 From: Zixun LI Date: Fri, 11 Jul 2025 17:56:56 +0200 Subject: fix last transfer size Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- src/class/usbtmc/usbtmc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 544da16b5..fb93388ca 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -562,7 +562,7 @@ bool usbtmcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint { size_t packetLen = usbtmc_state.transfer_size_remaining; memcpy(usbtmc_epbuf.epin, usbtmc_state.devInBuffer, usbtmc_state.transfer_size_remaining); - usbtmc_state.transfer_size_sent += sizeof(usbtmc_state.transfer_size_remaining); + usbtmc_state.transfer_size_sent += packetLen; usbtmc_state.transfer_size_remaining = 0; usbtmc_state.devInBuffer = NULL; TU_VERIFY(usbd_edpt_xfer(rhport, usbtmc_state.ep_bulk_in, usbtmc_epbuf.epin, (uint16_t) packetLen)); -- cgit v1.3.1 From 18626857f045e6ae6aab6e3b49e192374645cf08 Mon Sep 17 00:00:00 2001 From: Eli Lipsitz Date: Tue, 15 Jul 2025 21:55:06 -0400 Subject: Fix compilation when CH34X support is disabled --- src/class/cdc/cdc_host.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index f4567fac4..f9a37ed35 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -833,8 +833,11 @@ static bool set_line_state_on_enum(cdch_interface_t *p_cdc, tuh_xfer_t *xfer) { switch (state) { case ENUM_SET_LINE_CODING: { #ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM + #if CFG_TUH_CDC_CH34X // ch34x already set line coding in serial init - if (p_cdc->serial_drid != SERIAL_DRIVER_CH34X) { + if (p_cdc->serial_drid != SERIAL_DRIVER_CH34X) + #endif + { const cdc_line_coding_t line_coding = (cdc_line_coding_t) CFG_TUH_CDC_LINE_CODING_ON_ENUM; TU_ASSERT(tuh_cdc_set_line_coding(idx, &line_coding, cdch_process_line_state_on_enum, ENUM_SET_LINE_CONTROL)); -- cgit v1.3.1 From 673a916cd0193ff869ca7385f02b699f771ceb06 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Sat, 5 Jul 2025 16:52:09 -0700 Subject: Fix #3159: Handle MIDI interface descriptor after audio streaming interface --- src/class/midi/midi_host.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index cd6e115ee..77bacf24c 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -197,7 +197,6 @@ bool midih_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint //--------------------------------------------------------------------+ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { (void) rhport; - TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); const uint8_t *p_end = ((const uint8_t *) desc_itf) + max_len; const uint8_t *p_desc = (const uint8_t *) desc_itf; @@ -211,7 +210,15 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d desc_cb.jack_num = 0; // There can be just a MIDI or an Audio + MIDI interface - // If there is Audio Control Interface + Audio Header descriptor, skip it + // If there is Audio Control Interface + Audio Header descriptor, then skip it. + // If there is an Audio Control Interface + Audio Streaming Interface, then + // ignore the Audio Streaming Interface. + // Future: + // Note that if this driver is used with an USB Audio Streaming host driver, + // then call that driver first. If the MIDI interface comes before the + // audio streaming interface, then the audio driver will have to call this + // driver after parsing the audio control interface and then resume parsing + // the streaming audio interface. if (AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass) { TU_VERIFY(max_len > 2*sizeof(tusb_desc_interface_t) + sizeof(audio_desc_cs_ac_interface_t)); @@ -222,12 +229,21 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d p_desc = tu_desc_next(p_desc); desc_itf = (const tusb_desc_interface_t *)p_desc; - TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); p_midi->itf_count = 1; - } + // See issue #3159 + while ((p_desc < p_end) && (tu_desc_next(p_desc) <= p_end) && (desc_itf->bDescriptorType != TUSB_DESC_INTERFACE || (desc_itf->bInterfaceClass == TUSB_CLASS_AUDIO && desc_itf->bInterfaceSubClass != AUDIO_SUBCLASS_MIDI_STREAMING))) + { + if (desc_itf->bDescriptorType == TUSB_DESC_INTERFACE && desc_itf->bAlternateSetting == 0) { + p_midi->itf_count++; + } + p_desc = tu_desc_next(p_desc); + desc_itf = (tusb_desc_interface_t const *)p_desc; + } + TU_VERIFY(p_desc < p_end); // If MIDI interface comes after Audio Streaming, then max_len did not include the MIDI interface descriptor + TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); +} TU_VERIFY(AUDIO_SUBCLASS_MIDI_STREAMING == desc_itf->bInterfaceSubClass); - - TU_LOG_DRV("MIDI opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr); + p_midi->bInterfaceNumber = desc_itf->bInterfaceNumber; p_midi->iInterface = desc_itf->iInterface; p_midi->itf_count++; @@ -236,6 +252,7 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d p_desc = tu_desc_next(p_desc); // next to CS Header bool found_new_interface = false; + printf("%p %p %p\r\n", p_desc, tu_desc_next(p_desc), p_end); while ((p_desc < p_end) && (tu_desc_next(p_desc) <= p_end) && !found_new_interface) { switch (tu_desc_type(p_desc)) { case TUSB_DESC_INTERFACE: -- cgit v1.3.1 From 0d080ca7bac9d3ed1c0f080c111e0530284e2ee9 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Tue, 22 Jul 2025 16:52:47 -0700 Subject: Delete debugging printf --- src/class/midi/midi_host.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 77bacf24c..1ac24eb05 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -252,7 +252,6 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d p_desc = tu_desc_next(p_desc); // next to CS Header bool found_new_interface = false; - printf("%p %p %p\r\n", p_desc, tu_desc_next(p_desc), p_end); while ((p_desc < p_end) && (tu_desc_next(p_desc) <= p_end) && !found_new_interface) { switch (tu_desc_type(p_desc)) { case TUSB_DESC_INTERFACE: -- cgit v1.3.1 From 9030fe43fae06b52a0d88584aaff156c8c0cb7b8 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Wed, 23 Jul 2025 06:46:24 -0700 Subject: Restore accidentally erased debug log message --- src/class/midi/midi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 1ac24eb05..2395a0ef8 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -243,7 +243,7 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); } TU_VERIFY(AUDIO_SUBCLASS_MIDI_STREAMING == desc_itf->bInterfaceSubClass); - + TU_LOG_DRV("MIDI opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr); p_midi->bInterfaceNumber = desc_itf->bInterfaceNumber; p_midi->iInterface = desc_itf->iInterface; p_midi->itf_count++; -- cgit v1.3.1 From be114549c4f2203d1d29458ead29cd1dea656950 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Sat, 26 Jul 2025 19:01:02 +0700 Subject: Update src/class/usbtmc/usbtmc_device.c Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- src/class/usbtmc/usbtmc_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index fb93388ca..7ec939b64 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -165,7 +165,7 @@ tu_static uint8_t termChar; tu_static uint8_t termCharRequested = false; -tu_static uint8_t usbtmcVendorSpecificRequested = false; +tu_static bool usbtmcVendorSpecificRequested = false; #if OSAL_MUTEX_REQUIRED static OSAL_MUTEX_DEF(usbtmcLockBuffer); -- cgit v1.3.1 From 3682b6c6631c63f1dac2096787c0f983ac77e734 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Jul 2025 22:28:22 +0700 Subject: fix pre-commit, remove svd file since they are heavy and should be in mcu/sdk instead add cmake support for f403a_407 and f423 --- .../at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f402_405/at32f402_405_clock.c | 2 +- hw/bsp/at32f402_405/at32f402_405_clock.h | 1 - hw/bsp/at32f402_405/at32f402_405_int.c | 1 - hw/bsp/at32f402_405/at32f402_405_int.h | 1 - .../boards/AT_START_F402_405/AT32F405xC_FLASH.ld | 4 +- .../boards/AT_START_F402_405/AT32F405xx_v2.svd | 45983 --------------- .../at32f402_405/boards/AT_START_F402_405/board.h | 2 +- hw/bsp/at32f402_405/family.c | 23 +- hw/bsp/at32f402_405/family.mk | 1 - hw/bsp/at32f402_405/startup_at32f402_405.s | 30 +- .../at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f403a_407/at32f403a_407_clock.c | 2 +- hw/bsp/at32f403a_407/at32f403a_407_clock.h | 1 - hw/bsp/at32f403a_407/at32f403a_407_conf.h | 6 +- hw/bsp/at32f403a_407/at32f403a_407_int.h | 1 - .../boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld | 4 +- .../boards/AT_START_F403A_407/AT32F407xx_v2.svd | 28047 --------- .../boards/AT_START_F403A_407/board.cmake | 9 + .../boards/AT_START_F403A_407/board.mk | 1 + hw/bsp/at32f403a_407/family.c | 110 +- hw/bsp/at32f403a_407/family.cmake | 102 + hw/bsp/at32f403a_407/family.mk | 3 +- hw/bsp/at32f403a_407/startup_at32f403a_407.s | 2 +- hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f413/at32f413_clock.h | 1 - hw/bsp/at32f413/at32f413_int.c | 2 - hw/bsp/at32f413/at32f413_int.h | 1 - .../boards/AT_START_F413/AT32F413xC_FLASH.ld | 6 +- .../boards/AT_START_F413/AT32F413xx_v2.svd | 23368 -------- hw/bsp/at32f413/boards/AT_START_F413/board.h | 2 +- hw/bsp/at32f413/family.c | 12 +- hw/bsp/at32f413/family.mk | 1 - hw/bsp/at32f413/startup_at32f413.s | 2 +- hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f415/at32f415_clock.c | 14 +- hw/bsp/at32f415/at32f415_clock.h | 11 +- hw/bsp/at32f415/at32f415_conf.h | 12 +- hw/bsp/at32f415/at32f415_int.c | 22 +- hw/bsp/at32f415/at32f415_int.h | 11 +- .../boards/AT_START_F415/AT32F415xC_FLASH.ld | 4 +- .../boards/AT_START_F415/AT32F415xx_v2.svd | 27108 --------- hw/bsp/at32f415/family.c | 28 +- hw/bsp/at32f415/family.mk | 1 - hw/bsp/at32f415/startup_at32f415.s | 2 +- hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f423/at32f423_clock.c | 1 - hw/bsp/at32f423/at32f423_clock.h | 1 - hw/bsp/at32f423/at32f423_int.c | 1 - hw/bsp/at32f423/at32f423_int.h | 1 - .../boards/AT_START_F423/AT32F423xC_FLASH.ld | 4 +- .../boards/AT_START_F423/AT32F423xx_v2.svd | 36050 ------------ hw/bsp/at32f423/boards/AT_START_F423/board.cmake | 9 + hw/bsp/at32f423/boards/AT_START_F423/board.mk | 1 + hw/bsp/at32f423/family.c | 167 +- hw/bsp/at32f423/family.cmake | 104 + hw/bsp/at32f423/family.mk | 6 +- hw/bsp/at32f423/startup_at32f423.s | 2 +- hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f425/at32f425_clock.h | 1 - hw/bsp/at32f425/at32f425_int.c | 1 - hw/bsp/at32f425/at32f425_int.h | 1 - .../boards/AT_START_F425/AT32F425x8_FLASH.ld | 4 +- .../boards/AT_START_F425/AT32F425xx_v2.svd | 30790 ---------- hw/bsp/at32f425/family.c | 28 +- hw/bsp/at32f425/family.mk | 1 - hw/bsp/at32f425/startup_at32f425.s | 2 +- .../at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- hw/bsp/at32f435_437/at32f435_437_clock.h | 1 - hw/bsp/at32f435_437/at32f435_437_int.c | 1 - hw/bsp/at32f435_437/at32f435_437_int.h | 1 - .../boards/AT_START_F435_437/AT32F437xM_FLASH.ld | 4 +- .../boards/AT_START_F435_437/AT32F437xx_v2.svd | 58291 ------------------- hw/bsp/at32f435_437/family.c | 26 +- hw/bsp/at32f435_437/family.mk | 1 - hw/bsp/at32f435_437/startup_at32f435_437.s | 2 +- src/portable/synopsys/dwc2/dwc2_at32.h | 6 +- 77 files changed, 497 insertions(+), 249969 deletions(-) delete mode 100644 hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd delete mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd create mode 100644 hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake create mode 100644 hw/bsp/at32f403a_407/family.cmake delete mode 100644 hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd delete mode 100644 hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd delete mode 100644 hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd create mode 100644 hw/bsp/at32f423/boards/AT_START_F423/board.cmake create mode 100644 hw/bsp/at32f423/family.cmake delete mode 100644 hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd delete mode 100644 hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd (limited to 'src') diff --git a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h index d86c92542..1f75a7cb0 100644 --- a/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f402_405/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f402_405/at32f402_405_clock.c b/hw/bsp/at32f402_405/at32f402_405_clock.c index a74cd78ca..d9a1b5eef 100644 --- a/hw/bsp/at32f402_405/at32f402_405_clock.c +++ b/hw/bsp/at32f402_405/at32f402_405_clock.c @@ -121,7 +121,7 @@ void system_clock_config(void) #endif #ifdef AT32F402xx - /* reduce power comsumption */ + /* reduce power consumption */ reduce_power_consumption(); #endif } diff --git a/hw/bsp/at32f402_405/at32f402_405_clock.h b/hw/bsp/at32f402_405/at32f402_405_clock.h index b098f3718..30f5ae45d 100644 --- a/hw/bsp/at32f402_405/at32f402_405_clock.h +++ b/hw/bsp/at32f402_405/at32f402_405_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f402_405/at32f402_405_int.c b/hw/bsp/at32f402_405/at32f402_405_int.c index 924431ee2..7f2fb6fa7 100644 --- a/hw/bsp/at32f402_405/at32f402_405_int.c +++ b/hw/bsp/at32f402_405/at32f402_405_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f402_405/at32f402_405_int.h b/hw/bsp/at32f402_405/at32f402_405_int.h index f83964feb..207a7d6df 100644 --- a/hw/bsp/at32f402_405/at32f402_405_int.h +++ b/hw/bsp/at32f402_405/at32f402_405_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld index 26a1ecddb..0b3550ddb 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd b/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd deleted file mode 100644 index 94a12b0f4..000000000 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/AT32F405xx_v2.svd +++ /dev/null @@ -1,45983 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F405xx_v2 - AT32F405 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 168MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - SWPEN6 - Standby wake-up pin 6 enable - 13 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000012 - - - LDOOVSEL - LDO output voltage select - 0 - 2 - read-write - - - VREXLPEN - Voltage regulator extra low power mode enable - 4 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - PLLUSTBL - PLLU clock ready flag - 26 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FP - PLLP post-division - 16 - 4 - read-write - - - PLL_FU - PLLU post-division - 20 - 3 - read-write - - - PLLU_EN - PLLU enable - 29 - 1 - read-write - - - PLLRCS - PLL reference clock select - 30 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - I2S5CLKSEL - I2S clock select - 22 - 2 - read-write - - - CLKOUTDIV1 - Clock output division1 - 27 - 3 - read-write - - - CLKOUT_SEL1 - Clock output selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - OTGHSRST - OTGHS interface reset - 29 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - QSPI1RST - QSPI1 reset - 1 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - USART4RST - USART4 reset - 19 - 1 - - - USART5RST - USART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - UART7RST - UART7 reset - 30 - 1 - - - UART8RST - UART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - I2S5RST - I2S5 reset - 20 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - OTGHSPHYRST - OTGHS phy reset - 31 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - OTGHSEN - OTGHS clock enable - 29 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - QSPI1EN - QSPI1 clock enable - 1 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - USART5EN - USART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - UART7EN - UART7 clock enable - 30 - 1 - - - UART8EN - UART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADC1EN - ADC1 clock enable - 8 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - I2S5EN - I2S5 clock enable - 20 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAMLPEN - SRAM clock enable during sleep mode - 16 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - OTGHSLPEN - OTGHS clock enable during sleep mode - 29 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - QSPI1LPEN - QSPI1 clock enable during sleep mode - 1 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - USART4LPEN - USART4 clock enable during sleep mode - 19 - 1 - - - USART5LPEN - USART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - UART7LPEN - UART7 clock enable during sleep mode - 30 - 1 - - - UART8LPEN - UART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - I2S5LPEN - I2S5 clock enable during sleep mode - 20 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - OTGHSPHYLPEN - OTGHS phy clock enable during sleep mode - 31 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - OTGHS - OTGHS - OTGHS register - 0x78 - 0x20 - 0x00000000 - - - XTLSEL - PHY clock source select - 0 - 1 - read-write - - - USBHS_PHY12_SEL - USBHS phy12 select value - 3 - 2 - read-write - - - USBHS_PHY30_SEL - USBHS phy12 select value - 8 - 2 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - CLKOUT_SEL2 - Clock output select2 - 16 - 4 - read-write - - - CLKOUTDIV2 - Clock output division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - PLLU_USB48_SEL - USB clock source select - 10 - 1 - read-write - - - HICK_TO_SCLK_DIV - HICK as system clock frequency division - 16 - 3 - read-write - - - HEXT_TO_SCLK_DIV - HEXT as system clock frequency division - 19 - 3 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - TOGR - TOGR - GPIO bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - IOTB0 - toggle bit 0 - 0 - 1 - - - IOTB1 - toggle bit 1 - 1 - 1 - - - IOTB2 - toggle bit 2 - 2 - 1 - - - IOTB3 - toggle bit 3 - 3 - 1 - - - IOTB4 - toggle bit 4 - 4 - 1 - - - IOTB5 - toggle bit 5 - 5 - 1 - - - IOTB6 - toggle bit 6 - 6 - 1 - - - IOTB7 - toggle bit 7 - 7 - 1 - - - IOTB8 - toggle bit 8 - 8 - 1 - - - IOTB9 - toggle bit 9 - 9 - 1 - - - IOTB10 - toggle bit 10 - 10 - 1 - - - IOTB11 - toggle bit 11 - 11 - 1 - - - IOTB12 - toggle bit 12 - 12 - 1 - - - IOTB13 - toggle bit 13 - 13 - 1 - - - IOTB14 - toggle bit 14 - 14 - 1 - - - IOTB15 - toggle bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOF - 0x40021400 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - OTGHS_WKUP - OTGHS_WKUP interrupt connect to EXINT line20 - 76 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40026000 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026400 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - RMP - RMP - TMR2 input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_IS1_IRMP - TMR2 internal selection 3 remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - - TMR14 - 0x40002000 - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - SOFSEL - SOF Select - read-write - 2 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - I2SF5 - Serial peripheral interface - SPI - 0x40015000 - - 0x0 - 0x400 - registers - - - I2SF5 - I2SF5 global interrupt - 85 - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SFDUPEN - I2S full duplex mode enable - 13 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - MISC1 - MISC1 - MISC1 register - 0x30 - 0x20 - read-write - 00000000 - - - I2SFPCMCKSEL - I2S PCM clock edge select - 0 - 1 - - - - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CMDF - Character match detection flag - 17 - 1 - read-write - - - RTODF - Reiceiver time out detection flag - 11 - 1 - read-write - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - RTODEN - Receiver time out detection enable - 27 - 1 - - - RETODIE - Receiver time out detection interrupt enable - 26 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - CMDIE - Character match detection interrupt enable - 14 - 1 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - IDH - bit 7-4 for usart identification - 28 - 4 - - - MTF - MSB transmit first - 19 - 1 - - - DTREV - DT register polarity reverse - 18 - 1 - - - TXREV - TX polarity reverse - 17 - 1 - - - RXREV - RX polarity reverse - 16 - 1 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - IDL - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - RTOV - RTOV - Receiver time out value register - 0x1C - 0x20 - read-write - 0x0000 - - - RTOV - Receiver time out value - 0 - 24 - - - - - IFC - IFC - Interruption flag clear register - 0x20 - 0x20 - read-write - 0x0000 - - - CMDFC - Character match detection flag clear - 17 - 1 - - - RTODFC - Receiver time out detection flag clear - 11 - 1 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART4 - 0x40004C00 - - USART4 - USART4 global interrupt - 52 - - - - USART5 - 0x40005000 - - USART5 - USART5 global interrupt - 53 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - - - - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - - 20 - 1 - - - OCTESEL - Low bit of trigger event select for ordinary channels conversion - - 17 - 3 - - - PCTEN - - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - ADCDIV - ADC division - 16 - 4 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTGFS_GLOBAL - USB on-the-go full speed - USB_OTGFS - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTGFS - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTGFS - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTGFS - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - USB_OTGHS_GLOBAL - USB on the go high speed - USB_OTGHS - 0x40040000 - - 0x0 - 0x400 - registers - - - OTGHS - USB On The Go HS global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGHS control and status register - (OTGHS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGHS interrupt register - (OTGHS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGHS AHB configuration register - (OTGHS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - HBSTLEN - Burst Length - 1 - 4 - - - DMAEN - DMA Enable - 5 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGHS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - HS timeout calibration - 0 - 3 - read-write - - - PHYIF - PHY Interface - 3 - 1 - read-write - - - PHYSEL - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial - Transceiver Select - 6 - 1 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGHS reset register - (OTGHS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - DMAREQ - DMA Request Signal - 30 - 1 - read-only - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGHS core interrupt register - (OTGHS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTGHS interrupt mask register - (OTGHS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGHS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGHS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGHS Receive FIFO size register - (OTGHS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGHS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGHS non-periodic transmit FIFO/queue - status register (OTGHS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGHS general core configuration register - (OTGHS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - WAIT_CLK_RCV - Wait Clock Soure Recover - 22 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGHS Host periodic transmit FIFO size - register (OTGHS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGHS device IN endpoint transmit FIFO size - register (OTGHS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTGHS_HOST - USB on the go high speed - USB_OTGHS - 0x40040400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGHS host configuration register - (OTGHS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGHS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGHS host frame number/frame time - remaining register (OTGHS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGHS_Host periodic transmit FIFO/queue - status register (OTGHS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-only - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGHS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGHS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGHS host port control and status register - (OTGHS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGHS host channel-0 characteristics - register (OTGHS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGHS host channel-1 characteristics - register (OTGHS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGHS host channel-2 characteristics - register (OTGHS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGHS host channel-3 characteristics - register (OTGHS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGHS host channel-4 characteristics - register (OTGHS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGHS host channel-5 characteristics - register (OTGHS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGHS host channel-6 characteristics - register (OTGHS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGHS host channel-7 characteristics - register (OTGHS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGHS host channel-8 characteristics - register (OTGHS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGHS host channel-9 characteristics - register (OTGHS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGHS host channel-10 characteristics - register (OTGHS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGHS host channel-7 characteristics - register (OTGHS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGHS host channel-12 characteristics - register (OTGHS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGHS host channel-13 characteristics - register (OTGHS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGHS host channel-14 characteristics - register (OTGHS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGHS host channel-15 characteristics - register (OTGHS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCSPLT0 - HCSPLT0 - Host Channel 0 Split Control Register - 0x104 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT1 - HCSPLT1 - Host Channel 1 Split Control Register - 0x124 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT2 - HCSPLT2 - Host Channel 2 Split Control Register - 0x144 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT3 - HCSPLT3 - Host Channel 3 Split Control Register - 0x164 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT4 - HCSPLT4 - Host Channel 1 Split Control Register - 0x184 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT5 - HCSPLT5 - Host Channel 5 Split Control Register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT6 - HCSPLT6 - Host Channel 6 Split Control Register - 0x1C4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT7 - HCSPLT7 - Host Channel 7 Split Control Register - 0x1E4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT8 - HCSPLT8 - Host Channel 8 Split Control Register - 0x204 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT9 - HCSPLT9 - Host Channel 9 Split Control Register - 0x224 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT10 - HCSPLT10 - Host Channel 10 Split Control Register - 0x244 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT11 - HCSPLT11 - Host Channel 11 Split Control Register - 0x264 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT12 - HCSPLT12 - Host Channel 12 Split Control Register - 0x284 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT13 - HCSPLT13 - Host Channel 13 Split Control Register - 0x2A4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT14 - HCSPLT14 - Host Channel 14 Split Control Register - 0x2C4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCSPLT15 - HCSPLT15 - Host Channel 15 Split Control Register - 0x2E4 - 0x20 - read-write - 0x00000000 - - - PRTADDR - Port Address - 0 - 7 - - - HUBADDR - Hub Address - 7 - 7 - - - XACTPOS - Transaction Position - 14 - 2 - - - COMPSPLT - Do Complete Split - 16 - 1 - - - SPLTENA - Split Enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGHS host channel-0 interrupt register - (OTGHS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTGHS host channel-1 interrupt register - (OTGHS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGHS host channel-2 interrupt register - (OTGHS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGHS host channel-3 interrupt register - (OTGHS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGHS host channel-4 interrupt register - (OTGHS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGHS host channel-5 interrupt register - (OTGHS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGHS host channel-6 interrupt register - (OTGHS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGHS host channel-7 interrupt register - (OTGHS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGHS host channel-8 interrupt register - (OTGHS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGHS host channel-9 interrupt register - (OTGHS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGHS host channel-10 interrupt register - (OTGHS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGHS host channel-11 interrupt register - (OTGHS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGHS host channel-12 interrupt register - (OTGHS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGHS host channel-13 interrupt register - (OTGHS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGHS host channel-14 interrupt register - (OTGHS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGHS host channel-15 interrupt register - (OTGHS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - AHBERR - AHB Error - 2 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - NYET - NYET Response Received - interrupt - 6 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGHS host channel-0 mask register - (OTGHS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGHS host channel-1 mask register - (OTGHS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGHS host channel-2 mask register - (OTGHS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGHS host channel-3 mask register - (OTGHS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGHS host channel-4 mask register - (OTGHS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGHS host channel-5 mask register - (OTGHS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGHS host channel-6 mask register - (OTGHS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGHS host channel-7 mask register - (OTGHS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGHS host channel-8 mask register - (OTGHS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGHS host channel-9 mask register - (OTGHS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGHS host channel-10 mask register - (OTGHS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGHS host channel-11 mask register - (OTGHS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGHS host channel-12 mask register - (OTGHS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGHS host channel-13 mask register - (OTGHS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGHS host channel-14 mask register - (OTGHS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGHS host channel-15 mask register - (OTGHS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - AHBERRMSK - AHB Error Mask - 2 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - NYETMSK - NYET Response Received - interrupt mask - 6 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGHS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ1 - HCTSIZ1 - OTGHS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ2 - HCTSIZ2 - OTGHS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ3 - HCTSIZ3 - OTGHS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ4 - HCTSIZ4 - OTGHS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ5 - HCTSIZ5 - OTGHS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ6 - HCTSIZ6 - OTGHS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ7 - HCTSIZ7 - OTGHS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ8 - HCTSIZ8 - OTGHS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ9 - HCTSIZ9 - OTGHS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ10 - HCTSIZ10 - OTGHS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ11 - HCTSIZ11 - OTGHS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ12 - HCTSIZ12 - OTGHS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ13 - HCTSIZ13 - OTGHS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ14 - HCTSIZ14 - OTGHS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCTSIZ15 - HCTSIZ15 - OTGHS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - DOPNG - Do Ping - 31 - 1 - - - - - HCDMA0 - HCDMA0 - Host channel 0 DMA address - register - 0x114 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA1 - HCDMA1 - Host channel 1 DMA address - register - 0x134 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA2 - HCDMA2 - Host channel 2 DMA address - register - 0x154 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA3 - HCDMA3 - Host channel 3 DMA address - register - 0x174 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA4 - HCDMA4 - Host channel 4 DMA address - register - 0x194 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA5 - HCDMA5 - Host channel 5 DMA address - register - 0x1B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA6 - HCDMA6 - Host channel 6 DMA address - register - 0x1D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA7 - HCDMA7 - Host channel 7 DMA address - register - 0x1F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA8 - HCDMA8 - Host channel 8 DMA address - register - 0x214 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA9 - HCDMA9 - Host channel 9 DMA address - register - 0x234 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA10 - HCDMA10 - Host channel 10 DMA address - register - 0x254 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA11 - HCDMA11 - Host channel 11 DMA address - register - 0x274 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA12 - HCDMA12 - Host channel 12 DMA address - register - 0x294 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA13 - HCDMA13 - Host channel 13 DMA address - register - 0x2B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA14 - HCDMA14 - Host channel 14 DMA address - register - 0x2D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - HCDMA15 - HCDMA15 - Host channel 15 DMA address - register - 0x2F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - - - USB_OTGHS_DEVICE - USB on the go high speed - USB_OTGHS - 0x40040800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGHS device configuration register - (OTGHS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGHS device control register - (OTGHS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - DEVLNSTS - Device Line Status - 22 - 2 - - - - - DIEPMSK - DIEPMSK - OTGHS device IN endpoint common interrupt - mask register (OTGHS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - - - DOEPMSK - DOEPMSK - OTGHS device OUT endpoint common interrupt - mask register (OTGHS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - STSPHSERCVDMSK - Status Phase Received - mask - 5 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - BBLEERRMSK - Babble Error interrupt - mask - 12 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - NYETMSK - NYET interrupt - mask - 14 - 1 - - - - - DAINT - DAINT - OTGHS device all endpoints interrupt - register (OTGHS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGHS all endpoints interrupt mask register - (OTGHS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGHS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DEACHINT - DEACHINT - ODevice Each Endpoints - Interrupt Register - 0x38 - 0x20 - read-write - 0x00000000 - - - ECHINEPINT - Each IN Endpoint Interrupt - bits - 0 - 16 - - - ECHOUTEPINT - Each OUT Endpoint Interrupt - bits - 16 - 16 - - - - - DEACHINTMSK - DEACHINTMSK - Device Each Endpoints - Interrupt Mask Register - 0x3C - 0x20 - read-write - 0x00000000 - - - ECHINEPINTMSK - Each IN Endpoint Interrupt Mask - bits - 0 - 16 - - - ECHOUTEPINTMSK - Each OUT Endpoint Interrupt Mask - bits - 16 - 16 - - - - - DIEPEACHMSK1 - DIEPEACHMSK1 - Device Each IN Endpoint 1 Interrupt Register - 0x44 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - - - DOEPEACHMSK1 - DOEPEACHMSK1 - Device Each OUT Endpoint 1 Interrupt Register - 0x84 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - AHBERRMSK - AHB Error - mask - 2 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - STSPHSERCVDMSK - Status Phase Received - mask - 5 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - BBLEERRMSK - Babble Error interrupt - mask - 12 - 1 - - - NAKMSK - NAK interrupt - mask - 13 - 1 - - - NYETMSK - NYET interrupt - mask - 14 - 1 - - - - - DIEPCTL0 - DIEPCTL0 - OTGHS device control IN endpoint 0 control - register (OTGHS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL1 - DIEPCTL1 - OTGHS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGHS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGHS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGHS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGHS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGHS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGHS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGHS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGHS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGHS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGHS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGHS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGHS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGHS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGHS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGHS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT1 - DIEPINT1 - OTGHS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT2 - DIEPINT2 - OTGHS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT3 - DIEPINT3 - OTGHS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT4 - DIEPINT4 - OTGHS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT5 - DIEPINT5 - OTGHS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT6 - DIEPINT6 - OTGHS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DIEPINT7 - DIEPINT7 - OTGHS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - AHBERR - AHB Error - interrupt - 2 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - TXFIFOUNDRN - Fifo Underrun - 8 - 1 - read-write - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - - - DOEPINT0 - DOEPINT0 - OTGHS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT1 - DOEPINT1 - OTGHS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT2 - DOEPINT2 - OTGHS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT3 - DOEPINT3 - OTGHS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT4 - DOEPINT4 - OTGHS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT5 - DOEPINT5 - OTGHS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT6 - DOEPINT6 - OTGHS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DOEPINT7 - DOEPINT7 - OTGHS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - OUTPKTERR - OUT Packet Error - 8 - 1 - - - BNAINTR - Buffer Not Available Error - 9 - 1 - - - PKTDRPSTS - Packet Drop Status - 11 - 1 - read-write - - - BBLEERR - BBLE error - 12 - 1 - read-write - - - NAKINTPT - NAK interrupt - 13 - 1 - read-write - - - NYETINTPT - NYET interrupt - 14 - 1 - read-write - - - STUPPKTRCVD - Setup Packet Received - 15 - 1 - read-write - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGHS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGHS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGHS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGHS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPDMA0 - DIEPDMA0 - Device IN Endpoint 0 DMA Address - register - 0x114 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA1 - DIEPDMA1 - Device IN Endpoint 1 DMA Address - register - 0x134 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA2 - DIEPDMA2 - Device IN Endpoint 2 DMA Address - register - 0x154 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA3 - DIEPDMA3 - Device IN Endpoint 3 DMA Address - register - 0x174 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA4 - DIEPDMA4 - Device IN Endpoint 4 DMA Address - register - 0x194 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA5 - DIEPDMA5 - Device IN Endpoint 5 DMA Address - register - 0x1B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA6 - DIEPDMA6 - Device IN Endpoint 6 DMA Address - register - 0x1D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DIEPDMA7 - DIEPDMA7 - Device IN Endpoint 7 DMA Address - register - 0x1F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DTXFSTS0 - DTXFSTS0 - OTGHS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGHS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGHS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGHS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGHS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGHS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGHS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGHS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGHS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGHS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGHS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGHS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGHS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGHS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGHS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPDMA0 - DOEPDMA0 - Device OUT Endpoint 0 DMA Address - register - 0x314 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA1 - DOEPDMA1 - Device OUT Endpoint 1 DMA Address - register - 0x334 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA2 - DOEPDMA2 - Device OUT Endpoint 2 DMA Address - register - 0x354 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA3 - DOEPDMA3 - Device OUT Endpoint 3 DMA Address - register - 0x374 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA4 - DOEPDMA4 - Device OUT Endpoint 4 DMA Address - register - 0x394 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA5 - DOEPDMA5 - Device OUT Endpoint 5 DMA Address - register - 0x3B4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA6 - DOEPDMA6 - Device OUT Endpoint 6 DMA Address - register - 0x3D4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - DOEPDMA7 - DOEPDMA7 - Device OUT Endpoint 7 DMA Address - register - 0x3F4 - 0x20 - read-write - 0x00000000 - - - DMAADDR - DMA Address - 0 - 32 - - - - - - - USB_OTGHS_PWRCLK - USB on the go high speed - USB_OTGHS - 0x40040E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGHS power and clock gating control - register (OTGHS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - LOCKUP_LK - CM4F LOCKUP bit enable - 0 - 1 - - - SRAM_OPERR_LK - SRAM odd parity error lock enable - 1 - 1 - - - PVM_LK - PVM lock enable - 2 - 1 - - - SRAM_OPERR_STS - SRAM odd parity error status - 8 - 1 - - - I2S_FD - I2S full duplex config - 30 - 2 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PB10_UH - PB10 ultra high sourcing/sinking strength - 2 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - PB3_UH - PB3 ultra high sourcing/sinking strength - 0 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 5 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 5 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - diff --git a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h index 9c07bf192..0061fd242 100644 --- a/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h +++ b/hw/bsp/at32f402_405/boards/AT_START_F402_405/board.h @@ -55,7 +55,7 @@ #define PRINT_UART_TX_PIN_SOURCE GPIO_PINS_SOURCE9 #define PRINT_UART_TX_PIN_MUX_NUM GPIO_MUX_7 -//USB +//USB #ifdef BOARD_TUD_RHPORT #if BOARD_TUD_RHPORT == 0 #define USB_ID USB_OTG1_ID diff --git a/hw/bsp/at32f402_405/family.c b/hw/bsp/at32f402_405/family.c index dd8e7de10..e6a3bce22 100644 --- a/hw/bsp/at32f402_405/family.c +++ b/hw/bsp/at32f402_405/family.c @@ -36,11 +36,11 @@ void usb_gpio_config(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGHS_IRQHandler(void) +void OTGHS_IRQHandler(void) { tusb_int_handler(1, true); } @@ -53,7 +53,7 @@ void OTGHS_WKUP_IRQHandler(void) tusb_int_handler(1, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -94,7 +94,7 @@ void board_init(void) //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ -void led_and_botton_init(void) +void led_and_botton_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -217,7 +217,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -238,17 +238,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -264,11 +264,11 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -280,7 +280,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } @@ -294,4 +294,3 @@ void assert_failed(const char *file, uint32_t line) /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ - diff --git a/hw/bsp/at32f402_405/family.mk b/hw/bsp/at32f402_405/family.mk index 9dbdb1a55..461264561 100644 --- a/hw/bsp/at32f402_405/family.mk +++ b/hw/bsp/at32f402_405/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F402_405_SDK = hw/mcu/artery/at32f402_405 -DEPS_SUBMODULES += $(AT32F402_405_SDK) # AT32 SDK path AT32F402_405_SDK_SRC = $(AT32F402_405_SDK)/libraries diff --git a/hw/bsp/at32f402_405/startup_at32f402_405.s b/hw/bsp/at32f402_405/startup_at32f402_405.s index 251ec5058..9b0dad9ef 100644 --- a/hw/bsp/at32f402_405/startup_at32f402_405.s +++ b/hw/bsp/at32f402_405/startup_at32f402_405.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array @@ -104,7 +104,7 @@ Infinite_Loop: * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object @@ -128,7 +128,7 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - + /* External Interrupts */ .word WWDT_IRQHandler /* Window Watchdog Timer */ .word PVM_IRQHandler /* PVM through EXINT Line detect */ @@ -237,20 +237,20 @@ g_pfnVectors: /******************************************************************************* * -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override * this definition. -* +* *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler - + .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler - + .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler @@ -267,10 +267,10 @@ g_pfnVectors: .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - + .thumb_set SysTick_Handler,Default_Handler + .weak WWDT_IRQHandler - .thumb_set WWDT_IRQHandler,Default_Handler + .thumb_set WWDT_IRQHandler,Default_Handler .weak PVM_IRQHandler .thumb_set PVM_IRQHandler,Default_Handler @@ -294,7 +294,7 @@ g_pfnVectors: .thumb_set EXINT1_IRQHandler,Default_Handler .weak EXINT2_IRQHandler - .thumb_set EXINT2_IRQHandler,Default_Handler + .thumb_set EXINT2_IRQHandler,Default_Handler .weak EXINT3_IRQHandler .thumb_set EXINT3_IRQHandler,Default_Handler @@ -312,7 +312,7 @@ g_pfnVectors: .thumb_set DMA1_Channel3_IRQHandler,Default_Handler .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler .weak DMA1_Channel5_IRQHandler .thumb_set DMA1_Channel5_IRQHandler,Default_Handler @@ -479,7 +479,7 @@ g_pfnVectors: .weak QSPI1_IRQHandler .thumb_set QSPI1_IRQHandler,Default_Handler - .weak DMAMUX_IRQHandler + .weak DMAMUX_IRQHandler .thumb_set DMAMUX_IRQHandler ,Default_Handler .weak ACC_IRQHandler diff --git a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h index d63959c4e..a89d8c282 100644 --- a/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f403a_407/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f403a_407/at32f403a_407_clock.c b/hw/bsp/at32f403a_407/at32f403a_407_clock.c index 38b20c8a3..7a028cebd 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_clock.c +++ b/hw/bsp/at32f403a_407/at32f403a_407_clock.c @@ -84,4 +84,4 @@ void system_clock_config(void) /* update system_core_clock global variable */ system_core_clock_update(); -} \ No newline at end of file +} diff --git a/hw/bsp/at32f403a_407/at32f403a_407_clock.h b/hw/bsp/at32f403a_407/at32f403a_407_clock.h index bed47d7ea..ddedfa619 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_clock.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F403A_407_CLOCK_H */ - diff --git a/hw/bsp/at32f403a_407/at32f403a_407_conf.h b/hw/bsp/at32f403a_407/at32f403a_407_conf.h index 856f34fda..172e972d2 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_conf.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_conf.h @@ -32,7 +32,7 @@ extern "C" { /** - * @brief in the following line adjust the value of high speed exernal crystal (hext) + * @brief in the following line adjust the value of high speed external crystal (hext) * used in your application * * tip: to avoid modifying this file each time you need to use different hext, you @@ -40,11 +40,11 @@ extern "C" { * */ #if !defined HEXT_VALUE -#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed exernal crystal in hz */ +#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */ #endif /** - * @brief in the following line adjust the high speed exernal crystal (hext) startup + * @brief in the following line adjust the high speed external crystal (hext) startup * timeout value */ #define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */ diff --git a/hw/bsp/at32f403a_407/at32f403a_407_int.h b/hw/bsp/at32f403a_407/at32f403a_407_int.h index f82b6a499..6d85c70ca 100644 --- a/hw/bsp/at32f403a_407/at32f403a_407_int.h +++ b/hw/bsp/at32f403a_407/at32f403a_407_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld index 00475df6f..c3d8aca80 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F403AxG_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd deleted file mode 100644 index 323218b23..000000000 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/AT32F407xx_v2.svd +++ /dev/null @@ -1,28047 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F407xx_v2 - AT32F407 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK2CTRL - BK2CTRL - PC Card/NAND Flash control register 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK2IS - BK2IS - FIFO status and interrupt register 2 - 0x64 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK2TMGMEM - BK2TMGMEM - Regular memory space timing register 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK2TMGATT - BK2TMGATT - special memory space timing register 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK2ECC - BK2ECC - ECC result register 2 - 0x74 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - BUSLATW2W - 0 - 8 - - - BUSLATR2R - BUSLATR2R - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - PLLRANGE - PLL clock output frequency up 72MHz or not - 31 - 1 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O - reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOERST - IO port E reset - 6 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - ADC2RST - ADC2 reset - 10 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TMR8RST - Timer8 reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - ADC3RST - ADC3 reset - 15 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - USART6RST - USART6 reset - 24 - 1 - - - UART7RST - UART7 reset - 25 - 1 - - - UART8RST - UART8 reset - 26 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - TMR6RST - Timer 6 reset - 4 - 1 - - - TMR7RST - Timer 7 reset - 5 - 1 - - - TMR12RST - Timer 12 reset - 6 - 1 - - - TMR13RST - Timer 13 reset - 7 - 1 - - - TMR14RST - Timer 14 reset - 8 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - SPI4RST - SPI4 reset - 16 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - BPRRST - Battery powered domain register reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - XMCEN - XMC clock enable - 8 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - SDIO2EN - SDIO2 clock enable - 11 - 1 - - - EMACEN - EMACEN clock enable - 14 - 1 - - - EMACTXEN - EMACEN Tx clock enable - 15 - 1 - - - EMACRXEN - EMACEN Rx clock enable - 16 - 1 - - - EMACPTPEN - EMACPTP clock enable - 28 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock - enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOEEN - I/O port E clock enable - 6 - 1 - - - ADC1EN - ADC1 clock - enable - 9 - 1 - - - ADC2EN - ADC2 clock - enable - 10 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TMR8EN - Timer8 clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - ADC3EN - ADC3 clock enable - 15 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - USART6EN - USART6 clock enable - 24 - 1 - - - UART7EN - UART7 clock enable - 25 - 1 - - - UART8EN - UART8 clock enable - 26 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - SPI4EN - SPI4 clock enable - 16 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - BPREN - Barrery powered domain register clock - enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - EMACRST - EMAC reset - 14 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - USBBUFS - USB buffer size selection - 24 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x50 - 0x20 - 0x00000000 - - - CLK_TO_TMR - Clock output internal connect to timer10 - 16 - 1 - read-write - - - - - MISC3 - MISC3 - Miscellaneous register3 - 0x54 - 0x20 - 0x00000000 - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - HEXTDIV - HEXT division - 12 - 2 - read-write - - - EMAC_PPS_SEL - Ethernet pulse width Select - 15 - 1 - read-write - - - - - INTMAP - INTMAP - Interrupt remap register - 0x5C - 0x20 - 0x00000000 - - - USB_INT_MAP - USBDEV interrupt remap - 0 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect - register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - HDRV - HDRV - Port configuration driver - register - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port hdrv bit 0 - 0 - 1 - - - HDRV1 - Port hdrv bit 1 - 1 - 1 - - - HDRV2 - Port hdrv bit 2 - 2 - 1 - - - HDRV3 - Port hdrv bit 3 - 3 - 1 - - - HDRV4 - Port hdrv bit 4 - 4 - 1 - - - HDRV5 - Port hdrv bit 5 - 5 - 1 - - - HDRV6 - Port hdrv bit 6 - 6 - 1 - - - HDRV7 - Port hdrv bit 7 - 7 - 1 - - - HDRV8 - Port hdrv bit 8 - 8 - 1 - - - HDRV9 - Port hdrv bit 9 - 9 - 1 - - - HDRV10 - Port hdrv bit 10 - 10 - 1 - - - HDRV11 - Port hdrv bit 11 - 11 - 1 - - - HDRV12 - Port hdrv bit 12 - 12 - 1 - - - HDRV13 - Port hdrv bit 13 - 13 - 1 - - - HDRV14 - Port hdrv bit 14 - 14 - 1 - - - HDRV15 - Port hdrv bit 15 - 15 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - (IOMUX_EVTOUT) - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - (IOMUX_REMAP) - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART2_MUX - USART2 muxing - 3 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - TMR4_MUX - TMR4 muxing - 12 - 1 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted - conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary - conversion muxing - 18 - 1 - read-write - - - ADC2_ETP_MUX - ADC2 external trigger preempted - conversion muxing - 19 - 1 - read-write - - - ADC2_ETO_MUX - ADC2 external trigger ordinary - conversion muxing - 20 - 1 - read-write - - - EMAC_MUX - Ethernet MAC muxing - 21 - 1 - read-write - - - CAN2_MUX - CAN2 muxing - 22 - 1 - read-write - - - MII_RMII_SEL_MUX - MII_RMII select muxing - 23 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI3_MUX - SPI3 muxing - 28 - 1 - read-write - - - TMR2ITR1_MUX - TMR2 internal trigger 1 - muxing - 29 - 1 - read-write - - - PTP_PPS_MUX - PTP_PPS muxing - 30 - 1 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - (IOMUX_EXINTC1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - (IOMUX_EXINTC2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - (IOMUX_EXINTC3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - (IOMUX_EXINTC4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - (IOMUX_REMAP2) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR9_MUX - TMR9 muxing - 5 - 1 - - - XMC_NADV_MUX - NADV connect/disconnect - 10 - 1 - - - SPI4_MUX - SPI4 muxing - 17 - 1 - - - I2C3_MUX - I2C3 muxing - 18 - 1 - - - SDIO2_MUX - SDIO2 muxing - 19 - 2 - - - EXT_SPIM_EN_MUX - SPIM enable muxing - 21 - 1 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - (IOMUX_REMAP3) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - (IOMUX_REMAP4) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 2 - - - TMR2ITR1_GMUX - TMR2 internal trigger 1 - muxing - 6 - 2 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR4_GMUX - TMR4 muxing - 12 - 4 - - - TMR5CH4_GMUX - TMR5 channel4 internal - muxing - 19 - 1 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - (IOMUX_REMAP5) - 0x28 - 0x20 - read-write - 0x00000000 - - - USART5_GMUX - USART5 muxing - 0 - 4 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - I2C3_GMUX - I2C3 muxing - 12 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - SPI3_GMUX - SPI3 muxing - 24 - 4 - - - SPI4_GMUX - SPI4 muxing - 28 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - (IOMUX_REMAP6) - 0x2C - 0x20 - read-write - 0x00000000 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - CAN2_GMUX - CAN2 muxing - 4 - 4 - - - SDIO2_GMUX - SDIO2 muxing - 12 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - USART2_GMUX - USART2 muxing - 20 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - (IOMUX_REMAP7) - 0x30 - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_GMUX - SPIM muxing - 0 - 3 - - - EXT_SPIM_GEN - SPIM enable - 3 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted - conversion muxing - 4 - 1 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary - conversion muxing - 5 - 1 - - - ADC2_ETP_GMUX - ADC2 external trigger preempted - conversion muxing - 8 - 1 - - - ADC2_ETO_GMUX - ADC2 external trigger ordinary - conversion muxing - 9 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - PD01_GMUX - PortD0/PortD1 mappingon - OSC_IN/OSC_OUT - 20 - 1 - - - XMC_GMUX - XMC muxing - 24 - 3 - - - XMC_NADV_GMUX - XMC_NADV muxing - 27 - 1 - - - - - REMAP8 - REMAP8 - IO MUX remap register 8 - (IOMUX_REMAP8) - 0x34 - 0x20 - read-write - 0x00000000 - - - EMAC_GMUX - Ethernet MAC muxing - 16 - 2 - - - MII_RMII_SEL_GMUX - MII_RMII select muxing - 18 - 1 - - - PTP_PPS_GMUX - PTP_PPS muxing - 19 - 1 - - - USART6_GMUX - USART6 muxing - 20 - 4 - - - UART7_GMUX - UART7 muxing - 24 - 4 - - - UART8_GMUX - UART8 muxing - 28 - 4 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - RTCALARM - RTC Alarm interrupt connect to EXINT line17 - 41 - - - USBFSWakeUp - USB Device FS Wakeup interrupt connect to EXINT line18 - 42 - - - EMAC_WKUP - EMAC_WKUP interrupt connect to EXINT line19 - 80 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global - interrupt - 75 - - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO interrupt enable register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x40023400 - - SDIO2 - SDIO2 global interrupt - 60 - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - - CTRLH - CTRLH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - TAIEN - Time alarm interrupt enable - 1 - 1 - - - TSIEN - Time second interrupt enable - 2 - 1 - - - - - CTRLL - CTRLL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - TSF - Time second flag - 0 - 1 - read-write - - - TAF - Time alarm flag - 1 - 1 - read-write - - - OVFF - Overflow Flag - 2 - 1 - read-write - - - UPDF - RTC update finish - 3 - 1 - read-write - - - CFGEN - RTC configuration enable - 4 - 1 - read-write - - - CFGF - RTC configuration finish - 5 - 1 - read-only - - - - - DIVH - DIVH - RTC Divider Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - DIV - RTC divider high - 0 - 4 - - - - - DIVL - DIVL - RTC Divider Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - DIV - RTC divider low - 0 - 16 - - - - - DIVCNTH - DIVCNTH - RTC Divider Register High - 0x10 - 0x20 - read-write - 0x00000000 - - - DIVCNT - RTC divider register high - 0 - 4 - - - - - DIVCNTL - DIVCNTL - RTC Divider Register Low - 0x14 - 0x20 - read-write - 0x8000 - - - DIVCNT - RTC divider register low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register low - 0 - 16 - - - - - TAH - TAH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - TA - Time alarm register high - 0 - 16 - - - - - TAL - TAL - Time alarm register low - 0x24 - 0x20 - write-only - 0xFFFF - - - TA - RTC alarm register low - 0 - 16 - - - - - - - BPR - Battery powered register - BPR - 0x40006C04 - - 0x0 - 0x3FC - registers - - - - DT1 - DT1 - Battery powered domain data - register (BPR_DTx) - 0x0 - 0x20 - read-write - 0x00000000 - - - DT1 - BPR data1 - 0 - 16 - - - - - DT2 - DT2 - Battery powered domain data - register (BPR_DTx) - 0x4 - 0x20 - read-write - 0x00000000 - - - DT2 - BPR data2 - 0 - 16 - - - - - DT3 - DT3 - Battery powered domain data - register (BPR_DTx) - 0x8 - 0x20 - read-write - 0x00000000 - - - DT3 - BPR data3 - 0 - 16 - - - - - DT4 - DT4 - Battery powered domain data - register (BPR_DTx) - 0xC - 0x20 - read-write - 0x00000000 - - - DT4 - BPR data4 - 0 - 16 - - - - - DT5 - DT5 - Battery powered domain data - register (BPR_DTx) - 0x10 - 0x20 - read-write - 0x00000000 - - - DT5 - BPR data5 - 0 - 16 - - - - - DT6 - DT6 - Battery powered domain data - register (BPR_DTx) - 0x14 - 0x20 - read-write - 0x00000000 - - - DT6 - BPR data6 - 0 - 16 - - - - - DT7 - DT7 - Battery powered domain data - register (BPR_DTx) - 0x18 - 0x20 - read-write - 0x00000000 - - - DT7 - BPR data7 - 0 - 16 - - - - - DT8 - DT8 - Battery powered domain data - register (BPR_DTx) - 0x1C - 0x20 - read-write - 0x00000000 - - - DT8 - BPR data8 - 0 - 16 - - - - - DT9 - DT9 - Battery powered domain data - register (BPR_DTx) - 0x20 - 0x20 - read-write - 0x00000000 - - - DT9 - BPR data9 - 0 - 16 - - - - - DT10 - DT10 - Battery powered domain data - register (BPR_DTx) - 0x24 - 0x20 - read-write - 0x00000000 - - - DT10 - BPR data10 - 0 - 16 - - - - - DT11 - DT11 - Battery powered domain data - register (BPR_DTx) - 0x3C - 0x20 - read-write - 0x00000000 - - - DT11 - BPR data11 - 0 - 16 - - - - - DT12 - DT12 - Battery powered domain data - register (BPR_DTx) - 0x40 - 0x20 - read-write - 0x00000000 - - - DT12 - BPR data12 - 0 - 16 - - - - - DT13 - DT13 - Battery powered domain data - register (BPR_DTx) - 0x44 - 0x20 - read-write - 0x00000000 - - - DT13 - BPR data13 - 0 - 16 - - - - - DT14 - DT14 - Battery powered domain data - register (BPR_DTx) - 0x48 - 0x20 - read-write - 0x00000000 - - - DT14 - BPR data14 - 0 - 16 - - - - - DT15 - DT15 - Battery powered domain data - register (BPR_DTx) - 0x4C - 0x20 - read-write - 0x00000000 - - - DT15 - BPR data15 - 0 - 16 - - - - - DT16 - DT16 - Battery powered domain data - register (BPR_DTx) - 0x50 - 0x20 - read-write - 0x00000000 - - - DT16 - BPR data16 - 0 - 16 - - - - - DT17 - DT17 - Battery powered domain data - register (BPR_DTx) - 0x54 - 0x20 - read-write - 0x00000000 - - - DT17 - BPR data17 - 0 - 16 - - - - - DT18 - DT18 - Battery powered domain data - register (BPR_DTx) - 0x58 - 0x20 - read-write - 0x00000000 - - - DT18 - BPR data18 - 0 - 16 - - - - - DT19 - DT19 - Battery powered domain data - register (BPR_DTx) - 0x5C - 0x20 - read-write - 0x00000000 - - - DT19 - BPR data19 - 0 - 16 - - - - - DT20 - DT20 - Battery powered domain data - register (BPR_DTx) - 0x60 - 0x20 - read-write - 0x00000000 - - - DT20 - BPR data20 - 0 - 16 - - - - - DT21 - DT21 - Battery powered domain data - register (BPR_DTx) - 0x64 - 0x20 - read-write - 0x00000000 - - - DT21 - BPR data21 - 0 - 16 - - - - - DT22 - DT22 - Battery powered domain data - register (BPR_DTx) - 0x68 - 0x20 - read-write - 0x00000000 - - - DT22 - BPR data22 - 0 - 16 - - - - - DT23 - DT23 - Battery powered domain data - register (BPR_DTx) - 0x6C - 0x20 - read-write - 0x00000000 - - - DT23 - BPR data23 - 0 - 16 - - - - - DT24 - DT24 - Battery powered domain data - register (BPR_DTx) - 0x70 - 0x20 - read-write - 0x00000000 - - - DT24 - BPR data24 - 0 - 16 - - - - - DT25 - DT25 - Battery powered domain data - register (BPR_DTx) - 0x74 - 0x20 - read-write - 0x00000000 - - - DT25 - BPR data25 - 0 - 16 - - - - - DT26 - DT26 - Battery powered domain data - register (BPR_DTx) - 0x78 - 0x20 - read-write - 0x00000000 - - - DT26 - BPR data26 - 0 - 16 - - - - - DT27 - DT27 - Battery powered domain data - register (BPR_DTx) - 0x7C - 0x20 - read-write - 0x00000000 - - - DT27 - BPR data27 - 0 - 16 - - - - - DT28 - DT28 - Battery powered domain data - register (BPR_DTx) - 0x80 - 0x20 - read-write - 0x00000000 - - - DT28 - BPR data28 - 0 - 16 - - - - - DT29 - DT29 - Battery powered domain data - register (BPR_DTx) - 0x84 - 0x20 - read-write - 0x00000000 - - - DT29 - BPR data29 - 0 - 16 - - - - - DT30 - DT30 - Battery powered domain data - register (BPR_DTx) - 0x88 - 0x20 - read-write - 0x00000000 - - - DT30 - BPR data30 - 0 - 16 - - - - - DT31 - DT31 - Battery powered domain data - register (BPR_DTx) - 0x8C - 0x20 - read-write - 0x00000000 - - - DT31 - BPR data31 - 0 - 16 - - - - - DT32 - DT32 - Battery powered domain data - register (BPR_DTx) - 0x90 - 0x20 - read-write - 0x00000000 - - - DT32 - BPR data32 - 0 - 16 - - - - - DT33 - DT33 - Battery powered domain data - register (BPR_DTx) - 0x94 - 0x20 - read-write - 0x00000000 - - - DT33 - BPR data33 - 0 - 16 - - - - - DT34 - DT34 - Battery powered domain data - register (BPR_DTx) - 0x98 - 0x20 - read-write - 0x00000000 - - - DT34 - BPR data34 - 0 - 16 - - - - - DT35 - DT35 - Battery powered domain data - register (BPR_DTx) - 0x9C - 0x20 - read-write - 0x00000000 - - - DT35 - BPR data35 - 0 - 16 - - - - - DT36 - DT36 - Battery powered domain data - register (BPR_DTx) - 0xA0 - 0x20 - read-write - 0x00000000 - - - DT36 - BPR data36 - 0 - 16 - - - - - DT37 - DT37 - Battery powered domain data - register (BPR_DTx) - 0xA4 - 0x20 - read-write - 0x00000000 - - - DT37 - BPR data37 - 0 - 16 - - - - - DT38 - DT38 - Battery powered domain data - register (BPR_DTx) - 0xA8 - 0x20 - read-write - 0x00000000 - - - DT38 - BPR data38 - 0 - 16 - - - - - DT39 - DT39 - Battery powered domain data - register (BPR_DTx) - 0xAC - 0x20 - read-write - 0x00000000 - - - DT39 - BPR data39 - 0 - 16 - - - - - DT40 - DT40 - Battery powered domain data - register (BPR_DTx) - 0xB0 - 0x20 - read-write - 0x00000000 - - - DT40 - BPR data40 - 0 - 16 - - - - - DT41 - DT41 - Battery powered domain data - register (BPR_DTx) - 0xB4 - 0x20 - read-write - 0x00000000 - - - DT41 - BPR data41 - 0 - 16 - - - - - DT42 - DT42 - Battery powered domain data - register (BPR_DTx) - 0xB8 - 0x20 - read-write - 0x00000000 - - - DT42 - BPR data42 - 0 - 16 - - - - - RTCCAL - RTCCAL - RTC clock calibration register - (BPR_RTCCAL) - 0x28 - 0x20 - read-write - 0x00000000 - - - CALVAL - Calibration value - 0 - 7 - - - CALOUT - Calibration Clock Output - 7 - 1 - - - OUTEN - Output enable - 8 - 1 - - - OUTSEL - Output selection - 9 - 1 - - - CCOS - Calibration clock output selection - 10 - 1 - - - OUTM - Output mode - 11 - 1 - - - - - CTRL - CTRL - BPR control register - (BPR_CTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPEN - Tamper pin enable - 0 - 1 - - - TPP - TAMPER pin polarity - 1 - 1 - - - - - CTRLSTS - CTRLSTS - BPR control/status register - (BPR_CTRLSTS) - 0x30 - 0x20 - 0x00000000 - - - TPEFCLR - Tamper event flag clear - 0 - 1 - write-only - - - TPIFCLR - Tamper interrupt flag clear - 1 - 1 - write-only - - - TPIEN - Tamper pin interrupt enable - 2 - 1 - read-write - - - TPEF - Tamper event flag - 8 - 1 - read-write - - - TPIF - Tamper interrupt flag - 9 - 1 - read-write - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR8 - 0x40013400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - TMR13 - 0x40001C00 - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - - TMR14 - 0x40002000 - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40015C00 - - I2C3_EVT - I2C3 event interrupt - 61 - - - I2C3_ERR - I2C3 error interrupt - 62 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - SPI4 - 0x40004000 - - SPI4 - SPI4 global interrupt - 63 - - - - I2S2_EXT - 0x40016C00 - - - I2S3_EXT - 0x40017000 - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40016000 - - USART6 - USART6 global interrupt - 76 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - MSSEL - Master slave mode select - 16 - 4 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ADC2ODT - ADC2 conversion data of ordinary channel - 16 - 16 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC3 - Analog to digital converter - ADC - 0x40013C00 - - 0x0 - 0x400 - registers - - - ADC3 - ADC3 global interrupt - 47 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - USBFS_H_CAN1_TX - CAN1 TX interrupt - 19 - - - USBFS_L_CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 68 - - - CAN2_RX0 - CAN2 RX0 interrupt - 69 - - - CAN2_RX1 - CAN2 RX1 interrupt - 70 - - - CAN2_SE - CAN2 SE interrupt - 71 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 17 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 19 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 20 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 21 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 25 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 26 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 27 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 31 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40016400 - - UART7 - UART7 global interrupt - 77 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40016800 - - UART8 - UART8 global interrupt - 78 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - UNLOCK3 - UNLOCK3 - Unlock 3 register - 0x84 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - SELECT - SELECT - Select register - 0x88 - 0x20 - write-only - 0x00000000 - - - SELECT - spim type selection - 0 - 32 - - - - - STS3 - STS3 - Status 3 register - 0x8C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL3 - CTRL3 - Control 3 register - 0x90 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - CHPERS - Chip erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR3 - ADDR3 - Address 3 register - 0x94 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - DA - DA - Spim decryption address - 0x98 - 0x20 - write-only - 0x00000000 - - - FDA - Flash decryption address - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - read-only - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - read-only - - - SLIB_ES - sLib end sector - 22 - 10 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting,valid input: 0~511 - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting,valid input: 0~511, 0 means no data area - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting,valid input: 0~511 - 22 - 10 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USBFS - Universal serial bus full-speed device - interface - USBFS - 0x40005C00 - - 0x0 - 0x400 - registers - - - - EPT0 - EPT0 - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT1 - EPT1 - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT2 - EPT2 - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT3 - EPT3 - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT4 - EPT4 - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT5 - EPT5 - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT6 - EPT6 - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT7 - EPT7 - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - CTRL - CTRL - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - CSRST - Core soft reset - 0 - 1 - - - DISUSB - Disable usb phy - 1 - 1 - - - LPM - Low power mode - 2 - 1 - - - SSP - Soft suspend config - 3 - 1 - - - GRESUME - Generate resume request - 4 - 1 - - - LSOFIEN - Lost start of frame interrupt enable - 8 - 1 - - - SOFIEN - Start of frame interrupt - enable - 9 - 1 - - - RSTIEN - Bus reset interrupt enable - 10 - 1 - - - SPIEN - Bus suspend mode interrupt - enable - 11 - 1 - - - WKIEN - Wakeup/Remote wakeup interrupt enable - 12 - 1 - - - BEIEN - Bus error interrupt enable - 13 - 1 - - - UCFORIEN - USB Core fifo overrun - interrupt enable - 14 - 1 - - - TCIEN - transmission completed interrupt - enable - 15 - 1 - - - - - INTSTS - INTSTS - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EPT_NUM - Endpoint number - 0 - 4 - - - INOUT - In/Out transaction - 4 - 1 - - - LSOF - Lost start of frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RST - Bus reset - 10 - 1 - - - SP - Bus suspend - 11 - 1 - - - WK - Wakeup - 12 - 1 - - - BE - Bus error - 13 - 1 - - - UCFOR - USB core fifo overrun memory - 14 - 1 - - - TC - transaction completed - 15 - 1 - - - - - SOFRNUM - SOFRNUM - frame number register - 0x48 - 0x20 - read-write - 0x0000 - - - SOFNUM - Start of frame number - 0 - 11 - - - LSOFNUM - Lost start of frame number - 11 - 2 - - - CLCK - Connect locked - 13 - 1 - - - DMSTS - DM status - 14 - 1 - - - DPSTS - DP status - 15 - 1 - - - - - DEVADDR - DEVADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADDR - Host assign device address - 0 - 7 - - - CEN - USB core enable - 7 - 1 - - - - - BUFTBL - BUFTBL - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTADDR - Endpoint buffer table start address - 3 - 13 - - - - - CFG - CFG - CFG control register - 0x60 - 0x20 - read-write - 0x0000 - - - PUO - DP pullup off - 1 - 1 - - - SOFOUTEN - SOF output enable - 0 - 1 - - - - - - - ETHERNET_MAC - Ethernet: media access control - ETHERNET - 0x40028000 - - 0x0 - 0x100 - registers - - - EMAC - Ethernet mac global interrupt - 79 - - - - MACCTRL - MACCTRL - Ethernet MAC configuration register - 0x0 - 0x20 - read-write - 0x00008000 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - DC - Deferral check - 4 - 1 - - - BL - Back-off limit - 5 - 2 - - - ACS - Automatic pad/CRC - stripping - 7 - 1 - - - DR - Disable retry - 9 - 1 - - - IPC - IPv4 checksum offload - 10 - 1 - - - DM - Duplex mode - 11 - 1 - - - LM - Loopback mode - 12 - 1 - - - DRO - Disable receive own - 13 - 1 - - - FES - Fast EMAC speed - 14 - 1 - - - DCS - Disable carrier sense - 16 - 1 - - - IFG - Interframe gap - 17 - 3 - - - JD - Jabber disable - 22 - 1 - - - WD - Watchdog disable - 23 - 1 - - - - - MACFRMF - MACFRMF - Ethernet MAC frame filter register - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Promiscuous mode - 0 - 1 - - - HUC - Hash unicast - 1 - 1 - - - HMC - Hash multicast - 2 - 1 - - - DAIF - Destination address inverse - filtering - 3 - 1 - - - PMC - Pass multicast - 4 - 1 - - - DBF - Disable broadcast frames - 5 - 1 - - - PCF - Pass control frames - 6 - 2 - - - SAIF - Source address inverse - filtering - 8 - 1 - - - SAF - Source address filter - 9 - 1 - - - HPF - Hash or perfect filter - 10 - 1 - - - RA - Receive all - 31 - 1 - - - - - MACHTH - MACHTH - Ethernet MAC hash table high register - 0x8 - 0x20 - read-write - 0x00000000 - - - HTH - Hash table high - 0 - 32 - - - - - MACHTL - MACHTL - Ethernet MAC hash table low register - 0xC - 0x20 - read-write - 0x00000000 - - - HTL - Hash table low - 0 - 32 - - - - - MACMIIADDR - MACMIIADDR - Ethernet MAC MII address register - 0x10 - 0x20 - read-write - 0x00000000 - - - MB - MII busy - 0 - 1 - - - MW - MII write - 1 - 1 - - - CR - Clock range - 2 - 3 - - - MII - MII register - 6 - 5 - - - PA - PHY address - 11 - 5 - - - - - MACMIIDT - MACMIIDT - Ethernet MAC MII data register - 0x14 - 0x20 - read-write - 0x00000000 - - - MD - MII data - 0 - 16 - - - - - MACFCTRL - MACFCTRL - Ethernet MAC flow control register - 0x18 - 0x20 - read-write - 0x00000000 - - - FCB_BPA - Flow control busy/back pressure - activate - 0 - 1 - - - ETF - Enable transmit flow control - - 1 - 1 - - - ERF - Enable receive flow control - - 2 - 1 - - - DUP - Detect unicast pause frame - 3 - 1 - - - PLT - Pause low threshold - 4 - 2 - - - DZQP - Disable zero-quanta pause - 7 - 1 - - - PT - Pass time - 16 - 16 - - - - - MACVLT - MACVLT - Ethernet MAC VLAN tag register - 0x1C - 0x20 - read-write - 0x00000000 - - - VTI - VLAN tag identifier (for receive - frames) - 0 - 16 - - - ETV - Enable 12-bit VLAN tag comparison - 16 - 1 - - - - - MACRWFF - MACRWFF - Ethernet MAC remote wakeup frame filter register - 0x28 - 0x20 - read-write - 0x00000000 - - - MACPMTCTRLSTS - MACPMTCTRLSTS - Ethernet MAC PMT control and status register - 0x2C - 0x20 - read-write - 0x00000000 - - - PD - Power down - 0 - 1 - - - EMP - Enable magic packet - 1 - 1 - - - ERWF - Enable remote wakeup frame - 2 - 1 - - - RMP - Received magic packet - 5 - 1 - - - RRWF - Recevied remote wakeup frame - 6 - 1 - - - GUC - Global unicast - 9 - 1 - - - RWFFPR - Remote wakeup frame filter register pointer - reset - 31 - 1 - - - - - MACISTS - MACISTS - Ethernet MAC interrupt status register - 0x38 - 0x20 - read-write - 0x00000000 - - - PIS - PMT interrupt status - 3 - 1 - - - MIS - MMC interrupt status - 4 - 1 - - - MRIS - MMC receive interrupt status - 5 - 1 - - - MTIS - MMC transmit interrupt status - 6 - 1 - - - TIS - Timestamp interrupt status - 9 - 1 - - - - - MACIMR - MACIMR - Ethernet MAC interrupt mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - PIM - PMT interrupt mask - 3 - 1 - - - TIM - Timestamp interrupt mask - 9 - 1 - - - - - MACA0H - MACA0H - Ethernet MAC address 0 high register - 0x40 - 0x20 - 0x0010FFFF - - - MA0H - MAC address0 high - 0 - 16 - read-write - - - AE - Address enable - 31 - 1 - read-only - - - - - MACA0L - MACA0L - Ethernet MAC address 0 low register - 0x44 - 0x20 - read-write - 0xFFFFFFFF - - - MA0L - MAC address0 low - 0 - 32 - - - - - MACA1H - MACA1H - Ethernet MAC address 1 high register - 0x48 - 0x20 - read-write - 0x0000FFFF - - - MA1H - MAC address1 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA1L - MACA1L - Ethernet MAC address1 low register - 0x4C - 0x20 - read-write - 0xFFFFFFFF - - - MA1L - MAC address1 low - 0 - 32 - - - - - MACA2H - MACA2H - Ethernet MAC address 2 high register - 0x50 - 0x20 - read-write - 0x0050 - - - MA2H - MAC address 2 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA2L - MACA2L - Ethernet MAC address 2 low register - 0x54 - 0x20 - read-write - 0xFFFFFFFF - - - MA2L - MAC address2 low - 0 - 31 - - - - - MACA3H - MACA3H - Ethernet MAC address 3 high register - 0x58 - 0x20 - read-write - 0x0000FFFF - - - MA3H - MAC address3 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA3L - MACA3L - Ethernet MAC address 3 low register - 0x5C - 0x20 - read-write - 0xFFFFFFFF - - - MA3L - MAC address3 low - 0 - 32 - - - - - - - ETHERNET_MMC - Ethernet: MAC management counters - ETHERNET - 0x40028100 - - 0x0 - 0x100 - registers - - - - MMCCTRL - MMCCTRL - Ethernet MMC control register - 0x0 - 0x20 - read-write - 0x00000000 - - - RC - Reset counter - 0 - 1 - - - SCR - Stop counter rollover - 1 - 1 - - - RR - Reset on read - 2 - 1 - - - FMC - Freeze MMC counter - 31 - 1 - - - - - MMCRI - MMCRI - Ethernet MMC receive interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - RFCE - Received frames CRC error - 5 - 1 - - - RFAE - Received frames alignment error - 6 - 1 - - - RGUF - Received good unicast frames - 17 - 1 - - - - - MMCTI - MMCTI - Ethernet MMC transmit interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - TSCGFCI - Transmit single collision good frame - counter interrupt - 14 - 1 - - - TGFMSC - Transmit good frames more single - collision - 15 - 1 - - - TGF - Transmitted good frames - 21 - 1 - - - - - MMCRIM - MMCRIM - Ethernet MMC receive interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - RCEFCIM - Received CRC error frame counter interrupt - mask - 5 - 1 - - - RAEFACIM - Received alignment error frame alignment - counter interrupt mask - 6 - 1 - - - RUGFCIM - Received unicast good frame counter - interrupt mask - 17 - 1 - - - - - MMCTIM - MMCTIM - Ethernet MMC transmit interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - TSCGFCIM - Transmit single collision good frame - counter interrupt mask - 14 - 1 - - - TMCGFCIM - Transmit multiple collision good frame - counter interrupt mask - 15 - 1 - - - TGFCIM - Transmitted good frame counter interrupt - mask - 21 - 1 - - - - - MMCTFSCC - MMCTFSCC - Ethernet MMC transmitted good frames after a single collision counter - 0x4C - 0x20 - read-only - 0x00000000 - - - TGFSCC - Transmitted good frames single - collision counter - 0 - 32 - - - - - MMCTFMSCC - MMCTFMSCC - Ethernet MMC transmitted good frames after more than a single collision - 0x50 - 0x20 - read-only - 0x00000000 - - - TGFMSCC - Transmitted good frame more single - collision counter - 0 - 32 - - - - - MMCTFCNT - MMCTFCNT - Ethernet MMC transmitted good frames counter register - 0x68 - 0x20 - read-only - 0x00000000 - - - TGFC - Transmitted good frames - counter - 0 - 32 - - - - - MMCRFCECNT - MMCRFCECNT - Ethernet MMC received frames with CRC error counter register - 0x94 - 0x20 - read-only - 0x00000000 - - - RFCEC - Received frames CRC error counter - 0 - 32 - - - - - MMCRFAECNT - MMCRFAECNT - Ethernet MMC received frames with alignment error counter register - 0x98 - 0x20 - read-only - 0x00000000 - - - RFAEC - Received frames alignment error counter - 0 - 32 - - - - - MMCRGUFCNT - MMCRGUFCNT - MMC received good unicast frames counter register - 0xC4 - 0x20 - read-only - 0x00000000 - - - RGUFC - Received good unicast frames - counter - 0 - 32 - - - - - - - ETHERNET_PTP - Ethernet: Precision time protocol - ETHERNET - 0x40028700 - - 0x0 - 0x100 - registers - - - - PTPTSCTRL - PTPTSCTRL - Ethernet PTP time stamp control register - 0x0 - 0x20 - read-write - 0x2000 - - - TE - Timestamp enable - 0 - 1 - - - TFCU - Timestamp fine or coarse - update - 1 - 1 - - - TI - Timestamp initialize - 2 - 1 - - - TU - Timestamp update - 3 - 1 - - - TITE - Timestamp interrupt trigger - enable - 4 - 1 - - - ARU - Addend register update - 5 - 1 - - - ETAF - Enable timestamp for all frames - 8 - 1 - - - TDBRC - Timestamp digital or binary - rollover control - 9 - 1 - - - EPPV2F - Enable PTP packet processing for - version2 format - 10 - 1 - - - EPPEF - Enable processing of PTP - over EMAC frames - 11 - 1 - - - EPPFSIP6U - Enable processing of PTP frames - sent over IPv6-UDP - 12 - 1 - - - EPPFSIP4U - Enable processing of PTP frames - sent over IPv4-UDP - 13 - 1 - - - ETSFEM - Enable timestamp snapshot for - event message - 14 - 1 - - - ESFMRTM - Enable snapshot for message - relevant to master - 15 - 1 - - - SPPFTS - Select PTP packet for taking snapshot - 16 - 2 - - - EMAFPFF - Enable MAC address for PTP frame filtering - 18 - 1 - - - - - PTPSSINC - PTPSSINC - Ethernet PTP subsecond increment register - 0x4 - 0x20 - read-write - 0x00000000 - - - SSIV - Sub-second increment value - 0 - 8 - - - - - PTPTSH - PTPTSH - Ethernet PTP time stamp high register - 0x8 - 0x20 - read-only - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSL - PTPTSL - Ethernet PTP time stamp low register - 0xC - 0x20 - read-only - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSHUD - PTPTSHUD - Ethernet PTP time stamp high update register - 0x10 - 0x20 - read-write - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSLUD - PTPTSLUD - Ethernet PTP time stamp low update register - 0x14 - 0x20 - read-write - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSAD - PTPTSAD - Ethernet PTP time stamp addend register - 0x18 - 0x20 - read-write - 0x00000000 - - - TAR - Timestamp addend register - 0 - 32 - - - - - PTPTTH - PTPTTH - Ethernet PTP target time high register - 0x1C - 0x20 - read-write - 0x00000000 - - - TTSR - Target time seconds register - 0 - 32 - - - - - PTPTTL - PTPTTL - Ethernet PTP target time low register - 0x20 - 0x20 - read-write - 0x00000000 - - - TTLR - Target timestamp low register - 0 - 32 - - - - - PTPTSSR - PTPTSSR - Ethernet PTP time stamp status register - 0x28 - 0x20 - read-only - 0x00000000 - - - TSO - Timestamp second overflow - 0 - 1 - - - TTTR - Timestamp target time reached - 1 - 1 - - - - - PTPPPSCR - PTPPPSCR - Ethernet PTP PPS control register - 0x2C - 0x20 - read-only - 0x00000000 - - - POFC - PPS Output frequency control - 0 - 4 - - - - - - - ETHERNET_DMA - Ethernet: DMA controller operation - ETHERNET - 0x40029000 - - 0x0 - 0x100 - registers - - - - DMABM - DMABM - Ethernet DMA bus mode register - 0x0 - 0x20 - read-write - 0x20101 - - - SWR - Software reset - 0 - 1 - - - DA - DMA Arbitration - 1 - 1 - - - DSL - Descriptor skip length - 2 - 5 - - - PBL - Programmable burst length - 8 - 6 - - - PR - Priority ratio - 14 - 2 - - - FB - Fixed burst - 16 - 1 - - - RDP - Rx DMA PBL - 17 - 6 - - - USP - Use separate PBL - 23 - 1 - - - PBLx8 - PNLx8 mode - 24 - 1 - - - AAB - Address-aligned beats - 25 - 1 - - - - - DMATPD - DMATPD - Ethernet DMA transmit poll demand register - 0x4 - 0x20 - read-write - 0x00000000 - - - TPD - Transmit poll demand - 0 - 32 - - - - - DMARPD - DMARPD - EHERNET DMA receive poll demand register - 0x8 - 0x20 - read-write - 0x00000000 - - - RPD - Receive poll demand - 0 - 32 - - - - - DMARDLADDR - DMARDLADDR - Ethernet DMA receive descriptor list address register - 0xC - 0x20 - read-write - 0x00000000 - - - SRL - Start of receive list - 0 - 32 - - - - - DMATDLADDR - DMATDLADDR - Ethernet DMA transmit descriptor list address register - 0x10 - 0x20 - read-write - 0x00000000 - - - STL - Start of transmit list - 0 - 32 - - - - - DMASTS - DMASTS - Ethernet DMA status register - 0x14 - 0x20 - 0x00000000 - - - TI - Transmit interrupt - 0 - 1 - read-write - - - TPS - Transmit process stopped - 1 - 1 - read-write - - - TBU - Transmit buffer unavailable - 2 - 1 - read-write - - - TJT - Transmit jabber timeout - 3 - 1 - read-write - - - OVF - Receive overflow - 4 - 1 - read-write - - - UNF - Transmit underflow - 5 - 1 - read-write - - - RI - Receive interrupt - 6 - 1 - read-write - - - RBU - Receive buffer unavailable - 7 - 1 - read-write - - - RPS - Receive process stopped - 8 - 1 - read-write - - - RWT - Receive watchdog timeout - 9 - 1 - read-write - - - ETI - Early transmit interrupt - 10 - 1 - read-write - - - FBEI - Fatal bus error interrupt - 13 - 1 - read-write - - - ERI - Early receive interrupt - 14 - 1 - read-write - - - AIS - Abnormal interrupt summary - 15 - 1 - read-write - - - NIS - Normal interrupt summary - 16 - 1 - read-write - - - RS - Receive process state - 17 - 3 - read-only - - - TS - Transmit process state - 20 - 3 - read-only - - - EB - Error bits - 23 - 3 - read-only - - - MMI - MAC MMC interrupt - 27 - 1 - read-only - - - MPI - MAC PMT interrupt - 28 - 1 - read-only - - - TTI - Timestamp trigger interrupt - 29 - 1 - read-only - - - - - DMAOPM - DMAOPM - Ethernet DMA operation mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - SSR - Start or stop receive - 1 - 1 - - - OSF - Operate on second frame - 2 - 1 - - - RTC - Receive threshold control - 3 - 2 - - - FUGF - Forward undersized good frames - 6 - 1 - - - FEF - Forward error frames - 7 - 1 - - - SSTC - Start of stop transmission command - 13 - 1 - - - TTC - Transmit threshold control - 14 - 3 - - - FTF - Flush transmit FIFO - 20 - 1 - - - TSF - Transmit store and forward - 21 - 1 - - - DFRF - Disable flushing of received - frames - 24 - 1 - - - RSF - Receive store and forward - 25 - 1 - - - DT - Disable dropping of TCP/IP - checksum error frames - 26 - 1 - - - - - DMAIE - DMAIE - Ethernet DMA interrupt enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIE - Transmit interrupt enable - 0 - 1 - - - TSE - Transmit stopped enable - 1 - 1 - - - TUE - Transmit buffer unavailable enable - 2 - 1 - - - TJE - Transmit jabber timeout enable - 3 - 1 - - - OVE - Overflow interrupt enable - 4 - 1 - - - UNE - Underflow interrupt enable - 5 - 1 - - - RIE - Receive interrupt enable - 6 - 1 - - - RBUE - Receive buffer unavailable enable - 7 - 1 - - - RSE - Receive stopped enable - 8 - 1 - - - RWTE - receive watchdog timeout enable - 9 - 1 - - - EIE - Early transmit interrupt enable - 10 - 1 - - - FBEE - Fatal bus error enable - 13 - 1 - - - ERE - Early receive interrupt - enable - 14 - 1 - - - AIE - Abnormal interrupt enable - 15 - 1 - - - NIE - Normal interrupt enable - 16 - 1 - - - - - DMAMFBOCNT - DMAMFBOCNT - Ethernet DMA missed frame and buffer overflow counter register - 0x20 - 0x20 - read-only - 0x00000000 - - - MFC - Missed frames control - 0 - 16 - - - OBMFC - Overflow bit for missed frame - counter - 16 - 1 - - - OFC - Overflow frame counter - 17 - 11 - - - OBFOC - Overflow bit for FIFO overflow - counter - 28 - 1 - - - - - DMACTD - DMACTD - Ethernet DMA current host transmit descriptor register - 0x48 - 0x20 - read-only - 0x00000000 - - - HTDAP - Host transmit descriptor address pointer - 0 - 32 - - - - - DMACRD - DMACRD - Ethernet DMA current host receive descriptor register - 0x4C - 0x20 - read-only - 0x00000000 - - - HRDAP - Host receive descriptor address pointer - 0 - 32 - - - - - DMACTBADDR - DMACTBADDR - Ethernet DMA current host transmit buffer address register - 0x50 - 0x20 - read-only - 0x00000000 - - - HTBAP - Host transmit buffer address pointer - 0 - 32 - - - - - DMACRBADDR - DMACRBADDR - Ethernet DMA current host receive buffer address register - 0x54 - 0x20 - read-only - 0x00000000 - - - HRBAP - Host receive buffer address pointer - 0 - 32 - - - - - - - diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake new file mode 100644 index 000000000..fb45caf23 --- /dev/null +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.cmake @@ -0,0 +1,9 @@ +set(MCU_VARIANT AT32F403ACGU7) +set(JLINK_DEVICE ${MCU_VARIANT}) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F403AxG_FLASH.ld) +set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F403AxG.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk index 58b3fdb11..e309c86bb 100644 --- a/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk +++ b/hw/bsp/at32f403a_407/boards/AT_START_F403A_407/board.mk @@ -1,3 +1,4 @@ +JLINK_DEVICE = at32f403acgu7 LD_FILE = $(BOARD_PATH)/AT32F403AxG_FLASH.ld CFLAGS += \ diff --git a/hw/bsp/at32f403a_407/family.c b/hw/bsp/at32f403a_407/family.c index 23798526f..f9a6dd70d 100644 --- a/hw/bsp/at32f403a_407/family.c +++ b/hw/bsp/at32f403a_407/family.c @@ -25,8 +25,8 @@ */ #include "at32f403a_407_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_clock48m_select(usb_clk48_s clk_s); void uart_print_init(uint32_t baudrate); @@ -50,8 +50,7 @@ void USBFSWakeUp_IRQHandler(void) { tud_int_handler(0); } -void board_init(void) -{ +void board_init(void) { system_clock_config(); /* config nvic priority group */ @@ -62,7 +61,7 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); - + /* enable usb clock */ crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); @@ -82,7 +81,7 @@ void board_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -114,10 +113,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -130,11 +127,8 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_1); @@ -172,13 +166,11 @@ void usb_clock48m_select(usb_clk48_s clk_s) default: break; - } } } -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -186,7 +178,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -207,8 +199,8 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -224,61 +216,57 @@ int board_uart_read(uint8_t *buf, int len) { return 0; } -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } - - void SVC_Handler(void) - { - } +uint32_t board_millis(void) { + return system_ticks; +} - void PendSV_Handler(void) - { - } +void SVC_Handler(void) { +} + +void PendSV_Handler(void) { +} #endif void HardFault_Handler(void) { __asm("BKPT #0\n"); } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f403a_407/family.cmake b/hw/bsp/at32f403a_407/family.cmake new file mode 100644 index 000000000..c121b166b --- /dev/null +++ b/hw/bsp/at32f403a_407/family.cmake @@ -0,0 +1,102 @@ +include_guard() + +set(AT_FAMILY at32f403a_407) +set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS AT32F403A_407 CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + + add_library(${BOARD_TARGET} STATIC + ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT_SDK_LIB}/cmsis/cm4/core_support + ${AT_SDK_LIB}/cmsis/cm4/device_support + ${AT_SDK_LIB}/drivers/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_AT32F403A_407) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f403a_407/family.mk b/hw/bsp/at32f403a_407/family.mk index 4a1c3949c..b3210a6d4 100644 --- a/hw/bsp/at32f403a_407/family.mk +++ b/hw/bsp/at32f403a_407/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F403A_407_SDK = hw/mcu/artery/at32f403a_407 -DEPS_SUBMODULES += $(AT32F403A_407_SDK) # AT32 SDK path AT32F403A_407_SDK_SRC = $(AT32F403A_407_SDK)/libraries @@ -16,7 +15,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F403A_407 LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ diff --git a/hw/bsp/at32f403a_407/startup_at32f403a_407.s b/hw/bsp/at32f403a_407/startup_at32f403a_407.s index 8bb76a062..3b81f2043 100644 --- a/hw/bsp/at32f403a_407/startup_at32f403a_407.s +++ b/hw/bsp/at32f403a_407/startup_at32f403a_407.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h index 599d22ffc..0a4184f34 100644 --- a/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f413/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f413/at32f413_clock.h b/hw/bsp/at32f413/at32f413_clock.h index 702948364..28c47d1e6 100644 --- a/hw/bsp/at32f413/at32f413_clock.h +++ b/hw/bsp/at32f413/at32f413_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F413_CLOCK_H */ - diff --git a/hw/bsp/at32f413/at32f413_int.c b/hw/bsp/at32f413/at32f413_int.c index 8b18bdbe1..7612e52f0 100644 --- a/hw/bsp/at32f413/at32f413_int.c +++ b/hw/bsp/at32f413/at32f413_int.c @@ -137,5 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - - diff --git a/hw/bsp/at32f413/at32f413_int.h b/hw/bsp/at32f413/at32f413_int.h index 2b477475e..fbbf30dbc 100644 --- a/hw/bsp/at32f413/at32f413_int.h +++ b/hw/bsp/at32f413/at32f413_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld index e654b3bbc..9d95a7d3d 100644 --- a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld +++ b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xC_FLASH.ld @@ -105,7 +105,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -118,7 +118,7 @@ SECTIONS _spim_init_base = LOADADDR(.spim); _spim_init_length = SIZEOF(.spim); - + .spim : { . = ALIGN(4); @@ -133,7 +133,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd b/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd deleted file mode 100644 index a4a95208e..000000000 --- a/hw/bsp/at32f413/boards/AT_START_F413/AT32F413xx_v2.svd +++ /dev/null @@ -1,23368 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F413xx_v2 - AT32F413 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 200MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - 0x0 - 0x20 - read-write - 0x00000000 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - PLLRANGE - PLL clock output frequency up 72MHz or not - 31 - 1 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O reset - 0 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOFRST - IO port F reset - 7 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - ADC2RST - ADC2 reset - 10 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TMR8RST - Timer8 reset - 13 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - USBRST - USB reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - BPRRST - Battery powered domain register reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - CAN2RST - CAN2 reset - 31 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOFEN - I/O port F clock enable - 7 - 1 - - - ADC1EN - ADC1 clock enable - 9 - 1 - - - ADC2EN - ADC2 clock enable - 10 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TMR8EN - Timer8 clock enable - 13 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - WWDTEN - Window watchdog timer clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - BPREN - Barrery powered domain register clock enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - CAN2EN - CAN2 clock enable - 31 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - RTCSEL - RTC clock selection - 8 - 2 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register 1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - USBBUFS - USB buffer size selection - 24 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register 2 - 0x50 - 0x20 - 0x00000000 - - - CLK_TO_TMR - Clock output internal connect to timer10 - 16 - 1 - read-write - - - - - MISC3 - MISC3 - Miscellaneous register 3 - 0x54 - 0x20 - 0x00000000 - - - AUTO_STEP_EN - Auto step en - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - INTMAP - INTMAP - Interrupt remap register - 0x5C - 0x20 - 0x00000000 - - - USB_INT_MAP - USBDEV interrupt remap - 0 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOE - 0x40011800 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on - OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted - conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary - conversion muxing - 18 - 1 - read-write - - - ADC2_ETP_MUX - ADC2 external trigger preempted - conversion muxing - 19 - 1 - read-write - - - ADC2_ETO_MUX - ADC2 external trigger ordinary - conversion muxing - 20 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_EN_MUX - SPIM enable - 21 - 1 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - TMR10_GMUX - TMR10 muxing - 4 - 4 - - - TMR11_GMUX - TMR11 muxing - 8 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 3 - - - TMR2ITR1_GMUX - TMR2 internal trigger 1 muxing - 7 - 1 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR5_GMUX - TMR5 muxing - 16 - 3 - - - TMR5CH4_GMUX - TMR5 channel4 internal muxing - 19 - 1 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - 0x28 - 0x20 - read-write - 0x00000000 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - I2C2_GMUX - I2C2 muxing - 8 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - 0x2C - 0x20 - read-write - 0x00000000 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - CAN2_GMUX - CAN2 muxing - 4 - 4 - - - SDIO1_GMUX - SDIO1 muxing - 8 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - 0x30 - 0x20 - read-write - 0x00000000 - - - EXT_SPIM_GMUX - SPIM muxing - 0 - 3 - - - EXT_SPIM_GEN - SPIM enable - 3 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted - conversion muxing - 4 - 1 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary - conversion muxing - 5 - 1 - - - ADC2_ETP_GMUX - ADC2 external trigger preempted - conversion muxing - 8 - 1 - - - ADC2_ETO_GMUX - ADC2 external trigger ordinary - conversion muxing - 9 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - PD01_GMUX - PortD0/PortD1 mappingon - OSC_IN/OSC_OUT - 20 - 1 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - TAMPER - Tamper interrupt - 2 - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - RTCALARM - RTC Alarm interrupt connect to EXINT line17 - 41 - - - USBFSWakeUp - USB Device FS Wakeup interrupt connect to EXINT line18 - 42 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global interrupt - 75 - - - - SDIO - Secure digital input/output interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO - SDIO global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC global interrupt - 3 - - - - CTRLH - CTRLH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - TAIEN - Time alarm interrupt enable - 1 - 1 - - - TSIEN - Time second interrupt enable - 2 - 1 - - - - - CTRLL - CTRLL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - TSF - Time second flag - 0 - 1 - read-write - - - TAF - Time alarm flag - 1 - 1 - read-write - - - OVFF - Overflow Flag - 2 - 1 - read-write - - - UPDF - RTC update finish - 3 - 1 - read-write - - - CFGEN - RTC configuration enable - 4 - 1 - read-write - - - CFGF - RTC configuration finish - 5 - 1 - read-only - - - - - DIVH - DIVH - RTC Divider Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - DIV - RTC divider high - 0 - 4 - - - - - DIVL - DIVL - RTC Divider Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - DIV - RTC divider low - 0 - 16 - - - - - DIVCNTH - DIVCNTH - RTC Divider Register High - 0x10 - 0x20 - read-write - 0x00000000 - - - DIVCNT - RTC divider register high - 0 - 4 - - - - - DIVCNTL - DIVCNTL - RTC Divider Register Low - 0x14 - 0x20 - read-write - 0x8000 - - - DIVCNT - RTC divider register low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNT - RTC counter register low - 0 - 16 - - - - - TAH - TAH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - TA - Time alarm register high - 0 - 16 - - - - - TAL - TAL - Time alarm register low - 0x24 - 0x20 - write-only - 0xFFFF - - - TA - RTC alarm register low - 0 - 16 - - - - - - - BPR - Battery powered register - BPR - 0x40006C04 - - 0x0 - 0x3FC - registers - - - - DT1 - DT1 - Battery powered domain data - register (BPR_DTx) - 0x0 - 0x20 - read-write - 0x00000000 - - - DT1 - BPR data1 - 0 - 16 - - - - - DT2 - DT2 - Battery powered domain data - register (BPR_DTx) - 0x4 - 0x20 - read-write - 0x00000000 - - - DT2 - BPR data2 - 0 - 16 - - - - - DT3 - DT3 - Battery powered domain data - register (BPR_DTx) - 0x8 - 0x20 - read-write - 0x00000000 - - - DT3 - BPR data3 - 0 - 16 - - - - - DT4 - DT4 - Battery powered domain data - register (BPR_DTx) - 0xC - 0x20 - read-write - 0x00000000 - - - DT4 - BPR data4 - 0 - 16 - - - - - DT5 - DT5 - Battery powered domain data - register (BPR_DTx) - 0x10 - 0x20 - read-write - 0x00000000 - - - DT5 - BPR data5 - 0 - 16 - - - - - DT6 - DT6 - Battery powered domain data - register (BPR_DTx) - 0x14 - 0x20 - read-write - 0x00000000 - - - DT6 - BPR data6 - 0 - 16 - - - - - DT7 - DT7 - Battery powered domain data - register (BPR_DTx) - 0x18 - 0x20 - read-write - 0x00000000 - - - DT7 - BPR data7 - 0 - 16 - - - - - DT8 - DT8 - Battery powered domain data - register (BPR_DTx) - 0x1C - 0x20 - read-write - 0x00000000 - - - DT8 - BPR data8 - 0 - 16 - - - - - DT9 - DT9 - Battery powered domain data - register (BPR_DTx) - 0x20 - 0x20 - read-write - 0x00000000 - - - DT9 - BPR data9 - 0 - 16 - - - - - DT10 - DT10 - Battery powered domain data - register (BPR_DTx) - 0x24 - 0x20 - read-write - 0x00000000 - - - DT10 - BPR data10 - 0 - 16 - - - - - DT11 - DT11 - Battery powered domain data - register (BPR_DTx) - 0x3C - 0x20 - read-write - 0x00000000 - - - DT11 - BPR data11 - 0 - 16 - - - - - DT12 - DT12 - Battery powered domain data - register (BPR_DTx) - 0x40 - 0x20 - read-write - 0x00000000 - - - DT12 - BPR data12 - 0 - 16 - - - - - DT13 - DT13 - Battery powered domain data - register (BPR_DTx) - 0x44 - 0x20 - read-write - 0x00000000 - - - DT13 - BPR data13 - 0 - 16 - - - - - DT14 - DT14 - Battery powered domain data - register (BPR_DTx) - 0x48 - 0x20 - read-write - 0x00000000 - - - DT14 - BPR data14 - 0 - 16 - - - - - DT15 - DT15 - Battery powered domain data - register (BPR_DTx) - 0x4C - 0x20 - read-write - 0x00000000 - - - DT15 - BPR data15 - 0 - 16 - - - - - DT16 - DT16 - Battery powered domain data - register (BPR_DTx) - 0x50 - 0x20 - read-write - 0x00000000 - - - DT16 - BPR data16 - 0 - 16 - - - - - DT17 - DT17 - Battery powered domain data - register (BPR_DTx) - 0x54 - 0x20 - read-write - 0x00000000 - - - DT17 - BPR data17 - 0 - 16 - - - - - DT18 - DT18 - Battery powered domain data - register (BPR_DTx) - 0x58 - 0x20 - read-write - 0x00000000 - - - DT18 - BPR data18 - 0 - 16 - - - - - DT19 - DT19 - Battery powered domain data - register (BPR_DTx) - 0x5C - 0x20 - read-write - 0x00000000 - - - DT19 - BPR data19 - 0 - 16 - - - - - DT20 - DT20 - Battery powered domain data - register (BPR_DTx) - 0x60 - 0x20 - read-write - 0x00000000 - - - DT20 - BPR data20 - 0 - 16 - - - - - DT21 - DT21 - Battery powered domain data - register (BPR_DTx) - 0x64 - 0x20 - read-write - 0x00000000 - - - DT21 - BPR data21 - 0 - 16 - - - - - DT22 - DT22 - Battery powered domain data - register (BPR_DTx) - 0x68 - 0x20 - read-write - 0x00000000 - - - DT22 - BPR data22 - 0 - 16 - - - - - DT23 - DT23 - Battery powered domain data - register (BPR_DTx) - 0x6C - 0x20 - read-write - 0x00000000 - - - DT23 - BPR data23 - 0 - 16 - - - - - DT24 - DT24 - Battery powered domain data - register (BPR_DTx) - 0x70 - 0x20 - read-write - 0x00000000 - - - DT24 - BPR data24 - 0 - 16 - - - - - DT25 - DT25 - Battery powered domain data - register (BPR_DTx) - 0x74 - 0x20 - read-write - 0x00000000 - - - DT25 - BPR data25 - 0 - 16 - - - - - DT26 - DT26 - Battery powered domain data - register (BPR_DTx) - 0x78 - 0x20 - read-write - 0x00000000 - - - DT26 - BPR data26 - 0 - 16 - - - - - DT27 - DT27 - Battery powered domain data - register (BPR_DTx) - 0x7C - 0x20 - read-write - 0x00000000 - - - DT27 - BPR data27 - 0 - 16 - - - - - DT28 - DT28 - Battery powered domain data - register (BPR_DTx) - 0x80 - 0x20 - read-write - 0x00000000 - - - DT28 - BPR data28 - 0 - 16 - - - - - DT29 - DT29 - Battery powered domain data - register (BPR_DTx) - 0x84 - 0x20 - read-write - 0x00000000 - - - DT29 - BPR data29 - 0 - 16 - - - - - DT30 - DT30 - Battery powered domain data - register (BPR_DTx) - 0x88 - 0x20 - read-write - 0x00000000 - - - DT30 - BPR data30 - 0 - 16 - - - - - DT31 - DT31 - Battery powered domain data - register (BPR_DTx) - 0x8C - 0x20 - read-write - 0x00000000 - - - DT31 - BPR data31 - 0 - 16 - - - - - DT32 - DT32 - Battery powered domain data - register (BPR_DTx) - 0x90 - 0x20 - read-write - 0x00000000 - - - DT32 - BPR data32 - 0 - 16 - - - - - DT33 - DT33 - Battery powered domain data - register (BPR_DTx) - 0x94 - 0x20 - read-write - 0x00000000 - - - DT33 - BPR data33 - 0 - 16 - - - - - DT34 - DT34 - Battery powered domain data - register (BPR_DTx) - 0x98 - 0x20 - read-write - 0x00000000 - - - DT34 - BPR data34 - 0 - 16 - - - - - DT35 - DT35 - Battery powered domain data - register (BPR_DTx) - 0x9C - 0x20 - read-write - 0x00000000 - - - DT35 - BPR data35 - 0 - 16 - - - - - DT36 - DT36 - Battery powered domain data - register (BPR_DTx) - 0xA0 - 0x20 - read-write - 0x00000000 - - - DT36 - BPR data36 - 0 - 16 - - - - - DT37 - DT37 - Battery powered domain data - register (BPR_DTx) - 0xA4 - 0x20 - read-write - 0x00000000 - - - DT37 - BPR data37 - 0 - 16 - - - - - DT38 - DT38 - Battery powered domain data - register (BPR_DTx) - 0xA8 - 0x20 - read-write - 0x00000000 - - - DT38 - BPR data38 - 0 - 16 - - - - - DT39 - DT39 - Battery powered domain data - register (BPR_DTx) - 0xAC - 0x20 - read-write - 0x00000000 - - - DT39 - BPR data39 - 0 - 16 - - - - - DT40 - DT40 - Battery powered domain data - register (BPR_DTx) - 0xB0 - 0x20 - read-write - 0x00000000 - - - DT40 - BPR data40 - 0 - 16 - - - - - DT41 - DT41 - Battery powered domain data - register (BPR_DTx) - 0xB4 - 0x20 - read-write - 0x00000000 - - - DT41 - BPR data41 - 0 - 16 - - - - - DT42 - DT42 - Battery powered domain data - register (BPR_DTx) - 0xB8 - 0x20 - read-write - 0x00000000 - - - DT42 - BPR data42 - 0 - 16 - - - - - RTCCAL - RTCCAL - RTC clock calibration register - (BPR_RTCCAL) - 0x28 - 0x20 - read-write - 0x00000000 - - - CALVAL - Calibration value - 0 - 7 - - - CALOUT - Calibration Clock Output - 7 - 1 - - - OUTEN - Output enable - 8 - 1 - - - OUTSEL - Output selection - 9 - 1 - - - - - CTRL - CTRL - BPR control register - (BPR_CTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TPEN - Tamper pin enable - 0 - 1 - - - TPP - TAMPER pin polarity - 1 - 1 - - - - - CTRLSTS - CTRLSTS - BPR control/status register - (BPR_CTRLSTS) - 0x30 - 0x20 - 0x00000000 - - - TPEFCLR - Tamper event flag clear - 0 - 1 - write-only - - - TPIFCLR - Tamper interrupt flag clear - 1 - 1 - write-only - - - TPIEN - Tamper pin interrupt enable - 2 - 1 - read-write - - - TPEF - Tamper event flag - 8 - 1 - read-write - - - TPIF - Tamper interrupt flag - 9 - 1 - read-write - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR8 - 0x40013400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - MSSEL - Master slave mode select - 16 - 4 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ADC2ODT - ADC2 conversion data of ordinary channel - 16 - 16 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - ADC2 - Analog to digital converter - ADC - 0x40012800 - - 0x0 - 0x400 - registers - - - ADC1_2 - ADC1 and ADC2 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - USBFS_H_CAN1_TX - CAN1 TX interrupt - 19 - - - USBFS_L_CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 68 - - - CAN2_RX0 - CAN2 RX0 interrupt - 69 - - - CAN2_RX1 - CAN2 RX1 interrupt - 70 - - - CAN2_SE - CAN2 SE interrupt - 71 - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 17 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 21 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK3 - UNLOCK3 - Unlock 3 register - 0x84 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - SELECT - SELECT - Select register - 0x88 - 0x20 - write-only - 0x00000000 - - - SELECT - spim type selection - 0 - 32 - - - - - STS3 - STS3 - Status 3 register - 0x8C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL3 - CTRL3 - Control 3 register - 0x90 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - CHPERS - Chip erase - 2 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR3 - ADDR3 - Address 3 register - 0x94 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - DA - DA - Spim decryption address - 0x98 - 0x20 - write-only - 0x00000000 - - - FDA - Flash decryption address - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - read-only - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - read-only - - - SLIB_ES - sLib end sector - 22 - 10 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 7 - - - CRC_SN - CRC sector numbler - 7 - 7 - - - CRC_STRT - CRC start - 14 - 1 - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USBFS - Universal serial bus full-speed device - interface - USBFS - 0x40005C00 - - 0x0 - 0x400 - registers - - - - EPT0 - EPT0 - endpoint 0 register - 0x0 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT1 - EPT1 - endpoint 1 register - 0x4 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT2 - EPT2 - endpoint 2 register - 0x8 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT3 - EPT3 - endpoint 3 register - 0xC - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT4 - EPT4 - endpoint 4 register - 0x10 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT5 - EPT5 - endpoint 5 register - 0x14 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT6 - EPT6 - endpoint 6 register - 0x18 - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - EPT7 - EPT7 - endpoint 7 register - 0x1C - 0x20 - read-write - 0x00000000 - - - EPTADDR - Endpoint address - 0 - 4 - - - TXSTS - Tx status - 4 - 2 - - - TXDTS - Tx data toggle synchronization - 6 - 1 - - - TXTC - Tx transaction completed - 7 - 1 - - - EXF - Endpoint extend function - 8 - 1 - - - TRANS_TYPE - Transfer type - 9 - 2 - - - SETUPTC - Setup transaction - completed - 11 - 1 - - - RXSTS - Rx Status - 12 - 2 - - - RXDTS - Rx data toggle synchronization - 14 - 1 - - - RXTC - Rx transaction completed - 15 - 1 - - - - - CTRL - CTRL - control register - 0x40 - 0x20 - read-write - 0x00000003 - - - CSRST - Core soft reset - 0 - 1 - - - DISUSB - Disable usb phy - 1 - 1 - - - LPM - Low power mode - 2 - 1 - - - SSP - Soft suspend config - 3 - 1 - - - GRESUME - Generate resume request - 4 - 1 - - - LSOFIEN - Lost start of frame interrupt enable - 8 - 1 - - - SOFIEN - Start of frame interrupt - enable - 9 - 1 - - - RSTIEN - Bus reset interrupt enable - 10 - 1 - - - SPIEN - Bus suspend mode interrupt - enable - 11 - 1 - - - WKIEN - Wakeup/Remote wakeup interrupt enable - 12 - 1 - - - BEIEN - Bus error interrupt enable - 13 - 1 - - - UCFORIEN - USB Core fifo overrun - interrupt enable - 14 - 1 - - - TCIEN - transmission completed interrupt - enable - 15 - 1 - - - - - INTSTS - INTSTS - interrupt status register - 0x44 - 0x20 - read-write - 0x00000000 - - - EPT_NUM - Endpoint number - 0 - 4 - - - INOUT - In/Out transaction - 4 - 1 - - - LSOF - Lost start of frame - 8 - 1 - - - SOF - start of frame - 9 - 1 - - - RST - Bus reset - 10 - 1 - - - SP - Bus suspend - 11 - 1 - - - WK - Wakeup - 12 - 1 - - - BE - Bus error - 13 - 1 - - - UCFOR - USB core fifo overrun memory - 14 - 1 - - - TC - transaction completed - 15 - 1 - - - - - SOFRNUM - SOFRNUM - frame number register - 0x48 - 0x20 - read-write - 0x0000 - - - SOFNUM - Start of frame number - 0 - 11 - - - LSOFNUM - Lost start of frame number - 11 - 2 - - - CLCK - Connect locked - 13 - 1 - - - DMSTS - DM status - 14 - 1 - - - DPSTS - DP status - 15 - 1 - - - - - DEVADDR - DEVADDR - device address - 0x4C - 0x20 - read-write - 0x0000 - - - ADDR - Host assign device address - 0 - 7 - - - CEN - USB core enable - 7 - 1 - - - - - BUFTBL - BUFTBL - Buffer table address - 0x50 - 0x20 - read-write - 0x0000 - - - BTADDR - Endpoint buffer table start address - 3 - 13 - - - - - CFG - CFG - CFG control register - 0x60 - 0x20 - read-write - 0x0000 - - - SOFOUTEN - SOF output enable - 0 - 1 - - - - - - - diff --git a/hw/bsp/at32f413/boards/AT_START_F413/board.h b/hw/bsp/at32f413/boards/AT_START_F413/board.h index f0bf0e4ae..13ec7a207 100644 --- a/hw/bsp/at32f413/boards/AT_START_F413/board.h +++ b/hw/bsp/at32f413/boards/AT_START_F413/board.h @@ -52,7 +52,7 @@ static inline void board_vbus_sense_init(void) { - + } #ifdef __cplusplus diff --git a/hw/bsp/at32f413/family.c b/hw/bsp/at32f413/family.c index a38fe450e..ffaf892e7 100644 --- a/hw/bsp/at32f413/family.c +++ b/hw/bsp/at32f413/family.c @@ -50,7 +50,7 @@ void USBFSWakeUp_IRQHandler(void) { tud_int_handler(0); } -void board_init(void) +void board_init(void) { system_clock_config(); @@ -62,7 +62,7 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); - + /* enable usb clock */ crm_periph_clock_enable(CRM_USB_PERIPH_CLOCK, TRUE); @@ -228,7 +228,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -252,16 +252,16 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } - + void SVC_Handler(void) { } diff --git a/hw/bsp/at32f413/family.mk b/hw/bsp/at32f413/family.mk index c56d1064c..a88c248dd 100644 --- a/hw/bsp/at32f413/family.mk +++ b/hw/bsp/at32f413/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F413_SDK = hw/mcu/artery/at32f413 -DEPS_SUBMODULES += $(AT32F413_SDK) # AT32 SDK path AT32F413_SDK_SRC = $(AT32F413_SDK)/libraries diff --git a/hw/bsp/at32f413/startup_at32f413.s b/hw/bsp/at32f413/startup_at32f413.s index 4fc1f2a86..42631da93 100644 --- a/hw/bsp/at32f413/startup_at32f413.s +++ b/hw/bsp/at32f413/startup_at32f413.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h index 73889ebf9..c7932efc0 100644 --- a/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f415/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f415/at32f415_clock.c b/hw/bsp/at32f415/at32f415_clock.c index d78f1bb8a..3d137fcd2 100644 --- a/hw/bsp/at32f415/at32f415_clock.c +++ b/hw/bsp/at32f415/at32f415_clock.c @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -46,8 +46,8 @@ void system_clock_config(void) { /* config flash psr register */ - flash_psr_set(FLASH_WAIT_CYCLE_4); - + flash_psr_set(FLASH_WAIT_CYCLE_4); + /* reset crm */ crm_reset(); diff --git a/hw/bsp/at32f415/at32f415_clock.h b/hw/bsp/at32f415/at32f415_clock.h index a4a2ec1cf..71f204f8b 100644 --- a/hw/bsp/at32f415/at32f415_clock.h +++ b/hw/bsp/at32f415/at32f415_clock.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif /* __AT32F415_CLOCK_H */ - diff --git a/hw/bsp/at32f415/at32f415_conf.h b/hw/bsp/at32f415/at32f415_conf.h index ddee93c75..284eee7d2 100644 --- a/hw/bsp/at32f415/at32f415_conf.h +++ b/hw/bsp/at32f415/at32f415_conf.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -141,5 +141,3 @@ extern "C" { #endif #endif /* __AT32F415_CONF_H */ - - diff --git a/hw/bsp/at32f415/at32f415_int.c b/hw/bsp/at32f415/at32f415_int.c index 40d2d44fb..c52adaf9a 100644 --- a/hw/bsp/at32f415/at32f415_int.c +++ b/hw/bsp/at32f415/at32f415_int.c @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -28,11 +28,11 @@ /** @addtogroup AT32F415_periph_examples * @{ */ - + /** @addtogroup 415_CRC_calculation * @{ */ - + /** * @brief this function handles nmi exception. * @param none @@ -52,9 +52,9 @@ void MemManage_Handler(void) /* go to infinite loop when memory manage exception occurs */ while(1) - { + { } - + } /** @@ -112,8 +112,8 @@ void DebugMon_Handler(void) /** * @} - */ + */ /** * @} - */ + */ diff --git a/hw/bsp/at32f415/at32f415_int.h b/hw/bsp/at32f415/at32f415_int.h index 21119e52d..2106538b6 100644 --- a/hw/bsp/at32f415/at32f415_int.h +++ b/hw/bsp/at32f415/at32f415_int.h @@ -5,11 +5,11 @@ ************************************************************************** * Copyright notice & Disclaimer * - * The software Board Support Package (BSP) that is made available to - * download from Artery official website is the copyrighted work of Artery. - * Artery authorizes customers to use, copy, and distribute the BSP - * software and its related documentation for the purpose of design and - * development in conjunction with Artery microcontrollers. Use of the + * The software Board Support Package (BSP) that is made available to + * download from Artery official website is the copyrighted work of Artery. + * Artery authorizes customers to use, copy, and distribute the BSP + * software and its related documentation for the purpose of design and + * development in conjunction with Artery microcontrollers. Use of the * software is governed by this copyright notice and the following disclaimer. * * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES, @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld index baf2e7d71..6da817705 100644 --- a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld +++ b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd b/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd deleted file mode 100644 index cd22346c7..000000000 --- a/hw/bsp/at32f415/boards/AT_START_F415/AT32F415xx_v2.svd +++ /dev/null @@ -1,27108 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F415xx_v2 - AT32F415 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 150MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control register - (PWC_CTRLST) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN - Standby wake-up pin enable - 8 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - IOMUXRST - MUX function I/O - reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - GPIOARST - IO port A reset - 2 - 1 - - - GPIOBRST - IO port B reset - 3 - 1 - - - GPIOCRST - IO port C reset - 4 - 1 - - - GPIODRST - IO port D reset - 5 - 1 - - - GPIOFRST - IO port F reset - 7 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - TMR1RST - Timer1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR9RST - Timer9 reset - 19 - 1 - - - TMR10RST - Timer10 reset - 20 - 1 - - - TMR11RST - Timer11 reset - 21 - 1 - - - ACCRST - ACC reset - 22 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR4RST - Timer 4 reset - 2 - 1 - - - TMR5RST - Timer 5 reset - 3 - 1 - - - CMPRST - Comparator reset - 9 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - UART4RST - UART 4 reset - 19 - 1 - - - UART5RST - UART 5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - DMA2EN - DMA2 clock enable - 1 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - SDIO1EN - SDIO1 clock enable - 10 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 12 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - IOMUXEN - MUX function I/O clock - enable - 0 - 1 - - - GPIOAEN - I/O port A clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 3 - 1 - - - GPIOCEN - I/O port C clock enable - 4 - 1 - - - GPIODEN - I/O port D clock enable - 5 - 1 - - - GPIOFEN - I/O port F clock enable - 7 - 1 - - - ADC1EN - ADC1 clock - enable - 9 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 19 - 1 - - - TMR10EN - Timer10 clock enable - 20 - 1 - - - TMR11EN - Timer11 clock enable - 21 - 1 - - - ACCEN - ACC clock enable - 22 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - CMPEN - Comparator clock enable - 9 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 12 - 1 - read-write - - - - - PLL - PLL - PLL configuration register - (RCC_PLL) - 0x2C - 0x20 - 0x00001F10 - - - PLL_FR - PLL_FR - 0 - 3 - read-write - - - PLL_MS - PLL_MS - 4 - 4 - read-write - - - PLL_NS - PLL_NS - 8 - 9 - read-write - - - PLL_FREF - PLL entry clock reference frequency - 24 - 3 - read-write - - - PLLCFGEN - PLL config enable - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - OTG_EXTCTRL - OTG_EXTCTRL - OTGFS external ctrl register1 - 0x44 - 0x20 - 0x00000000 - - - USBDIV_RST - USB divider reset - 30 - 1 - read-write - - - EP3_RMPEN - OTGFS end-point 3 remap enable - 31 - 1 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x54 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - HICK_TO_USB - HICK to usb clock - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - - - GPIOA - General purpose IO - GPIO - 0x40010800 - - 0x0 - 0x400 - registers - - - - CFGLR - CFGLR - GPIO function configurate low register - 0x0 - 0x20 - read-write - 0x44444444 - - - IOMC0 - Port n.0 mode configurate bits - 0 - 2 - - - IOFC0 - Port n.0 function configurate - bits - 2 - 2 - - - IOMC1 - Port n.1 mode configurate bits - 4 - 2 - - - IOFC1 - Port n.1 function configurate - bits - 6 - 2 - - - IOMC2 - Port n.2 mode configurate bits - 8 - 2 - - - IOFC2 - Port n.2 function configurate - bits - 10 - 2 - - - IOMC3 - Port n.3 mode configurate bits - 12 - 2 - - - IOFC3 - Port n.3 function configurate - bits - 14 - 2 - - - IOMC4 - Port n.4 mode configurate bits - 16 - 2 - - - IOFC4 - Port n.4 function configurate - bits - 18 - 2 - - - IOMC5 - Port n.5 mode configurate bits - 20 - 2 - - - IOFC5 - Port n.5 function configurate - bits - 22 - 2 - - - IOMC6 - Port n.6 mode configurate bits - 24 - 2 - - - IOFC6 - Port n.6 function configurate - bits - 26 - 2 - - - IOMC7 - Port n.7 mode configurate bits - 28 - 2 - - - IOFC7 - Port n.7 function configurate - bits - 30 - 2 - - - - - CFGHR - CFGHR - GPIO function configurate high register - 0x4 - 0x20 - read-write - 0x44444444 - - - IOMC8 - Port n.8 mode configurate bits - 0 - 2 - - - IOFC8 - Port n.8 function configurate - bits - 2 - 2 - - - IOMC9 - Port n.9 mode configurate bits - 4 - 2 - - - IOFC9 - Port n.9 function configurate - bits - 6 - 2 - - - IOMC10 - Port n.10 mode configurate bits - 8 - 2 - - - IOFC10 - Port n.10 function configurate - bits - 10 - 2 - - - IOMC11 - Port n.11 mode configurate bits - 12 - 2 - - - IOFC11 - Port n.11 function configurate - bits - 14 - 2 - - - IOMC12 - Port n.12 mode configurate bits - 16 - 2 - - - IOFC12 - Port n.12 function configurate - bits - 18 - 2 - - - IOMC13 - Port n.13 mode configurate bits - 20 - 2 - - - IOFC13 - Port n.13 function configurate - bits - 22 - 2 - - - IOMC14 - Port n.14 mode configurate bits - 24 - 2 - - - IOFC14 - Port n.14 function configurate - bits - 26 - 2 - - - IOMC15 - Port n.15 mode configurate bits - 28 - 2 - - - IOFC15 - Port n.15 function configurate - bits - 30 - 2 - - - - - IDT - IDT - Port input data register - 0x8 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - Port output data register - 0xC - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x10 - 0x20 - read-write - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - CLR - CLR - Port bit reset register - 0x14 - 0x20 - read-write - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - WPR - WPR - Port write protect - register - 0x18 - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - - - GPIOB - 0x40010C00 - - - GPIOC - 0x40011000 - - - GPIOD - 0x40011400 - - - GPIOF - 0x40011C00 - - - IOMUX - IO MUX function - IOMUX - 0x40010000 - - 0x0 - 0x400 - registers - - - - EVTOUT - EVTOUT - Event output register - (IOMUX_EVTOUT) - 0x0 - 0x20 - read-write - 0x00000000 - - - SELPIN - Select pin - 0 - 4 - - - SELPORT - Select port - 4 - 3 - - - EVOEN - Event output enable - 7 - 1 - - - - - REMAP - REMAP - IO MUX remap register - 0x4 - 0x20 - 0x00000000 - - - SPI1_MUX0 - SPI1 muxing bit0 - 0 - 1 - read-write - - - I2C1_MUX - I2C1 muxing - 1 - 1 - read-write - - - USART1_MUX - USART1 muxing - 2 - 1 - read-write - - - USART3_MUX - USART3 muxing - 4 - 2 - read-write - - - TMR1_MUX - TMR1 muxing - 6 - 2 - read-write - - - TMR2_MUX - TMR2 muxing - 8 - 2 - read-write - - - TMR3_MUX - TMR3 muxing - 10 - 2 - read-write - - - CAN_MUX - CAN1 muxing - 13 - 2 - read-write - - - PD01_MUX - PD0/PD1 muxing on OSCIN/OSCOUT - 15 - 1 - read-write - - - TMR5CH4_MUX - TMR5 channel4 internal muxing - 16 - 1 - read-write - - - ADC1_ETP_MUX - ADC1 external trigger preempted conversion muxing - 17 - 1 - read-write - - - ADC1_ETO_MUX - ADC1 external trigger ordinary conversion muxing - 18 - 1 - read-write - - - SWJTAG_MUX - SWD JTAG muxing - 24 - 3 - read-write - - - SPI1_MUX1 - SPI1 muxing bit1 - 31 - 1 - read-write - - - - - EXINTC1 - EXINTC1 - External interrupt configuration register 1 - (IOMUX_EXINTC1) - 0x8 - 0x20 - read-write - 0x00000000 - - - EXINT0 - Configure EXINT0 source - 0 - 4 - - - EXINT1 - Configure EXINT1 source - 4 - 4 - - - EXINT2 - Configure EXINT2 source - 8 - 4 - - - EXINT3 - Configure EXINT3 source - 12 - 4 - - - - - EXINTC2 - EXINTC2 - External interrupt configuration register 2 - (IOMUX_EXINTC2) - 0xC - 0x20 - read-write - 0x00000000 - - - EXINT4 - Configure EXINT4 source - 0 - 4 - - - EXINT5 - Configure EXINT5 source - 4 - 4 - - - EXINT6 - Configure EXINT6 source - 8 - 4 - - - EXINT7 - Configure EXINT7 source - 12 - 4 - - - - - EXINTC3 - EXINTC3 - External interrupt configuration register 3 - (IOMUX_EXINTC3) - 0x10 - 0x20 - read-write - 0x00000000 - - - EXINT8 - Configure EXINT8 source - 0 - 4 - - - EXINT9 - Configure EXINT9 source - 4 - 4 - - - EXINT10 - Configure EXINT10 source - 8 - 4 - - - EXINT11 - Configure EXINT11 source - 12 - 4 - - - - - EXINTC4 - EXINTC4 - External interrupt configuration register 4 - (IOMUX_EXINTC4) - 0x14 - 0x20 - read-write - 0x00000000 - - - EXINT12 - Configure EXINT12 source - 0 - 4 - - - EXINT13 - Configure EXINT13 source - 4 - 4 - - - EXINT14 - Configure EXINT14 source - 8 - 4 - - - EXINT15 - Configure EXINT15 source - 12 - 4 - - - - - REMAP2 - REMAP2 - IO MUX remap register 2 - 0x1C - 0x20 - write-only - 0x00000000 - - - CMP_MUX - CMP internal muxing - 26 - 2 - - - - - REMAP3 - REMAP3 - IO MUX remap register 3 - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR11_GMUX - TMR11 muxing - 8 - 4 - - - TMR10_GMUX - TMR10 muxing - 4 - 4 - - - TMR9_GMUX - TMR9 muxing - 0 - 4 - - - - - REMAP4 - REMAP4 - IO MUX remap register 4 - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR5CH4_GMUX - TMR5CH4 muxing - 19 - 1 - - - TMR5_GMUX - TMR5 muxing - 16 - 3 - - - TMR3_GMUX - TMR3 muxing - 8 - 4 - - - TMR2_GMUX - TMR2 muxing - 4 - 3 - - - TMR1_GMUX - TMR1 muxing - 0 - 4 - - - - - REMAP5 - REMAP5 - IO MUX remap register 5 - 0x28 - 0x20 - read-write - 0x00000000 - - - SPI2_GMUX - SPI2 muxing - 20 - 4 - - - SPI1_GMUX - SPI1 muxing - 16 - 4 - - - I2C2_GMUX - I2C2 muxing - 8 - 4 - - - I2C1_GMUX - I2C1 muxing - 4 - 4 - - - - - REMAP6 - REMAP6 - IO MUX remap register 6 - 0x2C - 0x20 - read-write - 0x00000000 - - - UART4_GMUX - UART4 muxing - 28 - 4 - - - USART3_GMUX - USART3 muxing - 24 - 4 - - - USART1_GMUX - USART1 muxing - 16 - 4 - - - SDIO1_GMUX - SDIO1 muxing - 8 - 4 - - - CAN1_GMUX - CAN1 muxing - 0 - 4 - - - - - REMAP7 - REMAP7 - IO MUX remap register 7 - 0x30 - 0x20 - read-write - 0x00000000 - - - PD01_GMUX - PortD0/PortD1 muxing on OSC_IN/OSC_OUT - 20 - 1 - - - SWJTAG_GMUX - Serial wire JTAG muxing - 16 - 3 - - - ADC1_ETO_GMUX - ADC1 external trigger ordinary conversion muxing - 5 - 1 - - - ADC1_ETP_GMUX - ADC1 external trigger preempted conversion muxing - 4 - 1 - - - - - REMAP8 - REMAP8 - IO MUX remap register 8 - 0x34 - 0x20 - read-write - 0x00000000 - - - TMR3_CH1_CMP_GMUX - TMR3 CH1 CMP muxing - 6 - 2 - - - TMR2_CH4_CMP_GMUX - TMR2 CH4 CMP muxing - 4 - 2 - - - TMR1_CH1_CMP_GMUX - TMR1 CH1 CMP muxing - 2 - 2 - - - TMR1_BK1_CMP_GMUX - TMR1 BK1 CMP muxing - 0 - 2 - - - - - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - PVM - PVD interrupt - 1 - - - ERTC - ERTC interrupt - 3 - - - TAMPER - Tamper interrupt - 2 - - - ERTCAlarm - ERTCAlarm interrupt - 41 - - - CMP1 - CMP1 interrupt - 70 - - - CMP2 - CMP2 interrupt - 71 - - - EXTINT0 - EXTI Line0 interrupt - 6 - - - EXTINT1 - EXTI Line1 interrupt - 7 - - - EXTINT2 - EXTI Line2 interrupt - 8 - - - EXTINT3 - EXTI Line3 interrupt - 9 - - - EXTINT4 - EXTI Line4 interrupt - 10 - - - EXTINT9_5 - EXTI Line[9:5] interrupts - 23 - - - EXTINT15_10 - EXTI Line[15:10] interrupts - 40 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - DMA2 - 0x40020400 - - DMA2_Channel1 - DMA2 Channel1 global interrupt - 56 - - - DMA2_Channel2 - DMA2 Channel2 global interrupt - 57 - - - DMA2_Channel3 - DMA2 Channel3 global interrupt - 58 - - - DMA2_Channel4_5 - DMA2 Channel4 and DMA2 Channel5 global - interrupt - 59 - - - DMA2_Channel6_7 - DMA2 Channel6 and DMA2 Channel7 global - interrupt - 75 - - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x40018000 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - POWER - POWER - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PWRCTRL - PWRCTRL - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SDI clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKPSC - Clock divide factor - 0 - 8 - - - CLKEN - Clock enable bit - 8 - 1 - - - PWRSVG - Power saving configuration - bit - 9 - 1 - - - BYPS - Clock divider bypass enable - bit - 10 - 1 - - - BUSWIDTH - Wide bus mode enable bit - 11 - 2 - - - CLKEDG - SDIO_CK dephasing selection - bit - 13 - 1 - - - FLWCTRLEN - HW Flow Control enable - 14 - 1 - - - CLKPSC98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARG - ARG - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARG - Command argument - 0 - 32 - - - - - CMD - CMD - SDIO command register - (SDIO_CMD) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - WAITRESP - 6 - 2 - - - INTWT - WAITINT - 8 - 1 - - - PNDWT - WAITPEND - 9 - 1 - - - CMDMEN - CPSMEN - 10 - 1 - - - SDIOSUSP - SDIOSuspend - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS3 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS4 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = DATATIME: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - SDIOEN - SDIOEN - 11 - 1 - - - - - DTCNTR - DTCNTR - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STS) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - CCRCFAIL - 0 - 1 - - - DTFAIL - DCRCFAIL - 1 - 1 - - - CMDTIMEOUT - CTIMEOUT - 2 - 1 - - - DTTIMEOUT - DTIMEOUT - 3 - 1 - - - TXERRU - TXUNDERR - 4 - 1 - - - RXERRO - RXOVERR - 5 - 1 - - - CMDRSPCMPL - CMDREND - 6 - 1 - - - CMDCMPL - CMDSENT - 7 - 1 - - - DTCMPL - DATAEND - 8 - 1 - - - SBITERR - STBITERR - 9 - 1 - - - DTBLKCMPL - DBCKEND - 10 - 1 - - - DOCMD - CMDACT - 11 - 1 - - - DOTX - TXACT - 12 - 1 - - - DORX - RXACT - 13 - 1 - - - TXBUF_H - TXFIFOHE - 14 - 1 - - - RXBUF_H - RXFIFOHF - 15 - 1 - - - TXBUF_F - TXFIFOF - 16 - 1 - - - RXBUF_F - RXFIFOF - 17 - 1 - - - TXBUF_E - TXFIFOE - 18 - 1 - - - RXBUF_E - RXFIFOE - 19 - 1 - - - TXBUF - TXDAVL - 20 - 1 - - - RXBUF - RXDAVL - 21 - 1 - - - SDIOIF - SDIOIT - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - CCRCFAILC - 0 - 1 - - - DTFAIL - DCRCFAILC - 1 - 1 - - - CMDTIMEOUT - CTIMEOUTC - 2 - 1 - - - DTTIMEOUT - DTIMEOUTC - 3 - 1 - - - TXERRU - TXUNDERRC - 4 - 1 - - - RXERRU - RXOVERRC - 5 - 1 - - - CMDRSPCMPL - CMDRENDC - 6 - 1 - - - CMDCMPL - CMDSENTC - 7 - 1 - - - DTCMPL - DATAENDC - 8 - 1 - - - SBITERR - STBITERRC - 9 - 1 - - - DTBLKCMPL - DBCKENDC - 10 - 1 - - - SDIOIF - SDIOITC - 22 - 1 - - - - - INTEN - INTEN - SDIO interrupt enable register - (SDIO_INTEN) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAIL - CCRCFAILIE - 0 - 1 - - - DTFAIL - DCRCFAILIE - 1 - 1 - - - CMDTIMEOUT - CTIMEOUTIE - 2 - 1 - - - DTTIMEOUT - DTIMEOUTIE - 3 - 1 - - - TXERRU - TXUNDERRIE - 4 - 1 - - - RXERRU - RXOVERRIE - 5 - 1 - - - CMDRSPCMPL - CMDRENDIE - 6 - 1 - - - CMDCMPL - CMDSENTIE - 7 - 1 - - - DTCMPL - DATAENDIE - 8 - 1 - - - SBITERR - STBITERRIE - 9 - 1 - - - DTBLKCMPL - DBACKENDIE - 10 - 1 - - - DOCMD - CMDACTIE - 11 - 1 - - - DOTX - TXACTIE - 12 - 1 - - - DORX - RXACTIE - 13 - 1 - - - TXBUF_H - TXFIFOHEIE - 14 - 1 - - - RXBUF_H - RXFIFOHFIE - 15 - 1 - - - TXBUF_F - TXFIFOFIE - 16 - 1 - - - RXBUF_F - RXFIFOFIE - 17 - 1 - - - TXBUF_E - TXFIFOEIE - 18 - 1 - - - RXBUF_E - RXFIFOEIE - 19 - 1 - - - TXBUF - TXDAVLIE - 20 - 1 - - - RXBUF - RXDAVLIE - 21 - 1 - - - SDIOIF - SDIOITIE - 22 - 1 - - - - - BUFCNTR - BUFCNTR - Bits 23:0 = FIFOCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = FIFOData: Receive and transmit - FIFO data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - FIFOData - 0 - 32 - - - - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40015800 - - 0x0 - 0x400 - registers - - - ACC - ACC global interrupt - 72 - - - - STS - STS - Status register - 0x0 - 0x20 - read-write - 0x00000000 - - - CALRDY - Internal high-speed clock calibration ready - 0 - 1 - - - RSLOST - Reference Signal Lost - 1 - 1 - - - - - CTRL1 - CTRL1 - Control register 1 - 0x4 - 0x20 - read-write - 0x00000100 - - - CALON - Internal high-speed clock calibration ready - 0 - 1 - - - ENTRIM - Enable trim - 1 - 1 - - - EIEN - RSLOST error interrupt enable - 4 - 1 - - - CALRDYIEN - CALRDY interrupt enable - 5 - 1 - - - STEP - STEP - 8 - 4 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x8 - 0x20 - read-only - 0x00002080 - - - ACC_HSICAL - Internal high-speed auto clock calibration - 0 - 8 - - - ACC_HSITRIM - Internal high-speed auto clock trimming - 8 - 6 - - - - - C1 - C1 - Compare 1 - 0xC - 0x20 - read-write - 0x00001F2C - - - C1 - Compare 1 - 0 - 16 - - - - - C2 - C2 - Compare 2 - 0x10 - 0x20 - read-write - 0x00001F40 - - - C2 - Compare 2 - 0 - 16 - - - - - C3 - C3 - Compare 3 - 0x14 - 0x20 - read-write - 0x00001F54 - - - C3 - Compare 3 - 0 - 16 - - - - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - read-write - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-write - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - 0x40000C00 - - TMR5 - TMR5 global interrupt - 50 - - - - TMR9 - General purpose timer - TIMER - 0x40014C00 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR10 - General purpose timer - TIMER - 0x40015000 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40015400 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - RESET - I2C peripheral reset - 15 - 1 - - - SMBALERT - SMBus alert pin set - 13 - 1 - - - PECTEN - Request PEC transmission enable - 12 - 1 - - - MACKCTRL - Master receiving mode acknowledge control - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - GENSTOP - Stop generation - 9 - 1 - - - GENSTART - Start generation - 8 - 1 - - - STRETCH - Clock stretching mode - 7 - 1 - - - GCAEN - General call address enable - 6 - 1 - - - PECEN - PEC calculation enable - 5 - 1 - - - ARPEN - SMBus address resolution protocol enable - 4 - 1 - - - SMBMODE - SMBus device mode - 3 - 1 - - - PERMODE - I2C peripheral mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - DMAEND - DMA transfer end indication - 12 - 1 - - - DMAEN - DMA transfer enable - 11 - 1 - - - DATAIEN - Data transmission interrupt enable - 10 - 1 - - - EVTIEN - Event interrupt enable - 9 - 1 - - - ERRIEN - Error interrupt enable - 8 - 1 - - - CLKFREQ - Input clock frequency - 0 - 8 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADDR1MODE - Address mode - 15 - 1 - - - ADDR1 - Own address 1 - 0 - 10 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x0000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2EN - Own address 2 enable - 0 - 1 - - - - - DT - DT - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DT - data register - 0 - 8 - - - - - STS1 - STS1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - ALERTF - SMBus alert - 15 - 1 - read-write - - - TMOUT - Timeout error - 14 - 1 - read-write - - - PECERR - PEC receive error - 12 - 1 - read-write - - - OUF - Overflow or underflow - 11 - 1 - read-write - - - ACKFAIL - Acknowledge failure - 10 - 1 - read-write - - - ARLOST - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BUSERR - Bus error - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - (transmitters) - 7 - 1 - read-only - - - RDBF - Receive data buffer full - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADDRHF - address header match (Master - mode) - 3 - 1 - read-only - - - TDC - Transmit data complete - 2 - 1 - read-only - - - ADDR7F - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - STARTF - Start bit (Master mode) - 0 - 1 - read-only - - - - - STS2 - STS2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PECVAL - PEC value - 8 - 8 - - - ADDR2F - Received address 2 - 7 - 1 - - - HOSTADDRF - SMBus host address receiving - 6 - 1 - - - DEVADDRF - SMBus device address receiving - 5 - 1 - - - GCADDRF - General call address reception - 4 - 1 - - - DIRF - Transmission direction - 2 - 1 - - - BUSYF - Bus busy - 1 - 1 - - - TRMODE - Transmission mode - 0 - 1 - - - - - CLKCTRL - CLKCTRL - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - SPEEDMODE - Speed mode selection - 15 - 1 - - - DUTYMODE - Fast mode duty cycle - 14 - 1 - - - SPEED - I2C bus speed config - 0 - 12 - - - - - TMRISE - TMRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - I2C bus rise time - 0 - 6 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UEN - USART enable - 13 - 1 - - - DBN - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - ADC1 - Analog to digital converter - ADC1 - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1 - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 25 - 1 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 24 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN1_RX1 - CAN1 RX1 interrupt - 21 - - - CAN1_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CMP - Comparator - CMP - 0x40002400 - - 0x0 - 0x3FF - registers - - - CMP1 - CMP1 interrupt - 70 - - - CMP2 - CMP2 interrupt - 71 - - - - CTRLSTS1 - CTRLSTS1 - CMP control/status register1 - 0x0 - 0x20 - 0x00000000 - - - CMP1EN - Comparator1 enable bit - 0 - 1 - read-write - - - CMP1IS - Comparator1 input shift - 1 - 1 - read-write - - - CMP1SSEL - Comparator1 speed selection - 2 - 2 - read-write - - - CMP1INVSEL - Comparator1 inverting selection - 4 - 3 - read-write - - - CMP1TAG - Comparator1 output target - 8 - 3 - read-write - - - CMP1P - Comparator1 polarity - 11 - 1 - read-write - - - CMP1HYST - Comparator1 hysteresis - 12 - 2 - read-write - - - CMP1VALUE - Comparator1 output value - 14 - 1 - read-only - - - CMP1WP - Comparator1 write protect - 15 - 1 - read-write - - - CMP2EN - Comparator2 enable bit - 16 - 1 - read-write - - - CMP2SSEL - Comparator2 speed selection - 18 - 2 - read-write - - - CMP2INVSEL - Comparator2 inverting selection - 20 - 3 - read-write - - - DCMPEN - Double comparator mode enable - 23 - 1 - read-write - - - CMP2TAG - Comparator2 output target - 24 - 3 - read-write - - - CMP2P - Comparator2 polarity - 27 - 1 - read-write - - - CMP2HYST - Comparator2 hysteresis - 28 - 2 - read-write - - - CMP2VALUE - Comparator2 output value - 30 - 1 - read-only - - - CMP2WP - Comparator2 write protect - 31 - 1 - read-write - - - - - CTRLSTS2 - CTRLSTS2 - CMP control/status register2 - 0x4 - 0x20 - 0x00000000 - - - COMP1NINVSEL - Comparator1 non-inverting input selection - 0 - 2 - read-write - - - COMP2NINVSEL - Comparator2 non-inverting input selection - 16 - 2 - read-write - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - DEBUG_IDCODE - DEBUG_IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - MCUDBG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - TRACE_IOEN - TRACE_IOEN - 5 - 1 - - - TRACE_MODE - TRACE_MODE - 6 - 2 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 13 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 18 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 28 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 29 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 30 - 1 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - WTCYC - Wait cycle - 0 - 3 - read-write - - - HFCYC_EN - Half cycle acceleration access enable - 3 - 1 - read-write - - - PFT_EN - Prefetch enable - 4 - 1 - read-write - - - PFT_ENF - Prefetch enabled flag - 5 - 1 - read-only - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - FAP_HL_DIS - FAP high level disable - 16 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - FAP_HL - FAP high level - 26 - 1 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0x74 - 0x20 - read-only - 0x00000000 - - - BTM_AP_ENF - Boot memory store application code enabled flag - 0 - 1 - - - EM_SLIB_ENF - Extension memory sLib enabled flag - 2 - 1 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - - - EM_SLIB_DAT_SS - Extension memory sLib data start sector - 16 - 8 - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0x78 - 0x20 - read-only - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 11 - - - SLIB_DAT_SS - sLib data start sector - 11 - 11 - - - SLIB_ES - sLib end sector - 22 - 10 - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0x7C - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0x80 - 0x20 - 0x00000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - - - CRC_ADDR - CRC_ADDR - Flash CRC data start address register - 0x84 - 0x20 - write-only - 0x00000000 - - - CRC_ADDR - CRC address - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controll register - 0x88 - 0x20 - 0x00000000 - - - CRC_SN - CRC sector numbler - 0 - 16 - read-write - - - CRC_STRT - CRC start - 16 - 1 - write-only - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0x8C - 0x20 - read-only - 0x00000000 - - - FCRC_OUT - CRC32 verification result of flash user code or SLIB code - 0 - 32 - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0x160 - 0x20 - write-only - 0x00000000 - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0x164 - 0x20 - write-only - 0x00000000 - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_DSS_SET - sLib data start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - EM_SLIB_SET - EM_SLIB_SET - Extension momery slib set register - 0x168 - 0x20 - write-only - 0x00000000 - - - EM_SLIB_SET - Extension memory sLib setting - 0 - 16 - - - EM_SLIB_DSS_SET - Extension memory sLib data start sector setting - 16 - 8 - - - - - BTM_MODE_SET - BTM_MODE_SET - Boot memory mode setting register - 0x16C - 0x20 - write-only - 0x00000000 - - - BTM_MODE_SET - Boot memory mode setting - 0 - 8 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0x170 - 0x20 - write-only - 0x00000000 - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB_OTG_GLOBAL - USB on the go full speed - USB_OTG - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS - USB On The Go FS global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - AVALIDSESEN - sense Avalid enable - 18 - 1 - - - BVALIDSESEN - sense Bvalid enable - 19 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG_HOST - USB on the go full speed - USB_OTG - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG_DEVICE - USB on the go full speed - USB_OTG - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG_PWRCLK - USB on the go full speed - USB_OTG - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - diff --git a/hw/bsp/at32f415/family.c b/hw/bsp/at32f415/family.c index 6c7600783..53897243a 100644 --- a/hw/bsp/at32f415/family.c +++ b/hw/bsp/at32f415/family.c @@ -35,16 +35,16 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -85,7 +85,7 @@ void board_init(void) /* config led and key */ led_and_button_init(); - + /* config usart printf */ uart_print_init(115200); printf("usart printf config success!\r\n"); @@ -128,13 +128,13 @@ void usb_clock48m_select(usb_clk48_s clk_s) case 144000000: crm_usb_clock_div_set(CRM_USB_DIV_3); break; - + default: break; } } -void led_and_button_init(void) +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -190,7 +190,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -203,7 +203,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -224,17 +224,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -252,12 +252,12 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -271,7 +271,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f415/family.mk b/hw/bsp/at32f415/family.mk index d0cca67ab..7af6a8cb8 100644 --- a/hw/bsp/at32f415/family.mk +++ b/hw/bsp/at32f415/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F415_SDK = hw/mcu/artery/at32f415 -DEPS_SUBMODULES += $(AT32F415_SDK) # AT32 SDK path AT32F415_SDK_SRC = $(AT32F415_SDK)/libraries diff --git a/hw/bsp/at32f415/startup_at32f415.s b/hw/bsp/at32f415/startup_at32f415.s index 47a913e36..2c4dbc9ef 100644 --- a/hw/bsp/at32f415/startup_at32f415.s +++ b/hw/bsp/at32f415/startup_at32f415.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h index 06afc3860..d5f8aafb0 100644 --- a/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f423/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f423/at32f423_clock.c b/hw/bsp/at32f423/at32f423_clock.c index 1c9467588..564208fcb 100644 --- a/hw/bsp/at32f423/at32f423_clock.c +++ b/hw/bsp/at32f423/at32f423_clock.c @@ -125,4 +125,3 @@ void system_clock_config(void) /** * @} */ - diff --git a/hw/bsp/at32f423/at32f423_clock.h b/hw/bsp/at32f423/at32f423_clock.h index 183748b39..27079924d 100644 --- a/hw/bsp/at32f423/at32f423_clock.h +++ b/hw/bsp/at32f423/at32f423_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f423/at32f423_int.c b/hw/bsp/at32f423/at32f423_int.c index a39c7bdda..2b623e053 100644 --- a/hw/bsp/at32f423/at32f423_int.c +++ b/hw/bsp/at32f423/at32f423_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f423/at32f423_int.h b/hw/bsp/at32f423/at32f423_int.h index 0a807d6d6..28550331e 100644 --- a/hw/bsp/at32f423/at32f423_int.h +++ b/hw/bsp/at32f423/at32f423_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld index c6333cb1c..ee08e979a 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld +++ b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xC_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd b/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd deleted file mode 100644 index 4954c417f..000000000 --- a/hw/bsp/at32f423/boards/AT_START_F423/AT32F423xx_v2.svd +++ /dev/null @@ -1,36050 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F423xx_v2 - AT32F423 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL2 - BK1CTRL2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG2 - BK1TMG2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR2 - BK1TMGWR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT2 - EXT2 - externl timeing register 2 - 0x224 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - SWPEN6 - Standby wake-up pin 6 enable - 13 - 1 - read-write - - - SWPEN7 - Standby wake-up pin 7 enable - 14 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000000 - - - LDOOVSEL - LDO output voltage select - 0 - 2 - read-write - - - VREXLPEN - Voltage regulator extra low power mode enable - 4 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FR - PLL post-division - 16 - 3 - read-write - - - PLLRCS - PLL reference clock select - 22 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - CLKOUTDIV1 - Clock output division1 - 27 - 3 - read-write - - - CLKOUT_SEL1 - Clock output selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOERST - IO port E reset - 4 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - XMCRST - XMC reset - 0 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR12RST - Timer12 reset - 6 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - USART4RST - USART4 reset - 19 - 1 - - - USART5RST - USART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - USART7RST - USART7 reset - 30 - 1 - - - USART8RST - USART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOEEN - IO E clock enable - 4 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - XMCEN - XMC clock enable - 0 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - USART5EN - USART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - USART7EN - USART7 clock enable - 30 - 1 - - - USART8EN - USART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADCEN - ADC clock enable - 8 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOELPEN - IO E clock enable during sleep mode - 4 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAMLPEN - SRAM clock enable during sleep mode - 16 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - XMCLPEN - XMC clock enable during sleep mode - 0 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR12LPEN - Timer12 clock enable during sleep mode - 6 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - USART4LPEN - USART4 clock enable during sleep mode - 19 - 1 - - - USART5LPEN - USART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - CAN2LPEN - CAN2 clock enable during sleep mode - 26 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - DACLPEN - DAC clock enable during sleep mode - 29 - 1 - - - USART7LPEN - USART7 clock enable during sleep mode - 30 - 1 - - - USART8LPEN - USART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - ADCLPEN - ADC clock enable during sleep mode - 8 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - - - PICLKS - PICLKS - Peripheral independent clock register - (CRM_PICLKS) - 0x68 - 0x20 - 0x00000000 - - - USART1SEL - USART1 clock select - 0 - 2 - read-write - - - USART2SEL - USART2 clock select - 2 - 2 - read-write - - - USART3SEL - USART3 clock select - 4 - 2 - read-write - - - I2C1SEL - I2C1 clock select - 12 - 2 - read-write - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_USB - HICK to usb clock - 13 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - PLLCLK_TO_ADC - ADC clock source select - 15 - 1 - read-write - - - CLKOUT_SEL2 - Clock output select2 - 16 - 4 - read-write - - - CLKOUTDIV2 - Clock output division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - USBDIV - USB division - 12 - 4 - read-write - - - HICK_TO_SCLK_DIV - HICK as system clock frequency division - 16 - 3 - read-write - - - HEXT_TO_SCLK_DIV - HEXT as system clock frequency division - 19 - 3 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 2 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - TOGR - TOGR - GPIO bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - IOTB0 - Toggle bit 0 - 0 - 1 - - - IOTB1 - Toggle bit 1 - 1 - 1 - - - IOTB2 - Toggle bit 2 - 2 - 1 - - - IOTB3 - Toggle bit 3 - 3 - 1 - - - IOTB4 - Toggle bit 4 - 4 - 1 - - - IOTB5 - Toggle bit 5 - 5 - 1 - - - IOTB6 - Toggle bit 6 - 6 - 1 - - - IOTB7 - Toggle bit 7 - 7 - 1 - - - IOTB8 - Toggle bit 8 - 8 - 1 - - - IOTB9 - Toggle bit 9 - 9 - 1 - - - IOTB10 - Toggle bit 10 - 10 - 1 - - - IOTB11 - Toggle bit 11 - 11 - 1 - - - IOTB12 - Toggle bit 12 - 12 - 1 - - - IOTB13 - Toggle bit 13 - 13 - 1 - - - IOTB14 - Toggle bit 14 - 14 - 1 - - - IOTB15 - Toggle bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOE - 0x40021000 - - - GPIOF - 0x40021400 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - I2C1_EVT - I2C1_EVT interrupt connect to EXINT line23 - 31 - - - USART1 - ERTC Global interrupt connect to EXINT line25 - 37 - - - USART2 - ERTC Global interrupt connect to EXINT line26 - 38 - - - USART3 - USART3 Global interrupt connect to EXINT line28 - 39 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - INTEN23 - Interrupt enable or disable on line 23 - 23 - 1 - - - INTEN25 - Interrupt enable or disable on line 25 - 25 - 1 - - - INTEN26 - Interrupt enable or disable on line 26 - 26 - 1 - - - INTEN28 - Interrupt enable or disable on line 28 - 28 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - EVTEN23 - Event enable or disable on line 23 - 23 - 1 - - - EVTEN25 - Event enable or disable on line 25 - 25 - 1 - - - EVTEN26 - Event enable or disable on line 26 - 26 - 1 - - - EVTEN28 - Event enable or disable on line 28 - 28 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - RP23 - Rising polarity configuration bit of line 23 - 23 - 1 - - - RP25 - Rising polarity configuration bit of line 25 - 25 - 1 - - - RP26 - Rising polarity configuration bit of line 26 - 26 - 1 - - - RP28 - Rising polarity configuration bit of line 28 - 28 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - FP23 - Falling polarity event configuration bit of line 23 - 23 - 1 - - - FP25 - Falling polarity event configuration bit of line 25 - 25 - 1 - - - FP26 - Falling polarity event configuration bit of line 26 - 26 - 1 - - - FP28 - Falling polarity event configuration bit of line 28 - 28 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - SWT23 - Software triggle on line 233 - 23 - 1 - - - SWT25 - Software triggle on line 255 - 25 - 1 - - - SWT26 - Software triggle on line 26 - 26 - 1 - - - SWT28 - Software triggle on line 28 - 28 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - LINE23 - Line 23 state bit - 23 - 1 - - - LINE25 - Line 25 state bit - 25 - 1 - - - LINE26 - Line 26 state bit - 26 - 1 - - - LINE28 - Line 28 state bit - 28 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40026000 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 11 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 12 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 13 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 14 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 15 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 16 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 17 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026400 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR2_RMP - TMR2_RMP - TMR2 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_CH1_IRMP - TMR2 channel 1 input remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - BKF - brake input filter - 16 - 4 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - - TMR14 - 0x40002000 - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HICK Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLKP - I2SCLKP - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - ID3_0 - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - RDY - ADC ready to conversion flag - 6 - 1 - read-only - - - OCCO - Ordinary channel conversion overflow flag - 5 - 1 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - OCCE - Ordinary channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCCOIEN - Ordinary channel conversion overflow interrupt enable - 26 - 1 - - - CRSEL - Conversion resolution select - 24 - 2 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - OCCEIEN - Ordinary channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCSWTRG - Ordinary channel software conversion trigger - 30 - 1 - - - OCETE - Ordinary channel external trigger edge select - 28 - 2 - - - OCTESEL - trigger event select for ordinary channels conversion - 24 - 4 - - - PCSWTRG - Preempted channel software conversion trigger - 22 - 1 - - - PCETE - Preempted channel external trigger edge select - 20 - 2 - - - PCTESEL - trigger event select for preempted channels conversion - 16 - 4 - - - DTALIGN - Data alignment - 11 - 1 - - - EOCSFEN - Each ordinary channel conversion set OCCE flag enable - 10 - 1 - - - OCDRCEN - Ordinary channel DMA request continuation enable for independent mode - 9 - 1 - - - OCDMAEN - Ordinary channel DMA transfer enable for independent mode - 8 - 1 - - - ADABRT - ADC conversion abort - 4 - 1 - - - ADCALINIT - Initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT18 - Selection sample time of channel ADC_IN18 - 24 - 3 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - SPT3 - SPT3 - sample time register 3 - 0x50 - 0x20 - read-write - 0x00000000 - - - CSPT27 - Selection sample time of channel ADC_IN27 - 21 - 3 - - - CSPT26 - Selection sample time of channel ADC_IN26 - 18 - 3 - - - CSPT25 - Selection sample time of channel ADC_IN25 - 15 - 3 - - - CSPT24 - Selection sample time of channel ADC_IN24 - 12 - 3 - - - CSPT23 - Selection sample time of channel ADC_IN23 - 9 - 3 - - - CSPT22 - Selection sample time of channel ADC_IN22 - 6 - 3 - - - CSPT21 - Selection sample time of channel ADC_IN21 - 3 - 3 - - - CSPT20 - Selection sample time of channel ADC_IN20 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 16 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 16 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 5 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - OSQ4 - OSQ4 - Ordinary sequence register 4 - 0x54 - 0x20 - read-write - 0x00000000 - - - OSN22 - Number of 22th conversion in ordinary sequence - 25 - 5 - - - OSN21 - Number of 21th conversion in ordinary sequence - 20 - 5 - - - OSN20 - Number of 20th conversion in ordinary sequence - 15 - 5 - - - OSN19 - number of 19rd conversion in ordinary sequence - 10 - 5 - - - OSN18 - Number of 18nd conversion in ordinary sequence - 5 - 5 - - - OSN17 - Number of 17st conversion in ordinary sequence - 0 - 5 - - - - - OSQ5 - OSQ5 - Ordinary sequence register 5 - 0x58 - 0x20 - read-write - 0x00000000 - - - OSN28 - Number of 28th conversion in ordinary sequence - 25 - 5 - - - OSN27 - Number of 27th conversion in ordinary sequence - 20 - 5 - - - OSN26 - Number of 26th conversion in ordinary sequence - 15 - 5 - - - OSN25 - number of 25rd conversion in ordinary sequence - 10 - 5 - - - OSN24 - Number of 24nd conversion in ordinary sequence - 5 - 5 - - - OSN23 - Number of 23st conversion in ordinary sequence - 0 - 5 - - - - - OSQ6 - OSQ6 - Ordinary sequence register 6 - 0x5C - 0x20 - read-write - 0x00000000 - - - OSN32 - Number of 32th conversion in ordinary sequence - 15 - 5 - - - OSN31 - number of 31rd conversion in ordinary sequence - 10 - 5 - - - OSN30 - Number of 30nd conversion in ordinary sequence - 5 - 5 - - - OSN29 - Number of 29st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - CALVAL - CALVAL - Calibration value register - 0xB4 - 0x20 - read-write - 0x00000000 - - - CALVAL - A/D Calibration value - 0 - 7 - - - - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CSTS - CSTS - Common status register - 0x0 - 0x20 - read-only - 0x00000000 - - - RDY1 - ADC ready to conversion flag of ADC1 - 6 - 1 - - - OCCO1 - Ordinary channel conversion overflow flag of ADC1 - 5 - 1 - - - OCCS1 - Ordinary channel conversion start flag of ADC1 - 4 - 1 - - - PCCS1 - Preempted channel conversion start flag of ADC1 - 3 - 1 - - - PCCE1 - Preempted channels conversion end flag of ADC1 - 2 - 1 - - - OCCE1 - Ordinary channels conversion end flag of ADC1 - 1 - 1 - - - VMOR1 - Voltage monitoring out of range flag of ADC1 - 0 - 1 - - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - VBATEN - VBAT enable - 22 - 1 - - - ADCDIV - ADC division - 16 - 4 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 63 - - - CAN2_RX0 - CAN2 RX0 interrupt - 64 - - - CAN2_RX1 - CAN2 RX1 interrupt - 65 - - - CAN2_SE - CAN2 SE interrupt - 66 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D1DMAUDRIEN - DAC1 DMA underrun interrupt enable - 13 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - D2DMAUDRIEN - DAC2 DMA underrun interrupt enable - 29 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - STS - STS - DAC2 status register - (DAC_STS) - 0x34 - 0x20 - read-write - 0x00000000 - - - D1DMAUDRF - DAC1 DMA underrun flag - 13 - 1 - - - D2DMAUDRF - DAC2 DMA underrun flag - 29 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 6 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 26 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 1 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - SER_ID - SER_ID - SERIES ID - 0x20 - 0x20 - read-only - 0x0 - - - REV_ID - version ID - 0 - 3 - - - SER_ID - series ID - 8 - 8 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTGFS_GLOBAL - USB on-the-go full speed - USB_OTGFS - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTGFS_HOST - USB on the go full speed - USB_OTGFS - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTGFS_DEVICE - USB on the go full speed - USB_OTGFS - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTGFS_PWRCLK - USB on the go full speed - USB_OTGFS - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - LOCKUP_LK - CM4 LOCKUP bit enable - 0 - 1 - - - PVM_LK - PVM lock enable - 2 - 1 - - - I2S_FD - I2S full duplex configuration bit - 30 - 2 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PD13_UH - PD13 ultra high sourcing/sinking strength - 6 - 1 - - - PD12_UH - PD12 ultra high sourcing/sinking strength - 5 - 1 - - - PB8_UH - PB8 ultra high sourcing/sinking strength - 3 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - ACTR - ACTR - AC timing control register - 0x14 - 0x20 - read-write - 0x0000000F - - - CSDLY - CS delay - 0 - 4 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 6 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 6 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - QSPI2 - 0xA0002000 - - QSPI2 - QSPI2 global interrupt - 91 - - - - diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.cmake b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake new file mode 100644 index 000000000..17e665a0b --- /dev/null +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.cmake @@ -0,0 +1,9 @@ +set(MCU_VARIANT AT32F423VCT7) +set(JLINK_DEVICE ${MCU_VARIANT}) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/AT32F423xC_FLASH.ld) +set(LD_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/linker/AT32F423xC.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC ${MCU_VARIANT}) +endfunction() diff --git a/hw/bsp/at32f423/boards/AT_START_F423/board.mk b/hw/bsp/at32f423/boards/AT_START_F423/board.mk index 95ec21d02..4c19c81bb 100644 --- a/hw/bsp/at32f423/boards/AT_START_F423/board.mk +++ b/hw/bsp/at32f423/boards/AT_START_F423/board.mk @@ -1,3 +1,4 @@ +JLINK_DEVICE = AT32F423VCT7 LD_FILE = $(BOARD_PATH)/AT32F423xC_FLASH.ld CFLAGS += \ diff --git a/hw/bsp/at32f423/family.c b/hw/bsp/at32f423/family.c index f63fb8962..afe3758ca 100644 --- a/hw/bsp/at32f423/family.c +++ b/hw/bsp/at32f423/family.c @@ -25,8 +25,8 @@ */ #include "at32f423_clock.h" -#include "bsp/board_api.h" #include "board.h" +#include "bsp/board_api.h" void usb_clock48m_select(usb_clk48_s clk_s); void led_and_button_init(void); @@ -34,17 +34,14 @@ void uart_print_init(uint32_t baudrate); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) -{ +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) -{ +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) -{ +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -63,24 +60,24 @@ void board_init(void) /* configure systick */ systick_clock_source_config(SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV); SysTick_Config(SystemCoreClock / 1000); - #if CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); - #endif - - /* otgfs use vbus pin */ - #ifndef USB_VBUS_IGNORE - gpio_init_type gpio_init_struct; - crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); - gpio_default_para_init(&gpio_init_struct); - gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; - gpio_init_struct.gpio_mode = GPIO_MODE_MUX; - gpio_init_struct.gpio_pins = OTG_PIN_VBUS; - gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; - gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); - gpio_init(OTG_PIN_GPIO, &gpio_init_struct); - #endif +#if CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(OTG_IRQ, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + +/* otgfs use vbus pin */ +#ifndef USB_VBUS_IGNORE + gpio_init_type gpio_init_struct; + crm_periph_clock_enable(OTG_PIN_GPIO_CLOCK, TRUE); + gpio_default_para_init(&gpio_init_struct); + gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_mode = GPIO_MODE_MUX; + gpio_init_struct.gpio_pins = OTG_PIN_VBUS; + gpio_init_struct.gpio_pull = GPIO_PULL_DOWN; + gpio_pin_mux_config(OTG_PIN_GPIO, OTG_PIN_VBUS_SOURCE, OTG_PIN_MUX); + gpio_init(OTG_PIN_GPIO, &gpio_init_struct); +#endif /* config led and key */ led_and_button_init(); @@ -98,10 +95,8 @@ void board_init(void) * @param clk_s:USB_CLK_HICK, USB_CLK_HEXT * @retval none */ -void usb_clock48m_select(usb_clk48_s clk_s) -{ - if(clk_s == USB_CLK_HICK) - { +void usb_clock48m_select(usb_clk48_s clk_s) { + if (clk_s == USB_CLK_HICK) { crm_usb_clock_source_select(CRM_USB_CLOCK_SOURCE_HICK); /* enable the acc calibration ready interrupt */ @@ -114,11 +109,8 @@ void usb_clock48m_select(usb_clk48_s clk_s) /* open acc calibration */ acc_calibration_mode_enable(ACC_CAL_HICKTRIM, TRUE); - } - else - { - switch(system_core_clock) - { + } else { + switch (system_core_clock) { /* 48MHz */ case 48000000: crm_usb_clock_div_set(CRM_USB_DIV_2); @@ -138,7 +130,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) case 120000000: crm_usb_clock_div_set(CRM_USB_DIV_5); break; - + /* 144MHz */ case 144000000: crm_usb_clock_div_set(CRM_USB_DIV_6); @@ -149,8 +141,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } } -void uart_print_init(uint32_t baudrate) -{ +void uart_print_init(uint32_t baudrate) { gpio_init_type gpio_init_struct; /* enable the uart and gpio clock */ crm_periph_clock_enable(PRINT_UART_CRM_CLK, TRUE); @@ -158,7 +149,7 @@ void uart_print_init(uint32_t baudrate) gpio_default_para_init(&gpio_init_struct); /* configure the uart tx pin */ gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_init_struct.gpio_mode = GPIO_MODE_MUX; gpio_init_struct.gpio_pins = PRINT_UART_TX_PIN; gpio_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -170,8 +161,7 @@ void uart_print_init(uint32_t baudrate) usart_enable(PRINT_UART, TRUE); } -void led_and_button_init(void) -{ +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; /* enable the led clock */ @@ -180,7 +170,7 @@ void led_and_button_init(void) gpio_default_para_init(&gpio_led_init_struct); /* configure the led gpio */ gpio_led_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER; - gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; + gpio_led_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL; gpio_led_init_struct.gpio_mode = GPIO_MODE_OUTPUT; gpio_led_init_struct.gpio_pins = LED_PIN; gpio_led_init_struct.gpio_pull = GPIO_PULL_NONE; @@ -200,21 +190,18 @@ void led_and_button_init(void) gpio_init(BUTTON_PORT, &gpio_button_init_struct); } -void board_led_write(bool state) -{ +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) -{ +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) -{ +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); - uint32_t* id32 = (uint32_t*) (uintptr_t) id; + volatile uint32_t *at32_uuid = ((volatile uint32_t *) 0x1FFFF7E8); + uint32_t *id32 = (uint32_t *) (uintptr_t) id; uint8_t const len = 12; id32[0] = at32_uuid[0]; @@ -224,68 +211,62 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) return len; } -int board_uart_read(uint8_t *buf, int len) -{ +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; return 0; } -int board_uart_write(void const *buf, int len) -{ - #if CFG_TUSB_OS == OPT_OS_NONE - int txsize = len; - u16 timeout = 0xffff; - while (txsize--) - { - while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) - { - timeout--; - if(timeout == 0) - { - return 0; - } +int board_uart_write(void const *buf, int len) { +#if CFG_TUSB_OS == OPT_OS_NONE + int txsize = len; + u16 timeout = 0xffff; + while (txsize--) { + while (usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { + timeout--; + if (timeout == 0) { + return 0; } - PRINT_UART->dt = (*((uint8_t const *)buf) & 0x01FF); - buf++; } - return len; - #else - (void) buf; - (void) len; - return 0; - #endif + PRINT_UART->dt = (*((uint8_t const *) buf) & 0x01FF); + buf++; + } + return len; +#else + (void) buf; + (void) len; + return 0; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE - volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) - { - system_ticks++; - } +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} - uint32_t board_millis(void) - { - return system_ticks; - } +uint32_t board_millis(void) { + return system_ticks; +} - void SVC_Handler(void) - { - } +void SVC_Handler(void) { +} - void PendSV_Handler(void) - { - } +void PendSV_Handler(void) { +} #endif -void HardFault_Handler(void) -{ +void HardFault_Handler(void) { __asm("BKPT #0\n"); } -#ifdef USE_FULL_ASSERT -void assert_failed(const char *file, uint32_t line) -{ +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +// void _init(void) { +// } + +#ifdef USE_FULL_ASSERT +void assert_failed(const char *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ diff --git a/hw/bsp/at32f423/family.cmake b/hw/bsp/at32f423/family.cmake new file mode 100644 index 000000000..ebc855949 --- /dev/null +++ b/hw/bsp/at32f423/family.cmake @@ -0,0 +1,104 @@ +include_guard() + +set(AT_FAMILY at32f423) +set(AT_SDK_LIB ${TOP}/hw/mcu/artery/${AT_FAMILY}/libraries) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS AT32F423 CACHE INTERNAL "") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/startup_${AT_FAMILY}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${AT_SDK_LIB}/cmsis/cm4/device_support/startup/iar/startup_${AT_FAMILY}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + + add_library(${BOARD_TARGET} STATIC + ${AT_SDK_LIB}/cmsis/cm4/device_support/system_${AT_FAMILY}.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_gpio.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_misc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_usart.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_acc.c + ${AT_SDK_LIB}/drivers/src/${AT_FAMILY}_crm.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${AT_SDK_LIB}/cmsis/cm4/core_support + ${AT_SDK_LIB}/cmsis/cm4/device_support + ${AT_SDK_LIB}/drivers/inc + ) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_clock.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${AT_FAMILY}_int.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_AT32F423) + target_sources(${TARGET} PUBLIC + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + ) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + + # Flashing + family_add_bin_hex(${TARGET}) + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/at32f423/family.mk b/hw/bsp/at32f423/family.mk index 2653842da..8ee1072be 100644 --- a/hw/bsp/at32f423/family.mk +++ b/hw/bsp/at32f423/family.mk @@ -1,6 +1,6 @@ -# Submodules +JLINK_DEVICE = AT32F423VCT7 + AT32F423_SDK = hw/mcu/artery/at32f423 -DEPS_SUBMODULES += $(AT32F423_SDK) # AT32 SDK path AT32F423_SDK_SRC = $(AT32F423_SDK)/libraries @@ -16,7 +16,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_AT32F423 \ LDFLAGS_GCC += \ - -flto --specs=nosys.specs + -flto --specs=nosys.specs -nostdlib -nostartfiles SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ diff --git a/hw/bsp/at32f423/startup_at32f423.s b/hw/bsp/at32f423/startup_at32f423.s index 764380f0e..3e5404009 100644 --- a/hw/bsp/at32f423/startup_at32f423.s +++ b/hw/bsp/at32f423/startup_at32f423.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h index 6cc39f727..f1784902e 100644 --- a/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f425/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f425/at32f425_clock.h b/hw/bsp/at32f425/at32f425_clock.h index acd442e42..785fcc81a 100644 --- a/hw/bsp/at32f425/at32f425_clock.h +++ b/hw/bsp/at32f425/at32f425_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f425/at32f425_int.c b/hw/bsp/at32f425/at32f425_int.c index eaef6af42..ed774f4f2 100644 --- a/hw/bsp/at32f425/at32f425_int.c +++ b/hw/bsp/at32f425/at32f425_int.c @@ -137,4 +137,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f425/at32f425_int.h b/hw/bsp/at32f425/at32f425_int.h index b40767ee4..ad9dc308b 100644 --- a/hw/bsp/at32f425/at32f425_int.h +++ b/hw/bsp/at32f425/at32f425_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld index 850d596f9..b1d767b51 100644 --- a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld +++ b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425x8_FLASH.ld @@ -103,7 +103,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -118,7 +118,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd b/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd deleted file mode 100644 index d18e75e8e..000000000 --- a/hw/bsp/at32f425/boards/AT_START_F425/AT32F425xx_v2.svd +++ /dev/null @@ -1,30790 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F425xx_v2 - AT32F425 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 120MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - PVM - PVM through EXTI line detection interrupt - 1 - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - read-write - - - LPSEL - Low power mode select when Cortex-M4 sleepdeep - 1 - 1 - read-write - - - CLSWEF - Clear SWEF flag - 2 - 1 - write-only - - - CLSEF - Clear SEF flag - 3 - 1 - write-only - - - PVMEN - Power voltage monitoring enable - 4 - 1 - read-write - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - read-write - - - BPWEN - Battery power domain write enable - 8 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Power control register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin2 enable - 9 - 1 - read-write - - - SWPEN4 - Standby wake-up pin4 enable - 11 - 1 - read-write - - - SWPEN5 - Standby wake-up pin5 enable - 12 - 1 - read-write - - - SWPEN6 - Standby wake-up pin6 enable - 13 - 1 - read-write - - - SWPEN7 - Standby wake-up pin7 enable - 14 - 1 - read-write - - - - - CTRL2 - CTRL2 - Power control register 2 - (PWC_CTRL2) - 0x20 - 0x20 - 0x00000000 - - - VREXLPEN - Voltage regulator extra low power mode enable - 5 - 1 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40021000 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 4 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - CFG - CFG - Clock configuration register - (CRM_CFG) - 0x4 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 8 - 3 - read-write - - - APB2DIV - APB2 division - 11 - 3 - read-write - - - ADCDIV1_0 - ADC division bit1 and bit0 - 14 - 2 - read-write - - - PLLRCS - PLL reference clock select - 16 - 1 - read-write - - - PLLHEXTDIV - HEXT division selection for PLL entry clock - 17 - 1 - read-write - - - PLLMULT3_0 - PLL Multiplication Factor bit3 to bit0 - 18 - 4 - read-write - - - USBDIV1_0 - USB division bit1 and bit0 - 22 - 2 - read-write - - - CLKOUT_SEL - Clock output selection bit2 to bit0 - 24 - 3 - read-write - - - USBDIV2 - USB division bit2 - 27 - 1 - read-write - - - ADCDIV2 - ADC division bit2 - 28 - 1 - read-write - - - PLLMULT5_4 - PLL Multiplication Factor bit5 and bit4 - 29 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0x8 - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0xC - 0x20 - read-write - 0x000000000 - - - SCFGRST - System config reset - 0 - 1 - - - EXINTRST - External interrupt reset - 1 - 1 - - - ADC1RST - ADC1 reset - 9 - 1 - - - TMR1RST - TMR1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TMR15RST - Timer15 reset - 16 - 1 - - - TMR16RST - Timer16 reset - 17 - 1 - - - TMR17RST - Timer17 reset - 18 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer 2 reset - 0 - 1 - - - TMR3RST - Timer 3 reset - 1 - 1 - - - TMR6RST - Timer 6 reset - 4 - 1 - - - TMR7RST - Timer 7 reset - 5 - 1 - - - TMR13RST - Timer 13 reset - 7 - 1 - - - TMR14RST - Timer 14 reset - 8 - 1 - - - WWDTRST - Window watchdog timer reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART 2 reset - 17 - 1 - - - USART3RST - USART 3 reset - 18 - 1 - - - USART4RST - USART 4 reset - 19 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - ACCRST - ACC reset - 27 - 1 - - - PWCRST - Power controller reset - 28 - 1 - - - - - AHBEN - AHBEN - AHB Peripheral Clock enable register - (CRM_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - DMA1EN - DMA1 clock enable - 0 - 1 - - - SRAMEN - SRAM interface clock - enable - 2 - 1 - - - FLASHEN - FLASH clock enable - 4 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 12 - 1 - - - GPIOAEN - I/O port A clock enable - 17 - 1 - - - GPIOBEN - I/O port B clock enable - 18 - 1 - - - GPIOCEN - I/O port C clock enable - 19 - 1 - - - GPIODEN - I/O port D clock enable - 20 - 1 - - - GPIOFEN - I/O port F clock enable - 22 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - SCFGEN - System config clock enable - 0 - 1 - - - ADC1EN - ADC1 clock enable - 9 - 1 - - - TMR1EN - Timer1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TMR15EN - Timer15 clock enable - 16 - 1 - - - TMR16EN - Timer16 clock enable - 17 - 1 - - - TMR17EN - Timer17 clock enable - 18 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - Window watchdog timer clock - enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - ACCEN - ACC clock enable - 27 - 1 - - - PWCEN - Power clock enable - 28 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x20 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x24 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - - 0x28 - 0x20 - 0x00000000 - - - OTGFS1RST - OTGFS1 reset - 12 - 1 - - - GPIOARST - IO port A reset - 17 - 1 - - - GPIOBRST - IO port B reset - 18 - 1 - - - GPIOCRST - IO port C reset - 19 - 1 - - - GPIODRST - IO port D reset - 20 - 1 - - - GPIOFRST - IO port F reset - 22 - 1 - - - - - PLL - PLL - PLL configuration register - (CRM_PLL) - 0x2C - 0x20 - 0x00001F10 - - - PLL_FR - PLL_FR - 0 - 3 - read-write - - - PLL_MS - PLL_MS - 4 - 4 - read-write - - - PLL_NS - PLL_NS - 8 - 9 - read-write - - - PLL_FREF - PLL entry clock reference frequency - 24 - 3 - read-write - - - PLLCFGEN - PLL config enable - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0x30 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - CLKOUT_SEL3 - Clock output bit3 - 16 - 1 - read-write - - - HICKDIV - HICK 6 divider selection - 25 - 1 - read-write - - - CLKOUTDIV - Clock output division - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0x54 - 0x20 - 0x0000000D - - - HICK_TO_USB - HICK_TO_USB - 8 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 9 - 1 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x48000000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x48000400 - - - GPIOC - 0x48000800 - - - GPIOD - 0x48000C00 - - - GPIOF - 0x48001400 - - - EXINT - EXINT - EXINT - 0x40010400 - - 0x0 - 0x400 - registers - - - PVM - PVM interrupt connect to EXTI line16 - 1 - - - ERTC - ERTC interrupt connect to EXTI line17_19_20 - 2 - - - EXTINT1_0 - EXINT Line1_0 interrupt - 5 - - - EXTINT3_2 - EXINT Line3_2 interrupt - 6 - - - EXTINT15_4 - EXINT Line15_4 interrupt - 7 - - - OTGFS - OTGFS interrupt connect to EXTI Line18 - 31 - - - - INTEN - INTEN - Interrupt enable register (EXTINT_INTEN) - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - - - EVTEN - EVTEN - Event enable register (EXTINT_EVTEN) - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register(EXTINT_POLCFG1) - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register(EXTINT_POLCFG2) - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - - - SWTRG - SWTRG - Software triggle register - (EXTINT_SWIE) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - - - INTSTS - INTSTS - Interrupt status register (EXTINT_INTSTS) - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - - - - - DMA1 - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 9 - - - DMA1_Channel3_2 - DMA1 Channel3_2 global interrupt - 10 - - - DMA1_Channel7_4 - DMA1 Channel7_4 global interrupt - 11 - - - - STS - STS - DMA interrupt status register (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Full data transfer interrupt enable - 1 - 1 - - - HDTIEN - Half data transfer interrupt enable - 2 - 1 - - - DTERRIEN - Data transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral address increment mode - 6 - 1 - - - MINCM - Memory address increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_SRC_SEL0 - DMA_SRC_SEL0 - DMA channel source assignment register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CH1_SRC - CH1 SRC select - 0 - 8 - - - CH2_SRC - CH2 SRC select - 8 - 8 - - - CH3_SRC - CH3 SRC select - 16 - 8 - - - CH4_SRC - CH4 SRC select - 24 - 8 - - - - - DMA_SRC_SEL1 - DMA_SRC_SEL1 - DMA channel source assignment register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CH5_SRC - CH5 SRC select - 0 - 8 - - - CH6_SRC - CH6 SRC select - 8 - 8 - - - CH7_SRC - CH7 SRC select - 16 - 8 - - - DMA_FLEX_EN - DMA FLEX Enable - 24 - 1 - - - - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TMR1_CH - TMR1 channel interrupt - 14 - - - TMR1_BRK_OVF_TRG_HALL - TMR1 overflow brake trigger hall interrupt - 13 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 15 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 16 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 17 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 18 - - - - TMR13 - General-purpose-timers - TIMER - 0x40001C00 - - 0x0 - 0x400 - registers - - - TMR13 - TMR13 global interrupt - 35 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR14 - General-purpose-timers - TIMER - 0x40002000 - - 0x0 - 0x400 - registers - - - TMR14 - TMR14 global interrupt - 19 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - RMP - RMP - TMR14 channel 1 input remap - 0x50 - 0x20 - read-write - 0x00000000 - - - TMR14_CH1_IRMP - TMR14 channel 1 input remap - 6 - 2 - - - - - - - TMR15 - General-purpose-timers - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - TMR15 - TMR15 global interrupt - 20 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR16 - General-purpose-timers - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR16 - TMR16 global interrupt - 21 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR17 - 0x40014800 - - TMR17 - TMR17 global interrupt - 22 - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 23 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 24 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1 - CAN1 global interrupt - 30 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit filtrate bit filtrate bit filtrate bit filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40006C00 - - 0x0 - 0x400 - registers - - - ACC - ACC interrupts - 8 - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - ACC_HSITRIM - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - ACC_HSICAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 25 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency 3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-only - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 26 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 33 - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 27 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - ID - USART identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 28 - - - - USART3 - 0x40004800 - - USART3 - USART4_3 global interrupt - 29 - - - - USART4 - 0x40004C00 - - - ADC - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC1 - ADC1 global interrupt - 12 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - CCE - Channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - CCEIEN - Channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - OCSWTRG - Conversion trigger by software of ordinary channels - 22 - 1 - - - PCSWTRG - Conversion trigger by software of preempted channels - 21 - 1 - - - OCTEN - Trigger mode enable for ordinary channels conversion - 20 - 1 - - - OCTESEL - Low bit of trigger event select for ordinary channels conversion - 17 - 3 - - - PCTEN - Trigger mode enable for preempted channels conversion - 15 - 1 - - - PCTESEL - Low bit of trigger event select for preempted channels conversion - 12 - 3 - - - DTALIGN - Data alignment - 11 - 1 - - - OCDMAEN - DMA transfer enable of ordinary channels - 8 - 1 - - - ADCALINIT - initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - - - SCFG - System configuration controller - SCFG - 0x40010000 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory mapping selection - bits - 0 - 2 - - - PA11_12_RMP - PA11/PA12 pins remapping bit - 4 - 1 - - - IR_POL - Infrared output polarity selection - 5 - 1 - - - IR_SRC_SEL - Infrared modulation envelope signal source selection - 6 - 2 - - - PB14_UH - PB14 Ultra high sourcing/sinking strength - 16 - 1 - - - PB13_UH - PB13 Ultra high sourcing/sinking strength - 17 - 1 - - - PB9_UH - PB9 Ultra high sourcing/sinking strength - 18 - 1 - - - PB8_UH - PB8 Ultra high sourcing/sinking strength - 19 - 1 - - - - - EXTIC1 - EXTIC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXTINT3 - EXTINT 3 configuration bits - 12 - 4 - - - EXTINT2 - EXTINT 2 configuration bits - 8 - 4 - - - EXTINT1 - EXTINT 1 configuration bits - 4 - 4 - - - EXTINT0 - EXTINT 0 configuration bits - 0 - 4 - - - - - EXTIC2 - EXTIC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXTINT7 - EXTINT 7 configuration bits - 12 - 4 - - - EXTINT6 - EXTINT 6 configuration bits - 8 - 4 - - - EXTINT5 - EXTINT 5 configuration bits - 4 - 4 - - - EXTINT4 - EXTINT 4 configuration bits - 0 - 4 - - - - - EXTIC3 - EXTIC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXTINT11 - EXTINT 11 configuration bits - 12 - 4 - - - EXTINT10 - EXTINT 10 configuration bits - 8 - 4 - - - EXTINT9 - EXTINT 9 configuration bits - 4 - 4 - - - EXTINT8 - EXTINT 8 configuration bits - 0 - 4 - - - - - EXTIC4 - EXTIC4 - external interrupt configuration register 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXTINT15 - EXTINT 15 configuration bits - 12 - 4 - - - EXTINT14 - EXTINT 14 configuration bits - 8 - 4 - - - EXTINT13 - EXTINT 13 configuration bits - 4 - 4 - - - EXTINT12 - EXTINT 12 configuration bits - 0 - 4 - - - - - CFG2 - CFG2 - configuration register 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - PVM_LK - PVM lock enable - 2 - 1 - - - I2S_FD - I2S full duplex - 30 - 2 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG_IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - PID - 0 - 32 - - - - - CTRL - CTRL - DEBUG_CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - CAN_PAUSE - CAN_PAUSE - 3 - 1 - - - WDT_PAUSE - WDT_PAUSE - 8 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 9 - 1 - - - TMR1_PAUSE - TMR1_PAUSE - 10 - 1 - - - TMR2_PAUSE - TMR2_PAUSE - 11 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 12 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 14 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 15 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 16 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 19 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 20 - 1 - - - ERTC_512_PAUSE - ERTC_512_PAUSE - 21 - 1 - - - TMR15_PAUSE - TMR15_PAUSE - 22 - 1 - - - TMR16_PAUSE - TMR16_PAUSE - 23 - 1 - - - TMR17_PAUSE - TMR17_PAUSE - 24 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 26 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 27 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 3 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000030 - - - WTCYC - Wait cycle - 0 - 3 - read-write - - - HFCYC_EN - Half cycle acceleration access enable - 3 - 1 - read-write - - - PFT_EN - Prefetch enable - 4 - 1 - read-write - - - PFT_ENF - Prefetch enabled flag - 5 - 1 - read-only - - - PFT_EN2 - Prefetch enable 2 - 6 - 1 - read-write - - - PFT_ENF2 - Prefetch enabled flag 2 - 7 - 1 - read-only - - - PFT_LAT_DIS - Prefetch latency disable - 8 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00020080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - LPMEN - Low power mode enable - 17 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - nBOOT1 - boot1 - 6 - 1 - - - nDEPSLP_WDT - Deepsleep wdt stop count - 7 - 1 - - - nSTDBY_WDT - Standby wdt stop count - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - FAP_HL - FAP high level - 26 - 1 - - - - - EPPS - EPPS - Erase/program protection status register - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0x74 - 0x20 - 0x00000000 - - - BTM_AP_ENF - Boot memory store application code enabled flag - 0 - 1 - - - EM_SLIB_ENF - Extension memory sLib enabled flag - 2 - 1 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - - - EM_SLIB_INST_SS - Extension memory sLib instruction start sector - 16 - 8 - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0x78 - 0x20 - 0x00000000 - - - SLIB_SS - sLib start sector - 0 - 11 - - - SLIB_INST_SS - sLib instruction start sector - 11 - 11 - - - SLIB_ES - sLib end sector - 22 - 10 - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0x7C - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0x80 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - - - CRC_ADDR - CRC_ADDR - Flash CRC data start address register - 0x84 - 0x20 - write-only - 0x00000000 - - - CRC_ADDR - CRC address - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - Flash CRC controll register - 0x88 - 0x20 - 0x00000000 - - - CRC_SN - CRC sector numbler - 0 - 16 - read-write - - - CRC_STRT - CRC start - 16 - 1 - write-only - - - - - CRC_CHKR - CRC_CHKR - FLASH CRC check result register - 0x8C - 0x20 - read-only - 0x00000000 - - - FCRC_OUT - CRC32 verification result of flash user code or SLIB code - 0 - 32 - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0x160 - 0x20 - write-only - 0x00000000 - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE - SLIB_SET_RANGE - Configure sLib range register - 0x164 - 0x20 - write-only - 0x00000000 - - - SLIB_SS_SET - sLib start sector setting - 0 - 11 - - - SLIB_ISS_SET - sLib instruction start sector setting - 11 - 11 - - - SLIB_ES_SET - sLib end sector setting - 22 - 10 - - - - - EM_SLIB_SET - EM_SLIB_SET - Extension momery slib set register - 0x168 - 0x20 - write-only - 0x00000000 - - - EM_SLIB_SET - Extension memory sLib setting - 0 - 16 - - - EM_SLIB_ISS_SET - Extension memory sLib instruction start sector setting - 16 - 8 - - - - - BTM_MODE_SET - BTM_MODE_SET - Boot memory mode setting register - 0x16C - 0x20 - write-only - 0x00000000 - - - BTM_MODE_SET - Boot memory mode setting - 0 - 8 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0x170 - 0x20 - write-only - 0x00000000 - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - USB_OTG1_GLOBAL - USB on-the-go full speed - USB_OTG1 - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTG1 - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTG1 - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTG1 - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - diff --git a/hw/bsp/at32f425/family.c b/hw/bsp/at32f425/family.c index e0b66730a..7c2db9258 100644 --- a/hw/bsp/at32f425/family.c +++ b/hw/bsp/at32f425/family.c @@ -35,16 +35,16 @@ void led_and_button_init(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS1_WKUP_IRQHandler(void) +void OTGFS1_WKUP_IRQHandler(void) { tusb_int_handler(0, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -85,7 +85,7 @@ void board_init(void) /* config led and key */ led_and_button_init(); - + /* config usart printf */ uart_print_init(115200); printf("usart printf config success!\r\n"); @@ -120,7 +120,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) { /* usb divider reset */ crm_usb_div_reset(); - + switch(system_core_clock) { /* 48MHz */ @@ -144,7 +144,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_button_init(void) +void led_and_button_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -201,7 +201,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -214,7 +214,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -235,17 +235,17 @@ int board_uart_write(void const *buf, int len) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -263,12 +263,12 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -282,7 +282,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f425/family.mk b/hw/bsp/at32f425/family.mk index d1bcdfda3..07b383ce9 100644 --- a/hw/bsp/at32f425/family.mk +++ b/hw/bsp/at32f425/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F425_SDK = hw/mcu/artery/at32f425 -DEPS_SUBMODULES += $(AT32F425_SDK) # AT32 SDK path AT32F425_SDK_SRC = $(AT32F425_SDK)/libraries diff --git a/hw/bsp/at32f425/startup_at32f425.s b/hw/bsp/at32f425/startup_at32f425.s index 38127c759..d41fd3f42 100644 --- a/hw/bsp/at32f425/startup_at32f425.s +++ b/hw/bsp/at32f425/startup_at32f425.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h index a42e4d414..4e24ead70 100644 --- a/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/at32f435_437/FreeRTOSConfig/FreeRTOSConfig.h @@ -109,7 +109,7 @@ #define INCLUDE_vTaskDelayUntil 1 #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTaskGetSchedulerState 0 -#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 #define INCLUDE_uxTaskGetStackHighWaterMark 0 #define INCLUDE_xTaskGetIdleTaskHandle 0 #define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 diff --git a/hw/bsp/at32f435_437/at32f435_437_clock.h b/hw/bsp/at32f435_437/at32f435_437_clock.h index 221f67b4a..6d0273f30 100644 --- a/hw/bsp/at32f435_437/at32f435_437_clock.h +++ b/hw/bsp/at32f435_437/at32f435_437_clock.h @@ -41,4 +41,3 @@ void system_clock_config(void); #endif #endif - diff --git a/hw/bsp/at32f435_437/at32f435_437_int.c b/hw/bsp/at32f435_437/at32f435_437_int.c index b2fd3db29..119a0c960 100644 --- a/hw/bsp/at32f435_437/at32f435_437_int.c +++ b/hw/bsp/at32f435_437/at32f435_437_int.c @@ -117,4 +117,3 @@ void DebugMon_Handler(void) /** * @} */ - diff --git a/hw/bsp/at32f435_437/at32f435_437_int.h b/hw/bsp/at32f435_437/at32f435_437_int.h index afd2ad14e..76bfaaae4 100644 --- a/hw/bsp/at32f435_437/at32f435_437_int.h +++ b/hw/bsp/at32f435_437/at32f435_437_int.h @@ -53,4 +53,3 @@ void SysTick_Handler(void); #endif #endif - diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld index 8b4db93ab..b9d5ba223 100644 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld +++ b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xM_FLASH.ld @@ -104,7 +104,7 @@ SECTIONS _sidata = LOADADDR(.data); /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : + .data : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(4); .bss : { - /* This is used by the startup in order to initialize the .bss secion */ + /* This is used by the startup in order to initialize the .bss section */ _sbss = .; /* define a global symbol at bss start */ __bss_start__ = _sbss; *(.bss) diff --git a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd b/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd deleted file mode 100644 index 4f34af9d3..000000000 --- a/hw/bsp/at32f435_437/boards/AT_START_F435_437/AT32F437xx_v2.svd +++ /dev/null @@ -1,58291 +0,0 @@ - - - - - - - - Keil - ArteryTek - AT32F437xx_v2 - AT32F437 - 1.0 - ARM 32-bit Cortex-M4 Microcontroller based device, CPU clock up to 288MHz, etc. - - ARM Limited (ARM) is supplying this software for use with Cortex-M\n - processor based microcontroller, but can be equally used for other\n - suitable processor architectures. This file can be freely distributed.\n - Modifications to this file shall be clearly marked.\n - \n - THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n - OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n - ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n - CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - - - CM4 - r0p1 - little - false - true - 4 - false - - 8 - 32 - - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - - XMC - Flexible static memory controller - XMC - 0xA0000000 - - 0x0 - 0x1000 - registers - - - XMC - XMC global interrupt - 48 - - - - BK1CTRL1 - BK1CTRL1 - SRAM/NOR-Flash chip-select control register - 1 - 0x0 - 0x20 - read-write - 0x000030DB - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG1 - BK1TMG1 - SRAM/NOR-Flash chip-select timing register - 1 - 0x4 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL2 - BK1CTRL2 - SRAM/NOR-Flash chip-select control register - 2 - 0x8 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG2 - BK1TMG2 - SRAM/NOR-Flash chip-select timing register - 2 - 0xC - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL3 - BK1CTRL3 - SRAM/NOR-Flash chip-select control register - 3 - 0x10 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG3 - BK1TMG3 - SRAM/NOR-Flash chip-select timing register - 3 - 0x14 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1CTRL4 - BK1CTRL4 - SRAM/NOR-Flash chip-select control register - 4 - 0x18 - 0x20 - read-write - 0x000030D2 - - - MWMC - Memory write mode control - 19 - 1 - - - CRPGS - CRAM page size - 16 - 3 - - - NWASEN - NWAIT in asynchronous transfer enable - 15 - 1 - - - RWTD - Read-write timing different - 14 - 1 - - - NWSEN - NWAIT in synchronous transfer enable - 13 - 1 - - - WEN - Write enable - 12 - 1 - - - NWTCFG - Wait timing configuration - 11 - 1 - - - WRAPEN - Wrapped enable - 10 - 1 - - - NWPOL - NWAIT polarity - 9 - 1 - - - SYNCBEN - Synchronous burst enable - 8 - 1 - - - NOREN - Nor flash access enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 2 - 2 - - - ADMUXEN - Address and data multiplexing enable - 1 - 1 - - - EN - Memory bank enable - 0 - 1 - - - - - BK1TMG4 - BK1TMG4 - SRAM/NOR-Flash chip-select timing register - 4 - 0x1C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - DTLAT - Data latency - 24 - 4 - - - CLKPSC - Clock prescale - 20 - 4 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK2CTRL - BK2CTRL - PC Card/NAND Flash control register - 2 - 0x60 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK2IS - BK2IS - FIFO status and interrupt register - 2 - 0x64 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK2TMGRG - BK2TMGRG - Regular memory space timing register - 2 - 0x68 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK2TMGSP - BK2TMGSP - special memory space timing register - 2 - 0x6C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK2ECC - BK2ECC - ECC result register 2 - 0x74 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK3CTRL - BK3CTRL - PC Card/NAND Flash control register - 3 - 0x80 - 0x20 - read-write - 0x00000018 - - - ECCPGS - ECC page size - 17 - 3 - - - TAR - ALE to RE delay - 13 - 4 - - - TCR - CLE to RE delay - 9 - 4 - - - ECCEN - ECC enable - 6 - 1 - - - EXTMDBW - External memory data bus width - 4 - 2 - - - DEV - Memory device type - 3 - 1 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK3IS - BK3IS - FIFO status and interrupt register - 3 - 0x84 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK3TMGRG - BK3TMGRG - Regular memory space timing register - 3 - 0x88 - 0x20 - read-write - 0xFCFCFCFC - - - RGDHIZT - Regular memory databus High resistance time - 24 - 8 - - - RGHT - Regular memory hold time - 16 - 8 - - - RGWT - Regular memory wait time - 8 - 8 - - - RGST - Regular memory setup time - 0 - 8 - - - - - BK3TMGSP - BK3TMGSP - special memory space timing register - 3 - 0x8C - 0x20 - read-write - 0xFCFCFCFC - - - SPDHIZT - special memory databus High resistance time - 24 - 8 - - - SPHT - special memory hold time - 16 - 8 - - - SPWT - special memory wait time - 8 - 8 - - - SPST - special memory setup time - 0 - 8 - - - - - BK3ECC - BK3ECC - ECC result register 3 - 0x94 - 0x20 - read-write - 0x00000000 - - - ECC - ECC result - 0 - 32 - - - - - BK4CTRL - BK4CTRL - PC Card/NAND Flash control register - 4 - 0xA0 - 0x20 - read-write - 0x00000018 - - - EN - Memory bank enable - 2 - 1 - - - NWEN - Wait feature enable - 1 - 1 - - - - - BK4IS - BK4IS - FIFO status and interrupt register - 4 - 0xA4 - 0x20 - 0x00000040 - - - FIFOE - FIFO empty - 6 - 1 - read-only - - - FEIEN - Falling edge interrupt enable - 5 - 1 - read-write - - - HLIEN - High-level interrupt enable - 4 - 1 - read-write - - - REIEN - Rising edge interrupt enable - 3 - 1 - read-write - - - FES - Falling edge status - 2 - 1 - read-write - - - HLS - High-level status - 1 - 1 - read-write - - - RES - Rising edge capture status - 0 - 1 - read-write - - - - - BK4TMGCM - BK4TMGCM - Regular memory space timing register - 4 - 0xA8 - 0x20 - read-write - 0xFCFCFCFC - - - CMDHIZT - Regular memory databus High resistance time - 24 - 8 - - - CMHT - Regular memory hold time - 16 - 8 - - - CMWT - Regular memory wait time - 8 - 8 - - - CMST - Regular memory setup time - 0 - 8 - - - - - BK4TMGAT - BK4TMGAT - special memory space timing register - 4 - 0xAC - 0x20 - read-write - 0xFCFCFCFC - - - ATDHIZT - special memory databus High resistance time - 24 - 8 - - - ATHT - special memory hold time - 16 - 8 - - - ATWT - special memory wait time - 8 - 8 - - - ATST - special memory setup time - 0 - 8 - - - - - BK4TMGIO - BK4TMGIO - I/O space timing register 4 - 0xB0 - 0x20 - read-write - 0xFCFCFCFC - - - IODHIZT - WRSTP - 24 - 8 - - - IOHT - HLD - 16 - 8 - - - IOWT - OP - 8 - 8 - - - IOST - STP - 0 - 8 - - - - - BK1TMGWR1 - BK1TMGWR1 - SRAM/NOR-Flash write timing registers - 1 - 0x104 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR2 - BK1TMGWR2 - SRAM/NOR-Flash write timing registers - 2 - 0x10C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR3 - BK1TMGWR3 - SRAM/NOR-Flash write timing registers - 3 - 0x114 - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - BK1TMGWR4 - BK1TMGWR4 - SRAM/NOR-Flash write timing registers - 4 - 0x11C - 0x20 - read-write - 0x0FFFFFFF - - - ASYNCM - Asynchronous mode - 28 - 2 - - - BUSLAT - Bus latency - 16 - 4 - - - DTST - Asynchronous data setup time - 8 - 8 - - - ADDRHT - Address-hold time - 4 - 4 - - - ADDRST - Address setup time - 0 - 4 - - - - - CTRL1 - CTRL1 - SDRAM Control Register 1 - 0x140 - 0x20 - read-write - 0x000002D0 - - - CA - Number of column address - bits - 0 - 2 - - - RA - Number of row address bits - 2 - 2 - - - DB - Memory data bus width - 4 - 2 - - - INBK - Number of internal banks - 6 - 1 - - - CAS - CAS latency - 7 - 2 - - - WRP - Write protection - 9 - 1 - - - CLKDIV - Clock division configuration - 10 - 2 - - - BSTR - Burst read - 12 - 1 - - - RD - Read delay - 13 - 2 - - - - - CTRL2 - CTRL2 - SDRAM Control Register 2 - 0x144 - 0x20 - read-write - 0x000002D0 - - - CA - Number of column address - bits - 0 - 2 - - - RA - Number of row address bits - 2 - 2 - - - DB - Memory data bus width - 4 - 2 - - - INBK - Number of internal banks - 6 - 1 - - - CAS - CAS latency - 7 - 2 - - - WRP - Write protection - 9 - 1 - - - CLKDIV - Clock division configuration - 10 - 2 - - - BSTR - Burst read - 12 - 1 - - - RD - Read pipe - 13 - 2 - - - - - TM1 - TM1 - SDRAM Timing register 1 - 0x148 - 0x20 - read-write - 0x0FFFFFFF - - - TMRD - Mode register program to active delay - 0 - 4 - - - TXSR - Exit Self-refresh to active delay - 4 - 4 - - - TRAS - Self refresh time - 8 - 4 - - - TRC - Refresh to active delay - 12 - 4 - - - TWR - Write Recovery delay - 16 - 4 - - - TRP - Precharge to active delay - 20 - 4 - - - TRCD - Row active to Read/Write delay - 24 - 4 - - - - - TM2 - TM2 - SDRAM Timing register 2 - 0x14C - 0x20 - read-write - 0x0FFFFFFF - - - TMRD - Mode register program to active delay - 0 - 4 - - - TXSR - Exit Self-refresh to active delay - 4 - 4 - - - TRAS - Self refresh time - 8 - 4 - - - TRC - Refresh to active delay - 12 - 4 - - - TWR - Write Recovery delay - 16 - 4 - - - TRP - Precharge to active delay - 20 - 4 - - - TRCD - Row active to Read/Write delay - 24 - 4 - - - - - CMD - CMD - SDRAM Command Mode register - 0x150 - 0x20 - 0x00000000 - - - CMD - SDRAM Command - 0 - 3 - write-only - - - BK2 - SDRAM Bank 2 - 3 - 1 - write-only - - - BK1 - SDRAM Bank 1 - 4 - 1 - write-only - - - ART - Auto-refresh times - 5 - 4 - read-write - - - MRD - Mode register data - 9 - 13 - read-write - - - - - RCNT - RCNT - SDRAM Refresh Timer register - 0x154 - 0x20 - 0x00000000 - - - ERRC - error flag clear - 0 - 1 - write-only - - - RC - Refresh Count - 1 - 13 - read-write - - - ERIEN - error Interrupt Enable - 14 - 1 - read-write - - - - - STS - STS - SDRAM Status register - 0x158 - 0x20 - read-only - 0x00000000 - - - ERR - error flag - 0 - 1 - - - BK1STS - Bank 1 Status - 1 - 2 - - - BK2STS - Bank 2 Status - 3 - 2 - - - BUSY - Busy status - 5 - 1 - - - - - EXT1 - EXT1 - externl timeing register 1 - 0x220 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT2 - EXT2 - externl timeing register 2 - 0x224 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT3 - EXT3 - externl timeing register 3 - 0x228 - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - EXT4 - EXT4 - externl timeing register 4 - 0x22C - 0x20 - read-write - 0x00000808 - - - BUSLATW2W - Bus turnaround phase for consecutive write duration - 0 - 8 - - - BUSLATR2R - Bus turnaround phase for consecutive read duration - 8 - 8 - - - - - - - PWC - Power control - PWC - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Power control register - (PWC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - VRSEL - Voltage regulator state select when deepsleep mode - 0 - 1 - - - LPSEL - Low power mode select when Cortex-M4F sleepdeep - 1 - 1 - - - CLSWEF - Clear SWEF flag - 2 - 1 - - - CLSEF - Clear SEF flag - 3 - 1 - - - PVMEN - Power voltage monitoring enable - 4 - 1 - - - PVMSEL - Power voltage monitoring boundary select - 5 - 3 - - - BPWEN - Battery powered domain write enable - 8 - 1 - - - - - CTRLSTS - CTRLSTS - Power control and status register - (PWC_CTRLSTS) - 0x4 - 0x20 - 0x00000000 - - - SWEF - Standby wake-up event flag - 0 - 1 - read-only - - - SEF - Standby mode entry flag - 1 - 1 - read-only - - - PVMOF - Power voltage monitoring output flag - 2 - 1 - read-only - - - SWPEN1 - Standby wake-up pin 1 enable - 8 - 1 - read-write - - - SWPEN2 - Standby wake-up pin 2 enable - 9 - 1 - read-write - - - - - LDOOV - LDOOV - LDO output voltage register - 0x10 - 0x20 - 0x00000000 - - - LDOOVSEL - LDO output voltage select - 0 - 3 - read-write - - - - - - - CRM - Clock and reset management - CRM - 0x40023800 - - 0x0 - 0x400 - registers - - - CRM - CRM global interrupt - 5 - - - - CTRL - CTRL - Clock control register - 0x0 - 0x20 - 0x00000083 - - - HICKEN - High speed internal clock enable - 0 - 1 - read-write - - - HICKSTBL - High speed internal clock ready flag - 1 - 1 - read-only - - - HICKTRIM - High speed internal clock trimming - 2 - 6 - read-write - - - HICKCAL - High speed internal clock calibration - 8 - 8 - read-only - - - HEXTEN - High speed exernal crystal enable - 16 - 1 - read-write - - - HEXTSTBL - High speed exernal crystal ready flag - 17 - 1 - read-only - - - HEXTBYPS - High speed exernal crystal bypass - 18 - 1 - read-write - - - CFDEN - Clock failure detection enable - 19 - 1 - read-write - - - PLLEN - PLL enable - 24 - 1 - read-write - - - PLLSTBL - PLL clock ready flag - 25 - 1 - read-only - - - - - PLLCFG - PLLCFG - PLL configuration register - (CRM_PLLCFG) - 0x4 - 0x20 - 0x00033002 - - - PLL_MS - PLL pre-division - 0 - 4 - read-write - - - PLL_NS - PLL frequency multiplication factor - 6 - 9 - read-write - - - PLL_FR - PLL post-division - 16 - 3 - read-write - - - PLLRCS - PLL reference clock select - 22 - 1 - read-write - - - - - CFG - CFG - Clock configuration register(CRM_CFG) - 0x8 - 0x20 - 0x00000000 - - - SCLKSEL - System clock select - 0 - 2 - read-write - - - SCLKSTS - System Clock select Status - 2 - 2 - read-only - - - AHBDIV - AHB division - 4 - 4 - read-write - - - APB1DIV - APB1 division - 10 - 3 - read-write - - - APB2DIV - APB2 division - 13 - 3 - read-write - - - ERTCDIV - HEXT division for ERTC clock - 16 - 5 - read-write - - - CLKOUT1_SEL - Clock output1 selection - 21 - 2 - read-write - - - CLKOUT1DIV1 - Clock output1 division1 - 24 - 3 - read-write - - - CLKOUT2DIV1 - Clock output2 division1 - 27 - 3 - read-write - - - CLKOUT2_SEL1 - Clock output2 selection1 - 30 - 2 - read-write - - - - - CLKINT - CLKINT - Clock interrupt register - (CRM_CLKINT) - 0xC - 0x20 - 0x00000000 - - - LICKSTBLF - LICK ready interrupt flag - 0 - 1 - read-only - - - LEXTSTBLF - LEXT ready interrupt flag - 1 - 1 - read-only - - - HICKSTBLF - HICK ready interrupt flag - 2 - 1 - read-only - - - HEXTSTBLF - HEXT ready interrupt flag - 3 - 1 - read-only - - - PLLSTBLF - PLL ready interrupt flag - 4 - 1 - read-only - - - CFDF - Clock failure detection interrupt flag - 7 - 1 - read-only - - - LICKSTBLIEN - LICK ready interrupt enable - 8 - 1 - read-write - - - LEXTSTBLIEN - LEXT ready interrupt enable - 9 - 1 - read-write - - - HICKSTBLIEN - HICK ready interrupt enable - 10 - 1 - read-write - - - HEXTSTBLIEN - HEXT ready interrupt enable - 11 - 1 - read-write - - - PLLSTBLIEN - PLL ready interrupt enable - 12 - 1 - read-write - - - LICKSTBLFC - LICK ready interrupt clear - 16 - 1 - write-only - - - LEXTSTBLFC - LEXT ready interrupt clear - 17 - 1 - write-only - - - HICKSTBLFC - HICK ready interrupt clear - 18 - 1 - write-only - - - HEXTSTBLFC - HEXT ready interrupt clear - 19 - 1 - write-only - - - PLLSTBLFC - PLL ready interrupt clear - 20 - 1 - write-only - - - CFDFC - Clock failure detection interrupt clear - 23 - 1 - write-only - - - - - AHBRST1 - AHBRST1 - AHB peripheral reset register1 - (CRM_AHBRST1) - 0x10 - 0x20 - read-write - 0x000000000 - - - GPIOARST - IO port A reset - 0 - 1 - - - GPIOBRST - IO port B reset - 1 - 1 - - - GPIOCRST - IO port C reset - 2 - 1 - - - GPIODRST - IO port D reset - 3 - 1 - - - GPIOERST - IO port E reset - 4 - 1 - - - GPIOFRST - IO port F reset - 5 - 1 - - - GPIOGRST - IO port G reset - 6 - 1 - - - GPIOHRST - IO port H reset - 7 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - EDMARST - EDMA reset - 21 - 1 - - - DMA1RST - DMA1 reset - 22 - 1 - - - DMA2RST - DMA2 reset - 24 - 1 - - - EMACRST - EMAC reset - 25 - 1 - - - OTGFS2RST - OTGFS2 interface reset - 29 - 1 - - - - - AHBRST2 - AHBRST2 - AHB peripheral reset register 2 - (CRM_AHBRST2) - 0x14 - 0x20 - read-write - 0x00000000 - - - DVPRST - DVP reset - 0 - 1 - - - OTGFS1RST - OTGFS1 reset - 7 - 1 - - - SDIO1RST - SDIO1 reset - 15 - 1 - - - - - AHBRST3 - AHBRST3 - AHB peripheral reset register 3 - (CRM_AHBRST3) - 0x18 - 0x20 - read-write - 0x00000000 - - - XMCRST - XMC reset - 0 - 1 - - - QSPI1RST - QSPI1 reset - 1 - 1 - - - QSPI2RST - QSPI2 reset - 14 - 1 - - - SDIO2RST - SDIO2 reset - 15 - 1 - - - - - APB1RST - APB1RST - APB1 peripheral reset register - (CRM_APB1RST) - 0x20 - 0x20 - read-write - 0x00000000 - - - TMR2RST - Timer2 reset - 0 - 1 - - - TMR3RST - Timer3 reset - 1 - 1 - - - TMR4RST - Timer4 reset - 2 - 1 - - - TMR5RST - Timer5 reset - 3 - 1 - - - TMR6RST - Timer6 reset - 4 - 1 - - - TMR7RST - Timer7 reset - 5 - 1 - - - TMR12RST - Timer12 reset - 6 - 1 - - - TMR13RST - Timer13 reset - 7 - 1 - - - TMR14RST - Timer14 reset - 8 - 1 - - - WWDTRST - Window watchdog reset - 11 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - SPI3RST - SPI3 reset - 15 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - UART4RST - UART4 reset - 19 - 1 - - - UART5RST - UART5 reset - 20 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C3RST - I2C3 reset - 23 - 1 - - - CAN1RST - CAN1 reset - 25 - 1 - - - CAN2RST - CAN2 reset - 26 - 1 - - - PWCRST - PWC reset - 28 - 1 - - - DACRST - DAC reset - 29 - 1 - - - UART7RST - UART7 reset - 30 - 1 - - - UART8RST - UART8 reset - 31 - 1 - - - - - APB2RST - APB2RST - APB2 peripheral reset register - (CRM_APB2RST) - 0x24 - 0x20 - read-write - 0x00000000 - - - TMR1RST - Timer1 reset - 0 - 1 - - - TMR8RST - Timer8 reset - 1 - 1 - - - USART1RST - USART1 reset - 4 - 1 - - - USART6RST - USART6 reset - 5 - 1 - - - ADCRST - ADC reset - 8 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - SPI4RST - SPI4 reset - 13 - 1 - - - SCFGRST - SCFG reset - 14 - 1 - - - TMR9RST - Timer9 reset - 16 - 1 - - - TMR10RST - Timer10 reset - 17 - 1 - - - TMR11RST - Timer 11 reset - 18 - 1 - - - TMR20RST - Timer20 reset - 20 - 1 - - - ACCRST - ACC reset - 29 - 1 - - - - - AHBEN1 - AHBEN1 - AHB Peripheral Clock enable register 1 - (CRM_AHBEN1) - 0x30 - 0x20 - read-write - 0x00000000 - - - GPIOAEN - IO A clock enable - 0 - 1 - - - GPIOBEN - IO B clock enable - 1 - 1 - - - GPIOCEN - IO C clock enable - 2 - 1 - - - GPIODEN - IO D clock enable - 3 - 1 - - - GPIOEEN - IO E clock enable - 4 - 1 - - - GPIOFEN - IO F clock enable - 5 - 1 - - - GPIOGEN - IO G clock enable - 6 - 1 - - - GPIOHEN - IO H clock enable - 7 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - EDMAEN - DMA1 clock enable - 21 - 1 - - - DMA1EN - DMA1 clock enable - 22 - 1 - - - DMA2EN - DMA2 clock enable - 24 - 1 - - - EMACEN - EMAC clock enable - 25 - 1 - - - EMACTXEN - EMAC Tx clock enable - 26 - 1 - - - EMACRXEN - EMAC Rx clock enable - 27 - 1 - - - EMACPTPEN - EMAC PTP clock enable - 28 - 1 - - - OTGFS2EN - OTGFS2 clock enable - 29 - 1 - - - - - AHBEN2 - AHBEN2 - AHB peripheral clock enable register 2 - (CRM_AHBEN2) - 0x34 - 0x20 - read-write - 0x00000000 - - - DVPEN - DVP clock enable - 0 - 1 - - - OTGFS1EN - OTGFS1 clock enable - 7 - 1 - - - SDIO1EN - SDIO1 clock enable - 15 - 1 - - - - - AHBEN3 - AHBEN3 - AHB peripheral clock enable register 3 - (CRM_AHBEN3) - 0x38 - 0x20 - read-write - 0x00000000 - - - XMCEN - XMC clock enable - 0 - 1 - - - QSPI1EN - QSPI1 clock enable - 1 - 1 - - - QSPI2EN - QSPI2 clock enable - 14 - 1 - - - SDIO2EN - SDIO 2 clock enable - 15 - 1 - - - - - APB1EN - APB1EN - APB1 peripheral clock enable register - (CRM_APB1EN) - 0x40 - 0x20 - read-write - 0x00000000 - - - TMR2EN - Timer2 clock enable - 0 - 1 - - - TMR3EN - Timer3 clock enable - 1 - 1 - - - TMR4EN - Timer4 clock enable - 2 - 1 - - - TMR5EN - Timer5 clock enable - 3 - 1 - - - TMR6EN - Timer6 clock enable - 4 - 1 - - - TMR7EN - Timer7 clock enable - 5 - 1 - - - TMR12EN - Timer12 clock enable - 6 - 1 - - - TMR13EN - Timer13 clock enable - 7 - 1 - - - TMR14EN - Timer14 clock enable - 8 - 1 - - - WWDTEN - WWDT clock enable - 11 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - SPI3EN - SPI3 clock enable - 15 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - UART4EN - UART4 clock enable - 19 - 1 - - - UART5EN - UART5 clock enable - 20 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C3EN - I2C3 clock enable - 23 - 1 - - - CAN1EN - CAN1 clock enable - 25 - 1 - - - CAN2EN - CAN2 clock enable - 26 - 1 - - - PWCEN - PWC clock enable - 28 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - UART7EN - UART7 clock enable - 30 - 1 - - - UART8EN - UART8 clock enable - 31 - 1 - - - - - APB2EN - APB2EN - APB2 peripheral clock enable register - (CRM_APB2EN) - 0x44 - 0x20 - read-write - 0x00000000 - - - TMR1EN - Timer1 clock enable - 0 - 1 - - - TMR8EN - Timer8 clock enable - 1 - 1 - - - USART1EN - USART1 clock enable - 4 - 1 - - - USART6EN - USART6 clock enable - 5 - 1 - - - ADC1EN - ADC1 clock enable - 8 - 1 - - - ADC2EN - ADC2 clock enable - 9 - 1 - - - ADC3EN - ADC3 clock enable - 10 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - SPI4EN - SPI4 clock enable - 13 - 1 - - - SCFGEN - SCFG clock enable - 14 - 1 - - - TMR9EN - Timer9 clock enable - 16 - 1 - - - TMR10EN - Timer10 clock enable - 17 - 1 - - - TMR11EN - Timer11 clock enable - 18 - 1 - - - TMR20EN - Timer20 clock enable - 20 - 1 - - - ACCEN - ACC clock enable - 29 - 1 - - - - - AHBLPEN1 - AHBLPEN1 - AHB Low-power Peripheral Clock enable - register 1 (CRM_AHBLPEN1) - 0x50 - 0x20 - read-write - 0x3E6390FF - - - GPIOALPEN - IO A clock enable during sleep mode - 0 - 1 - - - GPIOBLPEN - IO B clock enable during sleep mode - 1 - 1 - - - GPIOCLPEN - IO C clock enable during sleep mode - 2 - 1 - - - GPIODLPEN - IO D clock enable during sleep mode - 3 - 1 - - - GPIOELPEN - IO E clock enable during sleep mode - 4 - 1 - - - GPIOFLPEN - IO F clock enable during sleep mode - 5 - 1 - - - GPIOGLPEN - IO G clock enable during sleep mode - 6 - 1 - - - GPIOHLPEN - IO H clock enable during sleep mode - 7 - 1 - - - CRCLPEN - CRC clock enable during sleep mode - 12 - 1 - - - FLASHLPEN - Flash clock enable during sleep mode - 15 - 1 - - - SRAM1LPEN - SRAM1 clock enable during sleep mode - 16 - 1 - - - SRAM2LPEN - SRAM2 clock enable during sleep mode - 17 - 1 - - - EDMALPEN - EDMA clock enable during sleep mode - 21 - 1 - - - DMA1LPEN - DMA1 clock enable during sleep mode - 22 - 1 - - - DMA2LPEN - DMA2 clock enable during sleep mode - 24 - 1 - - - EMACLPEN - EMAC clock enable during sleep mode - 25 - 1 - - - EMACTXLPEN - EMAC Tx clock enable during sleep mode - 26 - 1 - - - EMACRXLPEN - EMAC Rx clock enable during sleep mode - 27 - 1 - - - EMACPTPLPEN - EMAC PTP clock enable during sleep mode - 28 - 1 - - - OTGFS2LPEN - OTGFS2 clock enable during sleep mode - 29 - 1 - - - - - AHBLPEN2 - AHBLPEN2 - AHB peripheral Low-power clock - enable register 2 (CRM_AHBLPEN2) - 0x54 - 0x20 - read-write - 0x00008081 - - - DVPLPEN - DVP clock enable during sleep mode - 0 - 1 - - - OTGFS1LPEN - OTGFS1 clock enable during sleep mode - 7 - 1 - - - SDIO1LPEN - SDIO1 clock enable during sleep mode - 15 - 1 - - - - - AHBLPEN3 - AHBLPEN3 - AHB peripheral Low-power clock - enable register 3 (CRM_AHBLPEN3) - 0x58 - 0x20 - read-write - 0x0000C003 - - - XMCLPEN - XMC clock enable during sleep mode - 0 - 1 - - - QSPI1LPEN - QSPI1 clock enable during sleep mode - 1 - 1 - - - QSPI2LPEN - QSPI2 clock enable during sleep mode - 14 - 1 - - - SDIO2LPEN - SDIO2 clock enable during sleep mode - 15 - 1 - - - - - APB1LPEN - APB1LPEN - APB1 peripheral Low-power clock - enable register (CRM_APB1LPEN) - 0x60 - 0x20 - read-write - 0xF6FEE9FF - - - TMR2LPEN - Timer2 clock enable during sleep mode - 0 - 1 - - - TMR3LPEN - Timer3 clock enable during sleep mode - 1 - 1 - - - TMR4LPEN - Timer4 clock enable during sleep mode - 2 - 1 - - - TMR5LPEN - Timer5 clock enable during sleep mode - 3 - 1 - - - TMR6LPEN - Timer6 clock enable during sleep mode - 4 - 1 - - - TMR7LPEN - Timer7 clock enable during sleep mode - 5 - 1 - - - TMR12LPEN - Timer12 clock enable during sleep mode - 6 - 1 - - - TMR13LPEN - Timer13 clock enable during sleep mode - 7 - 1 - - - TMR14LPEN - Timer14 clock enable during sleep mode - 8 - 1 - - - WWDTLPEN - WWDT clock enable during sleep mode - 11 - 1 - - - SPI2LPEN - SPI2 clock enable during sleep mode - 14 - 1 - - - SPI3LPEN - SPI3 clock enable during sleep mode - 15 - 1 - - - USART2LPEN - USART2 clock enable during sleep mode - 17 - 1 - - - USART3LPEN - USART3 clock enable during sleep mode - 18 - 1 - - - UART4LPEN - UART4 clock enable during sleep mode - 19 - 1 - - - UART5LPEN - UART5 clock enable during sleep mode - 20 - 1 - - - I2C1CPEN - I2C1 clock enable during sleep mode - 21 - 1 - - - I2C2CPEN - I2C2 clock enable during sleep mode - 22 - 1 - - - I2C3CPEN - I2C3 clock enable during sleep mode - 23 - 1 - - - CAN1LPEN - CAN1 clock enable during sleep mode - 25 - 1 - - - CAN2LPEN - CAN2 clock enable during sleep mode - 26 - 1 - - - PWCLPEN - PWC clock enable during sleep mode - 28 - 1 - - - DACLPEN - DAC clock enable during sleep mode - 29 - 1 - - - UART7LPEN - UART7 clock enable during sleep mode - 30 - 1 - - - UART8LPEN - UART8 clock enable during sleep mode - 31 - 1 - - - - - APB2LPEN - APB2LPEN - APB2 peripheral Low-power clock - enable register (CRM_APB2LPEN) - 0x64 - 0x20 - read-write - 0x20177733 - - - TMR1LPEN - Timer1 clock enable during sleep mode - 0 - 1 - - - TMR8LPEN - Timer8 clock enable during sleep mode - 1 - 1 - - - USART1LPEN - USART1 clock enable during sleep mode - 4 - 1 - - - USART6LPEN - USART6 clock enable during sleep mode - 5 - 1 - - - ADC1CPEN - ADC1 clock enable during sleep mode - 8 - 1 - - - ADC2CPEN - ADC2 clock enable during sleep mode - 9 - 1 - - - ADC3EN - ADC3 clock enable during sleep mode - 10 - 1 - - - SPI1LPEN - SPI1 clock enable during sleep mode - 12 - 1 - - - SPI4LPEN - SPI4 clock enable during sleep mode - 13 - 1 - - - SCFGLPEN - SCFG clock enable during sleep mode - 14 - 1 - - - TMR9LPEN - Timer9 clock enable during sleep mode - 16 - 1 - - - TMR10LPEN - Timer10 clock enable during sleep mode - 17 - 1 - - - TMR11LPEN - Timer11 clock enable during sleep mode - 18 - 1 - - - TMR20LPEN - Timer20 clock enable during sleep mode - 20 - 1 - - - ACCLPEN - ACC clock enable during sleep mode - 29 - 1 - - - - - BPDC - BPDC - Battery powered domain control register - (CRM_BPDC) - 0x70 - 0x20 - 0x00000000 - - - LEXTEN - Low speed external crystal enable - 0 - 1 - read-write - - - LEXTSTBL - Low speed external crystal ready - 1 - 1 - read-only - - - LEXTBYPS - Low speed external crystal bypass - 2 - 1 - read-write - - - ERTCSEL - ERTC clock source selection - 8 - 2 - read-write - - - ERTCEN - ERTC clock enable - 15 - 1 - read-write - - - BPDRST - Battery powered domain software reset - 16 - 1 - read-write - - - - - CTRLSTS - CTRLSTS - Control/status register - (CRM_CTRLSTS) - 0x74 - 0x20 - 0x0C000000 - - - LICKEN - Low speed internal clock enable - 0 - 1 - read-write - - - LICKSTBL - Low speed internal clock ready - 1 - 1 - read-only - - - RSTFC - Reset reset flag - 24 - 1 - read-write - - - NRSTF - PIN reset flag - 26 - 1 - read-write - - - PORRSTF - POR/LVR reset flag - 27 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - WDTRSTF - Watchdog timer reset flag - 29 - 1 - read-write - - - WWDTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - - - MISC1 - MISC1 - Miscellaneous register1 - 0xA0 - 0x20 - 0x00000000 - - - HICKCAL_KEY - HICKCAL write key value - 0 - 8 - read-write - - - HICKDIV - HICK 6 divider selection - 12 - 1 - read-write - - - HICK_TO_USB - HICK to usb clock - 13 - 1 - read-write - - - HICK_TO_SCLK - HICK to system clock - 14 - 1 - read-write - - - CLKOUT2_SEL2 - Clock output2 select2 - 16 - 4 - read-write - - - CLKOUT1DIV2 - Clock output1 division2 - 24 - 4 - read-write - - - CLKOUT2DIV2 - Clock output2 division2 - 28 - 4 - read-write - - - - - MISC2 - MISC2 - Miscellaneous register2 - 0xA4 - 0x20 - 0x0000000D - - - AUTO_STEP_EN - AUTO_STEP_EN - 4 - 2 - read-write - - - CLK_TO_TMR - Clock output internal connect to timer10 - 8 - 1 - read-write - - - USBDIV - USB division - 12 - 4 - read-write - - - - - - - GPIOA - General purpose I/Os - GPIO - 0x40020000 - - 0x0 - 0x400 - registers - - - - CFGR - CFGR - GPIO configuration register - 0x0 - 0x20 - read-write - 0x00000000 - - - IOMC15 - GPIOx pin 15 mode configurate - 30 - 2 - - - IOMC14 - GPIOx pin 14 mode configurate - 28 - 2 - - - IOMC13 - GPIOx pin 13 mode configurate - 26 - 2 - - - IOMC12 - GPIOx pin 12 mode configurate - 24 - 2 - - - IOMC11 - GPIOx pin 11 mode configurate - 22 - 2 - - - IOMC10 - GPIOx pin 10 mode configurate - 20 - 2 - - - IOMC9 - GPIOx pin 9 mode configurate - 18 - 2 - - - IOMC8 - GPIOx pin 8 mode configurate - 16 - 2 - - - IOMC7 - GPIOx pin 7 mode configurate - 14 - 2 - - - IOMC6 - GPIOx pin 6 mode configurate - 12 - 2 - - - IOMC5 - GPIOx pin 5 mode configurate - 10 - 2 - - - IOMC4 - GPIOx pin 4 mode configurate - 8 - 2 - - - IOMC3 - GPIOx pin 3 mode configurate - 6 - 2 - - - IOMC2 - GPIOx pin 2 mode configurate - 4 - 2 - - - IOMC1 - GPIOx pin 1 mode configurate - 2 - 2 - - - IOMC0 - GPIOx pin 0 mode configurate - 0 - 2 - - - - - OMODE - OMODE - GPIO output mode register - 0x4 - 0x20 - read-write - 0x00000000 - - - OM15 - GPIOx pin 15 outpu mode configurate - 15 - 1 - - - OM14 - GPIOx pin 14 outpu mode configurate - 14 - 1 - - - OM13 - GPIOx pin 13 outpu mode configurate - 13 - 1 - - - OM12 - GPIOx pin 12 outpu mode configurate - 12 - 1 - - - OM11 - GPIOx pin 11 outpu mode configurate - 11 - 1 - - - OM10 - GPIOx pin 10 outpu mode configurate - 10 - 1 - - - OM9 - GPIOx pin 9 outpu mode configurate - 9 - 1 - - - OM8 - GPIOx pin 8 outpu mode configurate - 8 - 1 - - - OM7 - GPIOx pin 7 outpu mode configurate - 7 - 1 - - - OM6 - GPIOx pin 6 outpu mode configurate - 6 - 1 - - - OM5 - GPIOx pin 5 outpu mode configurate - 5 - 1 - - - OM4 - GPIOx pin 4 outpu mode configurate - 4 - 1 - - - OM3 - GPIOx pin 3 outpu mode configurate - 3 - 1 - - - OM2 - GPIOx pin 2 outpu mode configurate - 2 - 1 - - - OM1 - GPIOx pin 1 outpu mode configurate - 1 - 1 - - - OM0 - GPIOx pin 0 outpu mode configurate - 0 - 1 - - - - - ODRVR - ODRVR - GPIO drive capability register - 0x8 - 0x20 - read-write - 0x00000000 - - - ODRV15 - GPIOx pin 15 output drive capability - 30 - 2 - - - ODRV14 - GPIOx pin 14 output drive capability - 28 - 2 - - - ODRV13 - GPIOx pin 13 output drive capability - 26 - 2 - - - ODRV12 - GPIOx pin 12 output drive capability - 24 - 2 - - - ODRV11 - GPIOx pin 11 output drive capability - 22 - 2 - - - ODRV10 - GPIOx pin 10 output drive capability - 20 - 2 - - - ODRV9 - GPIOx pin 9 output drive capability - 18 - 2 - - - ODRV8 - GPIOx pin 8 output drive capability - 16 - 2 - - - ODRV7 - GPIOx pin 7 output drive capability - 14 - 2 - - - ODRV6 - GPIOx pin 6 output drive capability - 12 - 2 - - - ODRV5 - GPIOx pin 5 output drive capability - 10 - 2 - - - ODRV4 - GPIOx pin 4 output drive capability - 8 - 2 - - - ODRV3 - GPIOx pin 3 output drive capability - 6 - 2 - - - ODRV2 - GPIOx pin 2 output drive capability - 4 - 2 - - - ODRV1 - GPIOx pin 1 output drive capability - 2 - 2 - - - ODRV0 - GPIOx pin 0 output drive capability - 0 - 2 - - - - - PULL - PULL - GPIO pull-up/pull-down register - 0xC - 0x20 - read-write - 0x00000000 - - - PULL15 - GPIOx pin 15 pull configuration - 30 - 2 - - - PULL14 - GPIOx pin 14 pull configuration - 28 - 2 - - - PULL13 - GPIOx pin 13 pull configuration - 26 - 2 - - - PULL12 - GPIOx pin 12 pull configuration - 24 - 2 - - - PULL11 - GPIOx pin 11 pull configuration - 22 - 2 - - - PULL10 - GPIOx pin 10 pull configuration - 20 - 2 - - - PULL9 - GPIOx pin 9 pull configuration - 18 - 2 - - - PULL8 - GPIOx pin 8 pull configuration - 16 - 2 - - - PULL7 - GPIOx pin 7 pull configuration - 14 - 2 - - - PULL6 - GPIOx pin 6 pull configuration - 12 - 2 - - - PULL5 - GPIOx pin 5 pull configuration - 10 - 2 - - - PULL4 - GPIOx pin 4 pull configuration - 8 - 2 - - - PULL3 - GPIOx pin 3 pull configuration - 6 - 2 - - - PULL2 - GPIOx pin 2 pull configuration - 4 - 2 - - - PULL1 - GPIOx pin 1 pull configuration - 2 - 2 - - - PULL0 - GPIOx pin 0 pull configuration - 0 - 2 - - - - - IDT - IDT - GPIO input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - IDT0 - Port input data - 0 - 1 - - - IDT1 - Port input data - 1 - 1 - - - IDT2 - Port input data - 2 - 1 - - - IDT3 - Port input data - 3 - 1 - - - IDT4 - Port input data - 4 - 1 - - - IDT5 - Port input data - 5 - 1 - - - IDT6 - Port input data - 6 - 1 - - - IDT7 - Port input data - 7 - 1 - - - IDT8 - Port input data - 8 - 1 - - - IDT9 - Port input data - 9 - 1 - - - IDT10 - Port input data - 10 - 1 - - - IDT11 - Port input data - 11 - 1 - - - IDT12 - Port input data - 12 - 1 - - - IDT13 - Port input data - 13 - 1 - - - IDT14 - Port input data - 14 - 1 - - - IDT15 - Port input data - 15 - 1 - - - - - ODT - ODT - GPIO output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - ODT0 - Port output data - 0 - 1 - - - ODT1 - Port output data - 1 - 1 - - - ODT2 - Port output data - 2 - 1 - - - ODT3 - Port output data - 3 - 1 - - - ODT4 - Port output data - 4 - 1 - - - ODT5 - Port output data - 5 - 1 - - - ODT6 - Port output data - 6 - 1 - - - ODT7 - Port output data - 7 - 1 - - - ODT8 - Port output data - 8 - 1 - - - ODT9 - Port output data - 9 - 1 - - - ODT10 - Port output data - 10 - 1 - - - ODT11 - Port output data - 11 - 1 - - - ODT12 - Port output data - 12 - 1 - - - ODT13 - Port output data - 13 - 1 - - - ODT14 - Port output data - 14 - 1 - - - ODT15 - Port output data - 15 - 1 - - - - - SCR - SCR - Port bit set/clear register - 0x18 - 0x20 - write-only - 0x00000000 - - - IOSB0 - Set bit 0 - 0 - 1 - - - IOSB1 - Set bit 1 - 1 - 1 - - - IOSB2 - Set bit 1 - 2 - 1 - - - IOSB3 - Set bit 3 - 3 - 1 - - - IOSB4 - Set bit 4 - 4 - 1 - - - IOSB5 - Set bit 5 - 5 - 1 - - - IOSB6 - Set bit 6 - 6 - 1 - - - IOSB7 - Set bit 7 - 7 - 1 - - - IOSB8 - Set bit 8 - 8 - 1 - - - IOSB9 - Set bit 9 - 9 - 1 - - - IOSB10 - Set bit 10 - 10 - 1 - - - IOSB11 - Set bit 11 - 11 - 1 - - - IOSB12 - Set bit 12 - 12 - 1 - - - IOSB13 - Set bit 13 - 13 - 1 - - - IOSB14 - Set bit 14 - 14 - 1 - - - IOSB15 - Set bit 15 - 15 - 1 - - - IOCB0 - Clear bit 0 - 16 - 1 - - - IOCB1 - Clear bit 1 - 17 - 1 - - - IOCB2 - Clear bit 2 - 18 - 1 - - - IOCB3 - Clear bit 3 - 19 - 1 - - - IOCB4 - Clear bit 4 - 20 - 1 - - - IOCB5 - Clear bit 5 - 21 - 1 - - - IOCB6 - Clear bit 6 - 22 - 1 - - - IOCB7 - Clear bit 7 - 23 - 1 - - - IOCB8 - Clear bit 8 - 24 - 1 - - - IOCB9 - Clear bit 9 - 25 - 1 - - - IOCB10 - Clear bit 10 - 26 - 1 - - - IOCB11 - Clear bit 11 - 27 - 1 - - - IOCB12 - Clear bit 12 - 28 - 1 - - - IOCB13 - Clear bit 13 - 29 - 1 - - - IOCB14 - Clear bit 14 - 30 - 1 - - - IOCB15 - Clear bit 15 - 31 - 1 - - - - - WPR - WPR - Port write protect - register - 0x1C - 0x20 - read-write - 0x00000000 - - - WPEN0 - Write protect enable 0 - 0 - 1 - - - WPEN1 - Write protect enable 1 - 1 - 1 - - - WPEN2 - Write protect enable 2 - 2 - 1 - - - WPEN3 - Write protect enable 3 - 3 - 1 - - - WPEN4 - Write protect enable 4 - 4 - 1 - - - WPEN5 - Write protect enable 5 - 5 - 1 - - - WPEN6 - Write protect enable 6 - 6 - 1 - - - WPEN7 - Write protect enable 7 - 7 - 1 - - - WPEN8 - Write protect enable 8 - 8 - 1 - - - WPEN9 - Write protect enable 9 - 9 - 1 - - - WPEN10 - Write protect enable 10 - 10 - 1 - - - WPEN11 - Write protect enable 11 - 11 - 1 - - - WPEN12 - Write protect enable 12 - 12 - 1 - - - WPEN13 - Write protect enable 13 - 13 - 1 - - - WPEN14 - Write protect enable 14 - 14 - 1 - - - WPEN15 - Write protect enable 15 - 15 - 1 - - - WPSEQ - Write protect sequence - 16 - 1 - - - - - MUXL - MUXL - GPIO muxing function low register - 0x20 - 0x20 - read-write - 0x00000000 - - - MUXL7 - GPIOx pin 7 muxing - 28 - 4 - - - MUXL6 - GPIOx pin 6 muxing - 24 - 4 - - - MUXL5 - GPIOx pin 5 muxing - 20 - 4 - - - MUXL4 - GPIOx pin 4 muxing - 16 - 4 - - - MUXL3 - GPIOx pin 3 muxing - 12 - 4 - - - MUXL2 - GPIOx pin 2 muxing - 8 - 4 - - - MUXL1 - GPIOx pin 1 muxing - 4 - 4 - - - MUXL0 - GPIOx pin 0 muxing - 0 - 4 - - - - - MUXH - MUXH - GPIO muxing function high register - 0x24 - 0x20 - read-write - 0x00000000 - - - MUXH15 - GPIOx pin 15 muxing - 28 - 4 - - - MUXH14 - GPIOx pin 14 muxing - 24 - 4 - - - MUXH13 - GPIOx pin 13 muxing - 20 - 4 - - - MUXH12 - GPIOx pin 12 muxing - 16 - 4 - - - MUXH11 - GPIOx pin 11 muxing - 12 - 4 - - - MUXH10 - GPIOx pin 10 muxing - 8 - 4 - - - MUXH9 - GPIOx pin 9 muxing - 4 - 4 - - - MUXH8 - GPIOx pin 8 muxing - 0 - 4 - - - - - CLR - CLR - GPIO bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - IOCB0 - Clear bit 0 - 0 - 1 - - - IOCB1 - Clear bit 1 - 1 - 1 - - - IOCB2 - Clear bit 1 - 2 - 1 - - - IOCB3 - Clear bit 3 - 3 - 1 - - - IOCB4 - Clear bit 4 - 4 - 1 - - - IOCB5 - Clear bit 5 - 5 - 1 - - - IOCB6 - Clear bit 6 - 6 - 1 - - - IOCB7 - Clear bit 7 - 7 - 1 - - - IOCB8 - Clear bit 8 - 8 - 1 - - - IOCB9 - Clear bit 9 - 9 - 1 - - - IOCB10 - Clear bit 10 - 10 - 1 - - - IOCB11 - Clear bit 11 - 11 - 1 - - - IOCB12 - Clear bit 12 - 12 - 1 - - - IOCB13 - Clear bit 13 - 13 - 1 - - - IOCB14 - Clear bit 14 - 14 - 1 - - - IOCB15 - Clear bit 15 - 15 - 1 - - - - - HDRV - HDRV - Huge current driver - 0x3C - 0x20 - read-write - 0x00000000 - - - HDRV0 - Port x driver bit y - 0 - 1 - - - HDRV1 - Port x driver bit y - 1 - 1 - - - HDRV2 - Port x driver bit y - 2 - 1 - - - HDRV3 - Port x driver bit y - 3 - 1 - - - HDRV4 - Port x driver bit y - 4 - 1 - - - HDRV5 - Port x driver bit y - 5 - 1 - - - HDRV6 - Port x driver bit y - 6 - 1 - - - HDRV7 - Port x driver bit y - 7 - 1 - - - HDRV8 - Port x driver bit y - 8 - 1 - - - HDRV9 - Port x driver bit y - 9 - 1 - - - HDRV10 - Port x driver bit y - 10 - 1 - - - HDRV11 - Port x driver bit y - 11 - 1 - - - HDRV12 - Port x driver bit y - 12 - 1 - - - HDRV13 - Port x driver bit y - 13 - 1 - - - HDRV14 - Port x driver bit y - 14 - 1 - - - HDRV15 - Port x driver bit y - 15 - 1 - - - - - - - GPIOB - 0x40020400 - - - GPIOC - 0x40020800 - - - GPIOD - 0x40020C00 - - - GPIOE - 0x40021000 - - - GPIOF - 0x40021400 - - - GPIOG - 0x40021800 - - - GPIOH - 0x40021C00 - - - EXINT - EXINT - EXINT - 0x40013C00 - - 0x0 - 0x400 - registers - - - EXINT0 - EXINT Line0 interrupt - 6 - - - EXINT1 - EXINT Line1 interrupt - 7 - - - EXINT2 - EXINT Line2 interrupt - 8 - - - EXINT3 - EXINT Line3 interrupt - 9 - - - EXINT4 - EXINT Line4 interrupt - 10 - - - EXINT9_5 - EXINT Line[9:5] interrupts - 23 - - - EXINT15_10 - EXINT Line[15:10] interrupts - 40 - - - PVM - PVM interrupt connect to EXINT line16 - 1 - - - ERTCALARM - ERTC Alarm interrupt connect to EXINT line17 - 41 - - - OTGFS1_WKUP - OTGFS1_WKUP interrupt connect to EXINT line18 - 42 - - - EMAC_WKUP - EMAC_WKUP interrupt connect to EXINT line19 - 62 - - - OTGFS2_WKUP - OTGFS2_WKUP interrupt connect to EXINT line20 - 76 - - - TAMPER - Tamper interrupt connect to EXINT line21 - 2 - - - ERTC_WKUP - ERTC Global interrupt connect to EXINT line22 - 3 - - - - INTEN - INTEN - Interrupt enable register - 0x0 - 0x20 - read-write - 0x00000000 - - - INTEN0 - Interrupt enable or disable on line 0 - 0 - 1 - - - INTEN1 - Interrupt enable or disable on line 1 - 1 - 1 - - - INTEN2 - Interrupt enable or disable on line 2 - 2 - 1 - - - INTEN3 - Interrupt enable or disable on line 3 - 3 - 1 - - - INTEN4 - Interrupt enable or disable on line 4 - 4 - 1 - - - INTEN5 - Interrupt enable or disable on line 5 - 5 - 1 - - - INTEN6 - Interrupt enable or disable on line 6 - 6 - 1 - - - INTEN7 - Interrupt enable or disable on line 7 - 7 - 1 - - - INTEN8 - Interrupt enable or disable on line 8 - 8 - 1 - - - INTEN9 - Interrupt enable or disable on line 9 - 9 - 1 - - - INTEN10 - Interrupt enable or disable on line 10 - 10 - 1 - - - INTEN11 - Interrupt enable or disable on line 11 - 11 - 1 - - - INTEN12 - Interrupt enable or disable on line 12 - 12 - 1 - - - INTEN13 - Interrupt enable or disable on line 13 - 13 - 1 - - - INTEN14 - Interrupt enable or disable on line 14 - 14 - 1 - - - INTEN15 - Interrupt enable or disable on line 15 - 15 - 1 - - - INTEN16 - Interrupt enable or disable on line 16 - 16 - 1 - - - INTEN17 - Interrupt enable or disable on line 17 - 17 - 1 - - - INTEN18 - Interrupt enable or disable on line 18 - 18 - 1 - - - INTEN19 - Interrupt enable or disable on line 19 - 19 - 1 - - - INTEN20 - Interrupt enable or disable on line 20 - 20 - 1 - - - INTEN21 - Interrupt enable or disable on line 21 - 21 - 1 - - - INTEN22 - Interrupt enable or disable on line 22 - 22 - 1 - - - - - EVTEN - EVTEN - Event enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - EVTEN0 - Event enable or disable on line 0 - 0 - 1 - - - EVTEN1 - Event enable or disable on line 1 - 1 - 1 - - - EVTEN2 - Event enable or disable on line 2 - 2 - 1 - - - EVTEN3 - Event enable or disable on line 3 - 3 - 1 - - - EVTEN4 - Event enable or disable on line 4 - 4 - 1 - - - EVTEN5 - Event enable or disable on line 5 - 5 - 1 - - - EVTEN6 - Event enable or disable on line 6 - 6 - 1 - - - EVTEN7 - Event enable or disable on line 7 - 7 - 1 - - - EVTEN8 - Event enable or disable on line 8 - 8 - 1 - - - EVTEN9 - Event enable or disable on line 9 - 9 - 1 - - - EVTEN10 - Event enable or disable on line 10 - 10 - 1 - - - EVTEN11 - Event enable or disable on line 11 - 11 - 1 - - - EVTEN12 - Event enable or disable on line 12 - 12 - 1 - - - EVTEN13 - Event enable or disable on line 13 - 13 - 1 - - - EVTEN14 - Event enable or disable on line 14 - 14 - 1 - - - EVTEN15 - Event enable or disable on line 15 - 15 - 1 - - - EVTEN16 - Event enable or disable on line 16 - 16 - 1 - - - EVTEN17 - Event enable or disable on line 17 - 17 - 1 - - - EVTEN18 - Event enable or disable on line 18 - 18 - 1 - - - EVTEN19 - Event enable or disable on line 19 - 19 - 1 - - - EVTEN20 - Event enable or disable on line 20 - 20 - 1 - - - EVTEN21 - Event enable or disable on line 21 - 21 - 1 - - - EVTEN22 - Event enable or disable on line 22 - 22 - 1 - - - - - POLCFG1 - POLCFG1 - Rising polarity configuration register - 0x8 - 0x20 - read-write - 0x00000000 - - - RP0 - Rising polarity configuration bit of line 0 - 0 - 1 - - - RP1 - Rising polarity configuration bit of line 1 - 1 - 1 - - - RP2 - Rising polarity configuration bit of line 2 - 2 - 1 - - - RP3 - Rising polarity configuration bit of line 3 - 3 - 1 - - - RP4 - Rising polarity configuration bit of line 4 - 4 - 1 - - - RP5 - Rising polarity configuration bit of line 5 - 5 - 1 - - - RP6 - Rising polarity configuration bit of linee 6 - 6 - 1 - - - RP7 - Rising polarity configuration bit of line 7 - 7 - 1 - - - RP8 - Rising polarity configuration bit of line 8 - 8 - 1 - - - RP9 - Rising polarity configuration bit of line 9 - 9 - 1 - - - RP10 - Rising polarity configuration bit of line 10 - 10 - 1 - - - RP11 - Rising polarity configuration bit of line 11 - 11 - 1 - - - RP12 - Rising polarity configuration bit of line 12 - 12 - 1 - - - RP13 - Rising polarity configuration bit of line 13 - 13 - 1 - - - RP14 - Rising polarity configuration bit of line 14 - 14 - 1 - - - RP15 - Rising polarity configuration bit of line 15 - 15 - 1 - - - RP16 - Rising polarity configuration bit of line 16 - 16 - 1 - - - RP17 - Rising polarity configuration bit of line 17 - 17 - 1 - - - RP18 - Rising polarity configuration bit of line 18 - 18 - 1 - - - RP19 - Rising polarity configuration bit of line 19 - 19 - 1 - - - RP20 - Rising polarity configuration bit of line 20 - 20 - 1 - - - RP21 - Rising polarity configuration bit of line 21 - 21 - 1 - - - RP22 - Rising polarity configuration bit of line 22 - 22 - 1 - - - - - POLCFG2 - POLCFG2 - Falling polarity configuration register - 0xC - 0x20 - read-write - 0x00000000 - - - FP0 - Falling polarity event configuration bit of line 0 - 0 - 1 - - - FP1 - Falling polarity event configuration bit of line 1 - 1 - 1 - - - FP2 - Falling polarity event configuration bit of line 2 - 2 - 1 - - - FP3 - Falling polarity event configuration bit of line 3 - 3 - 1 - - - FP4 - Falling polarity event configuration bit of line 4 - 4 - 1 - - - FP5 - Falling polarity event configuration bit of line 5 - 5 - 1 - - - FP6 - Falling polarity event configuration bit of line 6 - 6 - 1 - - - FP7 - Falling polarity event configuration bit of line 7 - 7 - 1 - - - FP8 - Falling polarity event configuration bit of line 8 - 8 - 1 - - - FP9 - Falling polarity event configuration bit of line 9 - 9 - 1 - - - FP10 - Falling polarity event configuration bit of line 10 - 10 - 1 - - - FP11 - Falling polarity event configuration bit of line 11 - 11 - 1 - - - FP12 - Falling polarity event configuration bit of line 12 - 12 - 1 - - - FP13 - Falling polarity event configuration bit of line 13 - 13 - 1 - - - FP14 - Falling polarity event configuration bit of line 14 - 14 - 1 - - - FP15 - Falling polarity event configuration bit of line 15 - 15 - 1 - - - FP16 - Falling polarity event configuration bit of line 16 - 16 - 1 - - - FP17 - Falling polarity event configuration bit of line 17 - 17 - 1 - - - FP18 - Falling polarity event configuration bit of line 18 - 18 - 1 - - - FP19 - Falling polarity event configuration bit of line 19 - 19 - 1 - - - FP20 - Falling polarity event configuration bit of line 20 - 20 - 1 - - - FP21 - Falling polarity event configuration bit of line 21 - 21 - 1 - - - FP22 - Falling polarity event configuration bit of line 22 - 22 - 1 - - - - - SWTRG - SWTRG - Software triggle register - 0x10 - 0x20 - read-write - 0x00000000 - - - SWT0 - Software triggle on line 0 - 0 - 1 - - - SWT1 - Software triggle on line 1 - 1 - 1 - - - SWT2 - Software triggle on line 2 - 2 - 1 - - - SWT3 - Software triggle on line 3 - 3 - 1 - - - SWT4 - Software triggle on line 4 - 4 - 1 - - - SWT5 - Software triggle on line 5 - 5 - 1 - - - SWT6 - Software triggle on line 6 - 6 - 1 - - - SWT7 - Software triggle on line 7 - 7 - 1 - - - SWT8 - Software triggle on line 8 - 8 - 1 - - - SWT9 - Software triggle on line 9 - 9 - 1 - - - SWT10 - Software triggle on line 10 - 10 - 1 - - - SWT11 - Software triggle on line 11 - 11 - 1 - - - SWT12 - Software triggle on line 12 - 12 - 1 - - - SWT13 - Software triggle on line 13 - 13 - 1 - - - SWT14 - Software triggle on line 14 - 14 - 1 - - - SWT15 - Software triggle on line 15 - 15 - 1 - - - SWT16 - Software triggle on line 16 - 16 - 1 - - - SWT17 - Software triggle on line 17 - 17 - 1 - - - SWT18 - Software triggle on line 18 - 18 - 1 - - - SWT19 - Software triggle on line 19 - 19 - 1 - - - SWT20 - Software triggle on line 20 - 20 - 1 - - - SWT21 - Software triggle on line 21 - 21 - 1 - - - SWT22 - Software triggle on line 22 - 22 - 1 - - - - - INTSTS - INTSTS - Interrupt status register - 0x14 - 0x20 - read-write - 0x00000000 - - - LINE0 - Line 0 state bit - 0 - 1 - - - LINE1 - Line 1 state bit - 1 - 1 - - - LINE2 - Line 2 state bit - 2 - 1 - - - LINE3 - Line 3 state bit - 3 - 1 - - - LINE4 - Line 4 state bit - 4 - 1 - - - LINE5 - Line 5 state bit - 5 - 1 - - - LINE6 - Line 6 state bit - 6 - 1 - - - LINE7 - Line 7 state bit - 7 - 1 - - - LINE8 - Line 8 state bit - 8 - 1 - - - LINE9 - Line 9 state bit - 9 - 1 - - - LINE10 - Line 10 state bit - 10 - 1 - - - LINE11 - Line 11 state bit - 11 - 1 - - - LINE12 - Line 12 state bit - 12 - 1 - - - LINE13 - Line 13 state bit - 13 - 1 - - - LINE14 - Line 14 state bit - 14 - 1 - - - LINE15 - Line 15 state bit - 15 - 1 - - - LINE16 - Line 16 state bit - 16 - 1 - - - LINE17 - Line 17 state bit - 17 - 1 - - - LINE18 - Line 18 state bit - 18 - 1 - - - LINE19 - Line 19 state bit - 19 - 1 - - - LINE20 - Line 20 state bit - 20 - 1 - - - LINE21 - Line 21 state bit - 21 - 1 - - - LINE22 - Line 22 state bit - 22 - 1 - - - - - - - EDMA - EDMA controller - EDMA - 0x40026000 - - 0x0 - 0x400 - registers - - - EDMA_Stream1 - EDMA Stream1 global interrupt - 11 - - - EDMA_Stream2 - EDMA Stream2 global interrupt - 12 - - - EDMA_Stream3 - EDMA Stream3 global interrupt - 13 - - - EDMA_Stream4 - EDMA Stream4 global interrupt - 14 - - - EDMA_Stream5 - EDMA Stream5 global interrupt - 15 - - - EDMA_Stream6 - EDMA Stream6 global interrupt - 16 - - - EDMA_Stream7 - EDMA Stream7 global interrupt - 17 - - - EDMA_Stream8 - EDMA Stream8 global interrupt - 47 - - - - STS1 - STS1 - Interrupt status register1 - 0x0 - 0x20 - read-only - 0x00000000 - - - FDTF4 - Stream 4 Full data transfer interrupt flag - - 27 - 1 - - - HDTF4 - Stream 4 half data transfer interrupt flag - - 26 - 1 - - - DTERRF4 - Stream 4 transfer error interrupt flag - - 25 - 1 - - - DMERRF4 - Stream 4 direct mode error interrupt flag - - 24 - 1 - - - FERRF4 - Stream 4 FIFO error interrupt flag - - 22 - 1 - - - FDTF3 - Stream 3 Full data transfer interrupt flag - - 21 - 1 - - - HDTF3 - Stream 3 half data transfer interrupt flag - - 20 - 1 - - - DTERRF3 - Stream 3 transfer error interrupt flag - - 19 - 1 - - - DMERRF3 - Stream 3 direct mode error interrupt flag - - 18 - 1 - - - FERRF3 - Stream 3 FIFO error interrupt flag - - 16 - 1 - - - FDTF2 - Stream 2 Full data transfer interrupt flag - - 11 - 1 - - - HDTF2 - Stream 2 half data transfer interrupt flag - - 10 - 1 - - - DTERRF2 - Stream 2 transfer error interrupt flag - - 9 - 1 - - - DMERRF2 - Stream 2 direct mode error interrupt flag - - 8 - 1 - - - FERRF2 - Stream 2 FIFO error interrupt flag - - 6 - 1 - - - FDTF1 - Stream 1 Full data transfer interrupt flag - - 5 - 1 - - - HDTF1 - Stream 1 half data transfer interrupt flag - - 4 - 1 - - - DTERRF1 - Stream 1 transfer error interrupt flag - - 3 - 1 - - - DMERRF1 - Stream 1 direct mode error interrupt flag - - 2 - 1 - - - FERRF1 - Stream 1 FIFO error interrupt flag - - 0 - 1 - - - - - STS2 - STS2 - Interrupt status register2 - 0x4 - 0x20 - read-only - 0x00000000 - - - FDTF8 - Stream 8 full data transfer interrupt flag - - 27 - 1 - - - HDTF8 - Stream 8 half data transfer interrupt flag - - 26 - 1 - - - DTERRF8 - Stream 8 transfer error interrupt flag - - 25 - 1 - - - DMERRF8 - Stream 8 direct mode error interrupt flag - - 24 - 1 - - - FERRF8 - Stream 8 FIFO error interrupt flag - - 22 - 1 - - - FDTF7 - Stream 7 full data transfer interrupt flag - - 21 - 1 - - - HDTF7 - Stream 7 half data transfer interrupt flag - - 20 - 1 - - - DTERRF7 - Stream 7 transfer error interrupt flag - - 19 - 1 - - - DMERRF7 - Stream 7 direct mode error interrupt flag - - 18 - 1 - - - FERRF7 - Stream 7 FIFO error interrupt flag - - 16 - 1 - - - FDTF6 - Stream 6 full data transfer interrupt flag - - 11 - 1 - - - HDTF6 - Stream 6 half data transfer interrupt flag - - 10 - 1 - - - DTERRF6 - Stream 6 transfer error interrupt flag - - 9 - 1 - - - DMERRF6 - Stream 6 direct mode error interrupt flag - - 8 - 1 - - - FERRF6 - Stream 6 FIFO error interrupt flag - - 6 - 1 - - - FDTF5 - Stream 5 full data transfer interrupt flag - - 5 - 1 - - - HDTF5 - Stream 5 half data transfer interrupt flag - - 4 - 1 - - - DTERRF5 - Stream 5 transfer error interrupt flag - - 3 - 1 - - - DMERRF5 - Stream 5 direct mode error interrupt flag - - 2 - 1 - - - FERRF5 - Stream 5 FIFO error interrupt flag - - 0 - 1 - - - - - CLR1 - CLR1 - Interrupt flag clear register1 - - 0x8 - 0x20 - read-write - 0x00000000 - - - FDTFC4 - Stream 4 clear full data transfer complete interrupt flag - - 27 - 1 - - - HDTFC4 - Stream 4 clear half data transfer interrupt flag - - 26 - 1 - - - DTERRFC4 - Stream 4 clear transfer error interrupt flag - - 25 - 1 - - - DMERRFC4 - Stream 4 clear direct mode error interrupt flag - - 24 - 1 - - - FERRFC4 - Stream 4 clear FIFO error interrupt flag - - 22 - 1 - - - FDTFC3 - Stream 3 clear full data transfer complete interrupt flag - - 21 - 1 - - - HDTFC3 - Stream 3 clear half data transfer interrupt flag - - 20 - 1 - - - DTERRFC3 - Stream 3 clear transfer error interrupt flag - - 19 - 1 - - - DMERRFC3 - Stream 3 clear direct mode error interrupt flag - - 18 - 1 - - - FERRFC3 - Stream 3 clear FIFO error interrupt flag - - 16 - 1 - - - FDTFC2 - Stream 2 clear full data transfer complete interrupt flag - - 11 - 1 - - - HDTFC2 - Stream 2 clear half data transfer interrupt flag - - 10 - 1 - - - DTERRFC2 - Stream 2 clear transfer error interrupt flag - - 9 - 1 - - - DMERRFC2 - Stream 2 clear direct mode error interrupt flag - - 8 - 1 - - - FERRFC2 - Stream 2 clear FIFO error interrupt flag - - 6 - 1 - - - FDTFC1 - Stream 1 clear full data transfer complete interrupt flag - - 5 - 1 - - - HDTFC1 - Stream 1 clear half data transfer interrupt flag - - 4 - 1 - - - DTERRFC1 - Stream 1 clear transfer error interrupt flag - - 3 - 1 - - - DMERRFC1 - Stream 1 clear direct mode error interrupt flag - - 2 - 1 - - - FERRFC1 - Stream 1 clear FIFO error interrupt flag - - 0 - 1 - - - - - CLR2 - CLR2 - Interrupt flag clear register2 - - 0xC - 0x20 - read-write - 0x00000000 - - - FDTFC8 - Stream 8 clear full data transfer complete interrupt flag - - 27 - 1 - - - HDTFC8 - Stream 8 clear half data transfer interrupt flag - - 26 - 1 - - - DTERRFC8 - Stream 8 clear transfer error interrupt flag - - 25 - 1 - - - DMERRFC8 - Stream 8 clear direct mode error interrupt flag - - 24 - 1 - - - FERRFC8 - Stream 8 clear FIFO error interrupt flag - - 22 - 1 - - - FDTFC7 - Stream 7 clear full data transfer complete interrupt flag - - 21 - 1 - - - HDTFC7 - Stream 7 clear half data transfer interrupt flag - - 20 - 1 - - - DTERRFC7 - Stream 7 clear transfer error interrupt flag - - 19 - 1 - - - DMERRFC7 - Stream 7 clear direct mode error interrupt flag - - 18 - 1 - - - FERRFC7 - Stream 7 clear FIFO error interrupt flag - - 16 - 1 - - - FDTFC6 - Stream 6 clear full data transfer complete interrupt flag - - 11 - 1 - - - HDTFC6 - Stream 6 clear half data transfer interrupt flag - - 10 - 1 - - - DTERRFC6 - Stream 6 clear transfer error interrupt flag - - 9 - 1 - - - DMERRFC6 - Stream 6 clear direct mode error interrupt flag - - 8 - 1 - - - FERRFC6 - Stream 6 clear FIFO error interrupt flag - - 6 - 1 - - - FDTFC5 - Stream 5 clear full data transfer complete interrupt flag - - 5 - 1 - - - HDTFC5 - Stream 5 clear half data transfer interrupt flag - - 4 - 1 - - - DTERRFC5 - Stream 5 clear transfer error interrupt flag - - 3 - 1 - - - DMERRFC5 - Stream 5 clear direct mode error interrupt flag - - 2 - 1 - - - FERRFC5 - Stream 5 clear FIFO error interrupt flag - - 0 - 1 - - - - - S1CTRL - S1CTRL - stream 1 control - register - 0x10 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S1DTCNT - S1DTCNT - stream 1 number of data - register - 0x14 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S1PADDR - S1PADDR - stream 1 peripheral address - register - 0x18 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S1M0ADDR - S1M0ADDR - stream 1 memory 0 address - register - 0x1C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S1M1ADDR - S1M1ADDR - stream 1 memory 1 address - register - 0x20 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S1FCTRL - S1FCTRL - stream 1 FIFO control register - 0x24 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S2CTRL - S2CTRL - stream 2 control - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S2DTCNT - S2DTCNT - stream 2 number of data - register - 0x2C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S2PADDR - S2PADDR - stream 2 peripheral address - register - 0x30 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S2M0ADDR - S2M0ADDR - stream 2 memory 0 address - register - 0x34 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S2M1ADDR - S2M1ADDR - stream 2 memory 1 address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S2FCTRL - S2FCTRL - stream 2 FIFO control register - 0x3C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S3CTRL - S3CTRL - stream 3 control - register - 0x40 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S3DTCNT - S3DTCNT - stream 3 number of data - register - 0x44 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S3PADDR - S3PADDR - stream 3 peripheral address - register - 0x48 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S3M0ADDR - S3M0ADDR - stream 3 memory 0 address - register - 0x4C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S3M1ADDR - S3M1ADDR - stream 3 memory 1 address - register - 0x50 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S3FCTRL - S3FCTRL - stream 3 FIFO control register - 0x54 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S4CTRL - S4CTRL - stream 4 control - register - 0x58 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S4DTCNT - S4DTCNT - stream 4 number of data - register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S4PADDR - S4PADDR - stream 4 peripheral address - register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S4M0ADDR - S4M0ADDR - stream 4 memory 0 address - register - 0x64 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S4M1ADDR - S4M1ADDR - stream 4 memory 1 address - register - 0x68 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S4FCTRL - S4FCTRL - stream 4 FIFO control register - 0x6C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S5CTRL - S5CTRL - stream 5 control - register - 0x70 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S5DTCNT - S5DTCNT - stream 5 number of data - register - 0x74 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S5PADDR - S5PADDR - stream 5 peripheral address - register - 0x78 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S5M0ADDR - S5M0ADDR - stream 5 memory 0 address - register - 0x7C - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S5M1ADDR - S5M1ADDR - stream 5 memory 1 address - register - 0x80 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S5FCTRL - S5FCTRL - stream 5 FIFO control register - 0x84 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S6CTRL - S6CTRL - stream 6 control - register - 0x88 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S6DTCNT - S6DTCNT - stream 6 number of data - register - 0x8C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S6PADDR - S6PADDR - stream 6 peripheral address - register - 0x90 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S6M0ADDR - S6M0ADDR - stream 6 memory 0 address - register - 0x94 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S6M1ADDR - S6M1ADDR - stream 6 memory 1 address - register - 0x98 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S6FCTRL - S6FCTRL - stream 6 FIFO control register - 0x9C - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S7CTRL - S7CTRL - stream 7 control - register - 0xA0 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S7DTCNT - S7DTCNT - stream 7 number of data - register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S7PADDR - S7PADDR - stream 7 peripheral address - register - 0xA8 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S7M0ADDR - S7M0ADDR - stream 7 memory 0 address - register - 0xAC - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S7M1ADDR - S7M1ADDR - stream 7 memory 1 address - register - 0xB0 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S7FCTRL - S7FCTRL - stream 7 FIFO control register - 0xB4 - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - S8CTRL - S8CTRL - stream 8 control - register - 0xB8 - 0x20 - read-write - 0x00000000 - - - MBURST - Memory burst transmission - - 23 - 2 - - - PBURST - Peripheral burst transmission - - 21 - 2 - - - CM - Current memory (only in double buffer - mode) - 19 - 1 - - - DMM - Double memory mode - 18 - 1 - - - SPL - Stream priority level - 16 - 2 - - - PINCOS - Peripheral increment offset - size - 15 - 1 - - - MWIDTH - Memory data width - 13 - 2 - - - PWIDTH - Peripheral data width - 11 - 2 - - - MINCM - Memory increment mode - 10 - 1 - - - PINCM - Peripheral increment mode - 9 - 1 - - - LM - Loop mode - 8 - 1 - - - DTD - Data transfer direction - 6 - 2 - - - PFCTRL - Peripheral flow controller - 5 - 1 - - - FDTIEN - Full data transfer complete interrupt - enable - 4 - 1 - - - HDTIEN - Half data transfer interrupt - enable - 3 - 1 - - - DTERRIEN - Transfer error interrupt - enable - 2 - 1 - - - DMERRIEN - Direct mode error interrupt - enable - 1 - 1 - - - SEN - Stream enable / flag stream ready when - read low - 0 - 1 - - - - - S8DTCNT - S8DTCNT - stream 8 number of data - register - 0xBC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data items to - transfer - 0 - 16 - - - - - S8PADDR - S8PADDR - stream 8 peripheral address - register - 0xC0 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - S8M0ADDR - S8M0ADDR - stream 8 memory 0 address - register - 0xC4 - 0x20 - read-write - 0x00000000 - - - M0ADDR - Memory 0 address - 0 - 32 - - - - - S8M1ADDR - S8M1ADDR - stream 8 memory 1 address - register - 0xC8 - 0x20 - read-write - 0x00000000 - - - M1ADDR - Memory 1 address (used in case of Double - buffer mode) - 0 - 32 - - - - - S8FCTRL - S8FCTRL - stream 8 FIFO control register - 0xCC - 0x20 - 0x00000021 - - - FERRIEN - FIFO error interrupt - enable - 7 - 1 - read-write - - - FSTS - FIFO status - 3 - 3 - read-only - - - FEN - FIFO mode enable - 2 - 1 - read-write - - - FTHSEL - FIFO threshold selection - 0 - 2 - read-write - - - - - LLCTRL - LLCTRL - DMA Link List Control Register - 0xD0 - 0x20 - 0x00000000 - - - S1LLEN - Stream 1 link list enable - 0 - 1 - read-write - - - S2LLEN - Stream 2 link list enable - 1 - 1 - read-write - - - S3LLEN - Stream 3 link list enable - 2 - 1 - read-write - - - S4LLEN - Stream 4 link list enable - 3 - 1 - read-write - - - S5LLEN - Stream 5 link list enable - 4 - 1 - read-write - - - S6LLEN - Stream 6 link list enable - 5 - 1 - read-write - - - S7LLEN - Stream 7 link list enable - 6 - 1 - read-write - - - S8LLEN - Stream 8 link list enable - 7 - 1 - read-write - - - - - S1LLP - S1LLP - Stream 1 Link List Pointer - 0xD4 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S2LLP - S2LLP - Stream 2 Link List Pointer - 0xD8 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S3LLP - S3LLP - Stream 3 Link List Pointer - 0xDC - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S4LLP - S4LLP - Stream 4 Link List Pointer - 0xE0 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S5LLP - S5LLP - Stream 5 Link List Pointer - 0xE4 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S6LLP - S6LLP - Stream 6 Link List Pointer - 0xE8 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S7LLP - S7LLP - Stream 7 Link List Pointer - 0xEC - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S8LLP - S8LLP - Stream 8 Link List Pointer - 0xF0 - 0x20 - 0x00000000 - - - LLP - Link list pointer - 0 - 32 - read-write - - - - - S2DCTRL - S2DCTRL - EDMA 2D Transfer Control Register - 0xF4 - 0x20 - 0x00000000 - - - S1_2DEN - Stream 1 2D transfer enable - 0 - 1 - read-write - - - S2_2DEN - Stream 2 2D transfer enable - 1 - 1 - read-write - - - S3_2DEN - Stream 3 2D transfer enable - 2 - 1 - read-write - - - S4_2DEN - Stream 4 2D transfer enable - 3 - 1 - read-write - - - S5_2DEN - Stream 5 2D transfer enable - 4 - 1 - read-write - - - S6_2DEN - Stream 6 2D transfer enable - 5 - 1 - read-write - - - S7_2DEN - Stream 7 2D transfer enable - 6 - 1 - read-write - - - S8_2DEN - Stream 8 2D transfer enable - 7 - 1 - read-write - - - - - S1_2DCNT - S1_2DCNT - Stream 1 2D Transfer Count - 0xF8 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S1_STRIDE - S1_STRIDE - Stream 1 2D Transfer Stride - 0xFC - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S2_2DCNT - S2_2DCNT - Stream 2 2D Transfer Count - 0x100 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S2_STRIDE - S2_STRIDE - Stream 2 2D Transfer Stride - 0x104 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S3_2DCNT - S3_2DCNT - Stream 3 2D Transfer Count - 0x108 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S3_STRIDE - S3_STRIDE - Stream 3 2D Transfer Stride - 0x10C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S4_2DCNT - S4_2DCNT - Stream 4 2D Transfer Count - 0x110 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S4_STRIDE - S4_STRIDE - Stream 4 2D Transfer Stride - 0x114 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S5_2DCNT - S5_2DCNT - Stream 5 2D Transfer Count - 0x118 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S5_STRIDE - S5_STRIDE - Stream 5 2D Transfer Stride - 0x11C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S6_2DCNT - S6_2DCNT - Stream 6 2D Transfer Count - 0x120 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S6_STRIDE - S6_STRIDE - Stream 6 2D Transfer Stride - 0x124 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S7_2DCNT - S7_2DCNT - Stream 7 2D Transfer Count - 0x128 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S7_STRIDE - S7_STRIDE - Stream 7 2D Transfer Stride - 0x12C - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - S8_2DCNT - S8_2DCNT - Stream 8 2D Transfer Count - 0x130 - 0x20 - 0x00000000 - - - XCONUT - X dimension transfer count - 0 - 16 - read-write - - - YCONUT - Y dimension transfer count - 16 - 16 - read-write - - - - - S8_STRIDE - S8_STRIDE - Stream 8 2D Transfer Stride - 0x134 - 0x20 - 0x00000000 - - - SRCSTD - Source stride - 0 - 16 - read-write - - - DSTSTD - Destination stride - 16 - 16 - read-write - - - - - SYNCEN - SYNCEN - Sync Enable - 0x138 - 0x20 - 0x00000000 - - - S1SYNC - Stream 1 sync enable - 0 - 1 - read-write - - - S2SYNC - Stream 2 sync enable - 1 - 1 - read-write - - - S3SYNC - Stream 3 sync enable - 2 - 1 - read-write - - - S4SYNC - Stream 4 sync enable - 3 - 1 - read-write - - - S5SYNC - Stream 5 sync enable - 4 - 1 - read-write - - - S6SYNC - Stream 6 sync enable - 5 - 1 - read-write - - - S7SYNC - Stream 7 sync enable - 6 - 1 - read-write - - - S8SYNC - Stream 8 sync enable - 7 - 1 - read-write - - - - - MUXSEL - MUXSEL - EDMA MUX Table Selection - 0x13C - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXS1CTRL - MUXS1CTRL - Stream 1 Configuration Register - 0x140 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS2CTRL - MUXS2CTRL - Stream 2 Configuration Register - 0x144 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS3CTRL - MUXS3CTRL - Stream 3 Configuration Register - 0x148 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS4CTRL - MUXS4CTRL - Stream 4 Configuration Register - 0x14C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS5CTRL - MUXS5CTRL - Stream x Configuration Register - 0x150 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS6CTRL - MUXS6CTRL - Stream 6 Configuration Register - 0x154 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS7CTRL - MUXS7CTRL - Stream 7 Configuration Register - 0x158 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXS8CTRL - MUXS8CTRL - Stream 8 Configuration Register - 0x15C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization select - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x160 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x164 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x168 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x16C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x170 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - SYNCOVF8 - Synchronizaton overrun interrupt flag - 7 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x174 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - SYNCOVFC8 - Clear synchronizaton overrun interrupt flag - 7 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x178 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x17C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA1 - DMA controller - DMA - 0x40026400 - - 0x0 - 0x200 - registers - - - DMA1_Channel1 - DMA1 Channel1 global interrupt - 56 - - - DMA1_Channel2 - DMA1 Channel2 global interrupt - 57 - - - DMA1_Channel3 - DMA1 Channel3 global interrupt - 58 - - - DMA1_Channel4 - DMA1 Channel4 global interrupt - 59 - - - DMA1_Channel5 - DMA1 Channel5 global interrupt - 60 - - - DMA1_Channel6 - DMA1 Channel6 global interrupt - 68 - - - DMA1_Channel7 - DMA1 Channel7 global interrupt - 69 - - - - STS - STS - DMA interrupt status register - (DMA_STS) - 0x0 - 0x20 - read-only - 0x00000000 - - - GF1 - Channel 1 Global event flag - 0 - 1 - - - FDTF1 - Channel 1 full data transfer event flag - 1 - 1 - - - HDTF1 - Channel 1 half data transfer event flag - 2 - 1 - - - DTERRF1 - Channel 1 data transfer error event flag - 3 - 1 - - - GF2 - Channel 2 Global event flag - 4 - 1 - - - FDTF2 - Channel 2 full data transfer event flag - 5 - 1 - - - HDTF2 - Channel 2 half data transfer event flag - 6 - 1 - - - DTERRF2 - Channel 2 data transfer error event flag - 7 - 1 - - - GF3 - Channel 3 Global event flag - 8 - 1 - - - FDTF3 - Channel 3 full data transfer event flag - 9 - 1 - - - HDTF3 - Channel 3 half data transfer event flag - 10 - 1 - - - DTERRF3 - Channel 3 data transfer error event flag - 11 - 1 - - - GF4 - Channel 4 Global event flag - 12 - 1 - - - FDTF4 - Channel 4 full data transfer event flag - 13 - 1 - - - HDTF4 - Channel 4 half data transfer event flag - 14 - 1 - - - DTERRF4 - Channel 4 data transfer error event flag - 15 - 1 - - - GF5 - Channel 5 Global event flag - 16 - 1 - - - FDTF5 - Channel 5 full data transfer event flag - 17 - 1 - - - HDTF5 - Channel 5 half data transfer event flag - 18 - 1 - - - DTERRF5 - Channel 5 data transfer error event flag - 19 - 1 - - - GF6 - Channel 6 Global event flag - 20 - 1 - - - FDTF6 - Channel 6 full data transfer event flag - 21 - 1 - - - HDTF6 - Channel 6 half data transfer event flag - 22 - 1 - - - DTERRF6 - Channel 6 data transfer error event flag - 23 - 1 - - - GF7 - Channel 7 Global event flag - 24 - 1 - - - FDTF7 - Channel 7 full data transfer event flag - 25 - 1 - - - HDTF7 - Channel 7 half data transfer event flag - 26 - 1 - - - DTERRF7 - Channel 7 data transfer error event flag - 27 - 1 - - - - - CLR - CLR - DMA interrupt flag clear register - (DMA_CLR) - 0x4 - 0x20 - read-write - 0x00000000 - - - GFC1 - Channel 1 Global flag clear - 0 - 1 - - - GFC2 - Channel 2 Global flag clear - 4 - 1 - - - GFC3 - Channel 3 Global flag clear - 8 - 1 - - - GFC4 - Channel 4 Global flag clear - 12 - 1 - - - GFC5 - Channel 5 Global flag clear - 16 - 1 - - - GFC6 - Channel 6 Global flag clear - 20 - 1 - - - GFC7 - Channel 7 Global flag clear - 24 - 1 - - - FDTFC1 - Channel 1 full data transfer flag clear - 1 - 1 - - - FDTFC2 - Channel 2 full data transfer flag clear - 5 - 1 - - - FDTFC3 - Channel 3 full data transfer flag clear - 9 - 1 - - - FDTFC4 - Channel 4 full data transfer flag clear - 13 - 1 - - - FDTFC5 - Channel 5 full data transfer flag clear - 17 - 1 - - - FDTFC6 - Channel 6 full data transfer flag clear - 21 - 1 - - - FDTFC7 - Channel 7 full data transfer flag clear - 25 - 1 - - - HDTFC1 - Channel 1 half data transfer flag clear - 2 - 1 - - - HDTFC2 - Channel 2 half data transfer flag clear - 6 - 1 - - - HDTFC3 - Channel 3 half data transfer flag clear - 10 - 1 - - - HDTFC4 - Channel 4 half data transfer flag clear - 14 - 1 - - - HDTFC5 - Channel 5 half data transfer flag clear - 18 - 1 - - - HDTFC6 - Channel 6 half data transfer flag clear - 22 - 1 - - - HDTFC7 - Channel 7 half data transfer flag clear - 26 - 1 - - - DTERRFC1 - Channel 1 data transfer error flag clear - 3 - 1 - - - DTERRFC2 - Channel 2 data transfer error flag clear - 7 - 1 - - - DTERRFC3 - Channel 3 data transfer error flag clear - 11 - 1 - - - DTERRFC4 - Channel 4 data transfer error flag clear - 15 - 1 - - - DTERRFC5 - Channel 5 data transfer error flag clear - 19 - 1 - - - DTERRFC6 - Channel 6 data transfer error flag clear - 23 - 1 - - - DTERRFC7 - Channel 7 data transfer error flag clear - 27 - 1 - - - - - C1CTRL - C1CTRL - DMA channel configuration register(DMA_C1CTRL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C1DTCNT - C1DTCNT - DMA channel 1 number of data to transfer register - 0xC - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C1PADDR - C1PADDR - DMA channel 1 peripheral base address register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C1MADDR - C1MADDR - DMA channel 1 memory base address register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C2CTRL - C2CTRL - DMA channel configuration register (DMA_C2CTRL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C2DTCNT - C2DTCNT - DMA channel 2 number of data to transferregister - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C2PADDR - C2PADDR - DMA channel 2 peripheral base address register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C2MADDR - C2MADDR - DMA channel 2 memory base address register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C3CTRL - C3CTRL - DMA channel configuration register (DMA_C3CTRL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C3DTCNT - C3DTCNT - DMA channel 3 number of data to transfer register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C3PADDR - C3PADDR - DMA channel 3 peripheral base address register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C3MADDR - C3MADDR - DMA channel 3 memory base address register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C4CTRL - C4CTRL - DMA channel configuration register (DMA_C4CTRL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C4DTCNT - C4DTCNT - DMA channel 4 number of data to transfer register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C4PADDR - C4PADDR - DMA channel 4 peripheral base address register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C4MADDR - C4MADDR - DMA channel 4 memory base address register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C5CTRL - C5CTRL - DMA channel configuration register (DMA_C5CTRL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C5DTCNT - C5DTCNT - DMA channel 5 number of data to transfer register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C5PADDR - C5PADDR - DMA channel 5 peripheral base address register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C5MADDR - C5MADDR - DMA channel 5 memory base address register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C6CTRL - C6CTRL - DMA channel configuration register(DMA_C6CTRL) - 0x6C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C6DTCNT - C6DTCNT - DMA channel 6 number of data to transfer register - 0x70 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C6PADDR - C6PADDR - DMA channel 6 peripheral address base register - 0x74 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C6MADDR - C6MADDR - DMA channel 6 memory address base register - 0x78 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - C7CTRL - C7CTRL - DMA channel configuration register(DMA_C7CTRL) - 0x80 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FDTIEN - Transfer complete interrupt enable - 1 - 1 - - - HDTIEN - Half transfer interrupt enable - 2 - 1 - - - DTERRIEN - Transfer error interrupt enable - 3 - 1 - - - DTD - Data transfer direction - 4 - 1 - - - LM - Loop mode - 5 - 1 - - - PINCM - Peripheral increment mode - 6 - 1 - - - MINCM - Memory increment mode - 7 - 1 - - - PWIDTH - Peripheral data bit width - 8 - 2 - - - MWIDTH - Memory data bit width - 10 - 2 - - - CHPL - Channel Priority level - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - C7DTCNT - C7DTCNT - DMA channel 7 number of data to transfer register - 0x84 - 0x20 - read-write - 0x00000000 - - - CNT - Number of data to transfer - 0 - 16 - - - - - C7PADDR - C7PADDR - DMA channel 7 peripheral base address register - 0x88 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral address - 0 - 32 - - - - - C7MADDR - C7MADDR - DMA channel 7 memory base address register - 0x8C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - DMA_MUXSEL - DMA_MUXSEL - DMAMUX Table Selection - 0x100 - 0x20 - 0x00000000 - - - TBL_SEL - Multiplexer Table Select - 0 - 1 - read-write - - - - - MUXC1CTRL - MUXC1CTRL - Channel 1 Configuration Register - 0x104 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC2CTRL - MUXC2CTRL - Channel 2 Configuration Register - 0x108 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC3CTRL - MUXC3CTRL - Channel 3 Configuration Register - 0x10C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC4CTRL - MUXC4CTRL - Channel 4 Configuration Register - 0x110 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC5CTRL - MUXC5CTRL - Channel 5 Configuration Register - 0x114 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC6CTRL - MUXC6CTRL - Channel 6 Configuration Register - 0x118 - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXC7CTRL - MUXC7CTRL - Channel 7 Configuration Register - 0x11C - 0x20 - 0x00000000 - - - REQSEL - DMA request select - 0 - 7 - read-write - - - SYNCOVIEN - Synchronization overrun interrupt enable - 8 - 1 - read-write - - - EVTGEN - Event generation enable - 9 - 1 - read-write - - - SYNCEN - Synchroniztion enable - 16 - 1 - read-write - - - SYNCPOL - Synchronization polarity - 17 - 2 - read-write - - - REQCNT - Number of DMA requests - 19 - 5 - read-write - - - SYNCSEL - Synchronization Identification - 24 - 5 - read-write - - - - - MUXG1CTRL - MUXG1CTRL - Generator 1 Configuration Register - 0x120 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG2CTRL - MUXG2CTRL - Generator 2 Configuration Register - 0x124 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG3CTRL - MUXG3CTRL - Generator 3 Configuration Register - 0x128 - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXG4CTRL - MUXG4CTRL - Generator 4 Configuration Register - 0x12C - 0x20 - 0x00000000 - - - SIGSEL - Signal select - 0 - 5 - read-write - - - TRGOVIEN - Trigger overrun interrupt enable - 8 - 1 - read-write - - - GEN - DMA request generator enable - 16 - 1 - read-write - - - GPOL - DMA request generator trigger polarity - 17 - 2 - read-write - - - GREQCNT - Number of DMA requests to be generated - 19 - 5 - read-write - - - - - MUXSYNCSTS - MUXSYNCSTS - Channel Interrupt Status Register - 0x130 - 0x20 - 0x00000000 - - - SYNCOVF1 - Synchronizaton overrun interrupt flag - 0 - 1 - read-only - - - SYNCOVF2 - Synchronizaton overrun interrupt flag - 1 - 1 - read-only - - - SYNCOVF3 - Synchronizaton overrun interrupt flag - 2 - 1 - read-only - - - SYNCOVF4 - Synchronizaton overrun interrupt flag - 3 - 1 - read-only - - - SYNCOVF5 - Synchronizaton overrun interrupt flag - 4 - 1 - read-only - - - SYNCOVF6 - Synchronizaton overrun interrupt flag - 5 - 1 - read-only - - - SYNCOVF7 - Synchronizaton overrun interrupt flag - 6 - 1 - read-only - - - - - MUXSYNCCLR - MUXSYNCCLR - Channel Interrupt Clear Flag Register - 0x134 - 0x20 - 0x00000000 - - - SYNCOVFC1 - Clear synchronizaton overrun interrupt flag - 0 - 1 - read-write - - - SYNCOVFC2 - Clear synchronizaton overrun interrupt flag - 1 - 1 - read-write - - - SYNCOVFC3 - Clear synchronizaton overrun interrupt flag - 2 - 1 - read-write - - - SYNCOVFC4 - Clear synchronizaton overrun interrupt flag - 3 - 1 - read-write - - - SYNCOVFC5 - Clear synchronizaton overrun interrupt flag - 4 - 1 - read-write - - - SYNCOVFC6 - Clear synchronizaton overrun interrupt flag - 5 - 1 - read-write - - - SYNCOVFC7 - Clear synchronizaton overrun interrupt flag - 6 - 1 - read-write - - - - - MUXGSTS - MUXGSTS - Generator Interrupt Status Register - 0x138 - 0x20 - 0x00000000 - - - TRGOVF1 - Trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVF2 - Trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVF3 - Trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVF4 - Trigger overrun interrupt flag - 3 - 1 - read-write - - - - - MUXGCLR - MUXGCLR - Generator Interrupt Clear Flag Register - 0x13C - 0x20 - 0x00000000 - - - TRGOVFC1 - Clear trigger overrun interrupt flag - 0 - 1 - read-write - - - TRGOVFC2 - Clear trigger overrun interrupt flag - 1 - 1 - read-write - - - TRGOVFC3 - Clear trigger overrun interrupt flag - 2 - 1 - read-write - - - TRGOVFC4 - Clear trigger overrun interrupt flag - 3 - 1 - read-write - - - - - - - DMA2 - 0x40026600 - - - SDIO1 - Secure digital input/output - interface - SDIO - 0x4002C400 - - 0x0 - 0x400 - registers - - - SDIO1 - SDIO1 global interrupt - 49 - - - - PWRCTRL - PWRCTRL - Bits 1:0 = PWRCTRL: Power supply control - bits - 0x0 - 0x20 - read-write - 0x00000000 - - - PS - Power switch - 0 - 2 - - - - - CLKCTRL - CLKCTRL - SD clock control register - (SDIO_CLKCTRL) - 0x4 - 0x20 - read-write - 0x00000000 - - - CLKDIV - Clock division - 0 - 8 - - - CLKOEN - Clock output enable - 8 - 1 - - - PWRSVEN - Power saving mode enable - 9 - 1 - - - BYPSEN - Clock divider bypass enable - bit - 10 - 1 - - - BUSWS - Bus width selection - 11 - 2 - - - CLKEDS - SDIO_CK edge selection bit - 13 - 1 - - - HFCEN - Hardware flow control enable - 14 - 1 - - - CLKDIV98 - Clock divide factor bit9 and bit8 - 15 - 2 - - - - - ARGU - ARGU - Bits 31:0 = : Command argument - 0x8 - 0x20 - read-write - 0x00000000 - - - ARGU - Command argument - 0 - 32 - - - - - CMDCTRL - CMDCTRL - SDIO command control register - (SDIO_CMDCTRL) - 0xC - 0x20 - read-write - 0x00000000 - - - CMDIDX - CMDIDX - 0 - 6 - - - RSPWT - Wait for response - 6 - 2 - - - INTWT - CCSM wait for interrupt - 8 - 1 - - - PNDWT - CCSM wait for end of transfer - 9 - 1 - - - CCSMEN - Command channel state machine - 10 - 1 - - - IOSUSP - SD I/O suspend command - 11 - 1 - - - - - RSPCMD - RSPCMD - SDIO command register - 0x10 - 0x20 - read-only - 0x00000000 - - - RSPCMD - RSPCMD - 0 - 6 - - - - - RSP1 - RSP1 - Bits 31:0 = CARDSTATUS1 - 0x14 - 0x20 - read-only - 0x00000000 - - - CARDSTS1 - CARDSTATUS1 - 0 - 32 - - - - - RSP2 - RSP2 - Bits 31:0 = CARDSTATUS2 - 0x18 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS2 - 0 - 32 - - - - - RSP3 - RSP3 - Bits 31:0 = CARDSTATUS3 - 0x1C - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS3 - 0 - 32 - - - - - RSP4 - RSP4 - Bits 31:0 = CARDSTATUS4 - 0x20 - 0x20 - read-only - 0x00000000 - - - CARDSTS2 - CARDSTATUS4 - 0 - 32 - - - - - DTTMR - DTTMR - Bits 31:0 = TIMEOUT: Data timeout - period - 0x24 - 0x20 - read-write - 0x00000000 - - - TIMEOUT - Data timeout period - 0 - 32 - - - - - DTLEN - DTLEN - Bits 24:0 = DATALENGTH: Data length - value - 0x28 - 0x20 - read-write - 0x00000000 - - - DTLEN - Data length value - 0 - 25 - - - - - DTCTRL - DTCTRL - SDIO data control register - (SDIO_DCTRL) - 0x2C - 0x20 - read-write - 0x00000000 - - - TFREN - DTEN - 0 - 1 - - - TFRDIR - DTDIR - 1 - 1 - - - TFRMODE - DTMODE - 2 - 1 - - - DMAEN - DMAEN - 3 - 1 - - - BLKSIZE - DBLOCKSIZE - 4 - 4 - - - RDWTSTART - PWSTART - 8 - 1 - - - RDWTSTOP - PWSTOP - 9 - 1 - - - RDWTMODE - RWMOD - 10 - 1 - - - IOEN - SD I/O function enable - 11 - 1 - - - - - DTCNT - DTCNT - Bits 24:0 = DATACOUNT: Data count - value - 0x30 - 0x20 - read-only - 0x00000000 - - - CNT - Data count value - 0 - 25 - - - - - STS - STS - SDIO status register - (SDIO_STA) - 0x34 - 0x20 - read-only - 0x00000000 - - - CMDFAIL - Command crc fail - 0 - 1 - - - DTFAIL - Data crc fail - 1 - 1 - - - CMDTIMEOUT - Command timeout - 2 - 1 - - - DTTIMEOUT - Data timeout - 3 - 1 - - - TXERRU - Tx under run error - 4 - 1 - - - RXERRO - Rx over run error - 5 - 1 - - - CMDRSPCMPL - Command response complete - 6 - 1 - - - CMDCMPL - Command sent - 7 - 1 - - - DTCMPL - Data sent - 8 - 1 - - - SBITERR - Start bit error - 9 - 1 - - - DTBLKCMPL - Data block sent - 10 - 1 - - - DOCMD - Command transfer in progress - 11 - 1 - - - DOTX - Data transmit in progress - 12 - 1 - - - DORX - Data receive in progress - 13 - 1 - - - TXBUFH - Tx buffer half empty - 14 - 1 - - - RXBUFH - Rx buffer half empty - 15 - 1 - - - TXBUFF - Tx buffer full - 16 - 1 - - - RXBUFF - Rx buffer full - 17 - 1 - - - TXBUFE - Tx buffer empty - 18 - 1 - - - RXBUFE - Rx buffer empty - 19 - 1 - - - TXBUF - Tx data vaild - 20 - 1 - - - RXBUF - Rx data vaild - 21 - 1 - - - IOIF - SD I/O interrupt - 22 - 1 - - - - - INTCLR - INTCLR - SDIO interrupt clear register - (SDIO_INTCLR) - 0x38 - 0x20 - read-write - 0x00000000 - - - CMDFAIL - Command crc fail flag clear - 0 - 1 - - - DTFAIL - Data crc fail flag clear - 1 - 1 - - - CMDTIMEOUT - Command timeout flag clear - 2 - 1 - - - DTTIMEOUT - Data timeout flag clear - 3 - 1 - - - TXERRU - Tx under run error flag clear - 4 - 1 - - - RXERRU - Rx over run error flag clear - 5 - 1 - - - CMDRSPCMPL - Command response complete flag clear - 6 - 1 - - - CMDCMPL - Command sent flag clear - 7 - 1 - - - DTCMPL - Data sent flag clear - 8 - 1 - - - SBITERR - Start bit error flag clear - 9 - 1 - - - DTBLKCMPL - Data block sent clear - 10 - 1 - - - IOIF - SD I/O interrupt flag clear - 22 - 1 - - - - - INTEN - INTEN - SDIO mask register (SDIO_MASK) - 0x3C - 0x20 - read-write - 0x00000000 - - - CMDFAILIEN - Command crc fail interrupt enable - 0 - 1 - - - DTFAILIEN - Data crc fail interrupt enable - 1 - 1 - - - CMDTIMEOUTIEN - Command timeout interrupt enable - 2 - 1 - - - DTTIMEOUTIEN - Data timeout interrupt enable - 3 - 1 - - - TXERRUIEN - Tx under run interrupt enable - 4 - 1 - - - RXERRUIEN - Rx over run interrupt enable - 5 - 1 - - - CMDRSPCMPLIEN - Command response complete interrupt enable - 6 - 1 - - - CMDCMPLIEN - Command sent complete interrupt enable - 7 - 1 - - - DTCMPLIEN - Data sent complete interrupt enable - 8 - 1 - - - SBITERRIEN - Start bit error interrupt enable - 9 - 1 - - - DTBLKCMPLIEN - Data block sent complete interrupt enable - 10 - 1 - - - DOCMDIEN - Command acting interrupt enable - 11 - 1 - - - DOTXIEN - Data transmit acting interrupt enable - 12 - 1 - - - DORXIEN - Data receive acting interrupt enable - 13 - 1 - - - TXBUFHIEN - Tx buffer half empty interrupt enable - 14 - 1 - - - RXBUFHIEN - Rx buffer half empty interrupt enable - 15 - 1 - - - TXBUFFIEN - Tx buffer full interrupt enable - 16 - 1 - - - RXBUFFIEN - Rx buffer full interrupt enable - 17 - 1 - - - TXBUFEIEN - Tx buffer empty interrupt enable - 18 - 1 - - - RXBUFEIEN - Rx buffer empty interrupt enable - 19 - 1 - - - TXBUFIEN - Tx buffer data vaild interrupt enable - 20 - 1 - - - RXBUFIEN - Rx buffer data vaild interrupt enable - 21 - 1 - - - IOIFIEN - SD I/O interrupt enable - 22 - 1 - - - - - BUFCNT - BUFCNT - Bits 23:0 = BUFCOUNT: Remaining number of - words to be written to or read from the - FIFO - 0x48 - 0x20 - read-only - 0x00000000 - - - CNT - FIF0COUNT - 0 - 24 - - - - - BUF - BUF - bits 31:0 = Buffer Data: Receive and transmit - buffer data - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Buffer data - 0 - 32 - - - - - - - SDIO2 - 0x50061000 - - SDIO2 - SDIO2 global interrupt - 102 - - - - ERTC - Real-time clock - ERTC - 0x40002800 - - 0x0 - 0x400 - registers - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - AMPM - AM/PM notation - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YT - Year tens - 20 - 4 - - - YU - Year units - 16 - 4 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - CTRL - CTRL - control register - 0x8 - 0x20 - read-write - 0x00000000 - - - CALOEN - Calibration output enable - 23 - 1 - - - OUTSEL - Output source selection - 21 - 2 - - - OUTP - Output polarity - 20 - 1 - - - CALOSEL - Calibration output selection - 19 - 1 - - - BPR - Battery power domain data register - 18 - 1 - - - DEC1H - Decrease 1 hour - 17 - 1 - - - ADD1H - Add 1 hour - 16 - 1 - - - TSIEN - Timestamp interrupt enable - 15 - 1 - - - WATIEN - Wakeup timer interrupt enable - 14 - 1 - - - ALBIEN - Alarm B interrupt enable - 13 - 1 - - - ALAIEN - Alarm A interrupt enable - 12 - 1 - - - TSEN - Timestamp enable - 11 - 1 - - - WATEN - Wakeup timer enable - 10 - 1 - - - ALBEN - Alarm B enable - 9 - 1 - - - ALAEN - Alarm A enable - 8 - 1 - - - CCALEN - Coarse calibration enable - 7 - 1 - - - HM - Hour mode - 6 - 1 - - - DREN - Date/time register direct read enable - 5 - 1 - - - RCDEN - Reference clock detection enable - 4 - 1 - - - TSEDG - Timestamp trigger edge - 3 - 1 - - - WATCLK - Wakeup timer clock selection - 0 - 3 - - - - - STS - STS - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - ALAWF - Alarm A register allows write flag - 0 - 1 - read-only - - - ALBWF - Alarm B register allows write flag - 1 - 1 - read-only - - - WATWF - Wakeup timer register allows write flag - 2 - 1 - read-only - - - TADJF - Time adjustment flag - 3 - 1 - read-write - - - INITF - Calendar initialization flag - 4 - 1 - read-only - - - UPDF - Calendar update flag - 5 - 1 - read-write - - - IMF - Enter initialization mode flag - 6 - 1 - read-only - - - IMEN - Initialization mode enable - 7 - 1 - read-write - - - ALAF - Alarm A flag - 8 - 1 - read-write - - - ALBF - Alarm B flag - 9 - 1 - read-write - - - WATF - Wakeup timer flag - 10 - 1 - read-write - - - TSF - Timestamp flag - 11 - 1 - read-write - - - TSOF - Timestamp overflow flag - 12 - 1 - read-write - - - TP1F - Tamper detection 1 flag - 13 - 1 - read-write - - - TP2F - Tamper detection 2 flag - 14 - 1 - read-write - - - CALUPDF - Calibration value update completed flag - 16 - 1 - read-only - - - - - DIV - DIV - Diveder register - 0x10 - 0x20 - read-write - 0x007F00FF - - - DIVA - Diveder A - 16 - 7 - - - DIVB - Diveder B - 0 - 15 - - - - - WAT - WAT - Wakeup timer register - 0x14 - 0x20 - read-write - 0x0000FFFF - - - VAL - Wakeup timer reload value - 0 - 16 - - - - - CCAL - CCAL - Calibration register - 0x18 - 0x20 - read-write - 0x00000000 - - - CALDIR - Calibration direction - 7 - 1 - - - CALVAL - Calibration value - 0 - 5 - - - - - ALA - ALA - Alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - ALB - ALB - Alarm B register - 0x20 - 0x20 - read-write - 0x00000000 - - - MASK4 - Date/week mask - 31 - 1 - - - WKSEL - Date/week mode select - 30 - 1 - - - DT - Date tens - 28 - 2 - - - DU - Date units - 24 - 4 - - - MASK3 - Hours mask - 23 - 1 - - - AMPM - AM/PM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MASK2 - Minutes mask - 15 - 1 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - MASK1 - Seconds mask - 7 - 1 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - WP - WP - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 8 - - - - - SBS - SBS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - TADJ - TADJ - time adjust register - 0x2C - 0x20 - write-only - 0x00000000 - - - ADD1S - Add 1 second - 31 - 1 - - - DECSBS - Decrease sub-second value - 0 - 15 - - - - - TSTM - TSTM - time stamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - AMPM - AMPM - 22 - 1 - - - HT - Hour tens - 20 - 2 - - - HU - Hour units - 16 - 4 - - - MT - Minute tens - 12 - 3 - - - MU - Minute units - 8 - 4 - - - ST - Second tens - 4 - 3 - - - SU - Second units - 0 - 4 - - - - - TSDT - TSDT - timestamp date register - 0x34 - 0x20 - read-only - 0x00000000 - - - WK - Week - 13 - 3 - - - MT - Month tens - 12 - 1 - - - MU - Month units - 8 - 4 - - - DT - Date tens - 4 - 2 - - - DU - Date units - 0 - 4 - - - - - TSSBS - TSSBS - timestamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SBS - Sub second value - 0 - 16 - - - - - SCAL - SCAL - calibration register - 0x3C - 0x20 - read-write - 0x00000000 - - - ADD - Add ERTC clock - 15 - 1 - - - CAL8 - 8-second calibration period - 14 - 1 - - - CAL16 - 16 second calibration period - 13 - 1 - - - DEC - Decrease ERTC clock - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - OUTTYPE - Output type - 18 - 1 - - - TSPIN - Time stamp detection pin selection - 17 - 1 - - - TP1PIN - Tamper detection pin selection - 16 - 1 - - - TPPU - Tamper detection pull-up - 15 - 1 - - - TPPR - Tamper detection pre-charge time - 13 - 2 - - - TPFLT - Tamper detection filter time - 11 - 2 - - - TPFREQ - Tamper detection frequency - 8 - 3 - - - TPTSEN - Tamper detection timestamp enable - 7 - 1 - - - TP2EDG - Tamper detection 2 valid edge - 4 - 1 - - - TP2EN - Tamper detection 2 enable - 3 - 1 - - - TPIEN - Tamper detection interrupt enable - 2 - 1 - - - TP1EDG - Tamper detection 1 valid edge - 1 - 1 - - - TP1EN - Tamper detection 1 enable - 0 - 1 - - - - - ALASBS - ALASBS - alarm A sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - ALBSBS - ALBSBS - alarm B sub second register - 0x48 - 0x20 - read-write - 0x00000000 - - - SBSMSK - Sub-second mask - 24 - 4 - - - SBS - Sub-seconds value - 0 - 15 - - - - - BPR1DT - BPR1DT - Battery powered domain register - 0x50 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR2DT - BPR2DT - Battery powered domain register - 0x54 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR3DT - BPR3DT - Battery powered domain register - 0x58 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR4DT - BPR4DT - Battery powered domain register - 0x5C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR5DT - BPR5DT - Battery powered domain register - 0x60 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR6DT - BPR6DT - Battery powered domain register - 0x64 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR7DT - BPR7DT - Battery powered domain register - 0x68 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR8DT - BPR8DT - Battery powered domain register - 0x6C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR9DT - BPR9DT - Battery powered domain register - 0x70 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR10DT - BPR10DT - Battery powered domain register - 0x74 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR11DT - BPR11DT - Battery powered domain register - 0x78 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR12DT - BPR12DT - Battery powered domain register - 0x7C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR13DT - BPR13DT - Battery powered domain register - 0x80 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR14DT - BPR14DT - Battery powered domain register - 0x84 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR15DT - BPR15DT - Battery powered domain register - 0x88 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR16DT - BPR16DT - Battery powered domain register - 0x8C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR17DT - BPR17DT - Battery powered domain register - 0x90 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR18DT - BPR18DT - Battery powered domain register - 0x94 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR19DT - BPR19DT - Battery powered domain register - 0x98 - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - BPR20DT - BPR20DT - Battery powered domain register - 0x9C - 0x20 - read-write - 0x00000000 - - - DT - Battery powered domain data - 0 - 32 - - - - - - - WDT - Watchdog - WDT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CMD - CMD - Command register - 0x0 - 0x20 - write-only - 0x00000000 - - - CMD - Command register - 0 - 16 - - - - - DIV - DIV - Division register - 0x4 - 0x20 - read-write - 0x00000000 - - - DIV - Division divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x8 - 0x20 - read-write - 0x00000FFF - - - RLD - Reload value - 0 - 12 - - - - - STS - STS - Status register - 0xC - 0x20 - read-only - 0x00000000 - - - DIVF - Division value update complete flag - 0 - 1 - - - RLDF - Reload value update complete flag - 1 - 1 - - - WINF - Window value update complete flag - 2 - 1 - - - - - WIN - WIN - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WIN - Window value - 0 - 12 - - - - - - - WWDT - Window watchdog - WWDT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDT - Window Watchdog interrupt - 0 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - CNT - Decrement counter - 0 - 7 - - - WWDTEN - Window watchdog enable - 7 - 1 - - - - - CFG - CFG - Configuration register - 0x4 - 0x20 - read-write - 0x0000007F - - - WIN - Window value - 0 - 7 - - - DIV - Clock division value - 7 - 2 - - - RLDIEN - Reload counter interrupt - 9 - 1 - - - - - STS - STS - Status register - 0x8 - 0x20 - read-write - 0x00000000 - - - RLDF - Reload counter interrupt flag - 0 - 1 - - - - - - - TMR1 - Advanced timer - TIMER - 0x40010000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - TMR1_CH - TMR1 channel interrupt - 27 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TRGOUT2EN - TRGOUT2 enable - 31 - 1 - - - C4IOS - Channel 4 idle output state - 14 - 1 - - - C3CIOS - Channel 3 complementary idle output state - 13 - 1 - - - C3IOS - Channel 3 idle output state - 12 - 1 - - - C2CIOS - Channel 2 complementary idle output state - 11 - 1 - - - C2IOS - Channel 2 idle output state - 10 - 1 - - - C1CIOS - Channel 1 complementary idle output state - 9 - 1 - - - C1IOS - Channel 1 idle output state - 8 - 1 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - CCFS - Channel control bit flash select - 2 - 1 - - - CBCTRL - Channel buffer control - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - HALLDE - HALL DMA request enable - 13 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - BRKIE - Brake interrupt enable - 7 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - HALLIEN - HALL interrupt enable - 5 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - BRKIF - Brake interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - HALLIF - HALL interrupt flag - 5 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - BRKSWTR - Brake event triggered by software - 7 - 1 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - HALLSWTR - HALL event triggered by software - 5 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3CP - Channel 3 complementary polarity - 11 - 1 - - - C3CEN - Channel 3 complementary enable - 10 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - RPR - RPR - Repetition of period value - 0x30 - 0x20 - read-write - 0x0000 - - - RPR - Repetition of period value - 0 - 8 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - BRK - BRK - Brake register - 0x44 - 0x20 - read-write - 0x0000 - - - OEN - Output enable - 15 - 1 - - - AOEN - Automatic output enable - 14 - 1 - - - BRKV - Brake input validity - 13 - 1 - - - BRKEN - Brake enable - 12 - 1 - - - FCSOEN - Frozen channel status when - holistic output enable - 11 - 1 - - - FCSODIS - Frozen channel status when - holistic output disable - 10 - 1 - - - WPC - Write protected configuration - 8 - 2 - - - DTC - Dead-time configuration - 0 - 8 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - CM3_OUTPUT - CM3_OUTPUT - Channel output mode register - 0x70 - 0x20 - read-write - 0x00000000 - - - C5OSEN - Channel 5 output switch enable - 7 - 1 - - - C5OCTRL - Channel 5 output control - 4 - 3 - - - C5OBEN - Channel 5 output buffer enable - 3 - 1 - - - C5OIEN - Channel 5 output immediately enable - 2 - 1 - - - - - C5DT - C5DT - Channel 5 data register - 0x74 - 0x20 - read-write - 0x00000000 - - - C5DT - Channel 5 data register - 0 - 16 - - - - - - - TMR8 - 0x40010400 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - TMR8_CH - TMR8 channel interrupt - 46 - - - - TMR20 - 0x40014C00 - - TMR20_BRK - TMR20 brake interrupt - 104 - - - TMR20_OVF - TMR20 overflow interrupt - 105 - - - TMR20_TRG_HALL - TMR20 trigger and HALL interrupts - 106 - - - TMR20_CH - TMR20 channel interrupt - 107 - - - - TMR2 - General purpose timer - TIMER - 0x40000000 - - 0x0 - 0x400 - registers - - - TMR2 - TMR2 global interrupt - 28 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR2_RMP - TMR2_RMP - TMR2 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR2_CH1_IRMP - TMR2 channel 1 input remap - 10 - 2 - - - - - - - TMR3 - General purpose timer - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TMR3 - TMR3 global interrupt - 29 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 16 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 16 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - - - TMR4 - 0x40000800 - - TMR4 - TMR4 global interrupt - 30 - - - - TMR5 - General purpose timer - TIMER - 0x40000C00 - - 0x0 - 0x400 - registers - - - TMR5 - TMR5 global interrupt - 50 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PMEN - Plus Mode Enable - 10 - 1 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - TWCMSEL - Two-way count mode - selection - 5 - 2 - - - OWCDIR - One-way count direction - 4 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - C1INSEL - C1IN selection - 7 - 1 - - - PTOS - Primary TMR output selection - 4 - 3 - - - DRS - DMA request source - 3 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - ESP - External signal polarity - 15 - 1 - - - ECMBEN - External clock mode B enable - 14 - 1 - - - ESDIV - External signal divider - 12 - 2 - - - ESF - External signal filter - 8 - 4 - - - STS - Subordinate TMR synchronization - 7 - 1 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDEN - Trigger DMA request enable - 14 - 1 - - - C4DEN - Channel 4 DMA request - enable - 12 - 1 - - - C3DEN - Channel 3 DMA request - enable - 11 - 1 - - - C2DEN - Channel 2 DMA request - enable - 10 - 1 - - - C1DEN - Channel 1 DMA request - enable - 9 - 1 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C4IEN - Channel 4 interrupt - enable - 4 - 1 - - - C3IEN - Channel 3 interrupt - enable - 3 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C4RF - Channel 4 recapture flag - 12 - 1 - - - C3RF - Channel 3 recapture flag - 11 - 1 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C4IF - Channel 4 interrupt flag - 4 - 1 - - - C3IF - Channel 3 interrupt flag - 3 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C4SWTR - Channel 4 event triggered by software - 4 - 1 - - - C3SWTR - Channel 3 event triggered by software - 3 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OSEN - Channel 2 output switch enable - 15 - 1 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OSEN - Channel 1 output switch enable - 7 - 1 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM2_OUTPUT - CM2_OUTPUT - Channel output mode register 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - C4OSEN - Channel 4 output switch enable - 15 - 1 - - - C4OCTRL - Channel 4 output control - 12 - 3 - - - C4OBEN - Channel 4 output buffer enable - 11 - 1 - - - C4OIEN - Channel 4 output immediately enable - 10 - 1 - - - C4C - Channel 4 configure - 8 - 2 - - - C3OSEN - Channel 3 output switch enable - 7 - 1 - - - C3OCTRL - Channel 3 output control - 4 - 3 - - - C3OBEN - Channel 3 output buffer enable - 3 - 1 - - - C3OIEN - Channel 3 output immediately enable - 2 - 1 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CM2_INPUT - CM2_INPUT - Channel input mode register 2 - CM2_OUTPUT - 0x1C - 0x20 - read-write - 0x00000000 - - - C4DF - Channel 4 digital filter - 12 - 4 - - - C4IDIV - Channel 4 input divider - 10 - 2 - - - C4C - Channel 4 configure - 8 - 2 - - - C3DF - Channel 3 digital filter - 4 - 4 - - - C3IDIV - Channel 3 input divider - 2 - 2 - - - C3C - Channel 3 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C4P - Channel 4 Polarity - 13 - 1 - - - C4EN - Channel 4 enable - 12 - 1 - - - C3P - Channel 3 Polarity - 9 - 1 - - - C3EN - Channel 3 enable - 8 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 32 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 32 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 32 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 32 - - - - - C3DT - C3DT - Channel 3 data register - 0x3C - 0x20 - read-write - 0x00000000 - - - C3DT - Channel 3 data register - 0 - 32 - - - - - C4DT - C4DT - Channel 4 data register - 0x40 - 0x20 - read-write - 0x00000000 - - - C4DT - Channel 4 data register - 0 - 32 - - - - - DMACTRL - DMACTRL - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DTB - DMA transfer bytes - 8 - 5 - - - ADDR - DMA transfer address offset - 0 - 5 - - - - - DMADT - DMADT - DMA data register - 0x4C - 0x20 - read-write - 0x0000 - - - DMADT - DMA data register - 0 - 16 - - - - - TMR5_RMP - TMR5_RMP - TMR5 channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - TMR5_CH4_IRMP - TMR5 channel 4 input remap - 6 - 2 - - - - - - - TMR9 - General purpose timer - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - TMR1_BRK_TMR9 - TMR1 brake interrupt and TMR9 global - interrupt - 24 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - STCTRL - STCTRL - Subordinate TMR control register - 0x8 - 0x20 - read-write - 0x0000 - - - STIS - Subordinate TMR input selection - 4 - 3 - - - SMSEL - Subordinate TMR mode selection - 0 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - TIEN - Trigger interrupt enable - 6 - 1 - - - C2IEN - Channel 2 interrupt - enable - 2 - 1 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C2RF - Channel 2 recapture flag - 10 - 1 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - C2IF - Channel 2 interrupt flag - 2 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - TRGSWTR - Trigger event triggered by software - 6 - 1 - - - C2SWTR - Channel 2 event triggered by software - 2 - 1 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C2OCTRL - Channel 2 output control - 12 - 3 - - - C2OBEN - Channel 2 output buffer enable - 11 - 1 - - - C2OIEN - Channel 2 output immediately enable - 10 - 1 - - - C2C - Channel 2 configure - 8 - 2 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C2DF - Channel 2 digital filter - 12 - 4 - - - C2IDIV - Channel 2 input divider - 10 - 2 - - - C2C - Channel 2 configure - 8 - 2 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C2CP - Channel 2 complementary polarity - 7 - 1 - - - C2CEN - Channel 2 complementary enable - 6 - 1 - - - C2P - Channel 2 Polarity - 5 - 1 - - - C2EN - Channel 2 enable - 4 - 1 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1CEN - Channel 1 complementary enable - 2 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - C2DT - C2DT - Channel 2 data register - 0x38 - 0x20 - read-write - 0x00000000 - - - C2DT - Channel 2 data register - 0 - 16 - - - - - - - TMR12 - 0x40001800 - - TMR8_BRK_TMR12 - TMR8 brake interrupt and TMR12 global - interrupt - 43 - - - - TMR10 - General purpose timer - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TMR1_OVF_TMR10 - TMR1 overflow interrupt and TMR10 global - interrupt - 25 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CLKDIV - Clock divider - 8 - 2 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - C1IEN - Channel 1 interrupt - enable - 1 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - C1RF - Channel 1 recapture flag - 9 - 1 - - - C1IF - Channel 1 interrupt flag - 1 - 1 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - C1SWTR - Channel 1 event triggered by software - 1 - 1 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CM1_OUTPUT - CM1_OUTPUT - Channel output mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - C1OCTRL - Channel 1 output control - 4 - 3 - - - C1OBEN - Channel 1 output buffer enable - 3 - 1 - - - C1OIEN - Channel 1 output immediately enable - 2 - 1 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CM1_INPUT - CM1_INPUT - Channel input mode register 1 - CM1_OUTPUT - 0x18 - 0x20 - read-write - 0x00000000 - - - C1DF - Channel 1 digital filter - 4 - 4 - - - C1IDIV - Channel 1 input divider - 2 - 2 - - - C1C - Channel 1 configure - 0 - 2 - - - - - CCTRL - CCTRL - Channel control - register - 0x20 - 0x20 - read-write - 0x0000 - - - C1CP - Channel 1 complementary polarity - 3 - 1 - - - C1P - Channel 1 Polarity - 1 - 1 - - - C1EN - Channel 1 enable - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - C1DT - C1DT - Channel 1 data register - 0x34 - 0x20 - read-write - 0x00000000 - - - C1DT - Channel 1 data register - 0 - 16 - - - - - - - TMR11 - 0x40014800 - - TMR1_TRG_HALL_TMR11 - TMR1 trigger and HALL interrupts and - TMR11 global interrupt - 26 - - - - TMR13 - 0x40001C00 - - TMR8_OVF_TMR13 - TMR8 overflow interrupt and TMR13 global - interrupt - 44 - - - - TMR14 - 0x40002000 - - TMR8_TRG_HALL_TMR14 - TMR8 trigger and HALL interrupts and - TMR14 global interrupt - 45 - - - - TMR6 - Basic timer - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TMR6 - TMR6 global interrupt - 54 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - PRBEN - Period buffer enable - 7 - 1 - - - OCMEN - One cycle mode enable - 3 - 1 - - - OVFS - Overflow event source - 2 - 1 - - - OVFEN - Overflow event enable - 1 - 1 - - - TMREN - TMR enable - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - PTOS - Primary TMR output selection - 4 - 3 - - - - - IDEN - IDEN - Interrupt/DMA enable register - 0xC - 0x20 - read-write - 0x0000 - - - OVFDEN - Overflow DMA request enable - 8 - 1 - - - OVFIEN - Overflow interrupt enable - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-write - 0x0000 - - - OVFIF - Overflow interrupt flag - 0 - 1 - - - - - SWEVT - SWEVT - Software event register - 0x14 - 0x20 - read-write - 0x0000 - - - OVFSWTR - Overflow event triggered by software - 0 - 1 - - - - - CVAL - CVAL - Counter value - 0x24 - 0x20 - read-write - 0x00000000 - - - CVAL - Counter value - 0 - 16 - - - - - DIV - DIV - Divider value - 0x28 - 0x20 - read-write - 0x0000 - - - DIV - Divider value - 0 - 16 - - - - - PR - PR - Period value - 0x2C - 0x20 - read-write - 0x00000000 - - - PR - Period value - 0 - 16 - - - - - - - TMR7 - 0x40001400 - - TMR7 - TMR7 global interrupt - 55 - - - - ACC - HSI Auto Clock Calibration - ACC - 0x40017400 - - 0x0 - 0x400 - registers - - - - STS - STS - status register - 0x0 - 0x20 - 0x0000 - - - RSLOST - Reference Signal Lost - read-write - 1 - 1 - - - CALRDY - Internal high-speed clock calibration ready - read-write - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x04 - 0x20 - 0x0100 - - - STEP - STEP - read-write - 8 - 4 - - - CALRDYIEN - CALRDY interrupt enable - read-write - 5 - 1 - - - EIEN - RSLOST error interrupt enable - read-write - 4 - 1 - - - SOFSEL - SOF Select - read-write - 2 - 1 - - - ENTRIM - Enable trim - read-write - 1 - 1 - - - CALON - Calibration on - read-write - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x08 - 0x20 - 0x2080 - - - HICKTWK - Internal high-speed auto clock trimming - read-only - 8 - 6 - - - HICKCAL - Internal high-speed auto clock calibration - read-only - 0 - 8 - - - - - C1 - C1 - compare value 1 - 0x0C - 0x20 - 0x1F2C - - - C1 - Compare 1 - read-write - 0 - 16 - - - - - C2 - C2 - compare value 2 - 0x10 - 0x20 - 0x1F40 - - - C2 - Compare 2 - read-write - 0 - 16 - - - - - C3 - C3 - compare value 3 - 0x14 - 0x20 - 0x1F54 - - - C3 - Compare 3 - read-write - 0 - 16 - - - - - - - I2C1 - Inter-integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1_EVT - I2C1 event interrupt - 31 - - - I2C1_ERR - I2C1 error interrupt - 32 - - - - CTRL1 - CTRL1 - Control register 1 - 0x0 - 0x20 - 0x00000000 - - - I2CEN - I2C peripheral enable - 0 - 1 - read-write - - - TDIEN - Transmit data interrupt enable - 1 - 1 - read-write - - - RDIEN - Receive data interrupt enable - 2 - 1 - read-write - - - ADDRIEN - Address match interrupt enable - 3 - 1 - read-write - - - ACKFAILIEN - Acknowledge fail interrupt enable - 4 - 1 - read-write - - - STOPIEN - Stop generation complete interrupt enable - 5 - 1 - read-write - - - TDCIEN - Transfer data complete interrupt enable - 6 - 1 - read-write - - - ERRIEN - Error interrupts enable - 7 - 1 - read-write - - - DFLT - Digital filter value - 8 - 4 - read-write - - - DMATEN - DMA Transmit data request enable - 14 - 1 - read-write - - - DMAREN - DMA receive data request enable - 15 - 1 - read-write - - - SCTRL - Slave receiving data control - 16 - 1 - read-write - - - STRETCH - Clock stretching mode - 17 - 1 - read-write - - - GCAEN - General call address enable - 19 - 1 - read-write - - - HADDREN - SMBus host address enable - 20 - 1 - read-write - - - DEVADDREN - SMBus device default address enable - 21 - 1 - read-write - - - SMBALERT - SMBus alert enable / pin set - 22 - 1 - read-write - - - PECEN - PEC calculation enable - 23 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - PECTEN - Request PEC transmission enable - 26 - 1 - - - ASTOPEN - Automatically send stop condition enable - 25 - 1 - - - RLDEN - Send data reload mode enable - 24 - 1 - - - CNT - Transmit data counter - 16 - 8 - - - NACKEN - Not acknowledge enable - 15 - 1 - - - GENSTOP - Generate stop condition - 14 - 1 - - - GENSTART - Generate start condition - 13 - 1 - - - READH10 - 10-bit address header read enable - 12 - 1 - - - ADDR10 - Host send 10-bit address mode enable - 11 - 1 - - - DIR - Master data transmission direction - 10 - 1 - - - SADDR - Slave address - 0 - 10 - - - - - OADDR1 - OADDR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x00000000 - - - ADDR1 - Interface address - 0 - 10 - - - ADDR1MODE - Own Address mode - 10 - 1 - - - ADDR1EN - Own address 1 enable - 15 - 1 - - - - - OADDR2 - OADDR2 - Own address register 2 - 0xC - 0x20 - read-write - 0x00000000 - - - ADDR2 - Own address 2 - 1 - 7 - - - ADDR2MASK - Own address 2-bit mask - 8 - 3 - - - ADDR2EN - Own address 2 enable - 15 - 1 - - - - - CLKCTRL - CLKCTRL - Clock contorl register - 0x10 - 0x20 - read-write - 0x00000000 - - - SCLL - SCL low level - 0 - 8 - - - SCLH - SCL high level - 8 - 8 - - - SDAD - SDA output delay - 16 - 4 - - - SCLD - SCL output delay - 20 - 4 - - - DIVH - High 4 bits of clock divider value - 24 - 4 - - - DIVL - Low 4 bits of clock divider value - 28 - 4 - - - - - TIMEOUT - TIMEOUT - Timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - TOTIME - Clock timeout detection time - 0 - 12 - - - TOMOED - Clock timeout detection mode - 12 - 1 - - - TOEN - Detect clock low/high timeout enable - 15 - 1 - - - EXTTIME - Cumulative clock low extend timeout value - 16 - 12 - - - EXTEN - Cumulative clock low extend timeout enable - 31 - 1 - - - - - STS - STS - Interrupt and Status register - 0x18 - 0x20 - 0x00000001 - - - ADDR - Slave address matching value - 17 - 7 - read-only - - - SDIR - Slave data transmit direction - 16 - 1 - read-only - - - BUSYF - Bus busy - 15 - 1 - read-only - - - ALERTF - SMBus alert flag - 13 - 1 - read-only - - - TMOUT - SMBus timeout flag - 12 - 1 - read-only - - - PECERR - PEC receive error flag - 11 - 1 - read-only - - - OUF - Overflow or underflow flag - 10 - 1 - read-only - - - ARLOST - Arbitration lost flag - 9 - 1 - read-only - - - BUSERR - Bus error flag - 8 - 1 - read-only - - - TCRLD - Transmission is complete, waiting to load data - 7 - 1 - read-only - - - TDC - Transmit data complete flag - 6 - 1 - read-only - - - STOPF - Stop condition generation complete flag - 5 - 1 - read-only - - - ACKFAIL - Acknowledge failure flag - 4 - 1 - read-only - - - ADDRF - 0~7 bit address match flag - 3 - 1 - read-only - - - RDBF - Receive data buffer full flag - 2 - 1 - read-only - - - TDIS - Send interrupt status - 1 - 1 - read-write - - - TDBE - Transmit data buffer empty flag - 0 - 1 - read-write - - - - - CLR - CLR - Interrupt clear register - 0x1C - 0x20 - write-only - 0x00000000 - - - ALERTC - Clear SMBus alert flag - 13 - 1 - - - TMOUTC - Clear SMBus timeout flag - 12 - 1 - - - PECERRC - Clear PEC receive error flag - 11 - 1 - - - OUFC - Clear overload / underload flag - 10 - 1 - - - ARLOSTC - Clear arbitration lost flag - 9 - 1 - - - BUSERRC - Clear bus error flag - 8 - 1 - - - STOPC - Clear stop condition generation complete flag - 5 - 1 - - - ACKFAILC - Clear acknowledge failure flag - 4 - 1 - - - ADDRC - Clear 0~7 bit address match flag - 3 - 1 - - - - - PEC - PEC - PEC register - 0x20 - 0x20 - read-only - 0x00000000 - - - PECVAL - PEC value - 0 - 8 - - - - - RXDT - RXDT - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - DT - Receive data register - 0 - 8 - - - - - TXDT - TXDT - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - DT - Transmit data register - 0 - 8 - - - - - - - I2C2 - 0x40005800 - - I2C2_EVT - I2C2 event interrupt - 33 - - - I2C2_ERR - I2C2 error interrupt - 34 - - - - I2C3 - 0x40005C00 - - I2C3_EVT - I2C3 event interrupt - 72 - - - I2C3_ERR - I2C3 error interrupt - 73 - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global interrupt - 35 - - - - CTRL1 - CTRL1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SLBEN - Single line bidirectional half-duplex enable - 15 - 1 - - - SLBTD - Single line bidirectional half-duplex transmission direction - 14 - 1 - - - CCEN - CRC calculation enable - 13 - 1 - - - NTC - Next transmission CRC - 12 - 1 - - - FBN - frame bit num - 11 - 1 - - - ORA - Only receive active - 10 - 1 - - - SWCSEN - Software CS enable - 9 - 1 - - - SWCSIL - Software CS internal level - 8 - 1 - - - LTF - LSB transmit first - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - MDIV2_0 - Master clock frequency division bit2-0 - 3 - 3 - - - MSTEN - Master enable - 2 - 1 - - - CLKPOL - Clock polarity - 1 - 1 - - - CLKPHA - Clock phase - 0 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - MDIV3EN - Master clock frequency3 division enable - 9 - 1 - - - MDIV3 - Master clock frequency division bit3 - 8 - 1 - - - TDBEIE - Transmit data buffer empty interrupt enable - 7 - 1 - - - RDBFIE - Receive data buffer full interrupt enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TIEN - TI mode enable - 4 - 1 - - - HWCSOE - Hardware CS output enable - 2 - 1 - - - DMATEN - DMA transmit enable - 1 - 1 - - - DMAREN - DMA receive enable - 0 - 1 - - - - - STS - STS - status register - 0x8 - 0x20 - 0x0002 - - - CSPAS - CS pulse abnormal setting fiag - 8 - 1 - read-write - - - BF - Busy flag - 7 - 1 - read-only - - - ROERR - Receiver overflow error - 6 - 1 - read-only - - - MMERR - Master mode error - 5 - 1 - read-only - - - CCERR - CRC calculation error - 4 - 1 - read-write - - - TUERR - Transmitter underload error - 3 - 1 - read-only - - - ACS - Audio channel state - 2 - 1 - read-only - - - TDBE - Transmit data buffer empty - 1 - 1 - read-only - - - RDBF - Receive data buffer full - 0 - 1 - read-only - - - - - DT - DT - data register - 0xC - 0x20 - read-write - 0x0000 - - - DT - Data value - 0 - 16 - - - - - CPOLY - CPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CPOLY - CRC polynomial - 0 - 16 - - - - - RCRC - RCRC - Receive CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - Receive CRC - 0 - 16 - - - - - TCRC - TCRC - Transmit CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Transmit CRC - 0 - 16 - - - - - I2SCTRL - I2SCTRL - I2S control register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SMSEL - I2S mode select - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - OPERSEL - I2S operation select - 8 - 2 - - - PCMFSSEL - PCM frame synchronization select - 7 - 1 - - - STDSEL - I2S standard select - 4 - 2 - - - I2SCLKPOL - I2S clock polarity - 3 - 1 - - - I2SDBN - I2S data bit num - 1 - 2 - - - I2SCBN - I2S channel bit num - 0 - 1 - - - - - I2SCLK - I2SCLK - I2S clock register - 0x20 - 0x20 - read-write - 00000010 - - - I2SDIV9_8 - I2S division bit9 and bit8 - 10 - 2 - - - I2SMCLKOE - I2S master clock output enable - 9 - 1 - - - I2SODD - Odd result for I2S division - 8 - 1 - - - I2SDIV7_0 - I2S division bit7 to bit0 - 0 - 8 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global interrupt - 36 - - - - SPI3 - 0x40003C00 - - SPI3 - SPI3 global interrupt - 51 - - - - SPI4 - 0x40013400 - - SPI4 - SPI4 global interrupt - 84 - - - - I2S2_EXT - 0x40017800 - - - I2S3_EXT - 0x40017C00 - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40011000 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global interrupt - 37 - - - - STS - STS - Status register - 0x0 - 0x20 - 0x00C0 - - - CTSCF - CTS change flag - 9 - 1 - read-write - - - BFF - Break frame flag - 8 - 1 - read-write - - - TDBE - Transmit data buffer empty - 7 - 1 - read-only - - - TDC - Transmit data complete - 6 - 1 - read-write - - - RDBF - Receive data buffer full - 5 - 1 - read-write - - - IDLEF - IDLE flag - 4 - 1 - read-only - - - ROERR - Receiver overflow error - 3 - 1 - read-only - - - NERR - Noise error - 2 - 1 - read-only - - - FERR - Framing error - 1 - 1 - read-only - - - PERR - Parity error - 0 - 1 - read-only - - - - - DT - DT - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DT - Data value - 0 - 9 - - - - - BAUDR - BAUDR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV - Division - 0 - 16 - - - - - CTRL1 - CTRL1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - DBN1 - high bit for Data bit num - 28 - 1 - - - TSDT - transmit start delay time - 21 - 5 - - - TCDT - transmit complete delay time - 16 - 5 - - - UEN - USART enable - 13 - 1 - - - DBN0 - low bit for Data bit num - 12 - 1 - - - WUM - Wake up mode - 11 - 1 - - - PEN - Parity enable - 10 - 1 - - - PSEL - Parity selection - 9 - 1 - - - PERRIEN - PERR interrupt enable - 8 - 1 - - - TDBEIEN - TDBE interrupt enable - 7 - 1 - - - TDCIEN - TDC interrupt enable - 6 - 1 - - - RDBFIEN - RDBF interrupt enable - 5 - 1 - - - IDLEIEN - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - RM - Receiver mute - 1 - 1 - - - SBF - Send break frame - 0 - 1 - - - - - CTRL2 - CTRL2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - ID7_4 - bit 7-4 for usart identification - 28 - 4 - - - TRPSWAP - Transmit receive pin swap - 15 - 1 - - - LINEN - LIN mode enable - 14 - 1 - - - STOPBN - STOP bit num - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CLKPOL - Clock polarity - 10 - 1 - - - CLKPHA - Clock phase - 9 - 1 - - - LBCP - Last bit clock pulse - 8 - 1 - - - BFIEN - Break frame interrupt enable - 6 - 1 - - - BFBN - Break frame bit num - 5 - 1 - - - IDBN - Identification bit num - 4 - 1 - - - ID3_0 - bit 3-0 for usart identification - 0 - 4 - - - - - CTRL3 - CTRL3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - DEP - DE polarity selection - 15 - 1 - - - RS485EN - RS485 enable - 14 - 1 - - - CTSCFIEN - CTSCF interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DMATEN - DMA transmitter enable - 7 - 1 - - - DMAREN - DMA receiver enable - 6 - 1 - - - SCMEN - Smartcard mode enable - 5 - 1 - - - SCNACKEN - Smartcard NACK enable - 4 - 1 - - - SLBEN - Single line bidirectional half-duplex enable - 3 - 1 - - - IRDALP - IrDA low-power mode - 2 - 1 - - - IRDAEN - IrDA enable - 1 - 1 - - - ERRIEN - Error interrupt enable - 0 - 1 - - - - - GDIV - GDIV - Guard time and division register - 0x18 - 0x20 - read-write - 0x0000 - - - SCGT - Smart card guard time value - 8 - 8 - - - ISDIV - IrDA/smartcard division value - 0 - 8 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global interrupt - 38 - - - - USART3 - 0x40004800 - - USART3 - USART3 global interrupt - 39 - - - - USART6 - 0x40011400 - - USART6 - USART6 global interrupt - 71 - - - - ADC1 - Analog to digital converter - ADC - 0x40012000 - - 0x0 - 0x100 - registers - - - ADC - ADC1 global interrupt - 18 - - - - STS - STS - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - RDY - ADC ready to conversion flag - 6 - 1 - read-only - - - OCCO - Ordinary channel conversion overflow flag - 5 - 1 - - - OCCS - Ordinary channel conversion start flag - 4 - 1 - - - PCCS - Preempted channel conversion start flag - 3 - 1 - - - PCCE - Preempted channels conversion end flag - 2 - 1 - - - OCCE - Ordinary channels conversion end flag - 1 - 1 - - - VMOR - Voltage monitoring out of range flag - 0 - 1 - - - - - CTRL1 - CTRL1 - control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - OCCOIEN - Ordinary channel conversion overflow interrupt enable - 26 - 1 - - - CRSEL - Conversion resolution select - 24 - 2 - - - OCVMEN - Voltage monitoring enable on ordinary channels - 23 - 1 - - - PCVMEN - Voltage monitoring enable on preempted channels - 22 - 1 - - - OCPCNT - Partitioned mode conversion count of ordinary channels - 13 - 3 - - - PCPEN - Partitioned mode enable on preempted channels - 12 - 1 - - - OCPEN - Partitioned mode enable on ordinary channels - 11 - 1 - - - PCAUTOEN - Preempted group automatic conversion enable after ordinary group - 10 - 1 - - - VMSGEN - Voltage monitoring enable on a single channel - 9 - 1 - - - SQEN - Sequence mode enable - 8 - 1 - - - PCCEIEN - Conversion end interrupt enable for preempted channels - 7 - 1 - - - VMORIEN - Voltage monitoring out of range interrupt enable - 6 - 1 - - - OCCEIEN - Ordinary channel conversion end interrupt enable - 5 - 1 - - - VMCSEL - Voltage monitoring channel select - 0 - 5 - - - - - CTRL2 - CTRL2 - control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - OCTESEL_H - High bit of trigger event select for ordinary channels conversion - 31 - 1 - - - OCSWTRG - Ordinary channel software conversion trigger - 30 - 1 - - - OCETE - Ordinary channel external trigger edge select - 28 - 2 - - - OCTESEL_L - Low bit of trigger event select for ordinary channels conversion - 24 - 4 - - - PCTESEL_H - High bit of trigger event select for preempted channels conversion - 23 - 1 - - - PCSWTRG - Preempted channel software conversion trigger - 22 - 1 - - - PCETE - Preempted channel external trigger edge select - 20 - 2 - - - PCTESEL_L - Low bit of trigger event select for preempted channels conversion - 16 - 4 - - - DTALIGN - Data alignment - 11 - 1 - - - EOCSFEN - Each ordinary channel conversion set OCCE flag enable - 10 - 1 - - - OCDRCEN - Ordinary channel DMA request continuation enable for independent mode - 9 - 1 - - - OCDMAEN - Ordinary channel DMA transfer enable for independent mode - 8 - 1 - - - ADABRT - ADC conversion abort - 4 - 1 - - - ADCALINIT - Initialize A/D calibration - 3 - 1 - - - ADCAL - A/D Calibration - 2 - 1 - - - RPEN - Repeat mode enable - 1 - 1 - - - ADCEN - A/D converter enable - 0 - 1 - - - - - SPT1 - SPT1 - sample time register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - CSPT18 - Selection sample time of channel ADC_IN18 - 24 - 3 - - - CSPT17 - Selection sample time of channel ADC_IN17 - 21 - 3 - - - CSPT16 - Selection sample time of channel ADC_IN16 - 18 - 3 - - - CSPT15 - Selection sample time of channel ADC_IN15 - 15 - 3 - - - CSPT14 - Selection sample time of channel ADC_IN14 - 12 - 3 - - - CSPT13 - Selection sample time of channel ADC_IN13 - 9 - 3 - - - CSPT12 - Selection sample time of channel ADC_IN12 - 6 - 3 - - - CSPT11 - Selection sample time of channel ADC_IN11 - 3 - 3 - - - CSPT10 - Selection sample time of channel ADC_IN10 - 0 - 3 - - - - - SPT2 - SPT2 - sample time register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CSPT9 - Selection sample time of channel ADC_IN9 - 27 - 3 - - - CSPT8 - Selection sample time of channel ADC_IN8 - 24 - 3 - - - CSPT7 - Selection sample time of channel ADC_IN7 - 21 - 3 - - - CSPT6 - Selection sample time of channel ADC_IN6 - 18 - 3 - - - CSPT5 - Selection sample time of channel ADC_IN5 - 15 - 3 - - - CSPT4 - Selection sample time of channel ADC_IN4 - 12 - 3 - - - CSPT3 - Selection sample time of channel ADC_IN3 - 9 - 3 - - - CSPT2 - Selection sample time of channel ADC_IN2 - 6 - 3 - - - CSPT1 - Selection sample time of channel ADC_IN1 - 3 - 3 - - - CSPT0 - Selection sample time of channel ADC_IN0 - 0 - 3 - - - - - PCDTO1 - PCDTO1 - Preempted channel 1 data offset register - 0x14 - 0x20 - read-write - 0x00000000 - - - PCDTO1 - Data offset for Preempted channel 1 - 0 - 12 - - - - - PCDTO2 - PCDTO2 - Preempted channel 2 data offset register - 0x18 - 0x20 - read-write - 0x00000000 - - - PCDTO2 - Data offset for Preempted channel 2 - 0 - 12 - - - - - PCDTO3 - PCDTO3 - Preempted channel 3 data offset register - 0x1C - 0x20 - read-write - 0x00000000 - - - PCDTO3 - Data offset for Preempted channel 3 - 0 - 12 - - - - - PCDTO4 - PCDTO4 - Preempted channel 4 data offset register - 0x20 - 0x20 - read-write - 0x00000000 - - - PCDTO4 - Data offset for Preempted channel 4 - 0 - 12 - - - - - VMHB - VMHB - Voltage monitoring high boundary register - 0x24 - 0x20 - read-write - 0x00000FFF - - - VMHB - Voltage monitoring high boundary - 0 - 12 - - - - - VMLB - VMLB - Voltage monitoring low boundary register - 0x28 - 0x20 - read-write - 0x00000000 - - - VMLB - Voltage monitoring low boundary - 0 - 12 - - - - - OSQ1 - OSQ1 - Ordinary sequence register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - OCLEN - Ordinary conversion sequence length - 20 - 4 - - - OSN16 - Number of 16th conversion in ordinary sequence - 15 - 5 - - - OSN15 - Number of 15th conversion in ordinary sequence - 10 - 5 - - - OSN14 - Number of 14th conversion in ordinary sequence - 5 - 5 - - - OSN13 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ2 - OSQ2 - Ordinary sequence register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - OSN12 - Number of 12th conversion in ordinary sequence - 25 - 5 - - - OSN11 - Number of 11th conversion in ordinary sequence - 20 - 5 - - - OSN10 - Number of 10th conversion in ordinary sequence - 15 - 5 - - - OSN9 - Number of 8th conversion in ordinary sequence - 10 - 5 - - - OSN8 - Number of 7th conversion in ordinary sequence - 5 - 5 - - - OSN7 - Number of 13th conversion in ordinary sequence - 0 - 5 - - - - - OSQ3 - OSQ3 - Ordinary sequence register 3 - 0x34 - 0x20 - read-write - 0x00000000 - - - OSN6 - Number of 6th conversion in ordinary sequence - 25 - 5 - - - OSN5 - Number of 5th conversion in ordinary sequence - 20 - 5 - - - OSN4 - Number of 4th conversion in ordinary sequence - 15 - 5 - - - OSN3 - number of 3rd conversion in ordinary sequence - 10 - 5 - - - OSN2 - Number of 2nd conversion in ordinary sequence - 5 - 5 - - - OSN1 - Number of 1st conversion in ordinary sequence - 0 - 5 - - - - - PSQ - PSQ - Preempted sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - PCLEN - Preempted conversion sequence length - 20 - 2 - - - PSN4 - Number of 4th conversion in Preempted sequence - 15 - 5 - - - PSN3 - Number of 3rd conversion in Preempted sequence - 10 - 5 - - - PSN2 - Number of 2nd conversion in Preempted sequence - 5 - 5 - - - PSN1 - Number of 1st conversion in Preempted sequence - 0 - 5 - - - - - PDT1 - PDT1 - Preempted data register 1 - 0x3C - 0x20 - read-only - 0x00000000 - - - PDT1 - Preempted data - 0 - 16 - - - - - PDT2 - PDT2 - Preempted data register 2 - 0x40 - 0x20 - read-only - 0x00000000 - - - PDT2 - Preempted data - 0 - 16 - - - - - PDT3 - PDT3 - Preempted data register 3 - 0x44 - 0x20 - read-only - 0x00000000 - - - PDT3 - Preempted data - 0 - 16 - - - - - PDT4 - PDT4 - Preempted data register 4 - 0x48 - 0x20 - read-only - 0x00000000 - - - PDT4 - Preempted data - 0 - 16 - - - - - ODT - ODT - Ordinary data register - 0x4C - 0x20 - read-only - 0x00000000 - - - ODT - Conversion data of ordinary channel - 0 - 16 - - - - - OVSP - OVSP - oversampling register - 0x80 - 0x20 - read-write - 0x00000000 - - - OOSRSEL - Ordinary oversampling recovery mode select - 10 - 1 - - - OOSTREN - Ordinary oversampling trigger mode enable - 9 - 1 - - - OSSSEL - Oversampling shift select - 5 - 4 - - - OSRSEL - Oversampling ratio select - 2 - 3 - - - POSEN - Preempted oversampling enable - 1 - 1 - - - OOSEN - Ordinary oversampling enable - 0 - 1 - - - - - CALVAL - CALVAL - Calibration value register - 0xB4 - 0x20 - read-write - 0x00000000 - - - CALVAL - A/D Calibration value - 0 - 7 - - - - - - - ADC2 - 0x40012100 - - ADC - ADC2 global interrupts - 18 - - - - ADC3 - 0x40012200 - - ADC - ADC3 global interrupts - 18 - - - - ADCCOM - ADC common area - ADC - 0x40012300 - - 0x0 - 0x100 - registers - - - - CSTS - CSTS - Common status register - 0x0 - 0x20 - read-only - 0x00000000 - - - RDY3 - ADC ready to conversion flag of ADC3 - 22 - 1 - - - OCCO3 - Ordinary channel conversion overflow flag of ADC3 - 21 - 1 - - - OCCS3 - Ordinary channel conversion start flag of ADC3 - 20 - 1 - - - PCCS3 - Preempted channel conversion start flag of ADC3 - 19 - 1 - - - PCCE3 - Preempted channels conversion end flag of ADC3 - 18 - 1 - - - OCCE3 - Ordinary channels conversion end flag of ADC3 - 17 - 1 - - - VMOR3 - Voltage monitoring out of range flag of ADC3 - 16 - 1 - - - RDY2 - ADC ready to conversion flag of ADC2 - 14 - 1 - - - OCCO2 - Ordinary channel conversion overflow flag of ADC2 - 13 - 1 - - - OCCS2 - Ordinary channel conversion start flag of ADC2 - 12 - 1 - - - PCCS2 - Preempted channel conversion start flag of ADC2 - 11 - 1 - - - PCCE2 - Preempted channels conversion end flag of ADC2 - 10 - 1 - - - OCCE2 - Ordinary channels conversion end flag of ADC2 - 9 - 1 - - - VMOR2 - Voltage monitoring out of range flag of ADC2 - 8 - 1 - - - RDY1 - ADC ready to conversion flag of ADC1 - 6 - 1 - - - OCCO1 - Ordinary channel conversion overflow flag of ADC1 - 5 - 1 - - - OCCS1 - Ordinary channel conversion start flag of ADC1 - 4 - 1 - - - PCCS1 - Preempted channel conversion start flag of ADC1 - 3 - 1 - - - PCCE1 - Preempted channels conversion end flag of ADC1 - 2 - 1 - - - OCCE1 - Ordinary channels conversion end flag of ADC1 - 1 - 1 - - - VMOR1 - Voltage monitoring out of range flag of ADC1 - 0 - 1 - - - - - CCTRL - CCTRL - Common control register - 0x4 - 0x20 - read-write - 0x00000000 - - - MSDMASEL_H - High bit of ordinary channel DMA transfer mode select for master slave mode - 28 - 1 - - - ITSRVEN - Internal temperature sensor and VINTRV enable - 23 - 1 - - - VBATEN - VBAT enable - 22 - 1 - - - ADCDIV - ADC division - 16 - 4 - - - MSDMASEL_L - Low bit of ordinary channel DMA transfer mode select for master slave mode - 14 - 2 - - - MSDRCEN - Ordinary channel DMA request continuation enable for master slave mode - 13 - 1 - - - ASISEL - Adjacent ADC sampling interval select for ordinary shifting mode - 8 - 4 - - - MSSEL - Master slave mode select - 0 - 5 - - - - - CODT - CODT - Common Ordinary data register - 0x8 - 0x20 - read-only - 0x00000000 - - - CODTH - Ordinary conversion high halfword data for master slave mode - 16 - 16 - - - CODTL - Ordinary conversion low halfword data for master slave mode - 0 - 16 - - - - - - - CAN1 - Can controller area network - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN1_TX - CAN1 TX interrupt - 19 - - - CAN1_RX0 - CAN1 RX0 interrupt - 20 - - - CAN_RX1 - CAN1 RX1 interrupt - 21 - - - CAN_SE - CAN1 SE interrupt - 22 - - - - MCTRL - MCTRL - Main control register - 0x0 - 0x20 - read-write - 0x00010002 - - - PTD - Prohibit transmission when debug - 16 - 1 - - - SPRST - Software partial reset - 15 - 1 - - - TTCEN - Time triggered communication mode enable - 7 - 1 - - - AEBOEN - Automatic exit bus-off enable - 6 - 1 - - - AEDEN - Automatic exit doze mode enable - 5 - 1 - - - PRSFEN - Prohibit retransmission when sending fails enable - 4 - 1 - - - MDRSEL - Message discarding rule select when overflow - 3 - 1 - - - MMSSR - Multiple message sending sequence rule - 2 - 1 - - - DZEN - Doze mode enable - 1 - 1 - - - FZEN - Freeze mode enable - 0 - 1 - - - - - MSTS - MSTS - Main status register - 0x4 - 0x20 - 0x00000C02 - - - REALRX - Real time level of RX pin - 11 - 1 - read-only - - - LSAMPRX - Last sample level of RX pin - 10 - 1 - read-only - - - CURS - Currently receiving status - 9 - 1 - read-only - - - CUSS - Currently sending status - 8 - 1 - read-only - - - EDZIF - Enter doze mode interrupt flag - 4 - 1 - read-write - - - QDZIF - Quit doze mode interrupt flag - 3 - 1 - read-write - - - EOIF - Error occur Interrupt flag - 2 - 1 - read-write - - - DZC - Doze mode confirm - 1 - 1 - read-only - - - FZC - Freeze mode confirm - 0 - 1 - read-only - - - - - TSTS - TSTS - Transmit status register - 0x8 - 0x20 - 0x1C000000 - - - TM2LPF - Transmit mailbox 2 lowest priority flag - 31 - 1 - read-only - - - TM1LPF - Transmit mailbox 1 lowest priority flag - 30 - 1 - read-only - - - TM0LPF - Transmit mailbox 0 lowest priority flag - 29 - 1 - read-only - - - TM2EF - Transmit mailbox 2 empty flag - 28 - 1 - read-only - - - TM1EF - Transmit mailbox 1 empty flag - 27 - 1 - read-only - - - TM0EF - Transmit mailbox 0 empty flag - 26 - 1 - read-only - - - TMNR - Transmit Mailbox number record - 24 - 2 - read-only - - - TM2CT - Transmit mailbox 2 cancel transmission - 23 - 1 - read-write - - - TM2TEF - Transmit mailbox 2 transmission error flag - 19 - 1 - read-write - - - TM2ALF - Transmit mailbox 2 arbitration lost flag - 18 - 1 - read-write - - - TM2TSF - Transmit mailbox 2 transmission success flag - 17 - 1 - read-write - - - TM2TCF - transmit mailbox 2 transmission complete flag - 16 - 1 - read-write - - - TM1CT - Transmit mailbox 1 cancel transmission - 15 - 1 - read-write - - - TM1TEF - Transmit mailbox 1 transmission error flag - 11 - 1 - read-write - - - TM1ALF - Transmit mailbox 1 arbitration lost flag - 10 - 1 - read-write - - - TM1TSF - Transmit mailbox 1 transmission success flag - 9 - 1 - read-write - - - TM1TCF - Transmit mailbox 1 transmission complete flag - 8 - 1 - read-write - - - TM0CT - Transmit mailbox 0 cancel transmission - 7 - 1 - read-write - - - TM0TEF - Transmit mailbox 0 transmission error flag - 3 - 1 - read-write - - - TM0ALF - Transmit mailbox 0 arbitration lost flag - 2 - 1 - read-write - - - TM0TSF - Transmit mailbox 0 transmission success flag - 1 - 1 - read-write - - - TM0TCF - Transmit mailbox 0 transmission complete flag - 0 - 1 - read-write - - - - - RF0 - RF0 - Receive FIFO 0 register - 0xC - 0x20 - 0x00000000 - - - RF0R - Receive FIFO 0 release - 5 - 1 - read-write - - - RF0OF - Receive FIFO 0 overflow flag - 4 - 1 - read-write - - - RF0FF - Receive FIFO 0 full flag - 3 - 1 - read-write - - - RF0MN - Receive FIFO 0 message num - 0 - 2 - read-only - - - - - RF1 - RF1 - Receive FIFO 1 register - 0x10 - 0x20 - 0x00000000 - - - RF1R - Receive FIFO 1 release - 5 - 1 - read-write - - - RF1OF - Receive FIFO 1 overflow flag - 4 - 1 - read-write - - - RF1FF - Receive FIFO 1 full flag - 3 - 1 - read-write - - - RF1MN - Receive FIFO 1 message num - 0 - 2 - read-only - - - - - INTEN - INTEN - Interrupt enable register - 0x14 - 0x20 - read-write - 0x00000000 - - - EDZIEN - Enter doze mode interrupt enable - 17 - 1 - - - QDZIEN - Quit doze mode interrupt enable - 16 - 1 - - - EOIEN - Error occur interrupt enable - 15 - 1 - - - ETRIEN - Error type record interrupt enable - 11 - 1 - - - BOIEN - Bus-off interrupt enable - 10 - 1 - - - EPIEN - Error passive interrupt enable - 9 - 1 - - - EAIEN - Error active interrupt enable - 8 - 1 - - - RF1OIEN - Receive FIFO 1 overflow interrupt enable - 6 - 1 - - - RF1FIEN - Receive FIFO 1 full interrupt enable - 5 - 1 - - - RF1MIEN - FIFO 1 receive message interrupt enable - 4 - 1 - - - RF0OIEN - Receive FIFO 0 overflow interrupt enable - 3 - 1 - - - RF0FIEN - Receive FIFO 0 full interrupt enable - 2 - 1 - - - RF0MIEN - FIFO 0 receive message interrupt enable - 1 - 1 - - - TCIEN - Transmission complete interrupt enable - 0 - 1 - - - - - ESTS - ESTS - Error status register - 0x18 - 0x20 - 0x00000000 - - - REC - Receive error counter - 24 - 8 - read-only - - - TEC - Transmit error counter - 16 - 8 - read-only - - - ETR - Error type record - 4 - 3 - read-write - - - BOF - Bus-off flag - 2 - 1 - read-only - - - EPF - Error passive flag - 1 - 1 - read-only - - - EAF - Error active flag - 0 - 1 - read-only - - - - - BTMG - BTMG - Bit timing register - 0x1C - 0x20 - read-write - 0x00000000 - - - LOEN - Listen-Only mode - 31 - 1 - - - LBEN - Loop back mode - 30 - 1 - - - RSAW - Resynchronization adjust width - 24 - 2 - - - BTS2 - Bit time segment 2 - 20 - 3 - - - BTS1 - Bit time segment 1 - 16 - 4 - - - BRDIV - Baud rate division - 0 - 12 - - - - - TMI0 - TMI0 - Transmit mailbox 0 identifier register - 0x180 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC0 - TMC0 - Transmit mailbox 0 data length and time stamp register - 0x184 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL0 - TMDTL0 - Transmit mailbox 0 low byte data register - 0x188 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH0 - TMDTH0 - Transmit mailbox 0 high byte data register - 0x18C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI1 - TMI1 - Transmit mailbox 1 identifier register - 0x190 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC1 - TMC1 - Transmit mailbox 1 data length and time stamp register - 0x194 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL1 - TMDTL1 - Transmit mailbox 1 low byte data register - 0x198 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH1 - TMDTH1 - Transmit mailbox 1 high byte data register - 0x19C - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - TMI2 - TMI2 - Transmit mailbox 2 identifier register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - TMSID - Transmit mailbox standard identifier or extended identifier high bytes - 21 - 11 - - - TMEID - Ttransmit mailbox extended identifier - 3 - 18 - - - TMIDSEL - Transmit mailbox identifier type select - 2 - 1 - - - TMFRSEL - Transmit mailbox frame type select - 1 - 1 - - - TMSR - Transmit mailbox send request - 0 - 1 - - - - - TMC2 - TMC2 - Transmit mailbox 2 data length and time stamp register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - TMTS - Transmit mailbox time stamp - 16 - 16 - - - TMTSTEN - Transmit mailbox time stamp transmit enable - 8 - 1 - - - TMDTBL - Transmit mailbox data byte length - 0 - 4 - - - - - TMDTL2 - TMDTL2 - Transmit mailbox 2 low byte data register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - TMDT3 - Transmit mailbox data byte 3 - 24 - 8 - - - TMDT2 - Transmit mailbox data byte 2 - 16 - 8 - - - TMDT1 - Transmit mailbox data byte 1 - 8 - 8 - - - TMDT0 - Transmit mailbox data byte 0 - 0 - 8 - - - - - TMDTH2 - TMDTH2 - Transmit mailbox 2 high byte data register - 0x1AC - 0x20 - read-write - 0x00000000 - - - TMDT7 - Transmit mailbox data byte 7 - 24 - 8 - - - TMDT6 - Transmit mailbox data byte 6 - 16 - 8 - - - TMDT5 - Transmit mailbox data byte 5 - 8 - 8 - - - TMDT4 - Transmit mailbox data byte 4 - 0 - 8 - - - - - RFI0 - RFI0 - Receive FIFO 0 register - 0x1B0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC0 - RFC0 - Receive FIFO 0 data length and time stamp register - 0x1B4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL0 - RFDTL0 - Receive FIFO 0 low byte data register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH0 - RFDTH0 - Receive FIFO 0 high byte data register - 0x1BC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - RFI1 - RFI1 - Receive FIFO 1 register - 0x1C0 - 0x20 - read-only - 0x00000000 - - - RFSID - Receive FIFO standard identifier or receive FIFO extended identifier - 21 - 11 - - - RFEID - Receive FIFO extended identifier - 3 - 18 - - - RFIDI - Receive FIFO identifier type indication - 2 - 1 - - - RFFRI - Receive FIFO frame type indication - 1 - 1 - - - - - RFC1 - RFC1 - Receive FIFO 1 data length and time stamp register - 0x1C4 - 0x20 - read-only - 0x00000000 - - - RFTS - Receive FIFO time stamp - 16 - 16 - - - RFFMN - Receive FIFO filter match number - 8 - 8 - - - RFDTL - Receive FIFO data length - 0 - 4 - - - - - RFDTL1 - RFDTL1 - Receive FIFO 1 low byte data register - 0x1C8 - 0x20 - read-only - 0x00000000 - - - RFDT3 - Receive FIFO data byte 3 - 24 - 8 - - - RFDT2 - Receive FIFO data byte 2 - 16 - 8 - - - RFDT1 - Receive FIFO data byte 1 - 8 - 8 - - - RFDT0 - Receive FIFO data byte 0 - 0 - 8 - - - - - RFDTH1 - RFDTH1 - Receive FIFO 1 high byte data register - 0x1CC - 0x20 - read-only - 0x00000000 - - - RFDT7 - Receive FIFO data byte 7 - 24 - 8 - - - RFDT6 - Receive FIFO data byte 6 - 16 - 8 - - - RFDT5 - Receive FIFO data byte 5 - 8 - 8 - - - RFDT4 - Receive FIFO data byte 4 - 0 - 8 - - - - - FCTRL - FCTRL - Filter control register - 0x200 - 0x20 - read-write - 0x00000000 - - - FCS - Filters configure switch - 0 - 1 - - - - - FMCFG - FMCFG - Filter mode config register - 0x204 - 0x20 - read-write - 0x00000000 - - - FMSEL0 - Filter mode select - 0 - 1 - - - FMSEL1 - Filter mode select - 1 - 1 - - - FMSEL2 - Filter mode select - 2 - 1 - - - FMSEL3 - Filter mode select - 3 - 1 - - - FMSEL4 - Filter mode select - 4 - 1 - - - FMSEL5 - Filter mode select - 5 - 1 - - - FMSEL6 - Filter mode select - 6 - 1 - - - FMSEL7 - Filter mode select - 7 - 1 - - - FMSEL8 - Filter mode select - 8 - 1 - - - FMSEL9 - Filter mode select - 9 - 1 - - - FMSEL10 - Filter mode select - 10 - 1 - - - FMSEL11 - Filter mode select - 11 - 1 - - - FMSEL12 - Filter mode select - 12 - 1 - - - FMSEL13 - Filter mode select - 13 - 1 - - - FMSEL14 - Filter mode select - 14 - 1 - - - FMSEL15 - Filter mode select - 15 - 1 - - - FMSEL16 - Filter mode select - 16 - 1 - - - FMSEL17 - Filter mode select - 17 - 1 - - - FMSEL18 - Filter mode select - 18 - 1 - - - FMSEL19 - Filter mode select - 19 - 1 - - - FMSEL20 - Filter mode select - 20 - 1 - - - FMSEL21 - Filter mode select - 21 - 1 - - - FMSEL22 - Filter mode select - 22 - 1 - - - FMSEL23 - Filter mode select - 23 - 1 - - - FMSEL24 - Filter mode select - 24 - 1 - - - FMSEL25 - Filter mode select - 25 - 1 - - - FMSEL26 - Filter mode select - 26 - 1 - - - FMSEL27 - Filter mode select - 27 - 1 - - - - - FBWCFG - FBWCFG - Filter bit width config register - 0x20C - 0x20 - read-write - 0x00000000 - - - FBWSEL0 - Filter bit width select - 0 - 1 - - - FBWSEL1 - Filter bit width select - 1 - 1 - - - FBWSEL2 - Filter bit width select - 2 - 1 - - - FBWSEL3 - Filter bit width select - 3 - 1 - - - FBWSEL4 - Filter bit width select - 4 - 1 - - - FBWSEL5 - Filter bit width select - 5 - 1 - - - FBWSEL6 - Filter bit width select - 6 - 1 - - - FBWSEL7 - Filter bit width select - 7 - 1 - - - FBWSEL8 - Filter bit width select - 8 - 1 - - - FBWSEL9 - Filter bit width select - 9 - 1 - - - FBWSEL10 - Filter bit width select - 10 - 1 - - - FBWSEL11 - Filter bit width select - 11 - 1 - - - FBWSEL12 - Filter bit width select - 12 - 1 - - - FBWSEL13 - Filter bit width select - 13 - 1 - - - FBWSEL14 - Filter bit width select - 14 - 1 - - - FBWSEL15 - Filter bit width select - 15 - 1 - - - FBWSEL16 - Filter bit width select - 16 - 1 - - - FBWSEL17 - Filter bit width select - 17 - 1 - - - FBWSEL18 - Filter bit width select - 18 - 1 - - - FBWSEL19 - Filter bit width select - 19 - 1 - - - FBWSEL20 - Filter bit width select - 20 - 1 - - - FBWSEL21 - Filter bit width select - 21 - 1 - - - FBWSEL22 - Filter bit width select - 22 - 1 - - - FBWSEL23 - Filter bit width select - 23 - 1 - - - FBWSEL24 - Filter bit width select - 24 - 1 - - - FBWSEL25 - Filter bit width select - 25 - 1 - - - FBWSEL26 - Filter bit width select - 26 - 1 - - - FBWSEL27 - Filter bit width select - 27 - 1 - - - - - FRF - FRF - Filter related FIFO register - 0x214 - 0x20 - read-write - 0x00000000 - - - FRFSEL0 - Filter relation FIFO select - 0 - 1 - - - FRFSEL1 - Filter relation FIFO select - 1 - 1 - - - FRFSEL2 - Filter relation FIFO select - 2 - 1 - - - FRFSEL3 - Filter relation FIFO select - 3 - 1 - - - FRFSEL4 - Filter relation FIFO select - 4 - 1 - - - FRFSEL5 - Filter relation FIFO select - 5 - 1 - - - FRFSEL6 - Filter relation FIFO select - 6 - 1 - - - FRFSEL7 - Filter relation FIFO select - 7 - 1 - - - FRFSEL8 - Filter relation FIFO select - 8 - 1 - - - FRFSEL9 - Filter relation FIFO select - 9 - 1 - - - FRFSEL10 - Filter relation FIFO select - 10 - 1 - - - FRFSEL11 - Filter relation FIFO select - 11 - 1 - - - FRFSEL12 - Filter relation FIFO select - 12 - 1 - - - FRFSEL13 - Filter relation FIFO select - 13 - 1 - - - FRFSEL14 - Filter relation FIFO select - 14 - 1 - - - FRFSEL15 - Filter relation FIFO select - 15 - 1 - - - FRFSEL16 - Filter relation FIFO select - 16 - 1 - - FRFSEL17 - Filter relation FIFO select - 17 - 1 - - - FRFSEL18 - Filter relation FIFO select - 18 - 1 - - - FRFSEL19 - Filter relation FIFO select - 19 - 1 - - - FRFSEL20 - Filter relation FIFO select - 20 - 1 - - - FRFSEL21 - Filter relation FIFO select - 21 - 1 - - - FRFSEL22 - Filter relation FIFO select - 22 - 1 - - - FRFSEL23 - Filter relation FIFO select - 23 - 1 - - - FRFSEL24 - Filter relation FIFO select - 24 - 1 - - - FRFSEL25 - Filter relation FIFO select - 25 - 1 - - - FRFSEL26 - Filter relation FIFO select - 26 - 1 - - - FRFSEL27 - Filter relation FIFO select - 27 - 1 - - - - - FACFG - FACFG - Filter activate configuration register - 0x21C - 0x20 - read-write - 0x00000000 - - - FAEN0 - Filter activate enable - 0 - 1 - - - FAEN1 - Filter activate enable - 1 - 1 - - - FAEN2 - Filter activate enable - 2 - 1 - - - FAEN3 - Filter activate enable - 3 - 1 - - - FAEN4 - Filter activate enable - 4 - 1 - - - FAEN5 - Filter activate enable - 5 - 1 - - - FAEN6 - Filter activate enable - 6 - 1 - - - FAEN7 - Filter activate enable - 7 - 1 - - - FAEN8 - Filter activate enable - 8 - 1 - - - FAEN9 - Filter activate enable - 9 - 1 - - - FAEN10 - Filter activate enable - 10 - 1 - - - FAEN11 - Filter activate enable - 11 - 1 - - - FAEN12 - Filter activate enable - 12 - 1 - - - FAEN13 - Filter activate enable - 13 - 1 - - - FAEN14 - Filter activate enable - 14 - 1 - - FAEN15 - Filter activate enable - 15 - 1 - - - FAEN16 - Filter activate enable - 16 - 1 - - - FAEN17 - Filter activate enable - 17 - 1 - - - FAEN18 - Filter activate enable - 18 - 1 - - - FAEN19 - Filter activate enable - 19 - 1 - - - FAEN20 - Filter activate enable - 20 - 1 - - - FAEN21 - Filter activate enable - 21 - 1 - - - FAEN22 - Filter activate enable - 22 - 1 - - - FAEN23 - Filter activate enable - 23 - 1 - - - FAEN24 - Filter activate enable - 24 - 1 - - - FAEN25 - Filter activate enable - 25 - 1 - - - FAEN26 - Filter activate enable - 26 - 1 - - - FAEN27 - Filter activate enable - 27 - 1 - - - - - F0FB1 - F0FB1 - Filter bank 0 filtrate bit register 1 - 0x240 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F0FB2 - F0FB2 - Filter bank 0 filtrate bit register 2 - 0x244 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB1 - F1FB1 - Filter bank 1 filtrate bit register 1 - 0x248 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F1FB2 - F1FB2 - Filter bank 1 filtrate bit register 2 - 0x24C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB1 - F2FB1 - Filter bank 2 filtrate bit register 1 - 0x250 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F2FB2 - F2FB2 - Filter bank 2 filtrate bit register 2 - 0x254 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB1 - F3FB1 - Filter bank 3 filtrate bit register 1 - 0x258 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F3FB2 - F3FB2 - Filter bank 3 filtrate bit register 2 - 0x25C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB1 - F4FB1 - Filter bank 4 filtrate bit register 1 - 0x260 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F4FB2 - F4FB2 - Filter bank 4 filtrate bit register 2 - 0x264 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB1 - F5FB1 - Filter bank 5 filtrate bit register 1 - 0x268 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F5FB2 - F5FB2 - Filter bank 5 filtrate bit register 2 - 0x26C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB1 - F6FB1 - Filter bank 6 filtrate bit register 1 - 0x270 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F6FB2 - F6FB2 - Filter bank 6 filtrate bit register 2 - 0x274 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - F7FB1 - F7FB1 - Filter bank 7 filtrate bit register 1 - 0x278 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F7FB2 - F7FB2 - Filter bank 7 filtrate bit register 2 - 0x27C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB1 - F8FB1 - Filter bank 8 filtrate bit register 1 - 0x280 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F8FB2 - F8FB2 - Filter bank 8 filtrate bit register 2 - 0x284 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB1 - F9FB1 - Filter bank 9 filtrate bit register 1 - 0x288 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F9FB2 - F9FB2 - Filter bank 9 filtrate bit register 2 - 0x28C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB1 - F10FB1 - Filter bank 10 filtrate bit register 1 - 0x290 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F10FB2 - F10FB2 - Filter bank 10 filtrate bit register 2 - 0x294 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB1 - F11FB1 - Filter bank 11 filtrate bit register 1 - 0x298 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F11FB2 - F11FB2 - Filter bank 11 filtrate bit register 2 - 0x29C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB1 - F12FB1 - Filter bank 12 filtrate bit register 1 - 0x2A0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F12FB2 - F12FB2 - Filter bank 12 filtrate bit register 2 - 0x2A4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB1 - F13FB1 - Filter bank 13 filtrate bit register 1 - 0x2A8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F13FB2 - F13FB2 - Filter bank 13 filtrate bit register 2 - 0x2AC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F14FB1 - F14FB1 - Filter bank 14 filtrate bit register 1 - 0x2B0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F14FB2 - F14FB2 - Filter bank 14 filtrate bit register 2 - 0x2B4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F15FB1 - F15FB1 - Filter bank 15 filtrate bit register 1 - 0x2B8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F15FB2 - F15FB2 - Filter bank 15 filtrate bit register 2 - 0x2BC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F16FB1 - F16FB1 - Filter bank 16 filtrate bit register 1 - 0x2C0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F16FB2 - F16FB2 - Filter bank 16 filtrate bit register 2 - 0x2C4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F17FB1 - F17FB1 - Filter bank 17 filtrate bit register 1 - 0x2C8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F17FB2 - F17FB2 - Filter bank 17 filtrate bit register 2 - 0x2CC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F18FB1 - F18FB1 - Filter bank 18 filtrate bit register 1 - 0x2D0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F18FB2 - F18FB2 - Filter bank 18 filtrate bit register 2 - 0x2D4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F19FB1 - F19FB1 - Filter bank 19 filtrate bit register 1 - 0x2D8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F19FB2 - F19FB2 - Filter bank 19 filtrate bit register 2 - 0x2DC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F20FB1 - F20FB1 - Filter bank 20 filtrate bit register 1 - 0x2E0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F20FB2 - F20FB2 - Filter bank 20 filtrate bit register 2 - 0x2E4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F21FB1 - F21FB1 - Filter bank 21 filtrate bit register 1 - 0x2E8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F21FB2 - F21FB2 - Filter bank 21 filtrate bit register 2 - 0x2EC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F22FB1 - F22FB1 - Filter bank 22 filtrate bit register 1 - 0x2F0 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F22FB2 - F22FB2 - Filter bank 22 filtrate bit register 2 - 0x2F4 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F23FB1 - F23FB1 - Filter bank 23 filtrate bit register 1 - 0x2F8 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F23FB2 - F23FB2 - Filter bank 23 filtrate bit register 2 - 0x2FC - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F24FB1 - F24FB1 - Filter bank 24 filtrate bit register 1 - 0x300 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F24FB2 - F24FB2 - Filter bank 24 filtrate bit register 2 - 0x304 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F25FB1 - F25FB1 - Filter bank 25 filtrate bit register 1 - 0x308 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F25FB2 - F25FB2 - Filter bank 25 filtrate bit register 2 - 0x30C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F26FB1 - F26FB1 - Filter bank 26 filtrate bit register 1 - 0x310 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F26FB2 - F26FB2 - Filter bank 26 filtrate bit register 2 - 0x314 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F27FB1 - F27FB1 - Filter bank 27 filtrate bit register 1 - 0x318 - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - F27FB2 - F27FB2 - Filter bank 27 filtrate bit register 2 - 0x31C - 0x20 - read-write - 0x00000000 - - - FFDB0 - Filter data bit - 0 - 1 - - - FFDB1 - Filter data bit - 1 - 1 - - - FFDB2 - Filter data bit - 2 - 1 - - - FFDB3 - Filter data bit - 3 - 1 - - - FFDB4 - Filter data bit - 4 - 1 - - - FFDB5 - Filter data bit - 5 - 1 - - - FFDB6 - Filter data bit - 6 - 1 - - - FFDB7 - Filter data bit - 7 - 1 - - - FFDB8 - Filter data bit - 8 - 1 - - - FFDB9 - Filter data bit - 9 - 1 - - - FFDB10 - Filter data bit - 10 - 1 - - - FFDB11 - Filter data bit - 11 - 1 - - - FFDB12 - Filter data bit - 12 - 1 - - - FFDB13 - Filter data bit - 13 - 1 - - - FFDB14 - Filter data bit - 14 - 1 - - - FFDB15 - Filter data bit - 15 - 1 - - - FFDB16 - Filter data bit - 16 - 1 - - - FFDB17 - Filter data bit - 17 - 1 - - - FFDB18 - Filter data bit - 18 - 1 - - - FFDB19 - Filter data bit - 19 - 1 - - - FFDB20 - Filter data bit - 20 - 1 - - - FFDB21 - Filter data bit - 21 - 1 - - - FFDB22 - Filter data bit - 22 - 1 - - - FFDB23 - Filter data bit - 23 - 1 - - - FFDB24 - Filter data bit - 24 - 1 - - - FFDB25 - Filter data bit - 25 - 1 - - - FFDB26 - Filter data bit - 26 - 1 - - - FFDB27 - Filter data bit - 27 - 1 - - - FFDB28 - Filter data bit - 28 - 1 - - - FFDB29 - Filter data bit - 29 - 1 - - - FFDB30 - Filter data bit - 30 - 1 - - - FFDB31 - Filter data bit - 31 - 1 - - - - - - - CAN2 - 0x40006800 - - CAN2_TX - CAN2 TX interrupt - 63 - - - CAN2_RX0 - CAN2 RX0 interrupt - 64 - - - CAN2_RX1 - CAN2 RX1 interrupt - 65 - - - CAN2_SE - CAN2 SE interrupt - 66 - - - - DAC - Digital to analog converter - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - - CTRL - CTRL - Control register (DAC_CTRL) - 0x0 - 0x20 - read-write - 0x00000000 - - - D1EN - DAC1 enable - 0 - 1 - - - D1OBDIS - DAC1 output buffer disable - 1 - 1 - - - D1TRGEN - DAC1 trigger enable - 2 - 1 - - - D1TRGSEL - DAC1 trigger selection - 3 - 3 - - - D1NM - DAC1 noise/triangle wave generation enable - 6 - 2 - - - D1NBSEL - DAC1 mask/amplitude selector - 8 - 4 - - - D1DMAEN - DAC1 DMA enable - 12 - 1 - - - D1DMAUDRIEN - DAC1 DMA underrun interrupt enable - 13 - 1 - - - D2EN - DAC2 enable - 16 - 1 - - - D2OBDIS - DAC2 output buffer disable - 17 - 1 - - - D2TRGEN - DAC2 trigger enable - 18 - 1 - - - D2TRGSEL - DAC2 trigger selection - 19 - 3 - - - D2NM - DAC2 noise/triangle wave generation enable - 22 - 2 - - - D2NBSEL - DAC2 mask/amplitude selector - 24 - 4 - - - D2DMAEN - DAC2 DMA enable - 28 - 1 - - - D2DMAUDRIEN - DAC2 DMA underrun interrupt enable - 29 - 1 - - - - - SWTRG - SWTRG - DAC software trigger register(DAC_SWTRIGR) - 0x4 - 0x20 - write-only - 0x00000000 - - - D1SWTRG - DAC1 software trigger - 0 - 1 - - - D2SWTRG - DAC2 software trigger - 1 - 1 - - - - - D1DTH12R - D1DTH12R - DAC1 12-bit right-aligned data holding register(DAC_D1DTH12R) - 0x8 - 0x20 - read-write - 0x00000000 - - - D1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - - - D1DTH12L - D1DTH12L - DAC1 12-bit left aligned data holding register (DAC_D1DTH12L) - 0xC - 0x20 - read-write - 0x00000000 - - - D1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - - - D1DTH8R - D1DTH8R - DAC1 8-bit right aligned data holding register (DAC_D1DTH8R) - 0x10 - 0x20 - read-write - 0x00000000 - - - D1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - - - D2DTH12R - D2DTH12R - DAC2 12-bit right aligned data holding register (DAC_D2DTH12R) - 0x14 - 0x20 - read-write - 0x00000000 - - - D2DT12R - DAC2 12-bit right-aligned - data - 0 - 12 - - - - - D2DTH12L - D2DTH12L - DAC2 12-bit left aligned data holding register (DAC_D2DTH12L) - 0x18 - 0x20 - read-write - 0x00000000 - - - D2DT12L - DAC2 12-bit left-aligned data - 4 - 12 - - - - - D2DTH8R - D2DTH8R - DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) - 0x1C - 0x20 - read-write - 0x00000000 - - - D2DT8R - DAC2 8-bit right-aligned - data - 0 - 8 - - - - - DDTH12R - DDTH12R - Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R), Bits 31:28 Reserved, Bits 15:12 Reserved - 0x20 - 0x20 - read-write - 0x00000000 - - - DD1DT12R - DAC1 12-bit right-aligned data - 0 - 12 - - - DD2DT12R - DAC2 12-bit right-aligned data - 16 - 12 - - - - - DDTH12L - DDTH12L - DUAL DAC 12-bit left aligned data holding register (DAC_DDTH12L), Bits 19:16 Reserved, Bits 3:0 Reserved - 0x24 - 0x20 - read-write - 0x00000000 - - - DD1DT12L - DAC1 12-bit left-aligned data - 4 - 12 - - - DD2DT12L - DAC2 12-bit right-aligned data - 20 - 12 - - - - - DDTH8R - DDTH8R - DUAL DAC 8-bit right aligned data holding register (DAC_DDTH8R), Bits 31:16 Reserved - 0x28 - 0x20 - read-write - 0x00000000 - - - DD1DT8R - DAC1 8-bit right-aligned data - 0 - 8 - - - DD2DT8R - DAC2 8-bit right-aligned data - 8 - 8 - - - - - D1ODT - D1ODT - DAC1 data output register (DAC_D1ODT) - 0x2C - 0x20 - read-only - 0x00000000 - - - D1ODT - DAC1 data output - 0 - 12 - - - - - D2ODT - D2ODT - DAC2 data output register (DAC_D2ODT) - 0x30 - 0x20 - read-only - 0x00000000 - - - D2ODT - DAC2 data output - 0 - 12 - - - - - STS - STS - DAC2 status register - (DAC_STS) - 0x34 - 0x20 - read-write - 0x00000000 - - - DMAUDR1 - DAC1 DMA underrun flag - 13 - 1 - - - DMAUDR2 - DAC2 DMA underrun flag - 29 - 1 - - - - - - - DEBUG - Debug support - DEBUG - 0xE0042000 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - DEBUG IDCODE - 0x0 - 0x20 - read-only - 0x0 - - - PID - Product ID - 0 - 32 - - - - - CTRL - CTRL - DEBUG CTRL - 0x4 - 0x20 - read-write - 0x0 - - - SLEEP_DEBUG - SLEEP_DEBUG - 0 - 1 - - - DEEPSLEEP_DEBUG - DEEPSLEEP_DEBUG - 1 - 1 - - - STANDBY_DEBUG - STANDBY_DEBUG - 2 - 1 - - - - - APB1_PAUSE - APB1_PAUSE - DEBUG APB1 PAUSE - 0x8 - 0x20 - read-write - 0x0 - - - TMR2_PAUSE - TMR2_PAUSE - 0 - 1 - - - TMR3_PAUSE - TMR3_PAUSE - 1 - 1 - - - TMR4_PAUSE - TMR4_PAUSE - 2 - 1 - - - TMR5_PAUSE - TMR5_PAUSE - 3 - 1 - - - TMR6_PAUSE - TMR6_PAUSE - 4 - 1 - - - TMR7_PAUSE - TMR7_PAUSE - 5 - 1 - - - TMR12_PAUSE - TMR12_PAUSE - 6 - 1 - - - TMR13_PAUSE - TMR13_PAUSE - 7 - 1 - - - TMR14_PAUSE - TMR14_PAUSE - 8 - 1 - - - ERTC_PAUSE - ERTC_PAUSE - 10 - 1 - - - WWDT_PAUSE - WWDT_PAUSE - 11 - 1 - - - WDT_PAUSE - WDT_PAUSE - 12 - 1 - - - ERTC512_PAUSE - ERTC512_PAUSE - 15 - 1 - - - I2C1_SMBUS_TIMEOUT - I2C1_SMBUS_TIMEOUT - 24 - 1 - - - CAN1_PAUSE - CAN1_PAUSE - 25 - 1 - - - CAN2_PAUSE - CAN2_PAUSE - 26 - 1 - - - I2C2_SMBUS_TIMEOUT - I2C2_SMBUS_TIMEOUT - 27 - 1 - - - I2C3_SMBUS_TIMEOUT - I2C3_SMBUS_TIMEOUT - 28 - 1 - - - - - APB2_PAUSE - APB2_PAUSE - DEBUG APB2 PAUSE - 0xC - 0x20 - read-write - 0x0 - - - TMR1_PAUSE - TMR1_PAUSE - 0 - 1 - - - TMR8_PAUSE - TMR8_PAUSE - 1 - 1 - - - TMR20_PAUSE - TIM20_PAUSE - 6 - 1 - - - TMR9_PAUSE - TMR9_PAUSE - 16 - 1 - - - TMR10_PAUSE - TMR10_PAUSE - 17 - 1 - - - TMR11_PAUSE - TMR11_PAUSE - 18 - 1 - - - - - SER_ID - SER_ID - SERIES ID - 0x20 - 0x20 - read-only - 0x0 - - - REV_ID - version ID - 0 - 3 - - - SER_ID - series ID - 8 - 8 - - - - - - - UART4 - Universal asynchronous receiver transmitter - 0x40004C00 - - UART4 - UART4 global interrupt - 52 - - - - UART5 - Universal asynchronous receiver transmitter - 0x40005000 - - UART5 - UART5 global interrupt - 53 - - - - UART7 - Universal asynchronous receiver transmitter - 0x40007800 - - UART7 - UART7 global interrupt - 82 - - - - UART8 - Universal asynchronous receiver transmitter - 0x40007C00 - - UART8 - UART8 global interrupt - 83 - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DT - DT - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DT - Data Register - 0 - 32 - - - - - CDT - CDT - Common data register - 0x4 - 0x20 - read-write - 0x00000000 - - - CDT - Common Data - 0 - 1 - - - - - CTRL - CTRL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - Reset bit - 0 - 1 - - - REVID - Reverse input data - 5 - 2 - - - REVOD - Reverse output data - 7 - 1 - - - - - IDT - IDT - Initial data register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDT - Initial Data - 0 - 32 - - - - - - - FLASH - Flash memory controler - FLASH - 0x40023C00 - - 0x0 - 0x400 - registers - - - FLASH - Flash global interrupt - 4 - - - - PSR - PSR - Performance selection register - 0x0 - 0x20 - 0x00000330 - - - NZW_BST_STS - Flash non-zero wait area boost status - 13 - 1 - read-only - - - NZW_BST - Flash non-zero wait area boost - 12 - 1 - read-write - - - - - UNLOCK - UNLOCK - Unlock register - 0x4 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - USD_UNLOCK - USD_UNLOCK - USD unlock register - 0x8 - 0x20 - write-only - 0x00000000 - - - USD_UKVAL - User system data Unlock key value - 0 - 32 - - - - - STS - STS - Status register - 0xC - 0x20 - 0x00000000 - - - ODF - Operate done flag - 5 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - PRGMERR - program error - 2 - 1 - read-write - - - OBF - Operate busy flag - 0 - 1 - read-only - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - USDPRGM - User system data program - 4 - 1 - - - USDERS - User system data erase - 5 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - USDULKS - User system data unlock success - 9 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - USD - USD - User system data register - 0x1C - 0x20 - read-only - 0x03FFFFFC - - - USDERR - User system data error - 0 - 1 - - - FAP - FLASH access protection - 1 - 1 - - - nWDT_ATO_EN - WDT auto enable - 2 - 1 - - - nDEPSLP_RST - Deepsleep reset - 3 - 1 - - - nSTDBY_RST - Standby reset - 4 - 1 - - - BTOPT - boot option - 5 - 1 - - - nWDT_DEPSLP - WDT deep sleep - 7 - 1 - - - nWDT_STDBY - WDT standby - 8 - 1 - - - USER_D0 - User data 0 - 10 - 8 - - - USER_D1 - User data 1 - 18 - 8 - - - - - EPPS0 - EPPS0 - Erase/program protection status register 0 - 0x20 - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - EPPS1 - EPPS1 - Erase/program protection status register 1 - 0x2C - 0x20 - read-only - 0xFFFFFFFF - - - EPPS - Erase/program protection status - 0 - 32 - - - - - UNLOCK2 - UNLOCK2 - Unlock 2 register - 0x44 - 0x20 - write-only - 0x00000000 - - - UKVAL - Unlock key value - 0 - 32 - - - - - STS2 - STS2 - Status 2 register - 0x4C - 0x20 - 0x00000000 - - - OBF - Operate busy flag - 0 - 1 - read-only - - - PRGMERR - program error - 2 - 1 - read-write - - - EPPERR - Erase/program protection error - 4 - 1 - read-write - - - ODF - Operate done flag - 5 - 1 - read-write - - - - - CTRL2 - CTRL2 - Control 2 register - 0x50 - 0x20 - read-write - 0x00000080 - - - FPRGM - Flash program - 0 - 1 - - - SECERS - Sector erase - 1 - 1 - - - BANKERS - Bank erase - 2 - 1 - - - BLKERS - Block erase - 3 - 1 - - - ERSTR - Erasing start - 6 - 1 - - - OPLK - Operation lock - 7 - 1 - - - ERRIE - Error interrupt enable - 10 - 1 - - - ODFIE - Operation done flag interrupt enable - 12 - 1 - - - - - ADDR2 - ADDR2 - Address 2 register - 0x54 - 0x20 - write-only - 0x00000000 - - - FA - Flash Address - 0 - 32 - - - - - CONTR - CONTR - Flash continue read register - 0x58 - 0x20 - read-write - 0x00000080 - - - FCONTR_EN - Flash continue read enable - 31 - 1 - - - - - DIVR - DIVR - Flash divider register - 0x60 - 0x20 - 0x00000022 - - - FDIV - Flash divider - 0 - 2 - read-write - - - FDIV_STS - Flash divider status - 4 - 2 - read-only - - - - - SLIB_STS2 - SLIB_STS2 - sLib status 2 register - 0xC8 - 0x20 - 0x0000FFFF - - - SLIB_INST_SS - sLib instruction start sector - 0 - 16 - read-only - - - - - SLIB_STS0 - SLIB_STS0 - sLib status 0 register - 0xCC - 0x20 - 0x00000000 - - - SLIB_ENF - sLib enabled flag - 3 - 1 - read-only - - - - - SLIB_STS1 - SLIB_STS1 - sLib status 1 register - 0xD0 - 0x20 - 0xFFFFFFFF - - - SLIB_SS - sLib start sector - 0 - 16 - read-only - - - SLIB_ES - sLib end sector - 16 - 16 - read-only - - - - - SLIB_PWD_CLR - SLIB_PWD_CLR - SLIB password clear register - 0xD4 - 0x20 - 0x00000000 - write-only - - - SLIB_PCLR_VAL - sLib password clear value - 0 - 32 - - - - - SLIB_MISC_STS - SLIB_MISC_STS - sLib misc status register - 0xD8 - 0x20 - 0x01000000 - - - SLIB_PWD_ERR - sLib password error - 0 - 1 - read-only - - - SLIB_PWD_OK - sLib password ok - 1 - 1 - read-only - - - SLIB_ULKF - sLib unlock flag - 2 - 1 - read-only - - - SLIB_RCNT - sLib remaining count - 16 - 9 - read-only - - - - - SLIB_SET_PWD - SLIB_SET_PWD - sLib password setting register - 0xDC - 0x20 - 0x00000000 - write-only - - - SLIB_PSET_VAL - sLib password setting val - 0 - 32 - - - - - SLIB_SET_RANGE0 - SLIB_SET_RANGE0 - Configure sLib range register 0 - 0xE0 - 0x20 - 0x00000000 - write-only - - - SLIB_SS_SET - sLib start sector setting - 0 - 16 - - - SLIB_ES_SET - sLib end sector setting - 16 - 16 - - - - - SLIB_SET_RANGE1 - SLIB_SET_RANGE1 - Configure sLib range register 1 - 0xE4 - 0x20 - 0x00000000 - write-only - - - SLIB_ISS_SET - sLib instruction start sector setting - 0 - 16 - - - SET_SLIB_STRT - sLib start setting - 31 - 1 - - - - - SLIB_UNLOCK - SLIB_UNLOCK - sLib unlock register - 0xF0 - 0x20 - 0x00000000 - write-only - - - SLIB_UKVAL - sLib unlock key value - 0 - 32 - - - - - CRC_CTRL - CRC_CTRL - CRC controler register - 0xF4 - 0x20 - 0x00000000 - write-only - - - CRC_SS - CRC start sector - 0 - 12 - - - CRC_SN - CRC sector numbler - 12 - 12 - - - CRC_STRT - CRC start - 31 - 1 - - - - - CRC_CHKR - CRC_CHKR - CRC check result register - 0xF8 - 0x20 - 0x00000000 - read-only - - - CRC_CHKR - CRC check result - 0 - 32 - - - - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E000 - - 0x0 - 0x1001 - registers - - - - ICTR - ICTR - Interrupt Controller Type - Register - 0x4 - 0x20 - read-only - 0x00000000 - - - INTLINESNUM - Total number of interrupt lines in - groups - 0 - 4 - - - - - STIR - STIR - Software Triggered Interrupt - Register - 0xF00 - 0x20 - write-only - 0x00000000 - - - INTID - interrupt to be triggered - 0 - 9 - - - - - ISER0 - ISER0 - Interrupt Set-Enable Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set-Enable Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear-Enable - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear-Enable - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x200 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x204 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active Bit Register - 0x300 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active Bit Register - 0x304 - 0x20 - read-only - 0x00000000 - - - ACTIVE - ACTIVE - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register - 0x400 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register - 0x404 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register - 0x408 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register - 0x40C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register - 0x410 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register - 0x414 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register - 0x418 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register - 0x41C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register - 0x420 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register - 0x424 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register - 0x428 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register - 0x42C - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register - 0x430 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register - 0x434 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register - 0x438 - 0x20 - read-write - 0x00000000 - - - IPR_N0 - IPR_N0 - 0 - 8 - - - IPR_N1 - IPR_N1 - 8 - 8 - - - IPR_N2 - IPR_N2 - 16 - 8 - - - IPR_N3 - IPR_N3 - 24 - 8 - - - - - - - DVP - Digital video parallel interface - DVP - 0x50050000 - - 0x0 - 0x400 - registers - - - DVP - DVP global interrupt - 78 - - - - CTRL - CTRL - Control register - 0x0 - 0x20 - 0x0000 - - - LCDS - Line capture/drop selection - 20 - 1 - read-write - - - LCDC - Line capture/drop control - - 19 - 1 - read-write - - - PCDS - Pixel capture/drop selection - - 18 - 1 - read-write - - - PCDC - Basic pixel capture/drop control - - 16 - 2 - read-write - - - ENA - DVP enable - 14 - 1 - read-write - - - PDL - Pixel data length - 10 - 2 - read-write - - - BFRC - Basic frame rate control - 8 - 2 - read-write - - - VSP - Vertical synchronization - polarity - 7 - 1 - read-write - - - HSP - Horizontal synchronization polarity - - 6 - 1 - read-write - - - CKP - Pixel clock polarity - 5 - 1 - read-write - - - SM - synchronization mode - 4 - 1 - read-write - - - JPEG - JPEG format - 3 - 1 - read-write - - - CRP - Cropping function enable - 2 - 1 - read-write - - - CFM - Capture fire mode - 1 - 1 - read-write - - - CAP - Capture function enable - 0 - 1 - read-write - - - - - STS - STS - status register - 0x4 - 0x20 - read-only - 0x0000 - - - OFNE - Output FIFO Non-empty - 2 - 1 - - - VSYN - Vertical synchronization status - 1 - 1 - - - HSYN - Horizontal synchronization status - 0 - 1 - - - - - ESTS - ESTS - Event status register - 0x8 - 0x20 - read-only - 0x0000 - - - HSES - Horizontal synchronization event status - 4 - 1 - - - VSES - Vertical synchronization event status - 3 - 1 - - - ESEES - Embedded synchronization error event status - - 2 - 1 - - - OVRES - Data FIFO overrun event status - - 1 - 1 - - - CFDES - Capture frame done event status - - 0 - 1 - - - - - IENA - IENA - interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - HSIE - Horizontal synchronization interrupt enable - - 4 - 1 - - - VSIE - Vertical synchronization interrupt enablee - - 3 - 1 - - - ESEIE - Embedded synchronization error interrupt - enable - 2 - 1 - - - OVRIE - Data FIFO overrun interrupt enable - - 1 - 1 - - - CFDIE - Capture frame done interrupt enable - - 0 - 1 - - - - - ISTS - ISTS - Interrupt status register - 0x10 - 0x20 - read-only - 0x0000 - - - HSIS - Horizontal synchronization interrupt - status - 4 - 1 - - - VSIS - Vertical synchronization interrupt - status - 3 - 1 - - - ESEIS - Embedded synchronization error - interrupt status - 2 - 1 - - - OVRIS - Data FIFO overrun interrupt - status - 1 - 1 - - - CFDIS - Capture frame done interrupt - status - 0 - 1 - - - - - ICLR - ICLR - Interrupt clear register - 0x14 - 0x20 - write-only - 0x0000 - - - HSIC - Horizontal synchronization - interrupt clear - 4 - 1 - - - VSIC - Vertical synchronization - interrupt clear - 3 - 1 - - - ESEIC - Embedded synchronization - error interrupt clear - 2 - 1 - - - OVRIC - Data FIFO overrun - interrupt clear - 1 - 1 - - - CFDIC - Capture frame done - interrupt clear - 0 - 1 - - - - - SCR - SCR - Synchronization code - register - 0x18 - 0x20 - read-write - 0x0000 - - - FMEC - Frame end code - 24 - 8 - - - LNEC - Line end code - 16 - 8 - - - LNSC - Line start code - 8 - 8 - - - FMSC - Frame start code - 0 - 8 - - - - - SUR - SUR - Synchronization unmask - register - 0x1C - 0x20 - read-write - 0x0000 - - - FMEU - Frame end unmask - 24 - 8 - - - LNEU - Line end unmask - 16 - 8 - - - LNSU - Line start unmask - - 8 - 8 - - - FMSU - Frame start unmask - - 0 - 8 - - - - - CWST - CWST - Crop window start - 0x20 - 0x20 - read-write - 0x0000 - - - CVSTR - Cropping window vertical start line - - 16 - 13 - - - CHSTR - Cropping window horizontal start pixel - - 0 - 14 - - - - - CWSZ - CWSZ - Crop window size - 0x24 - 0x20 - read-write - 0x0000 - - - CVNUM - Cropping window vertical line number - - 16 - 14 - - - CHNUM - Cropping window horizontal pixel number - - 0 - 14 - - - - - DT - DT - Data register - 0x28 - 0x20 - read-only - 0x0000 - - - DT - Data Port - 0 - 32 - - - - - ACTRL - ACTRL - Advanced Control register - - 0x40 - 0x20 - read-write - 0x0000 - - - VSEID - Vertical synchonization event and interrupt - definition - 17 - 1 - - - HSEID - Horizontal synchonization event and interrupt - definition - 16 - 1 - - - DMABT - DMA burst transfer configuration - - 12 - 1 - - - IDUS - Input data un-used setting - - 10 - 1 - - - IDUN - Input data un-used number - - 8 - 2 - - - EFDM - Enhanced function data format management - - 6 - 1 - - - EFDF - Enhanced function data format - - 4 - 2 - - - PCDES - Basic pixel capture/drop extended - selection - 3 - 1 - - - MIBE - Monochrome image binarization - enable - 2 - 1 - - - EFRCE - Enhanced frame rate control - enable - 1 - 1 - - - EISRE - Enhanced image scaling resize - enable - 0 - 1 - - - - - HSCF - HSCF - Horizontal scaling control flow - - 0x48 - 0x20 - read-write - 0x0000 - - - HSRTF - Horizontal scaling resize target factor - - 16 - 13 - - - HSRSF - Horizontal scaling resize source factor - - 0 - 13 - - - - - VSCF - VSCF - Vertical scaling control flow - - 0x4C - 0x20 - read-write - 0x0000 - - - VSRTF - Vertical scaling resize target factor - - 16 - 13 - - - VSRSF - Vertical scaling resize source factor - - 0 - 13 - - - - - FRF - FRF - Frame rate flow - - 0x50 - 0x20 - read-write - 0x0000 - - - EFRCTF - Enhanced frame rate control target factor - - 8 - 5 - - - EFRCSF - Enhanced frame rate contorl source factor - - 0 - 5 - - - - - BTH - BTH - Binarization threshold - - 0x54 - 0x20 - read-write - 0x0000 - - - MIBTHD - Monochrome image binarization threshold - - 0 - 8 - - - - - - - USB_OTG1_GLOBAL - USB on-the-go full speed - USB_OTG1 - 0x50000000 - - 0x0 - 0x400 - registers - - - OTGFS1 - USB On The Go FS global - interrupt - 67 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-write - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG1_HOST - USB on the go full speed - USB_OTG1 - 0x50000400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG1_DEVICE - USB on the go full speed - USB_OTG1 - 0x50000800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG1_PWRCLK - USB on the go full speed - USB_OTG1 - 0x50000E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - USB_OTG2_GLOBAL - USB on the go full speed - USB_OTG2 - 0x40040000 - - 0x0 - 0x400 - registers - - - OTGFS2 - USB On The Go FS2 global - interrupt - 77 - - - - GOTGCTL - GOTGCTL - OTGFS control and status register - (OTGFS_GOTGCTL) - 0x0 - 0x20 - 0x00000800 - - - CONIDSTS - Connector ID status - 16 - 1 - read-only - - - CURMOD - Current Mode of Operation - 21 - 1 - read-only - - - - - GOTGINT - GOTGINT - OTGFS interrupt register - (OTGFS_GOTGINT) - 0x4 - 0x20 - 0x00000000 - - - SESENDDET - VBUS is deasserted - 2 - 1 - read-write - - - - - GAHBCFG - GAHBCFG - OTGFS AHB configuration register - (OTGFS_GAHBCFG) - 0x8 - 0x20 - read-write - 0x00000000 - - - GLBINTMSK - Global interrupt mask - 0 - 1 - - - NPTXFEMPLVL - Non-Periodic TxFIFO empty level - 7 - 1 - - - PTXFEMPLVL - Periodic TxFIFO empty - level - 8 - 1 - - - - - GUSBCFG - GUSBCFG - USB configuration register - (OTGFS_GUSBCFG) - 0xC - 0x20 - 0x00000A00 - - - TOUTCAL - FS timeout calibration - 0 - 3 - read-write - - - USBTRDTIM - USB turnaround time - 10 - 4 - read-write - - - FHSTMODE - Force host mode - 29 - 1 - read-write - - - FDEVMODE - Force device mode - 30 - 1 - read-write - - - COTXPKT - Corrupt Tx packet - 31 - 1 - read-write - - - - - GRSTCTL - GRSTCTL - OTGFS reset register - (OTGFS_GRSTCTL) - 0x10 - 0x20 - 0x20000000 - - - CSFTRST - Core soft reset - 0 - 1 - read-write - - - PIUSFTRST - PIU FS Dedicated Controller Soft Reset - 1 - 1 - read-write - - - FRMCNTRST - Host frame counter reset - 2 - 1 - read-write - - - RXFFLSH - RxFIFO flush - 4 - 1 - read-write - - - TXFFLSH - TxFIFO flush - 5 - 1 - read-write - - - TXFNUM - TxFIFO number - 6 - 5 - read-write - - - AHBIDLE - AHB master idle - 31 - 1 - read-only - - - - - GINTSTS - GINTSTS - OTGFS core interrupt register - (OTGFS_GINTSTS) - 0x14 - 0x20 - 0x04000020 - - - CURMOD - Current mode of operation - 0 - 1 - read-only - - - MODEMIS - Mode mismatch interrupt - 1 - 1 - read-write - - - OTGINT - OTG interrupt - 2 - 1 - read-only - - - SOF - Start of frame - 3 - 1 - read-write - - - RXFLVL - RxFIFO non-empty - 4 - 1 - read-only - - - NPTXFEMP - Non-periodic TxFIFO empty - 5 - 1 - read-only - - - GINNAKEFF - Global IN non-periodic NAK - effective - 6 - 1 - read-only - - - GOUTNAKEFF - Global OUT NAK effective - 7 - 1 - read-only - - - ERLYSUSP - Early suspend - 10 - 1 - read-write - - - USBSUSP - USB suspend - 11 - 1 - read-write - - - USBRST - USB reset - 12 - 1 - read-write - - - ENUMDONE - Enumeration done - 13 - 1 - read-write - - - ISOOUTDROP - Isochronous OUT packet dropped - interrupt - 14 - 1 - read-write - - - EOPF - End of periodic frame - interrupt - 15 - 1 - read-write - - - IEPTINT - IN endpoint interrupt - 18 - 1 - read-only - - - OEPTINT - OUT endpoint interrupt - 19 - 1 - read-only - - - INCOMPISOIN - Incomplete isochronous IN - transfer - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUT - Incomplete periodic transfer(Host - mode)/Incomplete isochronous OUT transfer(Device - mode) - 21 - 1 - read-write - - - PRTINT - Host port interrupt - 24 - 1 - read-only - - - HCHINT - Host channels interrupt - 25 - 1 - read-only - - - PTXFEMP - Periodic TxFIFO empty - 26 - 1 - read-only - - - CONIDSCHG - Connector ID status change - 28 - 1 - read-write - - - DISCONINT - Disconnect detected - interrupt - 29 - 1 - read-write - - - WKUPINT - Resume/remote wakeup detected - interrupt - 31 - 1 - read-write - - - - - GINTMSK - GINTMSK - OTG_FS interrupt mask register - (OTG_FS_GINTMSK) - 0x18 - 0x20 - 0x00000000 - - - MODEMISMSK - Mode mismatch interrupt - mask - 1 - 1 - read-write - - - OTGINTMSK - OTG interrupt mask - 2 - 1 - read-write - - - SOFMSK - Start of frame mask - 3 - 1 - read-write - - - RXFLVLMSK - Receive FIFO non-empty - mask - 4 - 1 - read-write - - - NPTXFEMPMSK - Non-periodic TxFIFO empty - mask - 5 - 1 - read-write - - - GINNAKEFFMSK - Global non-periodic IN NAK effective - mask - 6 - 1 - read-write - - - GOUTNAKEFFMSK - Global OUT NAK effective - mask - 7 - 1 - read-write - - - ERLYSUSPMSK - Early suspend mask - 10 - 1 - read-write - - - USBSUSPMSK - USB suspend mask - 11 - 1 - read-write - - - USBRSTMSK - USB reset mask - 12 - 1 - read-write - - - ENUMDONEMSK - Enumeration done mask - 13 - 1 - read-write - - - ISOOUTDROPMSK - Isochronous OUT packet dropped interrupt - mask - 14 - 1 - read-write - - - EOPFMSK - End of periodic frame interrupt - mask - 15 - 1 - read-write - - - IEPTINTMSK - IN endpoints interrupt - mask - 18 - 1 - read-write - - - OEPTINTMSK - OUT endpoints interrupt - mask - 19 - 1 - read-write - - - INCOMISOINMSK - Incomplete isochronous IN transfer - mask - 20 - 1 - read-write - - - INCOMPIP_INCOMPISOOUTMSK - Incomplete periodic transfer mask(Host - mode)/Incomplete isochronous OUT transfer mask(Device - mode) - 21 - 1 - read-write - - - PRTINTMSK - Host port interrupt mask - 24 - 1 - read-only - - - HCHINTMSK - Host channels interrupt - mask - 25 - 1 - read-write - - - PTXFEMPMSK - Periodic TxFIFO empty mask - 26 - 1 - read-write - - - CONIDSCHGMSK - Connector ID status change - mask - 28 - 1 - read-write - - - DISCONINTMSK - Disconnect detected interrupt - mask - 29 - 1 - read-write - - - WKUPINTMSK - Resume/remote wakeup detected interrupt - mask - 31 - 1 - read-write - - - - - GRXSTSR_Device - GRXSTSR_Device - OTGFS Receive status debug read(Device - mode) - 0x1C - 0x20 - read-only - 0x00000000 - - - EPTNUM - Endpoint number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - FN - Frame number - 21 - 4 - - - - - GRXSTSR_Host - GRXSTSR_Host - OTGFS Receive status debug read(Host - mode) - GRXSTSR_Device - 0x1C - 0x20 - read-only - 0x00000000 - - - CHNUM - Channel number - 0 - 4 - - - BCNT - Byte count - 4 - 11 - - - DPID - Data PID - 15 - 2 - - - PKTSTS - Packet status - 17 - 4 - - - - - GRXFSIZ - GRXFSIZ - OTGFS Receive FIFO size register - (OTGFS_GRXFSIZ) - 0x24 - 0x20 - read-write - 0x00000200 - - - RXFDEP - RxFIFO depth - 0 - 16 - - - - - DIEPTXF0 - DIEPTXF0 - IN Endpoint TxFIFO 0 transmit FIFO size - register (Device mode) - 0x28 - 0x20 - read-write - 0x00000200 - - - INEPT0TXSTADDR - Endpoint 0 transmit RAM start - address - 0 - 16 - - - INEPT0TXDEP - Endpoint 0 TxFIFO depth - 16 - 16 - - - - - GNPTXFSIZ - GNPTXFSIZ - OTGFS non-periodic transmit FIFO size - register (Host mode) - DIEPTXF0 - 0x28 - 0x20 - read-write - 0x00000200 - - - NPTXFSTADDR - Non-periodic Transmit RAM Start - address - 0 - 16 - - - NPTXFDEP - Non-periodic TxFIFO depth - 16 - 16 - - - - - GNPTXSTS - GNPTXSTS - OTGFS non-periodic transmit FIFO/queue - status register (OTGFS_GNPTXSTS) - 0x2C - 0x20 - read-only - 0x00080200 - - - NPTXFSPCAVAIL - Non-periodic TxFIFO space - available - 0 - 16 - - - NPTXQSPCAVAIL - Non-periodic transmit request queue - space available - 16 - 8 - - - NPTXQTOP - Top of the non-periodic transmit request - queue - 24 - 7 - - - - - GCCFG - GCCFG - OTGFS general core configuration register - (OTGFS_GCCFG) - 0x38 - 0x20 - read-write - 0x00000000 - - - PWRDOWN - Power down - 16 - 1 - - - LP_MODE - Low power mode - 17 - 1 - - - SOFOUTEN - SOF output enable - 20 - 1 - - - VBUSIG - VBUS Ignored - 21 - 1 - - - - - GUID - GUID - Product ID register - 0x3C - 0x20 - read-write - 0x00001000 - - - USERID - Product ID field - 0 - 32 - - - - - HPTXFSIZ - HPTXFSIZ - OTGFS Host periodic transmit FIFO size - register (OTGFS_HPTXFSIZ) - 0x100 - 0x20 - read-write - 0x02000600 - - - PTXFSTADDR - Host periodic TxFIFO start - address - 0 - 16 - - - PTXFSIZE - Host periodic TxFIFO depth - 16 - 16 - - - - - DIEPTXF1 - DIEPTXF1 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF1) - 0x104 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO1 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF2 - DIEPTXF2 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF2) - 0x108 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO2 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF3 - DIEPTXF3 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF3) - 0x10C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO3 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF4 - DIEPTXF4 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF4) - 0x110 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO4 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF5 - DIEPTXF5 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF5) - 0x114 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO5 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF6 - DIEPTXF6 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF6) - 0x118 - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO6 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - DIEPTXF7 - DIEPTXF7 - OTGFS device IN endpoint transmit FIFO size - register (OTGFS_DIEPTXF7) - 0x11C - 0x20 - read-write - 0x02000400 - - - INEPTXFSTADDR - IN endpoint FIFO7 transmit RAM start - address - 0 - 16 - - - INEPTXFDEP - IN endpoint TxFIFO depth - 16 - 16 - - - - - - - USB_OTG2_HOST - USB on the go full speed - USB_OTG2 - 0x40040400 - - 0x0 - 0x400 - registers - - - - HCFG - HCFG - OTGFS host configuration register - (OTGFS_HCFG) - 0x0 - 0x20 - 0x00000000 - - - FSLSPCLKSEL - FS/LS PHY clock select - 0 - 2 - read-write - - - FSLSSUPP - FS- and LS-only support - 2 - 1 - read-only - - - - - HFIR - HFIR - OTGFS Host frame interval - register - 0x4 - 0x20 - read-write - 0x0000EA60 - - - FRINT - Frame interval - 0 - 16 - - - - - HFNUM - HFNUM - OTGFS host frame number/frame time - remaining register (OTGFS_HFNUM) - 0x8 - 0x20 - read-only - 0x00003FFF - - - FRNUM - Frame number - 0 - 16 - - - FTREM - Frame time remaining - 16 - 16 - - - - - HPTXSTS - HPTXSTS - OTGFS_Host periodic transmit FIFO/queue - status register (OTGFS_HPTXSTS) - 0x10 - 0x20 - 0x00080100 - - - PTXFSPCAVAIL - Periodic transmit data FIFO space - available - 0 - 16 - read-write - - - PTXQSPCAVAIL - Periodic transmit request queue space - available - 16 - 8 - read-only - - - PTXQTOP - Top of the periodic transmit request - queue - 24 - 8 - read-only - - - - - HAINT - HAINT - OTGFS Host all channels interrupt - register - 0x14 - 0x20 - read-only - 0x00000000 - - - HAINT - Channel interrupts - 0 - 16 - - - - - HAINTMSK - HAINTMSK - OTGFS host all channels interrupt mask - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HAINTMSK - Channel interrupt mask - 0 - 16 - - - - - HPRT - HPRT - OTGFS host port control and status register - (OTGFS_HPRT) - 0x40 - 0x20 - 0x00000000 - - - PRTCONSTS - Port connect status - 0 - 1 - read-only - - - PRTCONDET - Port connect detected - 1 - 1 - read-write - - - PRTENA - Port enable - 2 - 1 - read-write - - - PRTENCHNG - Port enable/disable change - 3 - 1 - read-write - - - PRTOVRCACT - Port overcurrent active - 4 - 1 - read-only - - - PRTOVRCCHNG - Port overcurrent change - 5 - 1 - read-write - - - PRTRES - Port resume - 6 - 1 - read-write - - - PRTSUSP - Port suspend - 7 - 1 - read-write - - - PRTRST - Port reset - 8 - 1 - read-write - - - PRTLNSTS - Port line status - 10 - 2 - read-only - - - PRTPWR - Port power - 12 - 1 - read-write - - - PRTTSTCTL - Port test control - 13 - 4 - read-write - - - PRTSPD - Port speed - 17 - 2 - read-only - - - - - HCCHAR0 - HCCHAR0 - OTGFS host channel-0 characteristics - register (OTGFS_HCCHAR0) - 0x100 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR1 - HCCHAR1 - OTGFS host channel-1 characteristics - register (OTGFS_HCCHAR1) - 0x120 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR2 - HCCHAR2 - OTGFS host channel-2 characteristics - register (OTGFS_HCCHAR2) - 0x140 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR3 - HCCHAR3 - OTGFS host channel-3 characteristics - register (OTGFS_HCCHAR3) - 0x160 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR4 - HCCHAR4 - OTGFS host channel-4 characteristics - register (OTGFS_HCCHAR4) - 0x180 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR5 - HCCHAR5 - OTGFS host channel-5 characteristics - register (OTGFS_HCCHAR5) - 0x1A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR6 - HCCHAR6 - OTGFS host channel-6 characteristics - register (OTGFS_HCCHAR6) - 0x1C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR7 - HCCHAR7 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR7) - 0x1E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR8 - HCCHAR8 - OTGFS host channel-8 characteristics - register (OTGFS_HCCHAR8) - 0x200 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR9 - HCCHAR9 - OTGFS host channel-9 characteristics - register (OTGFS_HCCHAR9) - 0x220 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR10 - HCCHAR10 - OTGFS host channel-10 characteristics - register (OTGFS_HCCHAR10) - 0x240 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR11 - HCCHAR11 - OTGFS host channel-7 characteristics - register (OTGFS_HCCHAR11) - 0x260 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR12 - HCCHAR12 - OTGFS host channel-12 characteristics - register (OTGFS_HCCHAR12) - 0x280 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR13 - HCCHAR13 - OTGFS host channel-13 characteristics - register (OTGFS_HCCHAR13) - 0x2A0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR14 - HCCHAR14 - OTGFS host channel-14 characteristics - register (OTGFS_HCCHAR14) - 0x2C0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCCHAR15 - HCCHAR15 - OTGFS host channel-15 characteristics - register (OTGFS_HCCHAR15) - 0x2E0 - 0x20 - read-write - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - - - EPTNUM - Endpoint number - 11 - 4 - - - EPTDIR - Endpoint direction - 15 - 1 - - - LSPDDEV - Low-speed device - 17 - 1 - - - EPTYPE - Endpoint type - 18 - 2 - - - MC - Multicount - 20 - 2 - - - DEVADDR - Device address - 22 - 7 - - - ODDFRM - Odd frame - 29 - 1 - - - CHDIS - Channel disable - 30 - 1 - - - CHENA - Channel enable - 31 - 1 - - - - - HCINT0 - HCINT0 - OTGFS host channel-0 interrupt register - (OTGFS_HCINT0) - 0x108 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT1 - HCINT1 - OTG_FS host channel-1 interrupt register - (OTG_FS_HCINT1) - 0x128 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT2 - HCINT2 - OTGFS host channel-2 interrupt register - (OTGFS_HCINT2) - 0x148 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT3 - HCINT3 - OTGFS host channel-3 interrupt register - (OTGFS_HCINT3) - 0x168 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT4 - HCINT4 - OTGFS host channel-4 interrupt register - (OTGFS_HCINT4) - 0x188 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT5 - HCINT5 - OTGFS host channel-5 interrupt register - (OTGFS_HCINT5) - 0x1A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT6 - HCINT6 - OTGFS host channel-6 interrupt register - (OTGFS_HCINT6) - 0x1C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT7 - HCINT7 - OTGFS host channel-7 interrupt register - (OTGFS_HCINT7) - 0x1E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT8 - HCINT8 - OTGFS host channel-8 interrupt register - (OTGFS_HCINT8) - 0x208 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT9 - HCINT9 - OTGFS host channel-9 interrupt register - (OTGFS_HCINT9) - 0x228 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT10 - HCINT10 - OTGFS host channel-10 interrupt register - (OTGFS_HCINT10) - 0x248 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT11 - HCINT11 - OTGFS host channel-11 interrupt register - (OTGFS_HCINT11) - 0x268 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT12 - HCINT12 - OTGFS host channel-12 interrupt register - (OTGFS_HCINT12) - 0x288 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT13 - HCINT13 - OTGFS host channel-13 interrupt register - (OTGFS_HCINT13) - 0x2A8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT14 - HCINT14 - OTGFS host channel-14 interrupt register - (OTGFS_HCINT14) - 0x2C8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINT15 - HCINT15 - OTGFS host channel-15 interrupt register - (OTGFS_HCINT15) - 0x2E8 - 0x20 - read-write - 0x00000000 - - - XFERC - Transfer completed - 0 - 1 - - - CHHLTD - Channel halted - 1 - 1 - - - STALL - STALL response received - interrupt - 3 - 1 - - - NAK - NAK response received - interrupt - 4 - 1 - - - ACK - ACK response received/transmitted - interrupt - 5 - 1 - - - XACTERR - Transaction error - 7 - 1 - - - BBLERR - Babble error - 8 - 1 - - - FRMOVRUN - Frame overrun - 9 - 1 - - - DTGLERR - Data toggle error - 10 - 1 - - - - - HCINTMSK0 - HCINTMSK0 - OTGFS host channel-0 mask register - (OTGFS_HCINTMSK0) - 0x10C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK1 - HCINTMSK1 - OTGFS host channel-1 mask register - (OTGFS_HCINTMSK1) - 0x12C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK2 - HCINTMSK2 - OTGFS host channel-2 mask register - (OTGFS_HCINTMSK2) - 0x14C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK3 - HCINTMSK3 - OTGFS host channel-3 mask register - (OTGFS_HCINTMSK3) - 0x16C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK4 - HCINTMSK4 - OTGFS host channel-4 mask register - (OTGFS_HCINTMSK4) - 0x18C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK5 - HCINTMSK5 - OTGFS host channel-5 mask register - (OTGFS_HCINTMSK5) - 0x1AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK6 - HCINTMSK6 - OTGFS host channel-6 mask register - (OTGFS_HCINTMSK6) - 0x1CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK7 - HCINTMSK7 - OTGFS host channel-7 mask register - (OTGFS_HCINTMSK7) - 0x1EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK8 - HCINTMSK8 - OTGFS host channel-8 mask register - (OTGFS_HCINTMSK8) - 0x20C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK9 - HCINTMSK9 - OTGFS host channel-9 mask register - (OTGFS_HCINTMSK9) - 0x22C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK10 - HCINTMSK10 - OTGFS host channel-10 mask register - (OTGFS_HCINTMSK10) - 0x24C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK11 - HCINTMSK11 - OTGFS host channel-11 mask register - (OTGFS_HCINTMSK11) - 0x26C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK12 - HCINTMSK12 - OTGFS host channel-12 mask register - (OTGFS_HCINTMSK12) - 0x28C - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK13 - HCINTMSK13 - OTGFS host channel-13 mask register - (OTGFS_HCINTMSK13) - 0x2AC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK14 - HCINTMSK14 - OTGFS host channel-14 mask register - (OTGFS_HCINTMSK14) - 0x2CC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCINTMSK15 - HCINTMSK15 - OTGFS host channel-15 mask register - (OTGFS_HCINTMSK15) - 0x2EC - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed mask - 0 - 1 - - - CHHLTDMSK - Channel halted mask - 1 - 1 - - - STALLMSK - STALL response received interrupt - mask - 3 - 1 - - - NAKMSK - NAK response received interrupt - mask - 4 - 1 - - - ACKMSK - ACK response received/transmitted - interrupt mask - 5 - 1 - - - XACTERRMSK - Transaction error mask - 7 - 1 - - - BBLERRMSK - Babble error mask - 8 - 1 - - - FRMOVRUNMSK - Frame overrun mask - 9 - 1 - - - DTGLERRMSK - Data toggle error mask - 10 - 1 - - - - - HCTSIZ0 - HCTSIZ0 - OTGFS host channel-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ1 - HCTSIZ1 - OTGFS host channel-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ2 - HCTSIZ2 - OTGFS host channel-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ3 - HCTSIZ3 - OTGFS host channel-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ4 - HCTSIZ4 - OTGFS host channel-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ5 - HCTSIZ5 - OTGFS host channel-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ6 - HCTSIZ6 - OTGFS host channel-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ7 - HCTSIZ7 - OTGFS host channel-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ8 - HCTSIZ8 - OTGFS host channel-8 transfer size - register - 0x210 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ9 - HCTSIZ9 - OTGFS host channel-9 transfer size - register - 0x230 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ10 - HCTSIZ10 - OTGFS host channel-10 transfer size - register - 0x250 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ11 - HCTSIZ11 - OTGFS host channel-11 transfer size - register - 0x270 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ12 - HCTSIZ12 - OTGFS host channel-12 transfer size - register - 0x290 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ13 - HCTSIZ13 - OTGFS host channel-13 transfer size - register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ14 - HCTSIZ14 - OTGFS host channel-14 transfer size - register - 0x2D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - HCTSIZ15 - HCTSIZ15 - OTGFS host channel-15 transfer size - register - 0x2F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - PID - PID - 29 - 2 - - - - - - - USB_OTG2_DEVICE - USB on the go full speed - USB_OTG2 - 0x40040800 - - 0x0 - 0x400 - registers - - - - DCFG - DCFG - OTGFS device configuration register - (OTGFS_DCFG) - 0x0 - 0x20 - read-write - 0x02200000 - - - DEVSPD - Device speed - 0 - 2 - - - NZSTSOUTHSHK - Non-zero-length status OUT - handshake - 2 - 1 - - - DEVADDR - Device address - 4 - 7 - - - PERFRINT - Periodic frame interval - 11 - 2 - - - - - DCTL - DCTL - OTGFS device control register - (OTGFS_DCTL) - 0x4 - 0x20 - 0x00000000 - - - RWKUPSIG - Remote wakeup signaling - 0 - 1 - read-write - - - SFTDISCON - Soft disconnect - 1 - 1 - read-write - - - GNPINNAKSTS - Global IN NAK status - 2 - 1 - read-only - - - GOUTNAKSTS - Global OUT NAK status - 3 - 1 - read-only - - - TSTCTL - Test control - 4 - 3 - read-write - - - SGNPINNAK - Set global IN NAK - 7 - 1 - read-write - - - CGNPINNAK - Clear global IN NAK - 8 - 1 - read-write - - - SGOUTNAK - Set global OUT NAK - 9 - 1 - read-write - - - CGOUTNAK - Clear global OUT NAK - 10 - 1 - read-write - - - PWROPRGDNE - Power-on programming done - 11 - 1 - read-write - - - - - DSTS - DSTS - OTGFS device status register - (OTGFS_DSTS) - 0x8 - 0x20 - read-only - 0x00000010 - - - SUSPSTS - Suspend status - 0 - 1 - - - ENUMSPD - Enumerated speed - 1 - 2 - - - ETICERR - Erratic error - 3 - 1 - - - SOFFN - Frame number of the received - SOF - 8 - 14 - - - - - DIEPMSK - DIEPMSK - OTGFS device IN endpoint common interrupt - mask register (OTGFS_DIEPMSK) - 0x10 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - TIMEOUTMSK - Timeout condition mask (Non-isochronous - endpoints) - 3 - 1 - - - INTKNTXFEMPMSK - IN token received when TxFIFO empty - mask - 4 - 1 - - - INTKNEPTMISMSK - IN token received with EP mismatch - mask - 5 - 1 - - - INEPTNAKMSK - IN endpoint NAK effective - mask - 6 - 1 - - - TXFIFOUDRMSK - FIFO underrun - mask - 8 - 1 - - - BNAINMSK - BNA interrupt - mask - 9 - 1 - - - - - DOEPMSK - DOEPMSK - OTGFS device OUT endpoint common interrupt - mask register (OTGFS_DOEPMSK) - 0x14 - 0x20 - read-write - 0x00000000 - - - XFERCMSK - Transfer completed interrupt - mask - 0 - 1 - - - EPTDISMSK - Endpoint disabled interrupt - mask - 1 - 1 - - - SETUPMSK - SETUP phase done mask - 3 - 1 - - - OUTTEPDMSK - OUT token received when endpoint - disabled mask - 4 - 1 - - - B2BSETUPMSK - Back-to-back SETUP packets - received mask - 6 - 1 - - - OUTPERRMSK - OUT packet error - mask - 8 - 1 - - - BNAOUTMSK - BNA interrupt - mask - 9 - 1 - - - - - DAINT - DAINT - OTGFS device all endpoints interrupt - register (OTGFS_DAINT) - 0x18 - 0x20 - read-only - 0x00000000 - - - INEPTINT - IN endpoint interrupt bits - 0 - 16 - - - OUTEPTINT - OUT endpoint interrupt - bits - 16 - 16 - - - - - DAINTMSK - DAINTMSK - OTGFS all endpoints interrupt mask register - (OTGFS_DAINTMSK) - 0x1C - 0x20 - read-write - 0x00000000 - - - INEPTMSK - IN EP interrupt mask bits - 0 - 16 - - - OUTEPTMSK - OUT endpoint interrupt - bits - 16 - 16 - - - - - DIEPEMPMSK - DIEPEMPMSK - OTGFS device IN endpoint FIFO empty - interrupt mask register - 0x34 - 0x20 - read-write - 0x00000000 - - - INEPTXFEMSK - IN EP Tx FIFO empty interrupt mask - bits - 0 - 16 - - - - - DIEPCTL0 - DIEPCTL0 - OTGFS device control IN endpoint 0 control - register (OTGFS_DIEPCTL0) - 0x100 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 2 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-only - - - EPTENA - Endpoint enable - 31 - 1 - read-only - - - - - DIEPCTL1 - DIEPCTL1 - OTGFS device IN endpoint-1 control - register - 0x120 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL2 - DIEPCTL2 - OTGFS device IN endpoint-2 control - register - 0x140 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL3 - DIEPCTL3 - OTGFS device IN endpoint-3 control - register - 0x160 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL4 - DIEPCTL4 - OTGFS device IN endpoint-4 control - register - 0x180 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL5 - DIEPCTL5 - OTGFS device IN endpoint-5 control - register - 0x1A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL6 - DIEPCTL6 - OTGFS device IN endpoint-6 control - register - 0x1C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPCTL7 - DIEPCTL7 - OTGFS device IN endpoint-7 control - register - 0x1E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-write - - - DPID - Endpoint Data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - TXFNUM - TxFIFO number - 22 - 4 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - SETD0PID - Set DATA0 PID - 28 - 1 - write-only - - - SETD1PID - Set DATA1 PID - 29 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL0 - DOEPCTL0 - OTGFS device OUT endpoint-0 control - register - 0x300 - 0x20 - 0x00008000 - - - MPS - Maximum packet size - 0 - 2 - read-only - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL1 - DOEPCTL1 - OTGFS device OUT endpoint-1 control - register - 0x320 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL2 - DOEPCTL2 - OTGFS device OUT endpoint-2 control - register - 0x340 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL3 - DOEPCTL3 - OTGFS device OUT endpoint-3 control - register - 0x360 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL4 - DOEPCTL4 - OTGFS device OUT endpoint-4 control - register - 0x380 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL5 - DOEPCTL5 - OTGFS device OUT endpoint-5 control - register - 0x3A0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL6 - DOEPCTL6 - OTGFS device OUT endpoint-6 control - register - 0x3C0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DOEPCTL7 - DOEPCTL7 - OTGFS device OUT endpoint-7 control - register - 0x3E0 - 0x20 - 0x00000000 - - - MPS - Maximum packet size - 0 - 11 - read-write - - - USBACEPT - USB active endpoint - 15 - 1 - read-only - - - DPID - Endpoint data PID - 16 - 1 - read-only - - - NAKSTS - NAK status - 17 - 1 - read-only - - - EPTYPE - Endpoint type - 18 - 2 - read-only - - - SNP - Snoop mode - 20 - 1 - read-write - - - STALL - STALL handshake - 21 - 1 - read-write - - - CNAK - Clear NAK - 26 - 1 - write-only - - - SNAK - Set NAK - 27 - 1 - write-only - - - EPTDIS - Endpoint disable - 30 - 1 - read-write - - - EPTENA - Endpoint enable - 31 - 1 - read-write - - - - - DIEPINT0 - DIEPINT0 - OTGFS device IN endpoint-0 interrupt - register - 0x108 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT1 - DIEPINT1 - OTGFS device IN endpoint-1 interrupt - register - 0x128 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT2 - DIEPINT2 - OTGFS device IN endpoint-2 interrupt - register - 0x148 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT3 - DIEPINT3 - OTGFS device IN endpoint-3 interrupt - register - 0x168 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT4 - DIEPINT4 - OTGFS device IN endpoint-4 interrupt - register - 0x188 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT5 - DIEPINT5 - OTGFS device IN endpoint-5 interrupt - register - 0x1A8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT6 - DIEPINT6 - OTGFS device IN endpoint-6 interrupt - register - 0x1C8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DIEPINT7 - DIEPINT7 - OTGFS device IN endpoint-7 interrupt - register - 0x1E8 - 0x20 - 0x00000080 - - - XFERC - Transfer completed - interrupt - 0 - 1 - read-write - - - EPTDISD - Endpoint disabled - interrupt - 1 - 1 - read-write - - - TIMEOUT - Timeout condition - 3 - 1 - read-write - - - INTKNTXFEMP - IN token received when - TxFIFO is empty - 4 - 1 - read-write - - - INEPTNAK - IN endpoint NAK - effective - 6 - 1 - read-write - - - TXFEMP - Transmit FIFO - empty - 7 - 1 - read-only - - - - - DOEPINT0 - DOEPINT0 - OTGFS device OUT endpoint-0 interrupt - register - 0x308 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT1 - DOEPINT1 - OTGFS device OUT endpoint-1 interrupt - register - 0x328 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT2 - DOEPINT2 - OTGFS device OUT endpoint-2 interrupt - register - 0x348 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT3 - DOEPINT3 - OTGFS device OUT endpoint-3 interrupt - register - 0x368 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT4 - DOEPINT4 - OTGFS device OUT endpoint-4 interrupt - register - 0x388 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT5 - DOEPINT5 - OTGFS device OUT endpoint-5 interrupt - register - 0x3A8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT6 - DOEPINT6 - OTGFS device OUT endpoint-6 interrupt - register - 0x3C8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DOEPINT7 - DOEPINT7 - OTGFS device OUT endpoint-7 interrupt - register - 0x3E8 - 0x20 - read-write - 0x00000080 - - - XFERC - Transfer completed interrupt - 0 - 1 - - - EPTDISD - Endpoint disabled interrupt - 1 - 1 - - - SETUP - SETUP phase done - 3 - 1 - - - OUTTEPD - OUT token received when - endpoint disabled - 4 - 1 - - - B2BSTUP - Back-to-back SETUP - packets received - 6 - 1 - - - - - DIEPTSIZ0 - DIEPTSIZ0 - OTGFS device IN endpoint-0 transfer size - register - 0x110 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 2 - - - - - DOEPTSIZ0 - DOEPTSIZ0 - OTGFS device OUT endpoint-0 transfer size - register - 0x310 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 7 - - - PKTCNT - Packet count - 19 - 1 - - - SETUPCNT - SETUP packet count - 29 - 2 - - - - - DIEPTSIZ1 - DIEPTSIZ1 - OTGFS device IN endpoint-1 transfer size - register - 0x130 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ2 - DIEPTSIZ2 - OTGFS device IN endpoint-2 transfer size - register - 0x150 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ3 - DIEPTSIZ3 - OTG device IN endpoint-3 transfer size - register - 0x170 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ4 - DIEPTSIZ4 - OTG device IN endpoint-4 transfer size - register - 0x190 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ5 - DIEPTSIZ5 - OTG device IN endpoint-5 transfer size - register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ6 - DIEPTSIZ6 - OTG device IN endpoint-6 transfer size - register - 0x1D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DIEPTSIZ7 - DIEPTSIZ7 - OTG device IN endpoint-7 transfer size - register - 0x1F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - MC - Multi count - 29 - 2 - - - - - DTXFSTS0 - DTXFSTS0 - OTGFS device IN endpoint-0 transmit FIFO - status register - 0x118 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS1 - DTXFSTS1 - OTGFS device IN endpoint-1 transmit FIFO - status register - 0x138 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS2 - DTXFSTS2 - OTGFS device IN endpoint-2 transmit FIFO - status register - 0x158 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS3 - DTXFSTS3 - OTGFS device IN endpoint-3 transmit FIFO - status register - 0x178 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS4 - DTXFSTS4 - OTGFS device IN endpoint-4 transmit FIFO - status register - 0x198 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS5 - DTXFSTS5 - OTGFS device IN endpoint-5 transmit FIFO - status register - 0x1B8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS6 - DTXFSTS6 - OTGFS device IN endpoint-6 transmit FIFO - status register - 0x1D8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DTXFSTS7 - DTXFSTS7 - OTGFS device IN endpoint-7 transmit FIFO - status register - 0x1F8 - 0x20 - read-only - 0x00000000 - - - INEPTXFSAV - IN endpoint TxFIFO space - available - 0 - 16 - - - - - DOEPTSIZ1 - DOEPTSIZ1 - OTGFS device OUT endpoint-1 transfer size - register - 0x330 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ2 - DOEPTSIZ2 - OTGFS device OUT endpoint-2 transfer size - register - 0x350 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ3 - DOEPTSIZ3 - OTGFS device OUT endpoint-3 transfer size - register - 0x370 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ4 - DOEPTSIZ4 - OTGFS device OUT endpoint-4 transfer size - register - 0x390 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ5 - DOEPTSIZ5 - OTGFS device OUT endpoint-5 transfer size - register - 0x3B0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ6 - DOEPTSIZ6 - OTGFS device OUT endpoint-6 transfer size - register - 0x3D0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - DOEPTSIZ7 - DOEPTSIZ7 - OTGFS device OUT endpoint-7 transfer size - register - 0x3F0 - 0x20 - read-write - 0x00000000 - - - XFERSIZE - Transfer size - 0 - 19 - - - PKTCNT - Packet count - 19 - 10 - - - RXDPID - Received data PID - 29 - 2 - - - - - - - USB_OTG2_PWRCLK - USB on the go full speed - USB_OTG2 - 0x40040E00 - - 0x0 - 0x400 - registers - - - - PCGCCTL - PCGCCTL - OTGFS power and clock gating control - register (OTGFS_PCGCCTL) - 0x0 - 0x20 - 0x00000000 - - - STOPPCLK - Stop PHY clock - 0 - 1 - read-write - - - SUSPENDM - PHY Suspended - 4 - 1 - read-only - - - - - - - SCFG - System configuration controller - SCFG - 0x40013800 - - 0x0 - 0x400 - registers - - - - CFG1 - CFG1 - configuration register 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - MEM_MAP_SEL - Memory address mapping selection bits - 0 - 3 - - - IR_POL - IR output polarity selection - 5 - 1 - - - IR_SRC_SEL - IR signal source selection - 6 - 2 - - - SWAP_XMC - XMC address mapping swap - 10 - 2 - - - - - CFG2 - CFG2 - configuration register 2 - 0x4 - 0x20 - read-write - 0x00000000 - - - MII_RMII_SEL - MII or RMII selection - bits - 23 - 1 - - - - - EXINTC1 - EXINTC1 - external interrupt configuration register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - EXINT3 - EXINT 3 configuration bits - 12 - 4 - - - EXINT2 - EXINT 2 configuration bits - 8 - 4 - - - EXINT1 - EXINT 1 configuration bits - 4 - 4 - - - EXINT0 - EXINT 0 configuration bits - 0 - 4 - - - - - EXINTC2 - EXINTC2 - external interrupt configuration register 2 - 0xC - 0x20 - read-write - 0x0000 - - - EXINT7 - EXINT 7 configuration bits - 12 - 4 - - - EXINT6 - EXINT 6 configuration bits - 8 - 4 - - - EXINT5 - EXINT 5 configuration bits - 4 - 4 - - - EXINT4 - EXINT 4 configuration bits - 0 - 4 - - - - - EXINTC3 - EXINTC3 - external interrupt configuration register 3 - 0x10 - 0x20 - read-write - 0x0000 - - - EXINT11 - EXINT 11 configuration bits - 12 - 4 - - - EXINT10 - EXINT 10 configuration bits - 8 - 4 - - - EXINT9 - EXINT 9 configuration bits - 4 - 4 - - - EXINT8 - EXINT 8 configuration bits - 0 - 4 - - - - - EXINTC4 - EXINTC4 - external interrupt configuration register - 4 - 0x14 - 0x20 - read-write - 0x0000 - - - EXINT15 - EXINT 15 configuration bits - 12 - 4 - - - EXINT14 - EXINT 14 configuration bits - 8 - 4 - - - EXINT13 - EXINT 13 configuration bits - 4 - 4 - - - EXINT12 - EXINT 12 configuration bits - 0 - 4 - - - - - UHDRV - UHDRV - Ultra high drive register - 0x2C - 0x20 - read-write - 0x0000 - - - PF15_UH - PF15 ultra high sourcing/sinking strength - 10 - 1 - - - PF14_UH - PF14 ultra high sourcing/sinking strength - 9 - 1 - - - PD15_UH - PD15 ultra high sourcing/sinking strength - 8 - 1 - - - PD14_UH - PD14 ultra high sourcing/sinking strength - 7 - 1 - - - PD13_UH - PD13 ultra high sourcing/sinking strength - 6 - 1 - - - PD12_UH - PD12 ultra high sourcing/sinking strength - 5 - 1 - - - PB10_UH - PB10 ultra high sourcing/sinking strength - 2 - 1 - - - PB9_UH - PB9 ultra high sourcing/sinking strength - 1 - 1 - - - PB3_UH - PB3 ultra high sourcing/sinking strength - 0 - 1 - - - - - - - QSPI1 - Quad SPI Controller - QSPI - 0xA0001000 - - 0x0 - 0x400 - registers - - - QSPI1 - QSPI1 global interrupt - 92 - - - - CMD_W0 - CMD_W0 - Command word 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - SPIADR - SPI flash address - 0 - 32 - - - - - CMD_W1 - CMD_W1 - Command word 1 - 0x4 - 0x20 - read-write - 0x01000003 - - - ADRLEN - SPI address length - 0 - 3 - - - DUM2 - Second dummy state cycle - 16 - 8 - - - INSLEN - Instruction code length - 24 - 2 - - - PEMEN - Perfrmance enhance mode enable - 28 - 1 - - - - - CMD_W2 - CMD_W2 - Command word 2 - 0x8 - 0x20 - read-write - 0x01000003 - - - DCNT - Read write data counter - 0 - 32 - - - - - CMD_W3 - CMD_W3 - Command word 3 - 0xC - 0x20 - read-write - 0x00000000 - - - WEN - Write data enable - 1 - 1 - - - RSTSEN - Read spi status enable - 2 - 1 - - - RSTSC - Read spi status configure - 3 - 1 - - - OPMODE - SPI operate mode - 5 - 3 - - - PEMOPC - Performance enhance mode operate code - 16 - 8 - - - INSC - Instruction code - 24 - 8 - - - - - CTRL - CTRL - Control register - 0x10 - 0x20 - read-write - 0x00000000 - - - CLKDIV - SPI clock divider - 0 - 3 - - - SCKMODE - Sckout mode - 4 - 1 - - - XIPIDLE - XIP port idle status - 7 - 1 - - - ABORT - Abort instruction - 8 - 1 - - - BUSY - Busy bit of spi status - 16 - 3 - - - XIPRCMDF - XIP read command flush - 19 - 1 - - - XIPSEL - XIP port selection - 20 - 1 - - - KEYEN - encryption key enable - 21 - 1 - - - - - ACTR - ACTR - AC timing control register - 0x14 - 0x20 - read-write - 0x0000000F - - - CSDLY - CS delay - 0 - 4 - - - - - FIFOSTS - FIFOSTS - FIFO Status register - 0x18 - 0x20 - read-only - 0x00000001 - - - TXFIFORDY - TxFIFO ready status - 0 - 1 - - - RXFIFORDY - RxFIFO ready status - 1 - 1 - - - - - CTRL2 - CTRL2 - control register 2 - 0x20 - 0x20 - read-write - 0x00000001 - - - DMAEN - DMA handshake enable - 0 - 1 - - - CMDIE - Command complete interrupt enable - 1 - 1 - - - TXFIFOTHOD - TxFIFO thod - 8 - 2 - - - RXFIFOTHOD - RxFIFO thod - 12 - 2 - - - - - CMDSTS - CMDSTS - CMD status register - 0x24 - 0x20 - read-only - 0x00000000 - - - CMDSTS - Command complete status - 0 - 1 - - - - - RSTS - RSTS - SPI read status register - 0x28 - 0x20 - read-only - 0x00000000 - - - SPISTS - SPI read status - 0 - 8 - - - - - FSIZE - FSIZE - SPI flash size - 0x2C - 0x20 - read-write - 0x00000000 - - - SPIFSIZE - SPI flash size - 0 - 32 - - - - - XIP_CMD_W0 - XIP_CMD_W0 - XIP command word 0 - 0x30 - 0x20 - read-write - 0x00000000 - - - XIPR_DUM2 - XIP read second dummy cycle - 0 - 8 - - - XIPR_OPMODE - XIP read operate mode - 8 - 3 - - - XIPR_ADRLEN - XIP read address length - 11 - 1 - - - XIPR_INSC - XIP read instruction code - 12 - 8 - - - - - XIP_CMD_W1 - XIP_CMD_W1 - XIP command word 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - XIPW_DUM2 - XIP write second dummy cycle - 0 - 8 - - - XIPW_OPMODE - XIP write operate mode - 8 - 3 - - - XIPW_ADRLEN - XIP write address length - 11 - 1 - - - XIPW_INSC - XIP write instruction code - 12 - 8 - - - - - XIP_CMD_W2 - XIP_CMD_W2 - XIP command word 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - XIPR_DCNT - XIP read data counter - 0 - 6 - - - XIPR_TCNT - XIP continue read cycle counter - 8 - 7 - - - XIPR_SEL - XIP read continue mode select - 15 - 1 - - - XIPW_DCNT - XIP write data counter - 16 - 6 - - - XIPW_TCNT - XIP continue write cycle counter - 24 - 7 - - - XIPW_SEL - XIP write continue mode select - 31 - 1 - - - - - XIP_CMD_W3 - XIP_CMD_W3 - XIP command word 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - BYPASSC - Bypass cache function - 0 - 1 - - - CSTS - Cache status - 3 - 1 - - - - - REV - REV - Revision - 0x50 - 0x20 - read-write - 0x00010500 - - - REVISION - Revision number - 0 - 31 - - - - - DT - DT - 32/16/8 bit data port register - 0x100 - 0x20 - read-write - 0x00000000 - - - - - QSPI2 - 0xA0002000 - - QSPI2 - QSPI2 global interrupt - 91 - - - - ETHERNET_MAC - Ethernet: media access control - ETHERNET - 0x40028000 - - 0x0 - 0x100 - registers - - - EMAC - Ethernet mac global interrupt - 61 - - - - MACCTRL - MACCTRL - Ethernet MAC configuration register - 0x0 - 0x20 - read-write - 0x00008000 - - - RE - Receiver enable - 2 - 1 - - - TE - Transmitter enable - 3 - 1 - - - DC - Deferral check - 4 - 1 - - - BL - Back-off limit - 5 - 2 - - - ACS - Automatic pad/CRC - stripping - 7 - 1 - - - DR - Disable retry - 9 - 1 - - - IPC - IPv4 checksum offload - 10 - 1 - - - DM - Duplex mode - 11 - 1 - - - LM - Loopback mode - 12 - 1 - - - DRO - Disable receive own - 13 - 1 - - - FES - Fast EMAC speed - 14 - 1 - - - DCS - Disable carrier sense - 16 - 1 - - - IFG - Interframe gap - 17 - 3 - - - JD - Jabber disable - 22 - 1 - - - WD - Watchdog disable - 23 - 1 - - - - - MACFRMF - MACFRMF - Ethernet MAC frame filter register - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Promiscuous mode - 0 - 1 - - - HUC - Hash unicast - 1 - 1 - - - HMC - Hash multicast - 2 - 1 - - - DAIF - Destination address inverse - filtering - 3 - 1 - - - PMC - Pass multicast - 4 - 1 - - - DBF - Disable broadcast frames - 5 - 1 - - - PCF - Pass control frames - 6 - 2 - - - SAIF - Source address inverse - filtering - 8 - 1 - - - SAF - Source address filter - 9 - 1 - - - HPF - Hash or perfect filter - 10 - 1 - - - RA - Receive all - 31 - 1 - - - - - MACHTH - MACHTH - Ethernet MAC hash table high register - 0x8 - 0x20 - read-write - 0x00000000 - - - HTH - Hash table high - 0 - 32 - - - - - MACHTL - MACHTL - Ethernet MAC hash table low register - 0xC - 0x20 - read-write - 0x00000000 - - - HTL - Hash table low - 0 - 32 - - - - - MACMIIADDR - MACMIIADDR - Ethernet MAC MII address register - 0x10 - 0x20 - read-write - 0x00000000 - - - MB - MII busy - 0 - 1 - - - MW - MII write - 1 - 1 - - - CR - Clock range - 2 - 3 - - - MII - MII register - 6 - 5 - - - PA - PHY address - 11 - 5 - - - - - MACMIIDT - MACMIIDT - Ethernet MAC MII data register - 0x14 - 0x20 - read-write - 0x00000000 - - - MD - MII data - 0 - 16 - - - - - MACFCTRL - MACFCTRL - Ethernet MAC flow control register - 0x18 - 0x20 - read-write - 0x00000000 - - - FCB_BPA - Flow control busy/back pressure - activate - 0 - 1 - - - ETF - Enable transmit flow control - - 1 - 1 - - - ERF - Enable receive flow control - - 2 - 1 - - - DUP - Detect unicast pause frame - 3 - 1 - - - PLT - Pause low threshold - 4 - 2 - - - DZQP - Disable zero-quanta pause - 7 - 1 - - - PT - Pass time - 16 - 16 - - - - - MACVLT - MACVLT - Ethernet MAC VLAN tag register - 0x1C - 0x20 - read-write - 0x00000000 - - - VTI - VLAN tag identifier (for receive - frames) - 0 - 16 - - - ETV - Enable 12-bit VLAN tag comparison - 16 - 1 - - - - - MACRWFF - MACRWFF - Ethernet MAC remote wakeup frame filter register - 0x28 - 0x20 - read-write - 0x00000000 - - - MACPMTCTRLSTS - MACPMTCTRLSTS - Ethernet MAC PMT control and status register - 0x2C - 0x20 - read-write - 0x00000000 - - - PD - Power down - 0 - 1 - - - EMP - Enable magic packet - 1 - 1 - - - ERWF - Enable remote wakeup frame - 2 - 1 - - - RMP - Received magic packet - 5 - 1 - - - RRWF - Recevied remote wakeup frame - 6 - 1 - - - GUC - Global unicast - 9 - 1 - - - RWFFPR - Remote wakeup frame filter register pointer - reset - 31 - 1 - - - - - MACISTS - MACISTS - Ethernet MAC interrupt status register - 0x38 - 0x20 - read-write - 0x00000000 - - - PIS - PMT interrupt status - 3 - 1 - - - MIS - MMC interrupt status - 4 - 1 - - - MRIS - MMC receive interrupt status - 5 - 1 - - - MTIS - MMC transmit interrupt status - 6 - 1 - - - TIS - Timestamp interrupt status - 9 - 1 - - - - - MACIMR - MACIMR - Ethernet MAC interrupt mask register - 0x3C - 0x20 - read-write - 0x00000000 - - - PIM - PMT interrupt mask - 3 - 1 - - - TIM - Timestamp interrupt mask - 9 - 1 - - - - - MACA0H - MACA0H - Ethernet MAC address 0 high register - 0x40 - 0x20 - 0x0010FFFF - - - MA0H - MAC address0 high - 0 - 16 - read-write - - - AE - Address enable - 31 - 1 - read-only - - - - - MACA0L - MACA0L - Ethernet MAC address 0 low register - 0x44 - 0x20 - read-write - 0xFFFFFFFF - - - MA0L - MAC address0 low - 0 - 32 - - - - - MACA1H - MACA1H - Ethernet MAC address 1 high register - 0x48 - 0x20 - read-write - 0x0000FFFF - - - MA1H - MAC address1 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA1L - MACA1L - Ethernet MAC address1 low register - 0x4C - 0x20 - read-write - 0xFFFFFFFF - - - MA1L - MAC address1 low - 0 - 32 - - - - - MACA2H - MACA2H - Ethernet MAC address 2 high register - 0x50 - 0x20 - read-write - 0x0050 - - - MA2H - MAC address 2 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA2L - MACA2L - Ethernet MAC address 2 low register - 0x54 - 0x20 - read-write - 0xFFFFFFFF - - - MA2L - MAC address2 low - 0 - 31 - - - - - MACA3H - MACA3H - Ethernet MAC address 3 high register - 0x58 - 0x20 - read-write - 0x0000FFFF - - - MA3H - MAC address3 high - 0 - 16 - - - MBC - Mask byte control - 24 - 6 - - - SA - Source address - 30 - 1 - - - AE - Address enable - 31 - 1 - - - - - MACA3L - MACA3L - Ethernet MAC address 3 low register - 0x5C - 0x20 - read-write - 0xFFFFFFFF - - - MA3L - MAC address3 low - 0 - 32 - - - - - - - ETHERNET_MMC - Ethernet: MAC management counters - ETHERNET - 0x40028100 - - 0x0 - 0x100 - registers - - - - MMCCTRL - MMCCTRL - Ethernet MMC control register - 0x0 - 0x20 - read-write - 0x00000000 - - - RC - Reset counter - 0 - 1 - - - SCR - Stop counter rollover - 1 - 1 - - - RR - Reset on read - 2 - 1 - - - FMC - Freeze MMC counter - 31 - 1 - - - - - MMCRI - MMCRI - Ethernet MMC receive interrupt register - 0x4 - 0x20 - read-write - 0x00000000 - - - RFCE - Received frames CRC error - 5 - 1 - - - RFAE - Received frames alignment error - 6 - 1 - - - RGUF - Received good unicast frames - 17 - 1 - - - - - MMCTI - MMCTI - Ethernet MMC transmit interrupt register - 0x8 - 0x20 - read-write - 0x00000000 - - - TSCGFCI - Transmit single collision good frame - counter interrupt - 14 - 1 - - - TGFMSC - Transmit good frames more single - collision - 15 - 1 - - - TGF - Transmitted good frames - 21 - 1 - - - - - MMCRIM - MMCRIM - Ethernet MMC receive interrupt mask register - 0xC - 0x20 - read-write - 0x00000000 - - - RCEFCIM - Received CRC error frame counter interrupt - mask - 5 - 1 - - - RAEFACIM - Received alignment error frame alignment - counter interrupt mask - 6 - 1 - - - RUGFCIM - Received unicast good frame counter - interrupt mask - 17 - 1 - - - - - MMCTIM - MMCTIM - Ethernet MMC transmit interrupt mask register - 0x10 - 0x20 - read-write - 0x00000000 - - - TSCGFCIM - Transmit single collision good frame - counter interrupt mask - 14 - 1 - - - TMCGFCIM - Transmit multiple collision good frame - counter interrupt mask - 15 - 1 - - - TGFCIM - Transmitted good frame counter interrupt - mask - 21 - 1 - - - - - MMCTFSCC - MMCTFSCC - Ethernet MMC transmitted good frames after a single collision counter - 0x4C - 0x20 - read-only - 0x00000000 - - - TGFSCC - Transmitted good frames single - collision counter - 0 - 32 - - - - - MMCTFMSCC - MMCTFMSCC - Ethernet MMC transmitted good frames after more than a single collision - 0x50 - 0x20 - read-only - 0x00000000 - - - TGFMSCC - Transmitted good frame more single - collision counter - 0 - 32 - - - - - MMCTFCNT - MMCTFCNT - Ethernet MMC transmitted good frames counter register - 0x68 - 0x20 - read-only - 0x00000000 - - - TGFC - Transmitted good frames - counter - 0 - 32 - - - - - MMCRFCECNT - MMCRFCECNT - Ethernet MMC received frames with CRC error counter register - 0x94 - 0x20 - read-only - 0x00000000 - - - RFCEC - Received frames CRC error counter - 0 - 32 - - - - - MMCRFAECNT - MMCRFAECNT - Ethernet MMC received frames with alignment error counter register - 0x98 - 0x20 - read-only - 0x00000000 - - - RFAEC - Received frames alignment error counter - 0 - 32 - - - - - MMCRGUFCNT - MMCRGUFCNT - MMC received good unicast frames counter register - 0xC4 - 0x20 - read-only - 0x00000000 - - - RGUFC - Received good unicast frames - counter - 0 - 32 - - - - - - - ETHERNET_PTP - Ethernet: Precision time protocol - ETHERNET - 0x40028700 - - 0x0 - 0x100 - registers - - - - PTPTSCTRL - PTPTSCTRL - Ethernet PTP time stamp control register - 0x0 - 0x20 - read-write - 0x2000 - - - TE - Timestamp enable - 0 - 1 - - - TFCU - Timestamp fine or coarse - update - 1 - 1 - - - TI - Timestamp initialize - 2 - 1 - - - TU - Timestamp update - 3 - 1 - - - TITE - Timestamp interrupt trigger - enable - 4 - 1 - - - ARU - Addend register update - 5 - 1 - - - ETAF - Enable timestamp for all frames - 8 - 1 - - - TDBRC - Timestamp digital or binary - rollover control - 9 - 1 - - - EPPV2F - Enable PTP packet processing for - version2 format - 10 - 1 - - - EPPEF - Enable processing of PTP - over EMAC frames - 11 - 1 - - - EPPFSIP6U - Enable processing of PTP frames - sent over IPv6-UDP - 12 - 1 - - - EPPFSIP4U - Enable processing of PTP frames - sent over IPv4-UDP - 13 - 1 - - - ETSFEM - Enable timestamp snapshot for - event message - 14 - 1 - - - ESFMRTM - Enable snapshot for message - relevant to master - 15 - 1 - - - SPPFTS - Select PTP packet for taking snapshot - 16 - 2 - - - EMAFPFF - Enable MAC address for PTP frame filtering - 18 - 1 - - - - - PTPSSINC - PTPSSINC - Ethernet PTP subsecond increment register - 0x4 - 0x20 - read-write - 0x00000000 - - - SSIV - Sub-second increment value - 0 - 8 - - - - - PTPTSH - PTPTSH - Ethernet PTP time stamp high register - 0x8 - 0x20 - read-only - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSL - PTPTSL - Ethernet PTP time stamp low register - 0xC - 0x20 - read-only - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSHUD - PTPTSHUD - Ethernet PTP time stamp high update register - 0x10 - 0x20 - read-write - 0x00000000 - - - TS - Timestamp second - 0 - 32 - - - - - PTPTSLUD - PTPTSLUD - Ethernet PTP time stamp low update register - 0x14 - 0x20 - read-write - 0x00000000 - - - TSS - Timestamp subseconds - 0 - 31 - - - AST - Add or subtract time - 31 - 1 - - - - - PTPTSAD - PTPTSAD - Ethernet PTP time stamp addend register - 0x18 - 0x20 - read-write - 0x00000000 - - - TAR - Timestamp addend register - 0 - 32 - - - - - PTPTTH - PTPTTH - Ethernet PTP target time high register - 0x1C - 0x20 - read-write - 0x00000000 - - - TTSR - Target time seconds register - 0 - 32 - - - - - PTPTTL - PTPTTL - Ethernet PTP target time low register - 0x20 - 0x20 - read-write - 0x00000000 - - - TTLR - Target timestamp low register - 0 - 32 - - - - - PTPTSSR - PTPTSSR - Ethernet PTP time stamp status register - 0x28 - 0x20 - read-only - 0x00000000 - - - TSO - Timestamp second overflow - 0 - 1 - - - TTTR - Timestamp target time reached - 1 - 1 - - - - - PTPPPSCR - PTPPPSCR - Ethernet PTP PPS control register - 0x2C - 0x20 - read-only - 0x00000000 - - - POFC - PPS Output frequency control - 0 - 4 - - - - - - - ETHERNET_DMA - Ethernet: DMA controller operation - ETHERNET - 0x40029000 - - 0x0 - 0x100 - registers - - - - DMABM - DMABM - Ethernet DMA bus mode register - 0x0 - 0x20 - read-write - 0x20101 - - - SWR - Software reset - 0 - 1 - - - DA - DMA Arbitration - 1 - 1 - - - DSL - Descriptor skip length - 2 - 5 - - - PBL - Programmable burst length - 8 - 6 - - - PR - Priority ratio - 14 - 2 - - - FB - Fixed burst - 16 - 1 - - - RDP - Rx DMA PBL - 17 - 6 - - - USP - Use separate PBL - 23 - 1 - - - PBLx8 - PNLx8 mode - 24 - 1 - - - AAB - Address-aligned beats - 25 - 1 - - - - - DMATPD - DMATPD - Ethernet DMA transmit poll demand register - 0x4 - 0x20 - read-write - 0x00000000 - - - TPD - Transmit poll demand - 0 - 32 - - - - - DMARPD - DMARPD - EHERNET DMA receive poll demand register - 0x8 - 0x20 - read-write - 0x00000000 - - - RPD - Receive poll demand - 0 - 32 - - - - - DMARDLADDR - DMARDLADDR - Ethernet DMA receive descriptor list address register - 0xC - 0x20 - read-write - 0x00000000 - - - SRL - Start of receive list - 0 - 32 - - - - - DMATDLADDR - DMATDLADDR - Ethernet DMA transmit descriptor list address register - 0x10 - 0x20 - read-write - 0x00000000 - - - STL - Start of transmit list - 0 - 32 - - - - - DMASTS - DMASTS - Ethernet DMA status register - 0x14 - 0x20 - 0x00000000 - - - TI - Transmit interrupt - 0 - 1 - read-write - - - TPS - Transmit process stopped - 1 - 1 - read-write - - - TBU - Transmit buffer unavailable - 2 - 1 - read-write - - - TJT - Transmit jabber timeout - 3 - 1 - read-write - - - OVF - Receive overflow - 4 - 1 - read-write - - - UNF - Transmit underflow - 5 - 1 - read-write - - - RI - Receive interrupt - 6 - 1 - read-write - - - RBU - Receive buffer unavailable - 7 - 1 - read-write - - - RPS - Receive process stopped - 8 - 1 - read-write - - - RWT - Receive watchdog timeout - 9 - 1 - read-write - - - ETI - Early transmit interrupt - 10 - 1 - read-write - - - FBEI - Fatal bus error interrupt - 13 - 1 - read-write - - - ERI - Early receive interrupt - 14 - 1 - read-write - - - AIS - Abnormal interrupt summary - 15 - 1 - read-write - - - NIS - Normal interrupt summary - 16 - 1 - read-write - - - RS - Receive process state - 17 - 3 - read-only - - - TS - Transmit process state - 20 - 3 - read-only - - - EB - Error bits - 23 - 3 - read-only - - - MMI - MAC MMC interrupt - 27 - 1 - read-only - - - MPI - MAC PMT interrupt - 28 - 1 - read-only - - - TTI - Timestamp trigger interrupt - 29 - 1 - read-only - - - - - DMAOPM - DMAOPM - Ethernet DMA operation mode register - 0x18 - 0x20 - read-write - 0x00000000 - - - SSR - Start or stop receive - 1 - 1 - - - OSF - Operate on second frame - 2 - 1 - - - RTC - Receive threshold control - 3 - 2 - - - FUGF - Forward undersized good frames - 6 - 1 - - - FEF - Forward error frames - 7 - 1 - - - SSTC - Start of stop transmission command - 13 - 1 - - - TTC - Transmit threshold control - 14 - 3 - - - FTF - Flush transmit FIFO - 20 - 1 - - - TSF - Transmit store and forward - 21 - 1 - - - DFRF - Disable flushing of received - frames - 24 - 1 - - - RSF - Receive store and forward - 25 - 1 - - - DT - Disable dropping of TCP/IP - checksum error frames - 26 - 1 - - - - - DMAIE - DMAIE - Ethernet DMA interrupt enable register - 0x1C - 0x20 - read-write - 0x00000000 - - - TIE - Transmit interrupt enable - 0 - 1 - - - TSE - Transmit stopped enable - 1 - 1 - - - TUE - Transmit buffer unavailable enable - 2 - 1 - - - TJE - Transmit jabber timeout enable - 3 - 1 - - - OVE - Overflow interrupt enable - 4 - 1 - - - UNE - Underflow interrupt enable - 5 - 1 - - - RIE - Receive interrupt enable - 6 - 1 - - - RBUE - Receive buffer unavailable enable - 7 - 1 - - - RSE - Receive stopped enable - 8 - 1 - - - RWTE - receive watchdog timeout enable - 9 - 1 - - - EIE - Early transmit interrupt enable - 10 - 1 - - - FBEE - Fatal bus error enable - 13 - 1 - - - ERE - Early receive interrupt - enable - 14 - 1 - - - AIE - Abnormal interrupt enable - 15 - 1 - - - NIE - Normal interrupt enable - 16 - 1 - - - - - DMAMFBOCNT - DMAMFBOCNT - Ethernet DMA missed frame and buffer overflow counter register - 0x20 - 0x20 - read-only - 0x00000000 - - - MFC - Missed frames control - 0 - 16 - - - OBMFC - Overflow bit for missed frame - counter - 16 - 1 - - - OFC - Overflow frame counter - 17 - 11 - - - OBFOC - Overflow bit for FIFO overflow - counter - 28 - 1 - - - - - DMACTD - DMACTD - Ethernet DMA current host transmit descriptor register - 0x48 - 0x20 - read-only - 0x00000000 - - - HTDAP - Host transmit descriptor address pointer - 0 - 32 - - - - - DMACRD - DMACRD - Ethernet DMA current host receive descriptor register - 0x4C - 0x20 - read-only - 0x00000000 - - - HRDAP - Host receive descriptor address pointer - 0 - 32 - - - - - DMACTBADDR - DMACTBADDR - Ethernet DMA current host transmit buffer address register - 0x50 - 0x20 - read-only - 0x00000000 - - - HTBAP - Host transmit buffer address pointer - 0 - 32 - - - - - DMACRBADDR - DMACRBADDR - Ethernet DMA current host receive buffer address register - 0x54 - 0x20 - read-only - 0x00000000 - - - HRBAP - Host receive buffer address pointer - 0 - 32 - - - - - - - diff --git a/hw/bsp/at32f435_437/family.c b/hw/bsp/at32f435_437/family.c index c238fff32..03bb5674b 100644 --- a/hw/bsp/at32f435_437/family.c +++ b/hw/bsp/at32f435_437/family.c @@ -36,11 +36,11 @@ int inHandlerMode(void); //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void OTGFS1_IRQHandler(void) +void OTGFS1_IRQHandler(void) { tusb_int_handler(0, true); } -void OTGFS2_IRQHandler(void) +void OTGFS2_IRQHandler(void) { tusb_int_handler(1, true); } @@ -53,7 +53,7 @@ void OTGFS2_WKUP_IRQHandler(void) tusb_int_handler(1, true); } -void board_init(void) +void board_init(void) { /* config nvic priority group */ nvic_priority_group_config(NVIC_PRIORITY_GROUP_4); @@ -185,7 +185,7 @@ void usb_clock48m_select(usb_clk48_s clk_s) } } -void led_and_botton_init(void) +void led_and_botton_init(void) { /* LED */ gpio_init_type gpio_led_init_struct; @@ -245,7 +245,7 @@ void uart_print_init(uint32_t baudrate) } // Get characters from UART. Return number of read bytes -int board_uart_read(uint8_t *buf, int len) +int board_uart_read(uint8_t *buf, int len) { (void) buf; (void) len; @@ -257,7 +257,7 @@ int board_uart_write(void const *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE int txsize = len; u16 timeout = 0xffff; - while (txsize--) + while (txsize--) { while(usart_flag_get(PRINT_UART, USART_TDBE_FLAG) == RESET) { @@ -280,7 +280,7 @@ int board_uart_write(void const *buf, int len) int inHandlerMode(void) { - return __get_IPSR(); + return __get_IPSR(); } void usb_gpio_config(void) @@ -312,17 +312,17 @@ void usb_gpio_config(void) #endif } -void board_led_write(bool state) +void board_led_write(bool state) { gpio_bits_write(LED_PORT, LED_PIN, state ^ (!LED_STATE_ON)); } -uint32_t board_button_read(void) +uint32_t board_button_read(void) { return gpio_input_data_bit_read(BUTTON_PORT, BUTTON_PIN); } -size_t board_get_unique_id(uint8_t id[], size_t max_len) +size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; volatile uint32_t * at32_uuid = ((volatile uint32_t*)0x1FFFF7E8); @@ -338,11 +338,11 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; - void SysTick_Handler(void) + void SysTick_Handler(void) { system_ticks++; } - uint32_t board_millis(void) + uint32_t board_millis(void) { return system_ticks; } @@ -354,7 +354,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) } #endif -void HardFault_Handler(void) +void HardFault_Handler(void) { __asm("BKPT #0\n"); } diff --git a/hw/bsp/at32f435_437/family.mk b/hw/bsp/at32f435_437/family.mk index 47731b621..f712a573d 100644 --- a/hw/bsp/at32f435_437/family.mk +++ b/hw/bsp/at32f435_437/family.mk @@ -1,6 +1,5 @@ # Submodules AT32F435_437_SDK = hw/mcu/artery/at32f435_437 -DEPS_SUBMODULES += $(AT32F435_437_SDK) # AT32 SDK path AT32F435_437_SDK_SRC = $(AT32F435_437_SDK)/libraries diff --git a/hw/bsp/at32f435_437/startup_at32f435_437.s b/hw/bsp/at32f435_437/startup_at32f435_437.s index aa1aa3f4a..70bc4ec89 100644 --- a/hw/bsp/at32f435_437/startup_at32f435_437.s +++ b/hw/bsp/at32f435_437/startup_at32f435_437.s @@ -78,7 +78,7 @@ LoopFillZerobss: cmp r2, r3 bcc FillZerobss -/* Call the clock system intitialization function.*/ +/* Call the clock system initialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h index 10832a702..1150d825b 100644 --- a/src/portable/synopsys/dwc2/dwc2_at32.h +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -109,13 +109,13 @@ static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) { (void) dwc2; // Enable on-chip HS PHY - if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { - + } else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { - + } } -- cgit v1.3.1 From e0f2343954c71743358f2b2362bef64bbc68e4a3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Jul 2025 23:26:27 +0700 Subject: clean up --- src/portable/st/stm32_fsdev/fsdev_at32.h | 148 +++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_at32.h | 106 ++++++++++------------ src/portable/synopsys/dwc2/dwc2_common.c | 16 ++-- 3 files changed, 124 insertions(+), 146 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h index 5f2ce4ba2..3a785bbbd 100644 --- a/src/portable/st/stm32_fsdev/fsdev_at32.h +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -35,82 +35,6 @@ #endif -//#include "fsdev_common.h" - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - -#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) -static const IRQn_Type fsdev_irq[] = { - USBFS_H_CAN1_TX_IRQn, - USBFS_L_CAN1_RX0_IRQn, - USBFSWakeUp_IRQn -}; -enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; - -#else - #error "Unsupported MCU" -#endif - -void dcd_int_enable(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) - // AT32F403A/407 devices allow to remap the USB interrupt vectors from - // shared USB/CAN IRQs to separate CAN and USB IRQs. - // This dynamically checks if this remap is active to enable the right IRQs. - if (CRM->intmap_bit.usbintmap) { - NVIC_DisableIRQ(USBFS_MAPH_IRQn); - NVIC_DisableIRQ(USBFS_MAPL_IRQn); - NVIC_DisableIRQ(USBFSWakeUp_IRQn); - } else - #endif - { - for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { - NVIC_EnableIRQ(fsdev_irq[i]); - } - } -} - -void dcd_int_disable(uint8_t rhport) { - (void)rhport; - #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) - // AT32F403A/407 devices allow to remap the USB interrupt vectors from - // shared USB/CAN IRQs to separate CAN and USB IRQs. - // This dynamically checks if this remap is active to enable the right IRQs. - if (CRM->intmap_bit.usbintmap) { - NVIC_DisableIRQ(USBFS_MAPH_IRQn); - NVIC_DisableIRQ(USBFS_MAPL_IRQn); - NVIC_DisableIRQ(USBFSWakeUp_IRQn); - } else - #endif - { - for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { - NVIC_DisableIRQ(fsdev_irq[i]); - } - } -} - -void dcd_disconnect(uint8_t rhport) { - (void) rhport; - /* disable usb phy */ - //USB->ctrl_bit.disusb = TRUE; - *(int *)(0x40000000+0x5C00+0x40) |= (1<<1); - *(int *)(0x40000000+0x5C00+0x60) |= (1<<1); - /* D+ 1.5k pull-up disable */ - //USB->cfg_bit.puo = TRUE; -} - -void dcd_connect(uint8_t rhport) { - (void) rhport; - /* enable usb phy */ - //USB->ctrl_bit.disusb = 0; - *(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1); - *(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1); - /* Dp 1.5k pull-up enable */ - //USB->cfg_bit.puo = 0; -} - #define FSDEV_PMA_SIZE (512u) #define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) #define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) @@ -221,4 +145,76 @@ void dcd_connect(uint8_t rhport) { #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */ #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) +#include "fsdev_type.h" + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ + +#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) +static const IRQn_Type fsdev_irq[] = { + USBFS_H_CAN1_TX_IRQn, + USBFS_L_CAN1_RX0_IRQn, + USBFSWakeUp_IRQn +}; +enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) }; + +#else + #error "Unsupported MCU" +#endif + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_EnableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + #if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413) + // AT32F403A/407 devices allow to remap the USB interrupt vectors from + // shared USB/CAN IRQs to separate CAN and USB IRQs. + // This dynamically checks if this remap is active to enable the right IRQs. + if (CRM->intmap_bit.usbintmap) { + NVIC_DisableIRQ(USBFS_MAPH_IRQn); + NVIC_DisableIRQ(USBFS_MAPL_IRQn); + NVIC_DisableIRQ(USBFSWakeUp_IRQn); + } else + #endif + { + for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) { + NVIC_DisableIRQ(fsdev_irq[i]); + } + } +} + +void dcd_disconnect(uint8_t rhport) { + (void) rhport; + /* disable usb phy */ + FSDEV_REG->CNTR |= USB_CNTR_PDWN; + /* D+ 1.5k pull-up disable, USB->cfg_bit.puo = TRUE; */ + *(uint32_t *)(FSDEV_REG_BASE+0x60) |= (1u<<1); +} + +void dcd_connect(uint8_t rhport) { + (void) rhport; + /* enable usb phy */ + FSDEV_REG->CNTR &= ~USB_CNTR_PDWN; + /* Dp 1.5k pull-up enable, USB->cfg_bit.puo = 0; */ + *(uint32_t *)(FSDEV_REG_BASE+0x60) &= ~(1u<<1); +} + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_at32.h b/src/portable/synopsys/dwc2/dwc2_at32.h index 1150d825b..37b6592c4 100644 --- a/src/portable/synopsys/dwc2/dwc2_at32.h +++ b/src/portable/synopsys/dwc2/dwc2_at32.h @@ -67,66 +67,52 @@ extern "C" { #endif -static const dwc2_controller_t _dwc2_controller[] = -{ - { .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE }, - #if defined DWC2_OTG2_REG_BASE - { .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE } - #endif -}; - -TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { - (void) role; - const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; - if (enabled) { - NVIC_EnableIRQ(irqn); - } else { - NVIC_DisableIRQ(irqn); - } -} - -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_enable(uint8_t rhport) -{ - NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); -} - -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_disable (uint8_t rhport) -{ - NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); -} - -static inline void dwc2_remote_wakeup_delay(void) -{ - // try to delay for 1 ms - uint32_t count = system_core_clock / 1000; - while ( count-- ) __asm volatile ("nop"); -} - -// MCU specific PHY init, called BEFORE core reset -static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - // Enable on-chip HS PHY - if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) - { - - } - else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) - { - - } -} - -// MCU specific PHY update, it is called AFTER init() and core reset -static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - (void) hs_phy_type; - - dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; -} + static const dwc2_controller_t _dwc2_controller[] = { +{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE}, +#if defined DWC2_OTG2_REG_BASE + {.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE} +#endif + }; + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum); + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { + NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum); + } + + TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { + // try to delay for 1 ms + uint32_t count = system_core_clock / 1000; + while (count--) __asm volatile("nop"); + } + + // MCU specific PHY init, called BEFORE core reset + TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { + (void) dwc2; + // Enable on-chip HS PHY + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { + } else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { + } + } + + // MCU specific PHY update, it is called AFTER init() and core reset + TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) { + (void) dwc2; + (void) hs_phy_type; + + dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN; + } #ifdef __cplusplus } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 56326d5a7..b001f343d 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -120,13 +120,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (ghwcfg4.phy_data_width) { + #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit gusbcfg |= GUSBCFG_PHYIF16; // 16 bit - - /* at32f402_405 does not actually support 16-bit */ - #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 - gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit #endif - } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } @@ -145,12 +141,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; - /* at32f402_405 does not actually support 16-bit */ - #if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos; - #endif +#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit + gusbcfg |= 9u << GUSBCFG_TRDT_Pos; +#else + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; +#endif dwc2->gusbcfg = gusbcfg; -- cgit v1.3.1 From f5974b041e858badab1fbf187926efa8b79367cd Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Aug 2025 22:44:32 +0700 Subject: add bufsize to tud_msc_inquiry2_cb() --- examples/device/cdc_msc/src/msc_disk.c | 3 ++- examples/device/cdc_msc_freertos/src/msc_disk.c | 5 +++-- examples/device/dynamic_configuration/src/msc_disk.c | 3 ++- examples/device/msc_dual_lun/src/msc_disk_dual.c | 3 ++- src/class/msc/msc_device.c | 6 +++--- src/class/msc/msc_device.h | 2 +- test/unit-test/test/device/msc/test_msc_device.c | 3 ++- 7 files changed, 15 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/examples/device/cdc_msc/src/msc_disk.c b/examples/device/cdc_msc/src/msc_disk.c index 6fd42dd80..96f9f19ec 100644 --- a/examples/device/cdc_msc/src/msc_disk.c +++ b/examples/device/cdc_msc/src/msc_disk.c @@ -119,8 +119,9 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = { // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t *inquiry_resp, uint32_t bufsize) { (void) lun; + (void) bufsize; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; diff --git a/examples/device/cdc_msc_freertos/src/msc_disk.c b/examples/device/cdc_msc_freertos/src/msc_disk.c index 3a652103f..3602c991d 100644 --- a/examples/device/cdc_msc_freertos/src/msc_disk.c +++ b/examples/device/cdc_msc_freertos/src/msc_disk.c @@ -166,7 +166,7 @@ static void io_task(void *params) { io_ops_t io_ops; while (1) { if (xQueueReceive(io_queue, &io_ops, portMAX_DELAY)) { - const uint8_t* addr = msc_disk[io_ops.lba] + io_ops.offset; + uint8_t* addr = (uint8_t*) (uintptr_t) (msc_disk[io_ops.lba] + io_ops.offset); int32_t nbytes = io_ops.bufsize; if (io_ops.is_read) { memcpy(io_ops.buffer, addr, io_ops.bufsize); @@ -191,8 +191,9 @@ void msc_disk_init() {} // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp, uint32_t bufsize) { (void) lun; + (void) bufsize; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; diff --git a/examples/device/dynamic_configuration/src/msc_disk.c b/examples/device/dynamic_configuration/src/msc_disk.c index 8987c06be..ebc86e260 100644 --- a/examples/device/dynamic_configuration/src/msc_disk.c +++ b/examples/device/dynamic_configuration/src/msc_disk.c @@ -119,8 +119,9 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE] = // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t *inquiry_resp, uint32_t bufsize) { (void) lun; + (void) bufsize; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; diff --git a/examples/device/msc_dual_lun/src/msc_disk_dual.c b/examples/device/msc_dual_lun/src/msc_disk_dual.c index a1ad220b3..98016808a 100644 --- a/examples/device/msc_dual_lun/src/msc_disk_dual.c +++ b/examples/device/msc_dual_lun/src/msc_disk_dual.c @@ -210,8 +210,9 @@ uint8_t tud_msc_get_maxlun_cb(void) { // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t *inquiry_resp, uint32_t bufsize) { (void) lun; + uint32_t bufsize const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 3a4b34e7e..a32014c2d 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -47,8 +47,8 @@ TU_ATTR_WEAK void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16], uint8_t product_rev[4]) { (void) lun; (void) vendor_id; (void) product_id; (void) product_rev; } -TU_ATTR_WEAK uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { - (void) lun; (void) inquiry_resp; +TU_ATTR_WEAK uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t *inquiry_resp, uint32_t bufsize) { + (void) lun; (void) inquiry_resp; (void) bufsize; return 0; } @@ -749,7 +749,7 @@ static int32_t proc_builtin_scsi(uint8_t lun, uint8_t const scsi_cmd[16], uint8_ inquiry_rsp->response_data_format = 2; inquiry_rsp->additional_length = sizeof(scsi_inquiry_resp_t) - 5; - resplen = (int32_t) tud_msc_inquiry2_cb(lun, inquiry_rsp); + resplen = (int32_t) tud_msc_inquiry2_cb(lun, inquiry_rsp, bufsize); if (resplen == 0) { // stub callback with no response, use v1 callback tud_msc_inquiry_cb(lun, inquiry_rsp->vendor_id, inquiry_rsp->product_id, inquiry_rsp->product_rev); diff --git a/src/class/msc/msc_device.h b/src/class/msc/msc_device.h index 195c6fa87..144b74f71 100644 --- a/src/class/msc/msc_device.h +++ b/src/class/msc/msc_device.h @@ -97,7 +97,7 @@ void tud_msc_inquiry_cb(uint8_t lun, uint8_t vendor_id[8], uint8_t product_id[16 // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp); +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t *inquiry_resp, uint32_t bufsize); // Invoked when received Test Unit Ready command. // return true allowing host to read/write this LUN e.g SD card inserted diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index e05e9c8b0..49843a921 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -97,8 +97,9 @@ uint8_t msc_disk[DISK_BLOCK_NUM][DISK_BLOCK_SIZE]; // Invoked when received SCSI_CMD_INQUIRY, v2 with full inquiry response // Some inquiry_resp's fields are already filled with default values, application can update them // Return length of inquiry response, typically sizeof(scsi_inquiry_resp_t) (36 bytes), can be longer if included vendor data. -uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp) { +uint32_t tud_msc_inquiry2_cb(uint8_t lun, scsi_inquiry_resp_t* inquiry_resp, uint32_t bufsize) { (void) lun; + (void) bufsize; const char vid[] = "TinyUSB"; const char pid[] = "Mass Storage"; const char rev[] = "1.0"; -- cgit v1.3.1 From 12a1d0e7ede97c793a5e11b3cce7284cdbe994c8 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 2 Aug 2025 11:23:15 +0700 Subject: use tu_desc_in_bounds() for descriptor loop --- src/class/midi/midi_host.c | 19 ++++++++++--------- src/class/vendor/vendor_device.c | 2 +- src/common/tusb_common.h | 38 ++++++++++++++++++++++++++++++++++++++ src/common/tusb_types.h | 40 ---------------------------------------- 4 files changed, 49 insertions(+), 50 deletions(-) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 2395a0ef8..50bda1e36 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -197,6 +197,7 @@ bool midih_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint //--------------------------------------------------------------------+ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { (void) rhport; + TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); const uint8_t *p_end = ((const uint8_t *) desc_itf) + max_len; const uint8_t *p_desc = (const uint8_t *) desc_itf; @@ -210,9 +211,8 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d desc_cb.jack_num = 0; // There can be just a MIDI or an Audio + MIDI interface - // If there is Audio Control Interface + Audio Header descriptor, then skip it. - // If there is an Audio Control Interface + Audio Streaming Interface, then - // ignore the Audio Streaming Interface. + // - If there is Audio Control Interface + Audio Header descriptor, then skip it. + // - If there is an Audio Control Interface + Audio Streaming Interface, then ignore the Audio Streaming Interface. // Future: // Note that if this driver is used with an USB Audio Streaming host driver, // then call that driver first. If the MIDI interface comes before the @@ -230,19 +230,20 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d p_desc = tu_desc_next(p_desc); desc_itf = (const tusb_desc_interface_t *)p_desc; p_midi->itf_count = 1; - // See issue #3159 - while ((p_desc < p_end) && (tu_desc_next(p_desc) <= p_end) && (desc_itf->bDescriptorType != TUSB_DESC_INTERFACE || (desc_itf->bInterfaceClass == TUSB_CLASS_AUDIO && desc_itf->bInterfaceSubClass != AUDIO_SUBCLASS_MIDI_STREAMING))) - { + // skip non-interface and non-midi streaming descriptors + while (tu_desc_in_bounds(p_desc, p_end) && + (desc_itf->bDescriptorType != TUSB_DESC_INTERFACE || (desc_itf->bInterfaceClass == TUSB_CLASS_AUDIO && desc_itf->bInterfaceSubClass != AUDIO_SUBCLASS_MIDI_STREAMING))) { if (desc_itf->bDescriptorType == TUSB_DESC_INTERFACE && desc_itf->bAlternateSetting == 0) { p_midi->itf_count++; } p_desc = tu_desc_next(p_desc); desc_itf = (tusb_desc_interface_t const *)p_desc; } - TU_VERIFY(p_desc < p_end); // If MIDI interface comes after Audio Streaming, then max_len did not include the MIDI interface descriptor + TU_VERIFY(p_desc < p_end); // TODO: If MIDI interface comes after Audio Streaming, then max_len did not include the MIDI interface descriptor TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass); -} + } TU_VERIFY(AUDIO_SUBCLASS_MIDI_STREAMING == desc_itf->bInterfaceSubClass); + TU_LOG_DRV("MIDI opening Interface %u (addr = %u)\r\n", desc_itf->bInterfaceNumber, dev_addr); p_midi->bInterfaceNumber = desc_itf->bInterfaceNumber; p_midi->iInterface = desc_itf->iInterface; @@ -252,7 +253,7 @@ bool midih_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *d p_desc = tu_desc_next(p_desc); // next to CS Header bool found_new_interface = false; - while ((p_desc < p_end) && (tu_desc_next(p_desc) <= p_end) && !found_new_interface) { + while (tu_desc_in_bounds(p_desc, p_end) && !found_new_interface) { switch (tu_desc_type(p_desc)) { case TUSB_DESC_INTERFACE: found_new_interface = true; diff --git a/src/class/vendor/vendor_device.c b/src/class/vendor/vendor_device.c index 6f109c321..b0332b0fe 100644 --- a/src/class/vendor/vendor_device.c +++ b/src/class/vendor/vendor_device.c @@ -211,7 +211,7 @@ uint16_t vendord_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uin TU_VERIFY(p_vendor, 0); p_vendor->itf_num = desc_itf->bInterfaceNumber; - while (tu_desc_is_valid(p_desc, desc_end)) { + while (tu_desc_in_bounds(p_desc, desc_end)) { const uint8_t desc_type = tu_desc_type(p_desc); if (desc_type == TUSB_DESC_INTERFACE || desc_type == TUSB_DESC_INTERFACE_ASSOCIATION) { break; // end of this interface diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 0351a3d8f..489e09a15 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -324,6 +324,44 @@ TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void *mem, uint16_ + TU_BIN8(dlsb)) #endif +//--------------------------------------------------------------------+ +// Descriptor helper +//--------------------------------------------------------------------+ + +// return next descriptor +TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) { + uint8_t const* desc8 = (uint8_t const*) desc; + return desc8 + desc8[DESC_OFFSET_LEN]; +} + +// get descriptor length +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) { + return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; +} + +// get descriptor type +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) { + return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; +} + +// get descriptor subtype +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_subtype(void const* desc) { + return ((uint8_t const*) desc)[DESC_OFFSET_SUBTYPE]; +} + +TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_in_bounds(uint8_t const* p_desc, uint8_t const* desc_end) { + return (p_desc < desc_end) && (tu_desc_next(p_desc) <= desc_end); +} + +// find descriptor that match byte1 (type) +uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1); + +// find descriptor that match byte1 (type) and byte2 +uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2); + +// find descriptor that match byte1 (type) and byte2 +uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3); + #ifdef __cplusplus } #endif diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index ee97069bd..b3ef1e9c9 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -562,46 +562,6 @@ TU_ATTR_ALWAYS_INLINE static inline const char *tu_edpt_type_str(tusb_xfer_type_ } #endif -//--------------------------------------------------------------------+ -// Descriptor helper -//--------------------------------------------------------------------+ - -// return next descriptor -TU_ATTR_ALWAYS_INLINE static inline uint8_t const * tu_desc_next(void const* desc) { - uint8_t const* desc8 = (uint8_t const*) desc; - return desc8 + desc8[DESC_OFFSET_LEN]; -} - -// get descriptor length -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_len(void const* desc) { - return ((uint8_t const*) desc)[DESC_OFFSET_LEN]; -} - -// get descriptor type -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_type(void const* desc) { - return ((uint8_t const*) desc)[DESC_OFFSET_TYPE]; -} - -// get descriptor subtype -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_subtype(void const* desc) { - return ((uint8_t const*) desc)[DESC_OFFSET_SUBTYPE]; -} - -TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_desc_is_valid(void const* desc, uint8_t const* desc_end) { - const uint8_t* desc8 = (uint8_t const*) desc; - return (desc8 < desc_end) && (tu_desc_next(desc) <= desc_end); -} - - -// find descriptor that match byte1 (type) -uint8_t const * tu_desc_find(uint8_t const* desc, uint8_t const* end, uint8_t byte1); - -// find descriptor that match byte1 (type) and byte2 -uint8_t const * tu_desc_find2(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2); - -// find descriptor that match byte1 (type) and byte2 -uint8_t const * tu_desc_find3(uint8_t const* desc, uint8_t const* end, uint8_t byte1, uint8_t byte2, uint8_t byte3); - #ifdef __cplusplus } #endif -- cgit v1.3.1 From d9aa4c6f6184eacafb534bf462d7a90ca71aeac9 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 2 Aug 2025 23:23:20 +0700 Subject: fix tud_audio_set_itf_close_EP_cb() typo --- examples/device/audio_test/src/main.c | 2 +- examples/device/audio_test_freertos/src/main.c | 2 +- examples/device/audio_test_multi_rate/src/main.c | 2 +- examples/device/cdc_uac2/src/uac2_app.c | 2 +- examples/device/uac2_headset/src/main.c | 2 +- examples/device/uac2_speaker_fb/src/main.c | 2 +- src/class/audio/audio_device.c | 6 +++--- src/class/audio/audio_device.h | 5 ++++- 8 files changed, 13 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index 07728e24a..ec47de7b8 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -386,7 +386,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false;// Yet not implemented } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; (void) p_request; startVal = 0; diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index b1119c888..b2bed295f 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -457,7 +457,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false;// Yet not implemented } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; (void) p_request; startVal = 0; diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 704a75b09..87f56f4b5 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -455,7 +455,7 @@ bool tud_audio_get_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false;// Yet not implemented } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; (void) p_request; startVal = 0; diff --git a/examples/device/cdc_uac2/src/uac2_app.c b/examples/device/cdc_uac2/src/uac2_app.c index 7d5da5ed0..a1a0dd73d 100644 --- a/examples/device/cdc_uac2/src/uac2_app.c +++ b/examples/device/cdc_uac2/src/uac2_app.c @@ -257,7 +257,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false; } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request) +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request) { (void)rhport; diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 33b8ea0ef..06a673f91 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -291,7 +291,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false; } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex)); diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c index 12425b919..d9f6e9259 100644 --- a/examples/device/uac2_speaker_fb/src/main.c +++ b/examples/device/uac2_speaker_fb/src/main.c @@ -299,7 +299,7 @@ bool tud_audio_set_req_entity_cb(uint8_t rhport, tusb_control_request_t const *p return false; } -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex)); diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 278c4514a..bb906c7cf 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -402,7 +402,7 @@ TU_ATTR_WEAK bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t co } // Invoked when audio set interface request received which closes an EP -TU_ATTR_WEAK bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const *p_request) { +TU_ATTR_WEAK bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const *p_request) { (void) rhport; (void) p_request; return true; @@ -1078,7 +1078,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p tu_fifo_clear(&audio->ep_in_ff); // Invoke callback - can be used to stop data sampling - TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); + TU_VERIFY(tud_audio_set_itf_close_ep_cb(rhport, p_request)); audio->ep_in = 0;// Necessary? @@ -1101,7 +1101,7 @@ static bool audiod_set_interface(uint8_t rhport, tusb_control_request_t const *p tu_fifo_clear(&audio->ep_out_ff); // Invoke callback - can be used to stop data sampling - TU_VERIFY(tud_audio_set_itf_close_EP_cb(rhport, p_request)); + TU_VERIFY(tud_audio_set_itf_close_ep_cb(rhport, p_request)); audio->ep_out = 0;// Necessary? diff --git a/src/class/audio/audio_device.h b/src/class/audio/audio_device.h index 307389418..6bcedc88c 100644 --- a/src/class/audio/audio_device.h +++ b/src/class/audio/audio_device.h @@ -381,7 +381,10 @@ void tud_audio_int_done_cb(uint8_t rhport); bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const * p_request); // Invoked when audio set interface request received which closes an EP -bool tud_audio_set_itf_close_EP_cb(uint8_t rhport, tusb_control_request_t const * p_request); +bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request); + +// backward compatible for typo +#define tud_audio_set_itf_close_EP_cb tud_audio_set_itf_close_ep_cb // Invoked when audio class specific set request received for an EP bool tud_audio_set_req_ep_cb(uint8_t rhport, tusb_control_request_t const * p_request, uint8_t *pBuff); -- cgit v1.3.1 From 2298c2f410faaf3016ae0e43aa51be869d502bc9 Mon Sep 17 00:00:00 2001 From: peppapighs Date: Tue, 5 Aug 2025 18:17:27 +0700 Subject: Fix AT32F405xx missing USB HS definition --- src/common/tusb_mcu.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a91759b84..6632341d7 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -601,6 +601,15 @@ #define TUP_USBIP_DWC2_AT32 #define TUP_DCD_ENDPOINT_MAX 8 + // AT32F405xx has on-chip HS PHY + #if defined(AT32F405CBT7) || defined(AT32F405CBU7) || \ + defined(AT32F405CCT7) || defined(AT32F405CCU7) || \ + defined(AT32F405KBU7_4) || defined(AT32F405KCU7_4) || \ + defined(AT32F405RBT7_7) || defined(AT32F405RBT7) || \ + defined(AT32F405RCT7_7) || defined(AT32F405RCT7) + #define TUP_RHPORT_HIGHSPEED 1 // Port0: FS, Port1: HS + #endif + #elif TU_CHECK_MCU(OPT_MCU_AT32F425) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_AT32 -- cgit v1.3.1 From 4bfba6b09a90d5321b3dbd2d986760438417c430 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Aug 2025 22:05:56 +0700 Subject: fix rp2 iso transfer: reset state before notify stack. since new audio driver can execute xfer_is() --- examples/device/uac2_headset/src/main.c | 6 ++++-- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 06a673f91..d4c2b41d9 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -297,8 +297,9 @@ bool tud_audio_set_itf_close_ep_cb(uint8_t rhport, tusb_control_request_t const uint8_t const itf = tu_u16_low(tu_le16toh(p_request->wIndex)); uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue)); - if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt == 0) + if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt == 0) { blink_interval_ms = BLINK_MOUNTED; + } return true; } @@ -309,8 +310,9 @@ bool tud_audio_set_itf_cb(uint8_t rhport, tusb_control_request_t const *p_reques uint8_t const alt = tu_u16_low(tu_le16toh(p_request->wValue)); TU_LOG2("Set interface %d alt %d\r\n", itf, alt); - if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0) + if (ITF_NUM_AUDIO_STREAMING_SPK == itf && alt != 0) { blink_interval_ms = BLINK_STREAMING; + } // Clear buffer when streaming format is changed spk_data_size = 0; diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 358ce84bc..a89c2f42b 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -190,8 +190,9 @@ static void __tusb_irq_path_func(hw_handle_buff_status)(void) { bool done = hw_endpoint_xfer_continue(ep); if (done) { // Notify - dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true); + const uint16_t xferred_len = ep->xferred_len; hw_endpoint_reset_transfer(ep); + dcd_event_xfer_complete(0, ep->ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); } remaining_buffers &= ~bit; } -- cgit v1.3.1 From 5b9908a39ba089dfd56b3a23475be5d9691d13e8 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Aug 2025 14:20:40 +0700 Subject: update at32f405 dwc2 info and phy width selection --- src/portable/synopsys/dwc2/dwc2_common.c | 24 +++---- src/portable/synopsys/dwc2/dwc2_info.md | 116 +++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 2 + 3 files changed, 72 insertions(+), 70 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index b001f343d..70876a64c 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -92,6 +92,14 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; const dwc2_ghwcfg4_t ghwcfg4 = {.value = dwc2->ghwcfg4}; + uint8_t phy_width; + if (CFG_TUSB_MCU != OPT_MCU_AT32F402_405 && // at32f402_405 does not support 16-bit + ghwcfg4.phy_data_width) { + phy_width = 16; // 16-bit PHY interface if supported + } else { + phy_width = 8; // 8-bit PHY interface + } + // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; @@ -119,12 +127,10 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; // Set 16-bit interface if supported - if (ghwcfg4.phy_data_width) { - #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit - gusbcfg |= GUSBCFG_PHYIF16; // 16 bit - #endif + if (phy_width == 16) { + gusbcfg |= GUSBCFG_PHYIF16; } else { - gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + gusbcfg &= ~GUSBCFG_PHYIF16; } } @@ -141,13 +147,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - -#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit - gusbcfg |= 9u << GUSBCFG_TRDT_Pos; -#else - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; -#endif - + gusbcfg |= (phy_width == 16 ? 5u : 9u) << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 595c89b75..00685e7ad 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| | AT32 F405 FS | AT32 F405 HS | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | +|:---------------------------|:---------------|:---------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| +| GUID | 0x00002000 | 0x00000000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | n/a | UTMI+/ULPI | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 7 | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 15 | 15 | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 512 | 1008 | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 7 | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 3b1993cc5..bc5ad9a7b 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -9,6 +9,8 @@ import pandas as pd # Note: FS is FullSpeed, HS is HighSpeed dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4'] dwc2_reg_value = { + 'AT32 F405 FS': [0x00002000, 0x4F54400A, 0x00000000, 0x228FDD00, 0x020004E8, 0x1FF0A020], + 'AT32 F405 HS': [0x00000000, 0x4F54400A, 0x00000000, 0x229FDDD0, 0x03F006E8, 0x1FF0A020], 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030], -- cgit v1.3.1 From ddb8f0fe73fd733b0fd97462b14825dcb6039949 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Fri, 15 Aug 2025 10:15:24 -0700 Subject: Add ESP32-C5 and ESP32-C61 definitions --- src/common/tusb_mcu.h | 2 +- src/tusb_option.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 6632341d7..3ffc2d1a4 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -414,7 +414,7 @@ #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64 -#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) +#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C5, OPT_MCU_ESP32C6, OPT_MCU_ESP32C61, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) #error "MCUs are only supported with CFG_TUH_MAX3421 enabled" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 17bf556a3..1533bb209 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -128,6 +128,8 @@ #define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2 #define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2 #define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4 +#define OPT_MCU_ESP32C5 908 ///< Espressif ESP32-C5 +#define OPT_MCU_ESP32C61 909 ///< Espressif ESP32-C61 #define TUSB_MCU_VENDOR_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU #define TUP_MCU_ESPRESSIF TUSB_MCU_VENDOR_ESPRESSIF // for backward compatibility -- cgit v1.3.1 From e1cd4aa91f184f79e3c069968c9ee1f634daba3e Mon Sep 17 00:00:00 2001 From: ohmdelta <64962148+ohmdelta@users.noreply.github.com> Date: Wed, 20 Aug 2025 01:23:33 +0100 Subject: add some consumer page configs --- src/class/hid/hid.h | 393 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 388 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h index c2434c20d..0fc0e1377 100644 --- a/src/class/hid/hid.h +++ b/src/class/hid/hid.h @@ -893,14 +893,51 @@ enum { /// HID Usage Table: Consumer Page (0x0C) /// Only contains controls that supported by Windows (whole list is too long) enum { + HID_USAGE_CONSUMER_UNASSIGNED = 0x0000, + // Generic Control HID_USAGE_CONSUMER_CONTROL = 0x0001, + HID_USAGE_CONSUMER_NUMERIC_KEY_PAD = 0x0002, + HID_USAGE_CONSUMER_PROGRAMMABLE_BUTTONS = 0x0003, + HID_USAGE_CONSUMER_MICROPHONE = 0x0004, + HID_USAGE_CONSUMER_HEADPHONE = 0x0005, + HID_USAGE_CONSUMER_GRAPHIC_EQUALIZER = 0x0006, + // 07-1F Reserved + + HID_USAGE_CONSUMER_PLUS_10 = 0x0020, + HID_USAGE_CONSUMER_PLUS_100 = 0x0021, + HID_USAGE_CONSUMER_AM_PM = 0x0022, + // 23-3F Reserved // Power Control HID_USAGE_CONSUMER_POWER = 0x0030, HID_USAGE_CONSUMER_RESET = 0x0031, HID_USAGE_CONSUMER_SLEEP = 0x0032, + HID_USAGE_CONSUMER_SLEEP_AFTER = 0x0033, + HID_USAGE_CONSUMER_SLEEP_MODE = 0x0034, + HID_USAGE_CONSUMER_ILLUMINATION = 0x0035, + HID_USAGE_CONSUMER_FUNCTION_BUTTONS = 0x0036, + // 37-3F Reserved + HID_USAGE_CONSUMER_MENU = 0x0040, + HID_USAGE_CONSUMER_MENU_PICK = 0x0041, + HID_USAGE_CONSUMER_MENU_UP = 0x0042, + HID_USAGE_CONSUMER_MENU_DOWN = 0x0043, + HID_USAGE_CONSUMER_MENU_LEFT = 0x0044, + HID_USAGE_CONSUMER_MENU_RIGHT = 0x0045, + HID_USAGE_CONSUMER_MENU_ESCAPE = 0x0046, + HID_USAGE_CONSUMER_MENU_VALUE_INCREASE = 0x0047, + HID_USAGE_CONSUMER_MENU_VALUE_DECREASE = 0x0048, + // 49-5F Reserved + HID_USAGE_CONSUMER_DATA_ON_SCREEN = 0x0060, + HID_USAGE_CONSUMER_CLOSED_CAPTION = 0x0061, + HID_USAGE_CONSUMER_CLOSED_CAPTION_SELECT = 0x0062, + HID_USAGE_CONSUMER_VCR_TV = 0x0063, + HID_USAGE_CONSUMER_BROADCAST_MODE = 0x0064, + HID_USAGE_CONSUMER_SNAPSHOT = 0x0065, + HID_USAGE_CONSUMER_STILL = 0x0066, + + // 67-7F Reserved // Screen Brightness HID_USAGE_CONSUMER_BRIGHTNESS_INCREMENT = 0x006F, HID_USAGE_CONSUMER_BRIGHTNESS_DECREMENT = 0x0070, @@ -912,40 +949,386 @@ enum { HID_USAGE_CONSUMER_WIRELESS_RADIO_LED = 0x00C7, HID_USAGE_CONSUMER_WIRELESS_RADIO_SLIDER_SWITCH = 0x00C8, - // Media Control - HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, + HID_USAGE_CONSUMER_SELECTION = 0x0080, + HID_USAGE_CONSUMER_ASSIGN_SELECTION = 0x0081, + HID_USAGE_CONSUMER_MODE_STEP = 0x0082, + HID_USAGE_CONSUMER_RECALL_LAST = 0x0083, + HID_USAGE_CONSUMER_ENTER_CHANNEL = 0x0084, + HID_USAGE_CONSUMER_ORDER_MOVIE = 0x0085, + HID_USAGE_CONSUMER_CHANNEL = 0x0086, + HID_USAGE_CONSUMER_MEDIA_SELECTION = 0x0087, + HID_USAGE_CONSUMER_MEDIA_SELECT_COMPUTER = 0x0088, + HID_USAGE_CONSUMER_MEDIA_SELECT_TV = 0x0089, + HID_USAGE_CONSUMER_MEDIA_SELECT_WWW = 0x008A, + HID_USAGE_CONSUMER_MEDIA_SELECT_DVD = 0x008B, + HID_USAGE_CONSUMER_MEDIA_SELECT_TELEPHONE = 0x008C, + HID_USAGE_CONSUMER_MEDIA_SELECT_PROGRAM_GUIDE = 0x008D, + HID_USAGE_CONSUMER_MEDIA_SELECT_VIDEO_PHONE = 0x008E, + HID_USAGE_CONSUMER_MEDIA_SELECT_GAMES = 0x008F, + HID_USAGE_CONSUMER_MEDIA_SELECT_MESSAGES = 0x0090, + HID_USAGE_CONSUMER_MEDIA_SELECT_CD = 0x0091, + HID_USAGE_CONSUMER_MEDIA_SELECT_VCR = 0x0092, + HID_USAGE_CONSUMER_MEDIA_SELECT_TUNER = 0x0093, + HID_USAGE_CONSUMER_QUIT = 0x0094, + HID_USAGE_CONSUMER_HELP = 0x0095, + HID_USAGE_CONSUMER_MEDIA_SELECT_TAPE = 0x0096, + HID_USAGE_CONSUMER_MEDIA_SELECT_CABLE = 0x0097, + HID_USAGE_CONSUMER_MEDIA_SELECT_SATELLITE = 0x0098, + HID_USAGE_CONSUMER_MEDIA_SELECT_SECURITY = 0x0099, + HID_USAGE_CONSUMER_MEDIA_SELECT_HOME = 0x009A, + HID_USAGE_CONSUMER_MEDIA_SELECT_CALL = 0x009B, + HID_USAGE_CONSUMER_CHANNEL_INCREMENT = 0x009C, + HID_USAGE_CONSUMER_CHANNEL_DECREMENT = 0x009D, + HID_USAGE_CONSUMER_MEDIA_SELECT_SAP = 0x009E, + // 9F Reserved + HID_USAGE_CONSUMER_VCR_PLUS = 0x00A0, + HID_USAGE_CONSUMER_ONCE = 0x00A1, + HID_USAGE_CONSUMER_DAILY = 0x00A2, + HID_USAGE_CONSUMER_WEEKLY = 0x00A3, + HID_USAGE_CONSUMER_MONTHLY = 0x00A4, + // A5-AF Reserved + + HID_USAGE_CONSUMER_PLAY = 0x00B0, + HID_USAGE_CONSUMER_PAUSE = 0x00B1, + HID_USAGE_CONSUMER_RECORD = 0x00B2, + HID_USAGE_CONSUMER_FAST_FORWARD = 0x00B3, + HID_USAGE_CONSUMER_REWIND = 0x00B4, + HID_USAGE_CONSUMER_SCAN_NEXT_TRACK = 0x00B5, HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, + HID_USAGE_CONSUMER_SCAN_PREVIOUS_TRACK = 0x00B6, HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, HID_USAGE_CONSUMER_STOP = 0x00B7, + HID_USAGE_CONSUMER_EJECT = 0x00B8, + HID_USAGE_CONSUMER_RANDOM_PLAY = 0x00B9, + HID_USAGE_CONSUMER_SELECT_DISC = 0x00BA, + HID_USAGE_CONSUMER_ENTER_DISC = 0x00BB, + HID_USAGE_CONSUMER_REPEAT = 0x00BC, + HID_USAGE_CONSUMER_TRACKING = 0x00BD, + HID_USAGE_CONSUMER_TRACK_NORMAL = 0x00BE, + HID_USAGE_CONSUMER_SLOW_TRACKING = 0x00BF, + HID_USAGE_CONSUMER_FRAME_FORWARD = 0x00C0, + HID_USAGE_CONSUMER_FRAME_BACK = 0x00C1, + HID_USAGE_CONSUMER_MARK = 0x00C2, + HID_USAGE_CONSUMER_CLEAR_MARK = 0x00C3, + HID_USAGE_CONSUMER_REPEAT_FROM_MARK = 0x00C4, + HID_USAGE_CONSUMER_RETURN_TO_MARK = 0x00C5, + HID_USAGE_CONSUMER_SEARCH_MARK_FORWARD = 0x00C6, + HID_USAGE_CONSUMER_SEARCH_MARK_BACKWARDS = 0x00C7, + HID_USAGE_CONSUMER_COUNTER_RESET = 0x00C8, + HID_USAGE_CONSUMER_SHOW_COUNTER = 0x00C9, + HID_USAGE_CONSUMER_TRACKING_INCREMENT = 0x00CA, + HID_USAGE_CONSUMER_TRACKING_DECREMENT = 0x00CB, + HID_USAGE_CONSUMER_STOP_EJECT = 0x00CC, + + + // Media Control + HID_USAGE_CONSUMER_PLAY_PAUSE = 0x00CD, + + HID_USAGE_CONSUMER_PLAY_SKIP = 0x00CE, + + // CF-DF Reserved HID_USAGE_CONSUMER_VOLUME = 0x00E0, + HID_USAGE_CONSUMER_BALANCE = 0x00E1, HID_USAGE_CONSUMER_MUTE = 0x00E2, HID_USAGE_CONSUMER_BASS = 0x00E3, HID_USAGE_CONSUMER_TREBLE = 0x00E4, HID_USAGE_CONSUMER_BASS_BOOST = 0x00E5, + HID_USAGE_CONSUMER_SURROUND_MODE = 0x00E6, + HID_USAGE_CONSUMER_LOUDNESS = 0x00E7, + HID_USAGE_CONSUMER_MPX = 0x00E8, HID_USAGE_CONSUMER_VOLUME_INCREMENT = 0x00E9, HID_USAGE_CONSUMER_VOLUME_DECREMENT = 0x00EA, + // EB-EF Reserved + HID_USAGE_CONSUMER_SPEED_SELECT = 0x00F0, + HID_USAGE_CONSUMER_PLAYBACK_SPEED = 0x00F1, + HID_USAGE_CONSUMER_STANDARD_PLAY = 0x00F2, + HID_USAGE_CONSUMER_LONG_PLAY = 0x00F3, + HID_USAGE_CONSUMER_EXTENDED_PLAY = 0x00F4, + HID_USAGE_CONSUMER_SLOW = 0x00F5, + // F6-FF Reserved + HID_USAGE_CONSUMER_FAN_ENABLE = 0x0100, + HID_USAGE_CONSUMER_FAN_SPEED = 0x0101, + HID_USAGE_CONSUMER_LIGHT_ENABLE = 0x0102, + HID_USAGE_CONSUMER_LIGHT_ILLUMINATION_LEVEL = 0x0103, + HID_USAGE_CONSUMER_CLIMATE_CONTROL_ENABLE = 0x0104, + HID_USAGE_CONSUMER_ROOM_TEMPERATURE = 0x0105, + HID_USAGE_CONSUMER_SECURITY_ENABLE = 0x0106, + HID_USAGE_CONSUMER_FIRE_ALARM = 0x0107, + HID_USAGE_CONSUMER_POLICE_ALARM = 0x0108, + HID_USAGE_CONSUMER_PROXIMITY = 0x0109, + HID_USAGE_CONSUMER_MOTION = 0x010A, + HID_USAGE_CONSUMER_DURESS_ALARM = 0x010B, + HID_USAGE_CONSUMER_HOLDUP_ALARM = 0x010C, + HID_USAGE_CONSUMER_MEDICAL_ALARM = 0x010D, + // 10E-14F Reserved + HID_USAGE_CONSUMER_BALANCE_RIGHT = 0x0150, + HID_USAGE_CONSUMER_BALANCE_LEFT = 0x0151, HID_USAGE_CONSUMER_BASS_INCREMENT = 0x0152, HID_USAGE_CONSUMER_BASS_DECREMENT = 0x0153, HID_USAGE_CONSUMER_TREBLE_INCREMENT = 0x0154, HID_USAGE_CONSUMER_TREBLE_DECREMENT = 0x0155, - // Application Launcher + // 156-15F Reserved + HID_USAGE_CONSUMER_SPEAKER_SYSTEM = 0x0160, + HID_USAGE_CONSUMER_CHANNEL_LEFT = 0x0161, + HID_USAGE_CONSUMER_CHANNEL_RIGHT = 0x0162, + HID_USAGE_CONSUMER_CHANNEL_CENTER = 0x0163, + HID_USAGE_CONSUMER_CHANNEL_FRONT = 0x0164, + HID_USAGE_CONSUMER_CHANNEL_CENTER_FRONT = 0x0165, + HID_USAGE_CONSUMER_CHANNEL_SIDE = 0x0166, + HID_USAGE_CONSUMER_CHANNEL_SURROUND = 0x0167, + HID_USAGE_CONSUMER_CHANNEL_LOW_FREQUENCY = 0x0168, + // Enhancement + // CL 15.12.1 + HID_USAGE_CONSUMER_CHANNEL_TOP = 0x0169, + HID_USAGE_CONSUMER_CHANNEL_UNKNOWN = 0x016A, + // 16B-16F Reserved + HID_USAGE_CONSUMER_SUB_CHANNEL = 0x0170, + HID_USAGE_CONSUMER_SUB_CHANNEL_INCREMENT = 0x0171, + HID_USAGE_CONSUMER_SUB_CHANNEL_DECREMENT = 0x0172, + HID_USAGE_CONSUMER_ALTERNATE_AUDIO_INCREMENT = 0x0173, + HID_USAGE_CONSUMER_ALTERNATE_AUDIO_DECREMENT = 0x0174, + // 175-17F Reserved + HID_USAGE_CONSUMER_APPLICATION_LAUNCH_BUTTONS = 0x0180, + HID_USAGE_CONSUMER_AL_LAUNCH_BUTTON_CONFIGURATION = 0x0181, + // Tool + // Sel 15.15 + HID_USAGE_CONSUMER_AL_PROGRAMMABLE_BUTTON = 0x0182, + // Configuration + // Sel 15.15 HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, + HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL = 0x0183, + // Configuration + // Sel 15.15 + HID_USAGE_CONSUMER_AL_WORD_PROCESSOR = 0x0184, + HID_USAGE_CONSUMER_AL_TEXT_EDITOR = 0x0185, + HID_USAGE_CONSUMER_AL_SPREADSHEET = 0x0186, + HID_USAGE_CONSUMER_AL_GRAPHICS_EDITOR = 0x0187, + HID_USAGE_CONSUMER_AL_PRESENTATION_APP = 0x0188, + HID_USAGE_CONSUMER_AL_DATABASE_APP = 0x0189, HID_USAGE_CONSUMER_AL_EMAIL_READER = 0x018A, + HID_USAGE_CONSUMER_AL_NEWSREADER = 0x018B, + HID_USAGE_CONSUMER_AL_VOICEMAIL = 0x018C, + HID_USAGE_CONSUMER_AL_CONTACTS_ADDRESS_BOOK = 0x018D, + HID_USAGE_CONSUMER_AL_CALENDAR_SCHEDULE = 0x018E, + HID_USAGE_CONSUMER_AL_TASK_PROJECT_MANAGER = 0x018F, + HID_USAGE_CONSUMER_AL_LOG_JOURNAL_TIMECARD = 0x0190, + HID_USAGE_CONSUMER_AL_CHECKBOOK_FINANCE = 0x0191, HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, + HID_USAGE_CONSUMER_AL_A_V_CAPTURE_PLAYBACK = 0x0193, + HID_USAGE_CONSUMER_AL_LOCAL_MACHINE_BROWSER = 0x0194, HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, - + HID_USAGE_CONSUMER_AL_LAN_WAN_BROWSER = 0x0195, + HID_USAGE_CONSUMER_AL_INTERNET_BROWSER = 0x0196, + HID_USAGE_CONSUMER_AL_REMOTE_NETWORKING_ISP = 0x0197, + // Connect + // Sel 15.15 + HID_USAGE_CONSUMER_AL_NETWORK_CONFERENCE = 0x0198, + HID_USAGE_CONSUMER_AL_NETWORK_CHAT = 0x0199, + HID_USAGE_CONSUMER_AL_TELEPHONY_DIALER = 0x019A, + HID_USAGE_CONSUMER_AL_LOGON = 0x019B, + HID_USAGE_CONSUMER_AL_LOGOFF = 0x019C, + HID_USAGE_CONSUMER_AL_LOGON_LOGOFF = 0x019D, + HID_USAGE_CONSUMER_AL_TERMINAL_LOCK_SCREENSAVER = 0x019E, + HID_USAGE_CONSUMER_AL_CONTROL_PANEL = 0x019F, + HID_USAGE_CONSUMER_AL_COMMAND_LINE_PROCESSOR_RUN = 0x01A0, + HID_USAGE_CONSUMER_AL_PROCESS_TASK_MANAGER = 0x01A1, + HID_USAGE_CONSUMER_AL_SELECT_TASK_APPLICATION = 0x01A2, + HID_USAGE_CONSUMER_AL_NEXT_TASK_APPLICATION = 0x01A3, + HID_USAGE_CONSUMER_AL_PREVIOUS_TASK_APPLICATION = 0x01A4, + HID_USAGE_CONSUMER_AL_PREEMPTIVE_HALT = 0x01A5, + // Task_Application + // Sel 15.15 + HID_USAGE_CONSUMER_AL_INTEGRATED_HELP_CENTER = 0x01A6, + HID_USAGE_CONSUMER_AL_DOCUMENTS = 0x01A7, + HID_USAGE_CONSUMER_AL_THESAURUS = 0x01A8, + HID_USAGE_CONSUMER_AL_DICTIONARY = 0x01A9, + HID_USAGE_CONSUMER_AL_DESKTOP = 0x01AA, + HID_USAGE_CONSUMER_AL_SPELL_CHECK = 0x01AB, + HID_USAGE_CONSUMER_AL_GRAMMAR_CHECK = 0x01AC, + HID_USAGE_CONSUMER_AL_WIRELESS_STATUS = 0x01AD, + HID_USAGE_CONSUMER_AL_KEYBOARD_LAYOUT = 0x01AE, + HID_USAGE_CONSUMER_AL_VIRUS_PROTECTION = 0x01AF, + HID_USAGE_CONSUMER_AL_ENCRYPTION = 0x01B0, + HID_USAGE_CONSUMER_AL_SCREEN_SAVER = 0x01B1, + HID_USAGE_CONSUMER_AL_ALARMS = 0x01B2, + HID_USAGE_CONSUMER_AL_CLOCK = 0x01B3, + HID_USAGE_CONSUMER_AL_FILE_BROWSER = 0x01B4, + HID_USAGE_CONSUMER_AL_POWER_STATUS = 0x01B5, + HID_USAGE_CONSUMER_AL_IMAGE_BROWSER = 0x01B6, + HID_USAGE_CONSUMER_AL_AUDIO_BROWSER = 0x01B7, + HID_USAGE_CONSUMER_AL_MOVIE_BROWSER = 0x01B8, + HID_USAGE_CONSUMER_AL_DIGITAL_RIGHTS_MANAGER = 0x01B9, + HID_USAGE_CONSUMER_AL_DIGITAL_WALLET = 0x01BA, + // 1BB Reserved + HID_USAGE_CONSUMER_AL_INSTANT_MESSAGING = 0x01BC, + HID_USAGE_CONSUMER_AL_OEM_FEATURES_TIPS_TUTORIAL = 0x01BD, + // Browser + // Sel 15.15 + HID_USAGE_CONSUMER_AL_OEM_HELP = 0x01BE, + HID_USAGE_CONSUMER_AL_ONLINE_COMMUNITY = 0x01BF, + HID_USAGE_CONSUMER_AL_ENTERTAINMENT_CONTENT = 0x01C0, + // Browser + // Sel 15.15 + HID_USAGE_CONSUMER_AL_ONLINE_SHOPPING_BROWSER = 0x01C1, + HID_USAGE_CONSUMER_AL_SMARTCARD_INFORMATION_HELP = 0x01C2, + HID_USAGE_CONSUMER_AL_MARKET_MONITOR_FINANCE = 0x01C3, + // Browser + // Sel 15.15 + HID_USAGE_CONSUMER_AL_CUSTOMIZED_CORPORATE_NEWS = 0x01C4, + // Browser + // Sel 15.15 + HID_USAGE_CONSUMER_AL_ONLINE_ACTIVITY_BROWSER = 0x01C5, + HID_USAGE_CONSUMER_AL_RESEARCH_SEARCH_BROWSER = 0x01C6, + HID_USAGE_CONSUMER_AL_AUDIO_PLAYER = 0x01C7, + // 1C8-1FF Reserved + HID_USAGE_CONSUMER_GENERIC_GUI_APPLICATION = 0x0200, + // ' Controls + // ' + HID_USAGE_CONSUMER_AC_NEW = 0x0201, + HID_USAGE_CONSUMER_AC_OPEN = 0x0202, + HID_USAGE_CONSUMER_AC_CLOSE = 0x0203, + HID_USAGE_CONSUMER_AC_EXIT = 0x0204, + HID_USAGE_CONSUMER_AC_MAXIMIZE = 0x0205, + HID_USAGE_CONSUMER_AC_MINIMIZE = 0x0206, + HID_USAGE_CONSUMER_AC_SAVE = 0x0207, + HID_USAGE_CONSUMER_AC_PRINT = 0x0208, + HID_USAGE_CONSUMER_AC_PROPERTIES = 0x0209, + HID_USAGE_CONSUMER_AC_UNDO = 0x021A, + HID_USAGE_CONSUMER_AC_COPY = 0x021B, + HID_USAGE_CONSUMER_AC_CUT = 0x021C, + HID_USAGE_CONSUMER_AC_PASTE = 0x021D, + HID_USAGE_CONSUMER_AC_SELECT_ALL = 0x021E, + HID_USAGE_CONSUMER_AC_FIND = 0x021F, + HID_USAGE_CONSUMER_AC_FIND_AND_REPLACE = 0x0220, // Browser/Explorer Specific HID_USAGE_CONSUMER_AC_SEARCH = 0x0221, + HID_USAGE_CONSUMER_AC_GO_TO = 0x0222, HID_USAGE_CONSUMER_AC_HOME = 0x0223, HID_USAGE_CONSUMER_AC_BACK = 0x0224, HID_USAGE_CONSUMER_AC_FORWARD = 0x0225, HID_USAGE_CONSUMER_AC_STOP = 0x0226, HID_USAGE_CONSUMER_AC_REFRESH = 0x0227, + HID_USAGE_CONSUMER_AC_PREVIOUS_LINK = 0x0228, + HID_USAGE_CONSUMER_AC_NEXT_LINK = 0x0229, HID_USAGE_CONSUMER_AC_BOOKMARKS = 0x022A, - + HID_USAGE_CONSUMER_AC_HISTORY = 0x022B, + HID_USAGE_CONSUMER_AC_SUBSCRIPTIONS = 0x022C, + HID_USAGE_CONSUMER_AC_ZOOM_IN = 0x022D, + HID_USAGE_CONSUMER_AC_ZOOM_OUT = 0x022E, + HID_USAGE_CONSUMER_AC_ZOOM = 0x022F, + HID_USAGE_CONSUMER_AC_FULL_SCREEN_VIEW = 0x0230, + HID_USAGE_CONSUMER_AC_NORMAL_VIEW = 0x0231, + HID_USAGE_CONSUMER_AC_VIEW_TOGGLE = 0x0232, + HID_USAGE_CONSUMER_AC_SCROLL_UP = 0x0233, + HID_USAGE_CONSUMER_AC_SCROLL_DOWN = 0x0234, + HID_USAGE_CONSUMER_AC_SCROLL = 0x0235, + HID_USAGE_CONSUMER_AC_PAN_LEFT = 0x0236, + HID_USAGE_CONSUMER_AC_PAN_RIGHT = 0x0237, // Mouse Horizontal scroll HID_USAGE_CONSUMER_AC_PAN = 0x0238, + HID_USAGE_CONSUMER_AC_NEW_WINDOW = 0x0239, + HID_USAGE_CONSUMER_AC_TILE_HORIZONTALLY = 0x023A, + HID_USAGE_CONSUMER_AC_TILE_VERTICALLY = 0x023B, + HID_USAGE_CONSUMER_AC_FORMAT = 0x023C, + HID_USAGE_CONSUMER_AC_EDIT = 0x023D, + HID_USAGE_CONSUMER_AC_BOLD = 0x023E, + HID_USAGE_CONSUMER_AC_ITALICS = 0x023F, + HID_USAGE_CONSUMER_AC_UNDERLINE = 0x0240, + HID_USAGE_CONSUMER_AC_STRIKETHROUGH = 0x0241, + HID_USAGE_CONSUMER_AC_SUBSCRIPT = 0x0242, + HID_USAGE_CONSUMER_AC_SUPERSCRIPT = 0x0243, + HID_USAGE_CONSUMER_AC_ALL_CAPS = 0x0244, + HID_USAGE_CONSUMER_AC_ROTATE = 0x0245, + HID_USAGE_CONSUMER_AC_RESIZE = 0x0246, + HID_USAGE_CONSUMER_AC_FLIP_HORIZONTAL = 0x0247, + HID_USAGE_CONSUMER_AC_FLIP_VERTICAL = 0x0248, + HID_USAGE_CONSUMER_AC_MIRROR_HORIZONTAL = 0x0249, + HID_USAGE_CONSUMER_AC_MIRROR_VERTICAL = 0x024A, + HID_USAGE_CONSUMER_AC_FONT_SELECT = 0x024B, + HID_USAGE_CONSUMER_AC_FONT_COLOR = 0x024C, + HID_USAGE_CONSUMER_AC_FONT_SIZE = 0x024D, + HID_USAGE_CONSUMER_AC_JUSTIFY_LEFT = 0x024E, + HID_USAGE_CONSUMER_AC_JUSTIFY_CENTER_H = 0x024F, + HID_USAGE_CONSUMER_AC_JUSTIFY_RIGHT = 0x0250, + HID_USAGE_CONSUMER_AC_JUSTIFY_BLOCK_H = 0x0251, + HID_USAGE_CONSUMER_AC_JUSTIFY_TOP = 0x0252, + HID_USAGE_CONSUMER_AC_JUSTIFY_CENTER_V = 0x0253, + HID_USAGE_CONSUMER_AC_JUSTIFY_BOTTOM = 0x0254, + HID_USAGE_CONSUMER_AC_JUSTIFY_BLOCK_V = 0x0255, + HID_USAGE_CONSUMER_AC_INDENT_DECREASE = 0x0256, + HID_USAGE_CONSUMER_AC_INDENT_INCREASE = 0x0257, + HID_USAGE_CONSUMER_AC_NUMBERED_LIST = 0x0258, + HID_USAGE_CONSUMER_AC_RESTART_NUMBERING = 0x0259, + HID_USAGE_CONSUMER_AC_BULLETED_LIST = 0x025A, + HID_USAGE_CONSUMER_AC_PROMOTE = 0x025B, + HID_USAGE_CONSUMER_AC_DEMOTE = 0x025C, + HID_USAGE_CONSUMER_AC_YES = 0x025D, + HID_USAGE_CONSUMER_AC_NO = 0x025E, + HID_USAGE_CONSUMER_AC_CANCEL = 0x025F, + HID_USAGE_CONSUMER_AC_CATALOG = 0x0260, + HID_USAGE_CONSUMER_AC_BUY_CHECKOUT = 0x0261, + HID_USAGE_CONSUMER_AC_ADD_TO_CART = 0x0262, + HID_USAGE_CONSUMER_AC_EXPAND = 0x0263, + HID_USAGE_CONSUMER_AC_EXPAND_ALL = 0x0264, + HID_USAGE_CONSUMER_AC_COLLAPSE = 0x0265, + HID_USAGE_CONSUMER_AC_COLLAPSE_ALL = 0x0266, + HID_USAGE_CONSUMER_AC_PRINT_PREVIEW = 0x0267, + HID_USAGE_CONSUMER_AC_PASTE_SPECIAL = 0x0268, + HID_USAGE_CONSUMER_AC_INSERT_MODE = 0x0269, + HID_USAGE_CONSUMER_AC_DELETE = 0x026A, + HID_USAGE_CONSUMER_AC_LOCK = 0x026B, + HID_USAGE_CONSUMER_AC_UNLOCK = 0x026C, + HID_USAGE_CONSUMER_AC_PROTECT = 0x026D, + HID_USAGE_CONSUMER_AC_UNPROTECT = 0x026E, + HID_USAGE_CONSUMER_AC_ATTACH_COMMENT = 0x026F, + HID_USAGE_CONSUMER_AC_DELETE_COMMENT = 0x0270, + HID_USAGE_CONSUMER_AC_VIEW_COMMENT = 0x0271, + HID_USAGE_CONSUMER_AC_SELECT_WORD = 0x0272, + HID_USAGE_CONSUMER_AC_SELECT_SENTENCE = 0x0273, + HID_USAGE_CONSUMER_AC_SELECT_PARAGRAPH = 0x0274, + HID_USAGE_CONSUMER_AC_SELECT_COLUMN = 0x0275, + HID_USAGE_CONSUMER_AC_SELECT_ROW = 0x0276, + HID_USAGE_CONSUMER_AC_SELECT_TABLE = 0x0277, + HID_USAGE_CONSUMER_AC_SELECT_OBJECT = 0x0278, + HID_USAGE_CONSUMER_AC_REDO_REPEAT = 0x0279, + HID_USAGE_CONSUMER_AC_SORT = 0x027A, + HID_USAGE_CONSUMER_AC_SORT_ASCENDING = 0x027B, + HID_USAGE_CONSUMER_AC_SORT_DESCENDING = 0x027C, + HID_USAGE_CONSUMER_AC_FILTER = 0x027D, + HID_USAGE_CONSUMER_AC_SET_CLOCK = 0x027E, + HID_USAGE_CONSUMER_AC_VIEW_CLOCK = 0x027F, + HID_USAGE_CONSUMER_AC_SELECT_TIME_ZONE = 0x0280, + HID_USAGE_CONSUMER_AC_EDIT_TIME_ZONES = 0x0281, + HID_USAGE_CONSUMER_AC_SET_ALARM = 0x0282, + HID_USAGE_CONSUMER_AC_CLEAR_ALARM = 0x0283, + HID_USAGE_CONSUMER_AC_SNOOZE_ALARM = 0x0284, + HID_USAGE_CONSUMER_AC_RESET_ALARM = 0x0285, + HID_USAGE_CONSUMER_AC_SYNCHRONIZE = 0x0286, + HID_USAGE_CONSUMER_AC_SEND_RECEIVE = 0x0287, + HID_USAGE_CONSUMER_AC_SEND_TO = 0x0288, + HID_USAGE_CONSUMER_AC_REPLY = 0x0289, + HID_USAGE_CONSUMER_AC_REPLY_ALL = 0x028A, + HID_USAGE_CONSUMER_AC_FORWARD_MSG = 0x028B, + HID_USAGE_CONSUMER_AC_SEND = 0x028C, + HID_USAGE_CONSUMER_AC_ATTACH_FILE = 0x028D, + HID_USAGE_CONSUMER_AC_UPLOAD = 0x028E, + HID_USAGE_CONSUMER_AC_DOWNLOAD_SAVE_TARGET_AS = 0x028F, + HID_USAGE_CONSUMER_AC_SET_BORDERS = 0x0290, + HID_USAGE_CONSUMER_AC_INSERT_ROW = 0x0291, + HID_USAGE_CONSUMER_AC_INSERT_COLUMN = 0x0292, + HID_USAGE_CONSUMER_AC_INSERT_FILE = 0x0293, + HID_USAGE_CONSUMER_AC_INSERT_PICTURE = 0x0294, + HID_USAGE_CONSUMER_AC_INSERT_OBJECT = 0x0295, + HID_USAGE_CONSUMER_AC_INSERT_SYMBOL = 0x0296, + HID_USAGE_CONSUMER_AC_SAVE_AND_CLOSE = 0x0297, + HID_USAGE_CONSUMER_AC_RENAME = 0x0298, + HID_USAGE_CONSUMER_AC_MERGE = 0x0299, + HID_USAGE_CONSUMER_AC_SPLIT = 0x029A, + HID_USAGE_CONSUMER_AC_DISRIBUTE_HORIZONTALLY = 0x029B, + HID_USAGE_CONSUMER_AC_DISTRIBUTE_VERTICALLY = 0x029C, + // 29D-FFFF Reserved + }; /// HID Usage Table: Digitizer Page (0x0D) -- cgit v1.3.1 From bd9dd75da8718dfd56b2e91b658f81613ed1bf3a Mon Sep 17 00:00:00 2001 From: Mitsumine Suzu <60875431+verylowfreq@users.noreply.github.com> Date: Sun, 24 Aug 2025 16:26:08 +0900 Subject: Small cleanups. --- src/portable/wch/hcd_ch32_usbfs.c | 25 ++++++++----------------- 1 file changed, 8 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index d176f40c5..fc52597c2 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -120,9 +120,6 @@ static usb_edpt_t *get_empty_record_slot(void) { static usb_edpt_t *add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t max_packet_size, uint8_t xfer_type) { usb_edpt_t *slot = get_empty_record_slot(); - if (slot == NULL) { - PANIC("add_edpt_record(0x%02x, 0x%02x, ...) no slot for new record\r\n", dev_addr, ep_addr); - } TU_ASSERT(slot != NULL, NULL); slot->dev_addr = dev_addr; @@ -412,10 +409,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } else { LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); usb_current_xfer_info.buffer += tx_len; - uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > usb_current_xfer_info.bufferlen) { - copylen = usb_current_xfer_info.bufferlen; - } + uint16_t copylen = TU_MIN(edpt_info->max_packet_size, usb_current_xfer_info.bufferlen); memcpy(USBFS_TX_Buf, usb_current_xfer_info.buffer, copylen); hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); return; @@ -445,7 +439,10 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } } default: { - PANIC("Unknown PID: 0x%02x\n", request_pid); + LOG_CH32_USBFSH("hcd_int_handler() L%d: unexpected response PID: 0x%02x\r\n", __LINE__, response_pid); + usb_current_xfer_info.is_busy = false; + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + return; } } } else { @@ -474,7 +471,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); return; } else { - LOG_CH32_USBFSH("In USBHD_IRQHandler, unexpected response PID: 0x%02x\r\n", response_pid); + LOG_CH32_USBFSH("hcd_int_handler() L%d: unexpected response PID: 0x%02x\r\n", __LINE__, response_pid); usb_current_xfer_info.is_busy = false; hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); return; @@ -519,9 +516,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b usb_current_xfer_info.is_busy = true; usb_edpt_t *edpt_info = get_edpt_record(dev_addr, ep_addr); - if (edpt_info == NULL) { - PANIC("get_edpt_record() returned NULL in hcd_edpt_xfer()\r\n"); - } + TU_ASSERT(edpt_info != NULL); hardware_set_port_address_speed(dev_addr); @@ -537,10 +532,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b return hardware_start_xfer(USB_PID_IN, ep_addr, edpt_info->data_toggle); } else { LOG_CH32_USBFSH("hcd_edpt_xfer(): WRITE, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); - uint16_t copylen = USBFS_TX_BUF_LEN; - if (copylen > buflen) { - copylen = buflen; - } + uint16_t copylen = TU_MIN(edpt_info->max_packet_size, buflen); USBOTG_H_FS->HOST_TX_LEN = copylen; memcpy(USBFS_TX_Buf, buffer, copylen); return hardware_start_xfer(USB_PID_OUT, ep_addr, edpt_info->data_toggle); @@ -596,7 +588,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { (void) rhport; (void) dev_addr; LOG_CH32_USBFSH("hcd_edpt_clear_stall(rhport=%d, dev_addr=0x%02x, ep_addr=0x%02x)\r\n", rhport, dev_addr, ep_addr); - // PANIC("\r\install\r\n"); uint8_t edpt_num = tu_edpt_number(ep_addr); uint8_t setup_request_clear_stall[8] = { 0x02, 0x01, 0x00, 0x00, edpt_num, 0x00, 0x00, 0x00 -- cgit v1.3.1 From 522a34ee28bcee6674ccd91973cb87869be98909 Mon Sep 17 00:00:00 2001 From: Mitsumine Suzu <60875431+verylowfreq@users.noreply.github.com> Date: Sun, 24 Aug 2025 16:28:32 +0900 Subject: Insert small delay for LowSpeed device --- src/portable/wch/hcd_ch32_usbfs.c | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index fc52597c2..38bb0ed59 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -55,18 +55,18 @@ TU_ATTR_ALIGNED(4) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; #define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) // Busywait for delay microseconds/nanoseconds -// static void loopdelay(uint32_t count) -// { -// volatile uint32_t c = count / 3; -// if (c == 0) { return; } -// // while (c-- != 0); -// asm volatile( -// "1: \n" // loop label -// " addi %0, %0, -1 \n" // c-- -// " bne %0, zero, 1b \n" // if (c != 0) goto loop -// : "+r"(c) // c is input/output operand -// ); -// } +static void loopdelay(uint32_t count) +{ + volatile uint32_t c = count / 3; + if (c == 0) { return; } + // while (c-- != 0); + asm volatile( + "1: \n" // loop label + " addi %0, %0, -1 \n" // c-- + " bne %0, zero, 1b \n" // if (c != 0) goto loop + : "+r"(c) // c is input/output operand + ); +} // Endpoint status @@ -194,10 +194,13 @@ static bool hardware_start_xfer(uint8_t pid, uint8_t ep_addr, uint8_t data_toggl : "(other)", pid, ep_addr, data_toggle); - // if (pid == USB_PID_IN) - // { // FIXME: long delay needed (at release build) about 30msec - // loopdelay(SystemCoreClock / 1000 * 30); - // } + //WORKAROUND: For LowSpeed device, insert small delay + bool is_lowspeed_device = tuh_speed_get(usb_current_xfer_info.dev_addr) == TUSB_SPEED_LOW; + if (is_lowspeed_device) { + //NOTE: worked -> SystemCoreClock / 1000000 * 50, 25 + // NOT worked -> 20 and less (at 144MHz internal clock) + loopdelay(SystemCoreClock / 1000000 * 40); + } uint8_t pid_edpt = (pid << 4) | (tu_edpt_number(ep_addr) & 0x0f); USBOTG_H_FS->HOST_TX_CTRL = (data_toggle != 0) ? USBFS_UH_T_TOG : 0; -- cgit v1.3.1 From a3bb7a90b3478f43d448443140b68c3473331f93 Mon Sep 17 00:00:00 2001 From: Mitsumine Suzu <60875431+verylowfreq@users.noreply.github.com> Date: Sun, 24 Aug 2025 16:46:12 +0900 Subject: Improve retry operation at NAK response. --- src/portable/wch/hcd_ch32_usbfs.c | 76 +++++++++++++++++++++++++++++++++------ 1 file changed, 66 insertions(+), 10 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 38bb0ed59..449908658 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -28,6 +28,8 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_WCH_USBFS) && defined(CFG_TUH_WCH_USBIP_USBFS) && CFG_TUH_WCH_USBIP_USBFS +#include + #include "host/hcd.h" #include "host/usbh.h" #include "host/usbh_pvt.h" @@ -95,6 +97,7 @@ typedef struct usb_current_xfer_st { uint8_t *buffer; uint16_t bufferlen; uint16_t xferred_len; + bool nak_pending; } usb_current_xfer_t; static volatile usb_current_xfer_t usb_current_xfer_info = {}; @@ -351,6 +354,34 @@ void hcd_int_disable(uint8_t rhport) { interrupt_enabled = false; } +typedef struct { + uint8_t rhport; + uint8_t dev_addr; + uint8_t ep_addr; + uint16_t buflen; + uint8_t* buf; +} xfer_retry_param_t; + +static void xfer_retry(void* _params) { + LOG_CH32_USBFSH("xfer_retry()\r\n"); + xfer_retry_param_t* params = (xfer_retry_param_t*)_params; + if (usb_current_xfer_info.nak_pending) { + usb_current_xfer_info.nak_pending = false; + + uint8_t dev_addr = params->dev_addr; + uint8_t ep_addr = params->ep_addr; + uint16_t buflen = params->buflen; + uint8_t* buf = params->buf; + free(params); + + usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); + if (edpt_info) { + hcd_edpt_xfer(0, dev_addr, ep_addr, buf, buflen); + } + } +} + + void hcd_int_handler(uint8_t rhport, bool in_isr) { (void) rhport; (void) in_isr; @@ -407,7 +438,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (usb_current_xfer_info.bufferlen == 0) { LOG_CH32_USBFSH("USB_PID_%s completed %d bytes\r\n", request_pid == USB_PID_OUT ? "OUT" : "SETUP", usb_current_xfer_info.xferred_len); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.xferred_len, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(dev_addr, ep_addr, usb_current_xfer_info.xferred_len, XFER_RESULT_SUCCESS, in_isr); return; } else { LOG_CH32_USBFSH("USB_PID_OUT continue...\r\n"); @@ -432,7 +463,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // USB device sent all data. LOG_CH32_USBFSH("USB_PID_IN completed\r\n"); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, true); + hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, XFER_RESULT_SUCCESS, in_isr); return; } else { // USB device may send more data. @@ -444,7 +475,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { default: { LOG_CH32_USBFSH("hcd_int_handler() L%d: unexpected response PID: 0x%02x\r\n", __LINE__, response_pid); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, in_isr); return; } } @@ -458,25 +489,46 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } else if (response_pid == USB_PID_NAK) { LOG_CH32_USBFSH("NAK reposense\r\n"); uint32_t elapsed_time = board_millis() - usb_current_xfer_info.start_ms; + (void)elapsed_time; if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT) { usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, true); - } else if (elapsed_time > USB_XFER_TIMEOUT_MILLIS) { - usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_SUCCESS, in_isr); + } else { - hardware_start_xfer(request_pid, ep_addr, edpt_info->data_toggle); + usb_current_xfer_info.is_busy = false; + usb_current_xfer_info.nak_pending = true; + + xfer_retry_param_t* param_buf = malloc(sizeof(xfer_retry_param_t)); + xfer_retry_param_t param = { + .rhport = 0, + .dev_addr = dev_addr, + .ep_addr = ep_addr, + .buflen = usb_current_xfer_info.bufferlen, + .buf = usb_current_xfer_info.buffer + }; + memcpy(param_buf, ¶m, sizeof(xfer_retry_param_t)); + + hcd_event_t event = { + .rhport = rhport, + .dev_addr = dev_addr, + .event_id = USBH_EVENT_FUNC_CALL, + .func_call = { + .func = xfer_retry, + .param = param_buf + } + }; + hcd_event_handler(&event, in_isr); } return; } else if (response_pid == USB_PID_DATA0 || response_pid == USB_PID_DATA1) { LOG_CH32_USBFSH("Data toggle mismatched and DATA0/1 (not STALL). RX_LEN=%d\r\n", USBOTG_H_FS->RX_LEN); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, in_isr); return; } else { LOG_CH32_USBFSH("hcd_int_handler() L%d: unexpected response PID: 0x%02x\r\n", __LINE__, response_pid); usb_current_xfer_info.is_busy = false; - hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, true); + hcd_event_xfer_complete(dev_addr, ep_addr, 0, XFER_RESULT_FAILED, in_isr); return; } } @@ -495,6 +547,8 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const uint8_t xfer_type = ep_desc->bmAttributes.xfer; LOG_CH32_USBFSH("hcd_edpt_open(rhport=%d, dev_addr=0x%02x, %p) EndpointAdderss=0x%02x,maxPacketSize=%d,xfer_type=%d\r\n", rhport, dev_addr, ep_desc, ep_addr, max_packet_size, xfer_type); + while (usb_current_xfer_info.is_busy) { } + if (ep_num == 0x00) { TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x00, max_packet_size, xfer_type) != NULL, false); TU_ASSERT(get_or_add_edpt_record(dev_addr, 0x80, max_packet_size, xfer_type) != NULL, false); @@ -529,6 +583,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b usb_current_xfer_info.bufferlen = buflen; usb_current_xfer_info.start_ms = board_millis(); usb_current_xfer_info.xferred_len = 0; + usb_current_xfer_info.nak_pending = false; if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { LOG_CH32_USBFSH("hcd_edpt_xfer(): READ, dev_addr=0x%02x, ep_addr=0x%02x, len=%d\r\n", dev_addr, ep_addr, buflen); @@ -581,6 +636,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet usb_current_xfer_info.buffer = USBFS_TX_Buf; usb_current_xfer_info.bufferlen = setup_packet_datalen; usb_current_xfer_info.xferred_len = 0; + usb_current_xfer_info.nak_pending = false; hardware_start_xfer(USB_PID_SETUP, 0, 0); -- cgit v1.3.1 From 6f2b5fc4952e0fc730466a8756ce6427c33ce2b7 Mon Sep 17 00:00:00 2001 From: Mitsumine Suzu <60875431+verylowfreq@users.noreply.github.com> Date: Sun, 24 Aug 2025 23:52:52 +0900 Subject: Remove dynamic memory allocation --- src/portable/wch/hcd_ch32_usbfs.c | 46 ++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index 449908658..ff34ae17a 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -84,6 +84,10 @@ typedef struct usb_edpt { // Data toggle (0 or not 0) for DATA0/1 uint8_t data_toggle; + + bool is_nak_pending; + uint16_t buflen; + uint8_t* buf; } usb_edpt_t; static usb_edpt_t usb_edpt_list[CFG_TUH_DEVICE_MAX * 6] = {}; @@ -130,6 +134,9 @@ static usb_edpt_t *add_edpt_record(uint8_t dev_addr, uint8_t ep_addr, uint16_t m slot->max_packet_size = max_packet_size; slot->xfer_type = xfer_type; slot->data_toggle = 0; + slot->is_nak_pending = false; + slot->buflen = 0; + slot->buf = NULL; slot->configured = true; @@ -354,28 +361,22 @@ void hcd_int_disable(uint8_t rhport) { interrupt_enabled = false; } -typedef struct { - uint8_t rhport; - uint8_t dev_addr; - uint8_t ep_addr; - uint16_t buflen; - uint8_t* buf; -} xfer_retry_param_t; static void xfer_retry(void* _params) { LOG_CH32_USBFSH("xfer_retry()\r\n"); - xfer_retry_param_t* params = (xfer_retry_param_t*)_params; + usb_edpt_t* edpt_info = (usb_edpt_t*)_params; if (usb_current_xfer_info.nak_pending) { usb_current_xfer_info.nak_pending = false; + edpt_info->is_nak_pending = false; - uint8_t dev_addr = params->dev_addr; - uint8_t ep_addr = params->ep_addr; - uint16_t buflen = params->buflen; - uint8_t* buf = params->buf; - free(params); + uint8_t dev_addr = edpt_info->dev_addr; + uint8_t ep_addr = edpt_info->ep_addr; + uint16_t buflen = edpt_info->buflen; + uint8_t* buf = edpt_info->buf; - usb_edpt_t* edpt_info = get_edpt_record(dev_addr, ep_addr); - if (edpt_info) { + // Check connectivity + usb_edpt_t* edpt_info_current = get_edpt_record(dev_addr, ep_addr); + if (edpt_info_current) { hcd_edpt_xfer(0, dev_addr, ep_addr, buf, buflen); } } @@ -498,15 +499,10 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { usb_current_xfer_info.is_busy = false; usb_current_xfer_info.nak_pending = true; - xfer_retry_param_t* param_buf = malloc(sizeof(xfer_retry_param_t)); - xfer_retry_param_t param = { - .rhport = 0, - .dev_addr = dev_addr, - .ep_addr = ep_addr, - .buflen = usb_current_xfer_info.bufferlen, - .buf = usb_current_xfer_info.buffer - }; - memcpy(param_buf, ¶m, sizeof(xfer_retry_param_t)); + + edpt_info->is_nak_pending = true; + edpt_info->buflen = usb_current_xfer_info.bufferlen; + edpt_info->buf = usb_current_xfer_info.buffer; hcd_event_t event = { .rhport = rhport, @@ -514,7 +510,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { .event_id = USBH_EVENT_FUNC_CALL, .func_call = { .func = xfer_retry, - .param = param_buf + .param = edpt_info } }; hcd_event_handler(&event, in_isr); -- cgit v1.3.1 From 12ee78df308aa80d6c2ef34bff1be0df38939027 Mon Sep 17 00:00:00 2001 From: Jerzy Kasenberg Date: Sun, 24 Aug 2025 17:19:51 +0200 Subject: Fix osal_spin_unlock for mynewt Mynewt version for osal_spin_unlock() called OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL. Signed-off-by: Jerzy Kasenberg --- src/osal/osal_mynewt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/osal/osal_mynewt.h b/src/osal/osal_mynewt.h index ee95e684f..6d51f8ec3 100644 --- a/src/osal/osal_mynewt.h +++ b/src/osal/osal_mynewt.h @@ -63,7 +63,7 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, if (!TUP_MCU_MULTIPLE_CORE && in_isr) { return; // single core MCU does not need to lock in ISR } - OS_ENTER_CRITICAL(*ctx); + OS_EXIT_CRITICAL(*ctx); } //--------------------------------------------------------------------+ -- cgit v1.3.1 From 38f41f5fa28943086cd36653e0914fd59cb7ed03 Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Thu, 28 Aug 2025 15:35:55 +0200 Subject: fix(dcd/dwc2): Fix reset procedure for versions >=4.20a --- src/portable/synopsys/dwc2/dwc2_common.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index b001f343d..9b8333ad2 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -1,7 +1,7 @@ /* * The MIT License (MIT) * - * Copyright (c) 2024 Ha Thach (tinyusb.org) + * Copyright (c) 2024-2025 Ha Thach (tinyusb.org) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -45,11 +45,14 @@ // //-------------------------------------------------------------------- static void reset_core(dwc2_regs_t* dwc2) { + // load gsnpsid (it is not readable after reset is asserted) + uint32_t gsnpsid = dwc2->gsnpsid; + // reset core dwc2->grstctl |= GRSTCTL_CSRST; - if ((dwc2->gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { - // prior v42.0 CSRST is self-clearing + if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { + // prior v4.20a CSRST is self-clearing while (dwc2->grstctl & GRSTCTL_CSRST) {} } else { // From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking. -- cgit v1.3.1 From f5d04833bb5841930476cc666193f2f362aef228 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 3 Sep 2025 13:30:20 +0700 Subject: use tusb_time_millis_api() instead of board_millis() make loopdelay() always inline --- src/portable/wch/hcd_ch32_usbfs.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) (limited to 'src') diff --git a/src/portable/wch/hcd_ch32_usbfs.c b/src/portable/wch/hcd_ch32_usbfs.c index ff34ae17a..200136906 100644 --- a/src/portable/wch/hcd_ch32_usbfs.c +++ b/src/portable/wch/hcd_ch32_usbfs.c @@ -57,20 +57,18 @@ TU_ATTR_ALIGNED(4) static uint8_t USBFS_TX_Buf[USBFS_TX_BUF_LEN]; #define LOG_CH32_USBFSH(...) TU_LOG3(__VA_ARGS__) // Busywait for delay microseconds/nanoseconds -static void loopdelay(uint32_t count) -{ - volatile uint32_t c = count / 3; - if (c == 0) { return; } - // while (c-- != 0); - asm volatile( - "1: \n" // loop label - " addi %0, %0, -1 \n" // c-- - " bne %0, zero, 1b \n" // if (c != 0) goto loop - : "+r"(c) // c is input/output operand +TU_ATTR_ALWAYS_INLINE static inline void loopdelay(uint32_t count) { + volatile uint32_t c = count / 3; + if (c == 0) { return; } + // while (c-- != 0); + asm volatile( + "1: \n" // loop label + " addi %0, %0, -1 \n" // c-- + " bne %0, zero, 1b \n" // if (c != 0) goto loop + : "+r"(c) // c is input/output operand ); } - // Endpoint status typedef struct usb_edpt { // Is this a valid struct @@ -346,7 +344,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return board_millis(); + return tusb_time_millis_api(); } void hcd_int_enable(uint8_t rhport) { @@ -489,7 +487,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { return; } else if (response_pid == USB_PID_NAK) { LOG_CH32_USBFSH("NAK reposense\r\n"); - uint32_t elapsed_time = board_millis() - usb_current_xfer_info.start_ms; + uint32_t elapsed_time = tusb_time_millis_api() - usb_current_xfer_info.start_ms; (void)elapsed_time; if (edpt_info->xfer_type == TUSB_XFER_INTERRUPT) { usb_current_xfer_info.is_busy = false; @@ -577,7 +575,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *b usb_current_xfer_info.ep_addr = ep_addr; usb_current_xfer_info.buffer = buffer; usb_current_xfer_info.bufferlen = buflen; - usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.start_ms = tusb_time_millis_api(); usb_current_xfer_info.xferred_len = 0; usb_current_xfer_info.nak_pending = false; @@ -628,7 +626,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet uint8_t ep_addr = (setup_packet[0] & 0x80) ? 0x80 : 0x00; usb_current_xfer_info.dev_addr = dev_addr; usb_current_xfer_info.ep_addr = ep_addr; - usb_current_xfer_info.start_ms = board_millis(); + usb_current_xfer_info.start_ms = tusb_time_millis_api(); usb_current_xfer_info.buffer = USBFS_TX_Buf; usb_current_xfer_info.bufferlen = setup_packet_datalen; usb_current_xfer_info.xferred_len = 0; -- cgit v1.3.1 From c5a390950f8616f42917bc6ecd8c8e528cdda49e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 3 Sep 2025 17:20:54 +0700 Subject: add at32f415 dwc2 info --- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 2 files changed, 59 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 00685e7ad..e6b7820bc 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | AT32 F405 FS | AT32 F405 HS | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | -|:---------------------------|:---------------|:---------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| -| GUID | 0x00002000 | 0x00000000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | -| - hs_phy_type | n/a | UTMI+/ULPI | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 7 | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - num_host_ch | 15 | 15 | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 512 | 1008 | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 7 | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | +|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| +| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index bc5ad9a7b..a90150632 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -11,6 +11,7 @@ dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4'] dwc2_reg_value = { 'AT32 F405 FS': [0x00002000, 0x4F54400A, 0x00000000, 0x228FDD00, 0x020004E8, 0x1FF0A020], 'AT32 F405 HS': [0x00000000, 0x4F54400A, 0x00000000, 0x229FDDD0, 0x03F006E8, 0x1FF0A020], + 'AT32 F415': [0x00001000, 0x4F54400A, 0x00000000, 0x228DCD00, 0x020004E8, 0x0F], 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030], -- cgit v1.3.1 From da9284e88baefc6d0e5f7c624f8f7da7f4d6aed0 Mon Sep 17 00:00:00 2001 From: "copilot-swe-agent[bot]" <198982749+Copilot@users.noreply.github.com> Date: Wed, 3 Sep 2025 10:42:17 +0000 Subject: Fix obsolete cnt assignment in _tu_fifo_peek() overflow check Co-authored-by: hathach <249515+hathach@users.noreply.github.com> --- src/common/tusb_fifo.c | 1 - 1 file changed, 1 deletion(-) (limited to 'src') diff --git a/src/common/tusb_fifo.c b/src/common/tusb_fifo.c index ecf002b09..f7679556f 100644 --- a/src/common/tusb_fifo.c +++ b/src/common/tusb_fifo.c @@ -428,7 +428,6 @@ static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wr_idx, uint16 if ( cnt > f->depth ) { rd_idx = _ff_correct_read_index(f, wr_idx); - cnt = f->depth; } uint16_t rd_ptr = idx2ptr(f->depth, rd_idx); -- cgit v1.3.1 From a96ee81a7ddc03f04a837d949c291f22362d6cb4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 4 Sep 2025 10:36:15 +0700 Subject: remove duplicated enum --- src/class/hid/hid.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid.h b/src/class/hid/hid.h index 0fc0e1377..bbc58af80 100644 --- a/src/class/hid/hid.h +++ b/src/class/hid/hid.h @@ -994,9 +994,7 @@ enum { HID_USAGE_CONSUMER_FAST_FORWARD = 0x00B3, HID_USAGE_CONSUMER_REWIND = 0x00B4, HID_USAGE_CONSUMER_SCAN_NEXT_TRACK = 0x00B5, - HID_USAGE_CONSUMER_SCAN_NEXT = 0x00B5, HID_USAGE_CONSUMER_SCAN_PREVIOUS_TRACK = 0x00B6, - HID_USAGE_CONSUMER_SCAN_PREVIOUS = 0x00B6, HID_USAGE_CONSUMER_STOP = 0x00B7, HID_USAGE_CONSUMER_EJECT = 0x00B8, HID_USAGE_CONSUMER_RANDOM_PLAY = 0x00B9, @@ -1097,7 +1095,6 @@ enum { // Configuration // Sel 15.15 HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL_CONFIGURATION = 0x0183, - HID_USAGE_CONSUMER_AL_CONSUMER_CONTROL = 0x0183, // Configuration // Sel 15.15 HID_USAGE_CONSUMER_AL_WORD_PROCESSOR = 0x0184, @@ -1117,7 +1114,6 @@ enum { HID_USAGE_CONSUMER_AL_CALCULATOR = 0x0192, HID_USAGE_CONSUMER_AL_A_V_CAPTURE_PLAYBACK = 0x0193, HID_USAGE_CONSUMER_AL_LOCAL_MACHINE_BROWSER = 0x0194, - HID_USAGE_CONSUMER_AL_LOCAL_BROWSER = 0x0194, HID_USAGE_CONSUMER_AL_LAN_WAN_BROWSER = 0x0195, HID_USAGE_CONSUMER_AL_INTERNET_BROWSER = 0x0196, HID_USAGE_CONSUMER_AL_REMOTE_NETWORKING_ISP = 0x0197, -- cgit v1.3.1 From 0263cfc01ab63d6799e80cbbf691af1979cf3ab7 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Sat, 6 Sep 2025 06:58:35 -0700 Subject: fix #3239: discard poorly formed packets --- src/class/midi/midi_host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src') diff --git a/src/class/midi/midi_host.c b/src/class/midi/midi_host.c index 50bda1e36..e6ace316c 100644 --- a/src/class/midi/midi_host.c +++ b/src/class/midi/midi_host.c @@ -575,6 +575,11 @@ uint32_t tuh_midi_stream_read(uint8_t idx, uint8_t *p_cable_num, uint8_t *p_buff } } } + else { + // bad packet discard + nread = tu_edpt_stream_read(p_midi->daddr, &p_midi->ep_stream.rx, p_midi->stream_read.buffer, 4); + continue; + } } else if (status < MIDI_STATUS_SYSEX_START) { // then it is a channel message either three bytes or two uint8_t fake_cin = (status & 0xf0) >> 4; @@ -617,6 +622,11 @@ uint32_t tuh_midi_stream_read(uint8_t idx, uint8_t *p_cable_num, uint8_t *p_buff bytes_to_add_to_stream = 1; } } + else { + // bad packet discard + nread = tu_edpt_stream_read(p_midi->daddr, &p_midi->ep_stream.rx, p_midi->stream_read.buffer, 4); + continue; + } for (uint8_t i = 1; i <= bytes_to_add_to_stream; i++) { *p_buffer++ = p_midi->stream_read.buffer[i]; -- cgit v1.3.1 From d70d4043dcccb1628424c39c231ed1f95fb52f8e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 10 Sep 2025 16:59:26 +0700 Subject: use tusb_time_delay_ms_api for delay, also move tusb_time api to common.h --- src/common/tusb_common.h | 8 +++++++- src/portable/synopsys/dwc2/dwc2_stm32.h | 3 +-- src/tusb.h | 10 ---------- 3 files changed, 8 insertions(+), 13 deletions(-) (limited to 'src') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 0351a3d8f..b5bdb76e3 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -78,10 +78,16 @@ #include "tusb_debug.h" //--------------------------------------------------------------------+ -// Optional API implemented by application if needed +// API implemented by application if needed // TODO move to a more obvious place/file //--------------------------------------------------------------------+ +// Get current milliseconds, required by some port/configuration without RTOS +extern uint32_t tusb_time_millis_api(void); + +// Delay in milliseconds, use tusb_time_millis_api() by default. required by some port/configuration with no RTOS +extern void tusb_time_delay_ms_api(uint32_t ms); + // flush data cache TU_ATTR_WEAK extern void tusb_app_dcache_flush(uintptr_t addr, uint32_t data_size); diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 0bbad55f5..14d95184e 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -224,8 +224,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; // Wait ~2ms until the PLL is ready (there's no RDY bit to query) - uint32_t count = (SystemCoreClock / 1000) * 2; - while (count--) __NOP(); + tusb_time_delay_ms_api(2); #else #endif diff --git a/src/tusb.h b/src/tusb.h index dfba21ddf..88815def1 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -169,16 +169,6 @@ void tusb_int_handler(uint8_t rhport, bool in_isr); #endif -//--------------------------------------------------------------------+ -// API Implemented by user -//--------------------------------------------------------------------+ - -// Get current milliseconds, required by some port/configuration without RTOS -uint32_t tusb_time_millis_api(void); - -// Delay in milliseconds, use tusb_time_millis_api() by default. required by some port/configuration with no RTOS -void tusb_time_delay_ms_api(uint32_t ms); - #ifdef __cplusplus } #endif -- cgit v1.3.1 From 19f67ffc22bcf9a59125b0f992bf6e8ee9819eec Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Tue, 9 Sep 2025 14:09:26 -0700 Subject: Initial STM32WBARI eval support Clean up includes definitions Remove wait that is not required Remove redundant settings Clean up clock configuration to look like other modules Remove MSP_Init that is not required Clean up driver code dhcp: Fix DHCP_OFFER/DHCP_ACK destinaton. In RFC 2131, the destination of DHCP OFFER/ACK is defined in Section 4.1. Fix the destination error by following the rule of RFC 2131. TODO: We implement all rule but the last one. ARP table is required to associate client's macaddr. Currently, fallback to broadcast. Signed-off-by: Elwin Huang Fix compile error. Fix goto indentation Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> Fix osal_spin_unlock for mynewt Mynewt version for osal_spin_unlock() called OS_ENTER_CRITICAL instead of OS_EXIT_CRITICAL. Signed-off-by: Jerzy Kasenberg Add ESP32-C5 and ESP32-C61 definitions fix(dcd/dwc2): Fix reset procedure for versions >=4.20a Fix STM32L4 GPIOD clock enable for variants without GPIOD Add weact blackpill support Add to boards.rst file Fix file Small cleanups. Insert small delay for LowSpeed device Improve retry operation at NAK response. Remove dynamic memory allocation use tusb_time_millis_api() instead of board_millis() make loopdelay() always inline update at32f405 dwc2 info and phy width selection add at32f415 dwc2 info add some consumer page configs remove duplicated enum Initial plan Fix obsolete cnt assignment in _tu_fifo_peek() overflow check Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Initial plan Update STM32 CMSIS dependencies to fix HSITRIM register bug Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Remove accidentally committed dependency directories Co-authored-by: hathach <249515+hathach@users.noreply.github.com> Update all STM32 HAL driver dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> fix linker h745 issue with clang fix linker h745 issue with clang Update all STM32 CMSIS device dependencies to latest versions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> update pio-usb Create comprehensive GitHub Copilot instructions and fix pre-commit configuration for TinyUSB (#3234) * Initial plan * Create comprehensive GitHub Copilot instructions for TinyUSB Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove accidentally committed dependencies, use tools/get_deps.py instead Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Fix .gitignore: ignore vendor/ directory not ceedling script Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Revert .gitignore changes and add README_processed.rst Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove README_processed.rst and revert ceedling file permissions Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Changes before error encountered Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * Remove redundant manual validation step, keep only pre-commit and build validation Co-authored-by: hathach <249515+hathach@users.noreply.github.com> * fix pre-commit --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: hathach <249515+hathach@users.noreply.github.com> modified the bsp files of at32 to make them work better the family name error of at32 has been corrected fix pre-commit STM32N6570-DK board is added. Build with DEBUG=1 (make BOARD=stm32n6570dk DEBUG=1 all), otherwise it does not work for now. Tested with examples/device/cdc_dual_ports --- docs/reference/boards.rst | 1 + docs/reference/dependencies.rst | 1 + hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h | 153 +++++++++ hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake | 10 + hw/bsp/stm32wba/boards/stm32wba_eval/board.h | 136 ++++++++ hw/bsp/stm32wba/boards/stm32wba_eval/board.mk | 6 + .../stm32wba_eval/include/stm32wbaxx_hal_conf.h | 368 +++++++++++++++++++++ hw/bsp/stm32wba/family.c | 233 +++++++++++++ hw/bsp/stm32wba/family.mk | 59 ++++ hw/bsp/stm32wba/stm32wbaxx_hal_conf.h | 367 ++++++++++++++++++++ src/common/tusb_mcu.h | 6 + src/portable/st/stm32_fsdev/fsdev_stm32.h | 8 + src/portable/synopsys/dwc2/dwc2_common.c | 5 + src/portable/synopsys/dwc2/dwc2_stm32.h | 23 +- src/tusb_option.h | 1 + tools/get_deps.py | 6 + 16 files changed, 1381 insertions(+), 2 deletions(-) create mode 100644 hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.cmake create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.h create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/board.mk create mode 100644 hw/bsp/stm32wba/boards/stm32wba_eval/include/stm32wbaxx_hal_conf.h create mode 100644 hw/bsp/stm32wba/family.c create mode 100644 hw/bsp/stm32wba/family.mk create mode 100644 hw/bsp/stm32wba/stm32wbaxx_hal_conf.h (limited to 'src') diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 71dca8e94..a930f485b 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -303,6 +303,7 @@ stm32u575eval STM32 U575 Eval stm32u5 https://www.s stm32u575nucleo STM32 U575 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html stm32u5a5nucleo STM32 U5a5 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html +stm32wba65nucleo STM32 NUCLEO-WBA65RI stm32wba https://www.st.com/en/evaluation-tools/nucleo-wba65ri.html =================== ================================= ========= ================================================================= ====== Sunxi diff --git a/docs/reference/dependencies.rst b/docs/reference/dependencies.rst index d75139aae..8a65eee86 100644 --- a/docs/reference/dependencies.rst +++ b/docs/reference/dependencies.rst @@ -71,6 +71,7 @@ hw/mcu/st/stm32l5xx_hal_driver https://github.com/STMicroelectronics/ hw/mcu/st/stm32n6xx_hal_driver https://github.com/STMicroelectronics/stm32n6xx-hal-driver.git 49f9989d10cf6817d4b07ac01848956b46bd0fd6 stm32n6 hw/mcu/st/stm32u5xx_hal_driver https://github.com/STMicroelectronics/stm32u5xx_hal_driver.git 4d93097a67928e9377e655ddd14622adc31b9770 stm32u5 hw/mcu/st/stm32wbxx_hal_driver https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git 2c5f06638be516c1b772f768456ba637f077bac8 stm32wb +hw/mcu/st/stm32wbaxx_hal_driver https://github.com/STMicroelectronics/stm32wbaxx-hal-driver.git 9442fbb71f855ff2e64fbf662b7726beba511a24 stm32wba hw/mcu/ti https://github.com/hathach/ti_driver.git 143ed6cc20a7615d042b03b21e070197d473e6e5 msp430 msp432e4 tm4c hw/mcu/wch/ch32f20x https://github.com/openwch/ch32f20x.git 77c4095087e5ed2c548ec9058e655d0b8757663b ch32f20x hw/mcu/wch/ch32v103 https://github.com/openwch/ch32v103.git 7578cae0b21f86dd053a1f781b2fc6ab99d0ec17 ch32v10x diff --git a/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..471d56aec --- /dev/null +++ b/hw/bsp/stm32wba/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,153 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32wbaxx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#if defined(__ARM_FP) && __ARM_FP >= 4 + #define configENABLE_FPU 1 +#else + #define configENABLE_FPU 0 +#endif +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 4 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< + +#include "stm32wbaxx_hal.h" +#include "bsp/board_api.h" +#include "board.h" + + //--------------------------------------------------------------------+ + // MACRO TYPEDEF CONSTANT ENUM + //--------------------------------------------------------------------+ +#ifndef CFG_BOARD_UART_BAUDRATE +#define CFG_BOARD_UART_BAUDRATE 115200 +#endif + +#ifndef USART_TIMEOUT_TICKS +#define USART_TIMEOUT_TICKS 1000 +#endif + +static UART_HandleTypeDef uart_handle; + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_OTG_HS_IRQHandler( void ) +{ + tud_int_handler( 0 ); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +static void board_gpio_configuration( void ) +{ + GPIO_InitTypeDef gpio_init = { 0 }; + + USART_GPIO_CLK_EN(); + USART_CLK_EN(); + + // Configure USART TX pin + gpio_init.Pin = USART_TX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_NOPULL; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = USART_GPIO_AF; + HAL_GPIO_Init( USART_TX_GPIO_PORT, &gpio_init ); + + // Configure USART RX pin + gpio_init.Pin = USART_RX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = USART_GPIO_AF; + HAL_GPIO_Init( USART_RX_GPIO_PORT, &gpio_init ); + + // Configure the LED + LED_CLK_EN(); + gpio_init.Pin = LED_PIN; + gpio_init.Mode = GPIO_MODE_OUTPUT_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_LOW; + gpio_init.Alternate = 0; + HAL_GPIO_Init( LED_PORT, &gpio_init ); + + // Default LED state is off + board_led_write( false ); + + // Configure the button + BUTTON_CLK_EN(); + gpio_init.Pin = BUTTON_PIN; + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_LOW; + gpio_init.Alternate = 0; + HAL_GPIO_Init( BUTTON_PORT, &gpio_init ); + + // Configure USB DM and DP pins. This is optional, and maintained only for user guidance. + gpio_init.Pin = (GPIO_PIN_7 | GPIO_PIN_6); + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = GPIO_NOPULL; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + HAL_GPIO_Init( GPIOD, &gpio_init ); +} + +static void board_uart_configuration( void ) +{ + uart_handle = ( UART_HandleTypeDef ) { + .Instance = USART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16 + }; + HAL_UART_Init( &uart_handle ); +} + +void board_init( void ) +{ + board_system_clock_config(); + board_gpio_configuration(); + board_uart_configuration(); + +#ifdef USB_OTG_HS + // STM32WBA65/64/62 only has 1 USB HS port + + #if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config( SystemCoreClock / 1000 ); + #elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority( OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + #endif + + // USB clock enable + __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); + __HAL_RCC_USB_OTG_HS_PHY_CLK_ENABLE(); + + // See the reference manual section 11.4.7 for the USB OTG powering sequence + + // Remove the VDDUSB power isolation + PWR->SVMCR |= PWR_SVMCR_USV; + + // Enable VDD11USB supply by clearing VDD11USBDIS to 0 + PWR->VOSR &= ~PWR_VOSR_VDD11USBDIS; + + // Enable USB OTG internal power by setting USBPWREN to 1 + PWR->VOSR |= PWR_VOSR_USBPWREN; + + // Wait for VDD11USB supply to be ready in VDD11USBRDY = 1 + while ((PWR->VOSR & PWR_VOSR_VDD11USBRDY) == 0) {} + + // Enable USB OTG booster by setting USBBOOSTEN to 1 + PWR->VOSR |= PWR_VOSR_USBBOOSTEN; + + // Wait for USB OTG booster to be ready in USBBOOSTRDY = 1 + while ((PWR->VOSR & PWR_VOSR_USBBOOSTRDY) == 0) {} + + // Enable USB power on Pwrctrl CR2 register + PWR->SVMCR |= PWR_SVMCR_USV; + + // Set the reference clock selection (must match the clock source) + SYSCFG->OTGHSPHYCR &= ~SYSCFG_OTGHSPHYCR_CLKSEL; + SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | + SYSCFG_OTGHSPHYCR_CLKSEL_3; // 32MHz clock + + // Configuring the SYSCFG registers OTG_HS PHY + SYSCFG->OTGHSPHYCR |= SYSCFG_OTGHSPHYCR_EN; + + // Disable VBUS sense (B device) + USB_OTG_HS->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + // B-peripheral session valid override enable + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; + USB_OTG_HS->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; +#endif // USB_OTG_FS +} + +void board_led_write( bool state ) +{ + HAL_GPIO_WritePin( LED_PORT, LED_PIN, state ? LED_STATE_ON : ( 1 - LED_STATE_ON ) ); +} + +uint32_t board_button_read( void ) +{ + return HAL_GPIO_ReadPin( BUTTON_PORT, BUTTON_PIN ) == BUTTON_STATE_ACTIVE; +} + +int board_uart_read( uint8_t *buf, int len ) +{ + ( void ) buf; + ( void ) len; + return 0; +} + +int board_uart_write( void const *buf, int len ) +{ + ( void ) HAL_UART_Transmit( &uart_handle, ( const uint8_t * ) buf, len, USART_TIMEOUT_TICKS ); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler( void ) +{ + HAL_IncTick(); + system_ticks++; +} + +uint32_t board_millis( void ) +{ + return system_ticks; +} +#endif + +void HardFault_Handler( void ) +{ + asm( "bkpt 1" ); +} + +// Required by __libc_init_array in startup code if we are compiling using -nostdlib/-nostartfiles. +void _init( void ); +void _init( void ) +{ } diff --git a/hw/bsp/stm32wba/family.mk b/hw/bsp/stm32wba/family.mk new file mode 100644 index 000000000..ca6459ab2 --- /dev/null +++ b/hw/bsp/stm32wba/family.mk @@ -0,0 +1,59 @@ +UF2_FAMILY_ID = 0x70d16657 +ST_FAMILY = wba + +ST_PREFIX = stm32${ST_FAMILY}xx +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m33 + +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32WBA + +CFLAGS_GCC += \ + -flto \ + -nostdlib -nostartfiles \ + -Wno-error=cast-align -Wno-unused-parameter + +LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs -Wl,--gc-sections + +SRC_C += \ + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_icache.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pcd_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_ll_usb.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(BOARD_PATH)/include \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# STM32WBA HAL uses uppercase MCU_VARIANT (excluding the x's) for linking and lowercase MCU_VARIANT for startup. +UPPERCASE_MCU_VARIANT = $(shell echo $(MCU_VARIANT) | sed 's/\([^x]\)/\U\1/g') + +# Startup - Manually specify lowercase version for startup file +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_GCC ?= ${ST_CMSIS}/Source/Templates/gcc/linker/${UPPERCASE_MCU_VARIANT}_FLASH_ns.ld +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash_cm33.icf + +# flash target using on-board stlink +flash: flash-stlink \ No newline at end of file diff --git a/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h new file mode 100644 index 000000000..f4e49f341 --- /dev/null +++ b/hw/bsp/stm32wba/stm32wbaxx_hal_conf.h @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file stm32wbaxx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32wbaxx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32WBAxx_HAL_CONF_H +#define STM32WBAxx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +// #define HAL_ADC_MODULE_ENABLED +// #define HAL_COMP_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +// #define HAL_CRC_MODULE_ENABLED +// #define HAL_CRYP_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GTZC_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_HSEM_MODULE_ENABLED +// #define HAL_I2C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +// #define HAL_IRDA_MODULE_ENABLED +// #define HAL_IWDG_MODULE_ENABLED +// #define HAL_LPTIM_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +// #define HAL_PKA_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMCFG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +// #define HAL_RNG_MODULE_ENABLED +// #define HAL_RTC_MODULE_ENABLED +// #define HAL_SAI_MODULE_ENABLED +// #define HAL_SMARTCARD_MODULE_ENABLED +// #define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +// #define HAL_TSC_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +// #define HAL_WWDG_MODULE_ENABLED +// #define HAL_XSPI_MODULE_ENABLED + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 32000000UL /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations in voltage + and temperature.*/ + +#if defined (RCC_LSI2_SUPPORT) +#if !defined (LSI2_VALUE) +#define LSI2_VALUE 32000UL /*!< LSI2 Typical Value in Hz*/ +#endif /* LSI2_VALUE */ +#endif + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for SAI1 peripheral + * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source + * frequency. + */ +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ################## Register callback feature configuration ############### */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32wbaxx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 1U + +/* ################## CRYP peripheral configuration ########################## */ + +#define USE_HAL_CRYP_SUSPEND_RESUME 0U + +/* ################## HASH peripheral configuration ########################## */ + +#define USE_HAL_HASH_SUSPEND_RESUME 0U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32wbaxx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32wbaxx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32wbaxx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32wbaxx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32wbaxx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32wbaxx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32wbaxx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32wbaxx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32wbaxx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32wbaxx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32wbaxx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32wbaxx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32wbaxx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_HSEM_MODULE_ENABLED +#include "stm32wbaxx_hal_hsem.h" +#endif /* HAL_HSEM_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32wbaxx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32wbaxx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32wbaxx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32wbaxx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32wbaxx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32wbaxx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32wbaxx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32wbaxx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32wbaxx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32wbaxx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32wbaxx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32wbaxx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32wbaxx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32wbaxx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32wbaxx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_TSC_MODULE_ENABLED +#include "stm32wbaxx_hal_tsc.h" +#endif /* HAL_TSC_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32wbaxx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32wbaxx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32wbaxx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32wbaxx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32WBAxx_HAL_CONF_H */ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 3ffc2d1a4..7722ca1e6 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -295,6 +295,12 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32WBA) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_STM32 + #define TUP_DCD_ENDPOINT_MAX 9 + #define TUP_RHPORT_HIGHSPEED 1 + #elif TU_CHECK_MCU(OPT_MCU_STM32U5) #if defined (STM32U535xx) || defined (STM32U545xx) #define TUP_USBIP_FSDEV diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index ccf31e035..01baf50ae 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -148,6 +148,12 @@ /* ST provided header has incorrect value of USB_PMAADDR */ #define FSDEV_PMA_BASE USB1_PMAADDR +#elif defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) + // Available only on STM32WBA62/64/65xx devices + #include "stm32wbaxx.h" + #define FSDEV_PMA_SIZE (2048u) + #define USB USB_DRD_FS + #elif CFG_TUSB_MCU == OPT_MCU_STM32L4 #include "stm32l4xx.h" #define FSDEV_PMA_SIZE (1024u) @@ -289,6 +295,8 @@ static const IRQn_Type fsdev_irq[] = { USB_LP_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 USB_IRQn, + #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA + USB_OTG_HS_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 USB_DRD_FS_IRQn, #else diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index d7d157149..f81cfceda 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -49,6 +49,11 @@ static void reset_core(dwc2_regs_t* dwc2) { uint32_t gsnpsid = dwc2->gsnpsid; // reset core + + // On the STM32WBA peripheral, the device seems to get stuck in reset unless + // this shadow register is utilized. + uint32_t gsnpsid = dwc2->gsnpsid; + dwc2->grstctl |= GRSTCTL_CSRST; if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 672891561..ca5ce5a7c 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -113,6 +113,22 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 #endif + +#elif CFG_TUSB_MCU == OPT_MCU_STM32WBA + #if defined(STM32WBA62xx) + #include "stm32wba62xx.h" + #elif defined(STM32WBA64xx) + #include "stm32wba64xx.h" + #elif defined(STM32WBA65xx) + #include "stm32wba65xx.h" + #else + #error "The selected STM32WBA series chip does not support OTG USB HS" + #endif + + #define USB_OTG_HS_PERIPH_BASE USB_OTG_HS_BASE_NS + #define OTG_HS_IRQn USB_OTG_HS_IRQn + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 #else #error "Unsupported MCUs" #endif @@ -166,6 +182,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // MCU specific PHY init, called BEFORE core reset // - dwc2 3.30a (H5) use USB_HS_PHYC // - dwc2 4.11a (U5) use femtoPHY +// - dwc2 x.xxx (WBA) use USB_OTG_HS static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { // Enable on-chip FS PHY @@ -194,11 +211,10 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { #endif } else { -#if CFG_TUSB_MCU != OPT_MCU_STM32U5 +#if CFG_TUSB_MCU != OPT_MCU_STM32U5 && CFG_TUSB_MCU != OPT_MCU_STM32WBA // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' dwc2->stm32_gccfg &= ~STM32_GCCFG_PWRDWN; #endif - // Enable on-chip HS PHY if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { #ifdef USB_HS_PHYC @@ -233,11 +249,14 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // Enable PLL internal PHY USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; +<<<<<<< HEAD // Wait ~2ms until the PLL is ready (there's no RDY bit to query) tusb_time_delay_ms_api(2); #else +======= +>>>>>>> 246a92c65 (It worksgit status!) #endif } } diff --git a/src/tusb_option.h b/src/tusb_option.h index 1533bb209..b2dd5fcb2 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -95,6 +95,7 @@ #define OPT_MCU_STM32H7RS 317 ///< ST F7RS #define OPT_MCU_STM32C0 318 ///< ST C0 #define OPT_MCU_STM32N6 319 ///< ST N6 +#define OPT_MCU_STM32WBA 320 ///< ST WBA // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 36b4d2d59..37d541785 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -130,6 +130,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', 'cda2cb9fc4a5232ab18efece0bb06b0b60910083', 'stm32wb'], + 'hw/mcu/st/cmsis_device_wba': ['https://github.com/STMicroelectronics/cmsis-device-wba', + '647d8522e5fd15049e9a1cc30ed19d85e5911eaf', + 'stm32wba'], 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', 'stm32h7'], @@ -193,6 +196,9 @@ deps_optional = { 'hw/mcu/st/stm32wbxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbxx_hal_driver.git', 'd60dd46996876506f1d2e9abd6b1cc110c8004cd', 'stm32wb'], + 'hw/mcu/st/stm32wbaxx_hal_driver': ['https://github.com/STMicroelectronics/stm32wbaxx_hal_driver.git', + '9442fbb71f855ff2e64fbf662b7726beba511a24', + 'stm32wba'], 'hw/mcu/ti': ['https://github.com/hathach/ti_driver.git', '143ed6cc20a7615d042b03b21e070197d473e6e5', 'msp430 msp432e4 tm4c'], -- cgit v1.3.1 From 48f6b95bd8b0c3d33832f289b02b53da410d5ef9 Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Tue, 9 Sep 2025 15:41:12 -0700 Subject: Incorporate upstream changes to dwc2_common.c --- src/portable/synopsys/dwc2/dwc2_common.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index f81cfceda..9b8333ad2 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -49,11 +49,6 @@ static void reset_core(dwc2_regs_t* dwc2) { uint32_t gsnpsid = dwc2->gsnpsid; // reset core - - // On the STM32WBA peripheral, the device seems to get stuck in reset unless - // this shadow register is utilized. - uint32_t gsnpsid = dwc2->gsnpsid; - dwc2->grstctl |= GRSTCTL_CSRST; if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { @@ -100,14 +95,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; const dwc2_ghwcfg4_t ghwcfg4 = {.value = dwc2->ghwcfg4}; - uint8_t phy_width; - if (CFG_TUSB_MCU != OPT_MCU_AT32F402_405 && // at32f402_405 does not support 16-bit - ghwcfg4.phy_data_width) { - phy_width = 16; // 16-bit PHY interface if supported - } else { - phy_width = 8; // 8-bit PHY interface - } - // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; @@ -135,10 +122,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; // Set 16-bit interface if supported - if (phy_width == 16) { - gusbcfg |= GUSBCFG_PHYIF16; + if (ghwcfg4.phy_data_width) { + #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit + gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + #endif } else { - gusbcfg &= ~GUSBCFG_PHYIF16; + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } } @@ -155,7 +144,13 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (phy_width == 16 ? 5u : 9u) << GUSBCFG_TRDT_Pos; + +#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit + gusbcfg |= 9u << GUSBCFG_TRDT_Pos; +#else + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; +#endif + dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset -- cgit v1.3.1 From c9527bc0964dcd883df7ec485e2d71333ed780c0 Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Wed, 10 Sep 2025 11:14:52 -0700 Subject: Bring up to date with master --- src/portable/synopsys/dwc2/dwc2_stm32.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index ca5ce5a7c..08950ccc0 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -249,14 +249,11 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // Enable PLL internal PHY USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; -<<<<<<< HEAD // Wait ~2ms until the PLL is ready (there's no RDY bit to query) tusb_time_delay_ms_api(2); #else -======= ->>>>>>> 246a92c65 (It worksgit status!) #endif } } -- cgit v1.3.1 From 5e661eac8809f3bfdafd357d00013d94b71b4000 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 11 Sep 2025 10:57:02 +0700 Subject: Revert "Incorporate upstream changes to dwc2_common.c" This reverts commit 48f6b95bd8b0c3d33832f289b02b53da410d5ef9. also revert gsnpsid shadown since it is already in the upstream --- src/portable/synopsys/dwc2/dwc2_common.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 9b8333ad2..d7d157149 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -95,6 +95,14 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2}; const dwc2_ghwcfg4_t ghwcfg4 = {.value = dwc2->ghwcfg4}; + uint8_t phy_width; + if (CFG_TUSB_MCU != OPT_MCU_AT32F402_405 && // at32f402_405 does not support 16-bit + ghwcfg4.phy_data_width) { + phy_width = 16; // 16-bit PHY interface if supported + } else { + phy_width = 8; // 8-bit PHY interface + } + // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; @@ -122,12 +130,10 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; // Set 16-bit interface if supported - if (ghwcfg4.phy_data_width) { - #if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit - gusbcfg |= GUSBCFG_PHYIF16; // 16 bit - #endif + if (phy_width == 16) { + gusbcfg |= GUSBCFG_PHYIF16; } else { - gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + gusbcfg &= ~GUSBCFG_PHYIF16; } } @@ -144,13 +150,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - -#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit - gusbcfg |= 9u << GUSBCFG_TRDT_Pos; -#else - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; -#endif - + gusbcfg |= (phy_width == 16 ? 5u : 9u) << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset -- cgit v1.3.1 From af7310b925c031d23ba490e8f70965f345da1a4d Mon Sep 17 00:00:00 2001 From: Dalton Caron Date: Thu, 11 Sep 2025 09:13:54 -0700 Subject: Revert fsdev_stm32.h changes --- src/portable/st/stm32_fsdev/fsdev_stm32.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index 01baf50ae..ccf31e035 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -148,12 +148,6 @@ /* ST provided header has incorrect value of USB_PMAADDR */ #define FSDEV_PMA_BASE USB1_PMAADDR -#elif defined(STM32WBA62xx) || defined(STM32WBA64xx) || defined(STM32WBA65xx) - // Available only on STM32WBA62/64/65xx devices - #include "stm32wbaxx.h" - #define FSDEV_PMA_SIZE (2048u) - #define USB USB_DRD_FS - #elif CFG_TUSB_MCU == OPT_MCU_STM32L4 #include "stm32l4xx.h" #define FSDEV_PMA_SIZE (1024u) @@ -295,8 +289,6 @@ static const IRQn_Type fsdev_irq[] = { USB_LP_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 USB_IRQn, - #elif CFG_TUSB_MCU == OPT_MCU_STM32WBA - USB_OTG_HS_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 USB_DRD_FS_IRQn, #else -- cgit v1.3.1 From 5755afa690f242988c02932068339ad5ffc4404e Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Sep 2025 11:39:41 +0200 Subject: Fix some IAR warnings Signed-off-by: HiFiPhile --- src/class/hid/hid_host.c | 3 ++- src/host/usbh.c | 29 +++++++++++++++-------------- src/portable/ehci/ehci.c | 5 +++-- 3 files changed, 20 insertions(+), 17 deletions(-) (limited to 'src') diff --git a/src/class/hid/hid_host.c b/src/class/hid/hid_host.c index 56fccdd22..a44c83433 100644 --- a/src/class/hid/hid_host.c +++ b/src/class/hid/hid_host.c @@ -519,7 +519,8 @@ bool hidh_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const* desc_ // Assume bNumDescriptors = 1 p_hid->report_desc_type = desc_hid->bReportType; - p_hid->report_desc_len = tu_unaligned_read16(&desc_hid->wReportLength); + // Use offsetof to avoid pointer to the odd/misaligned address + p_hid->report_desc_len = tu_unaligned_read16((uint8_t const*)desc_hid + offsetof(tusb_hid_descriptor_hid_t, wReportLength)); // Per HID Specs: default is Report protocol, though we will force Boot protocol when set_config p_hid->protocol_mode = _hidh_default_protocol; diff --git a/src/host/usbh.c b/src/host/usbh.c index ce83977c5..1c63ac712 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -400,7 +400,7 @@ bool tuh_descriptor_get_device_local(uint8_t daddr, tusb_desc_device_t* desc_dev tusb_speed_t tuh_speed_get(uint8_t daddr) { tuh_bus_info_t bus_info; tuh_bus_info_get(daddr, &bus_info); - return bus_info.speed; + return (tusb_speed_t)bus_info.speed; } bool tuh_rhport_is_active(uint8_t rhport) { @@ -651,7 +651,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { tuh_xfer_t xfer = { .daddr = event.dev_addr, .ep_addr = ep_addr, - .result = event.xfer_complete.result, + .result = (xfer_result_t)event.xfer_complete.result, .actual_len = event.xfer_complete.len, .buflen = 0, // not available .buffer = NULL, // not available @@ -832,18 +832,19 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t } TU_ATTR_FALLTHROUGH; - case CONTROL_STAGE_DATA: - if (request->wLength) { - TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr); - TU_LOG_MEM_USBH(ctrl_info->buffer, xferred_bytes, 2); - } - ctrl_info->actual_len = (uint16_t) xferred_bytes; - - // ACK stage: toggle is always 1 - _control_set_xfer_stage(CONTROL_STAGE_ACK); - const uint8_t ep_status = tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction); - TU_ASSERT(hcd_edpt_xfer(rhport, daddr, ep_status, NULL, 0)); - break; + case CONTROL_STAGE_DATA: { + if (request->wLength) { + TU_LOG_USBH("[%u:%u] Control data:\r\n", rhport, daddr); + TU_LOG_MEM_USBH(ctrl_info->buffer, xferred_bytes, 2); + } + ctrl_info->actual_len = (uint16_t) xferred_bytes; + + // ACK stage: toggle is always 1 + _control_set_xfer_stage(CONTROL_STAGE_ACK); + const uint8_t ep_status = tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction); + TU_ASSERT(hcd_edpt_xfer(rhport, daddr, ep_status, NULL, 0)); + break; + } case CONTROL_STAGE_ACK: { // Abort all pending transfers if SET_CONFIGURATION request diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index da9f49d29..b372fe635 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -184,7 +184,8 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { //--------------------------------------------------------------------+ uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3; + uint32_t uframe = ehci_data.regs->frame_index; + return (ehci_data.uframe_number + uframe) >> 3; } void hcd_port_reset(uint8_t rhport) { @@ -896,7 +897,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->used = 1; p_qhd->removing = 0; p_qhd->attached_qtd = NULL; - p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint + p_qhd->pid = tu_edpt_dir(ep_desc->bEndpointAddress) == TUSB_DIR_IN ? EHCI_PID_IN : EHCI_PID_OUT; // PID for TD under this endpoint //------------- active, but no TD list -------------// p_qhd->qtd_overlay.halted = 0; -- cgit v1.3.1 From 4db2bdad07f55b03df8c40928a2b56536fa823e3 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Sep 2025 14:08:54 +0200 Subject: echi: fix NXP USBPHY disconnection detection Signed-off-by: HiFiPhile --- src/portable/ehci/ehci.c | 60 +++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index b372fe635..76b0142b2 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -38,6 +38,11 @@ #include "ehci_api.h" #include "ehci.h" +// NXP specific fixes +#if TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX, OPT_MCU_LPC55, OPT_MCU_MCXN9) +#include "fsl_device_registers.h" +#endif + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -179,6 +184,36 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { } } +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +static void nxp_usbphy_disconn_detector_set(uint8_t port, bool enable) { + // unify naming convention +#if !defined(USBPHY1) && defined(USBPHY) + #define USBPHY1 USBPHY +#endif + + if (port == 0) { + if (enable) { + USBPHY1->CTRL_SET = USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } else { + USBPHY1->CTRL_CLR = USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + } +#if FSL_FEATURE_SOC_USBPHY_COUNT > 1U + else if (port == 1) { + if (enable) { + USBPHY2->CTRL_SET = USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } else { + USBPHY2->CTRL_CLR = USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + } +#endif + +#if !defined(USBPHY1) && defined(USBPHY) + #undef USBPHY1 +#endif +} +#endif + //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ @@ -213,16 +248,21 @@ void hcd_port_reset_end(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; - // skip if reset is already complete - if (!regs->portsc_bm.port_reset) { - return; - } + // stop reset only if is not complete yet + if (regs->portsc_bm.port_reset) { + // mask out all change bits since they are Write 1 to clear + uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C; + portsc &= ~EHCI_PORTSC_MASK_PORT_RESET; - // mask out all change bits since they are Write 1 to clear - uint32_t portsc = regs->portsc & ~EHCI_PORTSC_MASK_W1C; - portsc &= ~EHCI_PORTSC_MASK_PORT_RESET; + regs->portsc = portsc; + } - regs->portsc = portsc; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + // Enable disconnect detector for highspeed device only + if (hcd_port_speed_get(rhport) == TUSB_SPEED_HIGH) { + nxp_usbphy_disconn_detector_set(rhport, true); + } +#endif } bool hcd_port_connect_status(uint8_t rhport) { @@ -579,6 +619,10 @@ void port_connect_status_change_isr(uint8_t rhport) { hcd_event_device_attach(rhport, true); } else // device unplugged { +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + // Disable disconnect detector + nxp_usbphy_disconn_detector_set(rhport, false); +#endif hcd_event_device_remove(rhport, true); } } -- cgit v1.3.1 From 99bee6a900db60cf232766531e785108f50e614d Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Sep 2025 14:25:44 +0200 Subject: ehci: fix removed qhd get reused Signed-off-by: HiFiPhile --- src/host/usbh.c | 2 +- src/portable/ehci/ehci.c | 14 +++++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/host/usbh.c b/src/host/usbh.c index 1c63ac712..d09874d6e 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -844,7 +844,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t const uint8_t ep_status = tu_edpt_addr(0, 1 - request->bmRequestType_bit.direction); TU_ASSERT(hcd_edpt_xfer(rhport, daddr, ep_status, NULL, 0)); break; - } + } case CONTROL_STAGE_ACK: { // Abort all pending transfers if SET_CONFIGURATION request diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 76b0142b2..953483583 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -35,6 +35,7 @@ #include "host/hcd.h" #include "host/usbh.h" +#include "host/usbh_pvt.h" #include "ehci_api.h" #include "ehci.h" @@ -866,14 +867,21 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; + + // protect qhd_pool since 'used' and 'removing' can be changed in isr + ehci_qhd_t *result = NULL; + usbh_spin_lock(false); for (uint32_t i = 0; i < QHD_MAX; i++) { if ((qhd_pool[i].dev_addr == dev_addr) && - ep_addr == qhd_ep_addr(&qhd_pool[i])) { - return &qhd_pool[i]; + ep_addr == qhd_ep_addr(&qhd_pool[i]) && + qhd_pool[i].used && !qhd_pool[i].removing) { + result = &qhd_pool[i]; + break; } } + usbh_spin_unlock(false); - return NULL; + return result; } // Init queue head with endpoint descriptor -- cgit v1.3.1 From 8515e47ad9980f8ad380913bda72425b1bb83648 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Sep 2025 16:49:55 +0200 Subject: Update comment Signed-off-by: HiFiPhile --- src/portable/st/stm32_fsdev/fsdev_stm32.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index 770baa05a..95f40269a 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -268,7 +268,10 @@ #endif #ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP - // Defaults to double-buffered isochronous endpoints on devices with >1KB PMA + // Default configuration for double-buffered isochronous endpoints: + // - Enable double buffering on devices with >1KB Packet Memory Area (PMA) + // to improve isochronous transfer reliability and performance + // - Disable on devices with limited PMA to conserve memory space #if FSDEV_PMA_SIZE > 1024u #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 1 #else @@ -277,12 +280,16 @@ #endif #if FSDEV_HAS_SBUF_ISO != 0 && CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP == 0 - // If hardware has SBUF_ISO bit single-buffered endpoints consume only - // one half of endpoint pair register. + // SBUF_ISO configuration: + // - Some STM32 devices have special hardware support for single-buffered isochronous endpoints + // - When SBUF_ISO bit is available and double buffering is disabled: + // Enable SBUF_ISO to optimize endpoint register usage (one half of endpoint pair register) #define FSDEV_USE_SBUF_ISO 1 #else - // Otherwise it consumes entire endpoint pair but we can at least save - // memory by configuring the same buffer twice. + // When either: + // - Hardware doesn't support SBUF_ISO feature, or + // - Double buffering is enabled for isochronous endpoints + // We must use the entire endpoint pair register #define FSDEV_USE_SBUF_ISO 0 #endif -- cgit v1.3.1 From cf6cbf0d1aca1985dcc8d1b88279028ec044e7a8 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 12 Sep 2025 21:30:53 +0200 Subject: Fix AT32 compile after #3152 Signed-off-by: HiFiPhile --- src/portable/st/stm32_fsdev/fsdev_at32.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/fsdev_at32.h b/src/portable/st/stm32_fsdev/fsdev_at32.h index 3a785bbbd..f7ee89995 100644 --- a/src/portable/st/stm32_fsdev/fsdev_at32.h +++ b/src/portable/st/stm32_fsdev/fsdev_at32.h @@ -36,9 +36,14 @@ #endif #define FSDEV_PMA_SIZE (512u) +#define FSDEV_USE_SBUF_ISO 0 #define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL) #define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL) +#ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP + #define CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP 0 +#endif + /**************************** ISTR interrupt events *************************/ #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */ #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */ -- cgit v1.3.1 From cc19c02f860f96299ceccdfcaf1befb308c9fab8 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Sep 2025 15:47:06 +0700 Subject: dwc2: wait for ahb idle before core reset --- .idea/debugServers/AT32F423VCT7.xml | 13 +++++++++++++ .idea/debugServers/ST_LINK.xml | 13 +++++++++++++ .idea/debugServers/at32f403acgu7.xml | 13 +++++++++++++ .idea/debugServers/max32690.xml | 13 +++++++++++++ .idea/debugServers/s3.xml | 6 ++++++ .idea/debugServers/wch_riscv.xml | 14 ++++++++++++++ src/common/tusb_common.h | 4 ++-- src/portable/synopsys/dwc2/dwc2_common.c | 16 +++++++++++----- 8 files changed, 85 insertions(+), 7 deletions(-) create mode 100644 .idea/debugServers/AT32F423VCT7.xml create mode 100644 .idea/debugServers/ST_LINK.xml create mode 100644 .idea/debugServers/at32f403acgu7.xml create mode 100644 .idea/debugServers/max32690.xml create mode 100644 .idea/debugServers/s3.xml create mode 100644 .idea/debugServers/wch_riscv.xml (limited to 'src') diff --git a/.idea/debugServers/AT32F423VCT7.xml b/.idea/debugServers/AT32F423VCT7.xml new file mode 100644 index 000000000..38b3d76ef --- /dev/null +++ b/.idea/debugServers/AT32F423VCT7.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/ST_LINK.xml b/.idea/debugServers/ST_LINK.xml new file mode 100644 index 000000000..7c21d3879 --- /dev/null +++ b/.idea/debugServers/ST_LINK.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/at32f403acgu7.xml b/.idea/debugServers/at32f403acgu7.xml new file mode 100644 index 000000000..9df65140f --- /dev/null +++ b/.idea/debugServers/at32f403acgu7.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/max32690.xml b/.idea/debugServers/max32690.xml new file mode 100644 index 000000000..3551f591e --- /dev/null +++ b/.idea/debugServers/max32690.xml @@ -0,0 +1,13 @@ + + + + + + + + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/s3.xml b/.idea/debugServers/s3.xml new file mode 100644 index 000000000..a03abf744 --- /dev/null +++ b/.idea/debugServers/s3.xml @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/.idea/debugServers/wch_riscv.xml b/.idea/debugServers/wch_riscv.xml new file mode 100644 index 000000000..2e147f1b6 --- /dev/null +++ b/.idea/debugServers/wch_riscv.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + \ No newline at end of file diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 1fb93da11..e35d3e6fe 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -168,8 +168,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t ui16) { return TU_U16_LOW(ui16); } //------------- Bits -------------// -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); } -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); } TU_ATTR_ALWAYS_INLINE static inline bool tu_bit_test (uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; } //------------- Min -------------// diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index d7d157149..5ff18ab94 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -45,20 +45,26 @@ // //-------------------------------------------------------------------- static void reset_core(dwc2_regs_t* dwc2) { + // The software must check that bit 31 in this register is set to 1 (AHB Master is Idle) before starting any operation + while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) { + } + // load gsnpsid (it is not readable after reset is asserted) - uint32_t gsnpsid = dwc2->gsnpsid; + const uint32_t gsnpsid = dwc2->gsnpsid; // reset core dwc2->grstctl |= GRSTCTL_CSRST; if ((gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { - // prior v4.20a CSRST is self-clearing + // prior v4.20a: CSRST is self-clearing and the core clears this bit after all the necessary logic is reset in + // the core, which can take several clocks, depending on the current state of the core. Once this bit has been + // cleared, the software must wait at least 3 PHY clocks before accessing the PHY domain (synchronization delay). while (dwc2->grstctl & GRSTCTL_CSRST) {} } else { - // From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking. - // CSRST must also be explicitly cleared + // From v4.20a: CSRST bit is write only. The application must clear this bit after checking the bit 29 of this + // register i.e Core Soft Reset Done CSRT_DONE (w1c) while (!(dwc2->grstctl & GRSTCTL_CSRST_DONE)) {} - dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE; + dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE; } while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE -- cgit v1.3.1 From 6f06effd03d1163b3e4069d61cf158fc55eb9133 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 15 Sep 2025 16:18:07 +0700 Subject: add nrf54 to dwc2 info --- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 2 files changed, 59 insertions(+), 58 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index e6b7820bc..f655e4dba 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | -|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| -| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | -| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | -| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | -| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | -| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | -| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | -| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | -| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | -| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | -| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | -| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | -| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | -| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | -| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| | AT32 F405 FS | AT32 F405 HS | AT32 F415 | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | nRF54 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5/H7RS/N6 HS | XMC4500 | GD32VF103 | +|:---------------------------|:---------------|:---------------|:------------|:----------------|:-------------|:--------------|:-------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:---------------------|:-------------|:------------| +| GUID | 0x00002000 | 0x00000000 | 0x00001000 | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54400A | 0x4F54400A | 0x4F54400A | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54430A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 4.00a | 4.00a | 4.00a | 2.80a | 3.30a | 4.00a | 4.00a | 4.30a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0xAA555000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228FDD00 | 0x229FDDD0 | 0x228DCD00 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x228BFC72 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | Slave only | DMA internal | Slave only | DMA internal | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | hub | hub | hub | n/a | hub | n/a | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | n/a | UTMI+/ULPI | n/a | UTMI+ | n/a | n/a | UTMI+/ULPI | UTMI+ | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Shared ULPI | n/a | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 7 | 3 | 7 | 6 | 6 | 15 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 15 | 15 | 7 | 7 | 13 | 7 | 15 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 8 | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x020004E8 | 0x03F006E8 | 0x020004E8 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x0BEAC0E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 8 | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 6 | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 512 | 1008 | 512 | 4080 | 498 | 200 | 896 | 3050 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF0A020 | 0x1FF0A020 | 0x0000000F | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x1E10AA60 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 7 | 0 | 7 | 6 | 4 | 7 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index a90150632..f6bd2785a 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -16,6 +16,7 @@ dwc2_reg_value = { 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030], 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], + 'nRF54': [0, 0x4F54430A, 0xAA555000, 0x228BFC72, 0x0BEAC0E8, 0x1E10AA60], 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030], 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030], 'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], -- cgit v1.3.1