From e84efd2771858b9f00d78824ccf8b1fade5f103c Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 25 Jan 2025 13:00:41 +0100
Subject: Add STM32 DWC2 cache support

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/common/tusb_mcu.h                   | 15 +++++++
 src/portable/synopsys/dwc2/dcd_dwc2.c   |  2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h | 73 +++++++++++++++++++++++++++++++++
 src/portable/synopsys/dwc2/hcd_dwc2.c   |  2 +-
 4 files changed, 90 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 2ee2132bf..8b30c98cd 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -220,12 +220,23 @@
     #define TUP_RHPORT_HIGHSPEED  1 // Port0: FS, Port1: HS
   #endif
 
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
+  #include "stm32h7xx.h"
   #define TUP_USBIP_DWC2
   #define TUP_USBIP_DWC2_STM32
 
   #define TUP_DCD_ENDPOINT_MAX    9
 
+  #if __CORTEX_M == 7
+    #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+    #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+    #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+  #endif
+
 #elif TU_CHECK_MCU(OPT_MCU_STM32H5)
   #define TUP_USBIP_FSDEV
   #define TUP_USBIP_FSDEV_STM32
@@ -322,6 +333,10 @@
   // MCU with on-chip HS Phy
   #define TUP_RHPORT_HIGHSPEED    1
 
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+
 //--------------------------------------------------------------------+
 // Sony
 //--------------------------------------------------------------------+
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index 5f86d6b76..f7e9aacfe 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
-#if CFG_TUD_MEM_DCACHE_ENABLE
+#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE
 bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
   TU_VERIFY(addr && data_size);
   return dwc2_dcache_clean(addr, data_size);
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index dc4251c29..f01d11fe8 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -279,6 +279,79 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   }
 }
 
+//------------- DCache -------------//
+#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE)
+
+typedef struct
+{
+  uintptr_t start;
+  uintptr_t end;
+} mem_region_t;
+
+// Can be used to define additional uncached regions
+#ifndef CFG_DWC2_MEM_UNCACHED_REGIONS
+#define CFG_DWC2_MEM_UNCACHED_REGIONS
+#endif
+
+static mem_region_t uncached_regions[] = {
+  // DTCM (although USB DMA can't transfer to/from DTCM)
+#if CFG_TUSB_MCU == OPT_MCU_STM32H7
+  {.start = 0x20000000, .end = 0x2001FFFF},
+#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS
+  // DTCM (although USB DMA can't transfer to/from DTCM)
+  {.start = 0x20000000, .end = 0x2002FFFF},
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F7
+    // DTCM
+  {.start = 0x20000000, .end = 0x2000FFFF},
+#else
+#error "Cache maintenance is not supported yet"
+#endif
+  CFG_DWC2_MEM_UNCACHED_REGIONS
+};
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
+  if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) {
+    size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE;
+  }
+  return size;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
+  for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
+    if (addr >= uncached_regions[i].start && addr <= uncached_regions[i].end)
+      return false;
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
+  const uintptr_t addr32 = (uintptr_t) addr;
+  if (is_cache_mem(addr32)) {
+    data_size = round_up_to_cache_line_size(data_size);
+    SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size);
+  }
+  return true;
+}
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index 257fa2833..6b48c2346 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
   return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
 }
 
-#if CFG_TUH_MEM_DCACHE_ENABLE
+#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE
 bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
   TU_VERIFY(addr && data_size);
   return dwc2_dcache_clean(addr, data_size);
-- 
cgit v1.3.1


From e19ff3ecae3b5a04756749a3d8496e6284f37d85 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 13 Jun 2025 13:17:41 +0200
Subject: Add cache line size alignment to buffer macro

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/common/tusb_types.h | 12 ++++++------
 src/tusb_option.h       | 14 ++++++++++++++
 2 files changed, 20 insertions(+), 6 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index fd7f01b67..2099e1af8 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -36,39 +36,39 @@
 #endif
 
 //------------- Device DCache declaration -------------//
-#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
+#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \
   (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
 
 // Declare an endpoint buffer with uint8_t[size]
 #define TUD_EPBUF_DEF(_name, _size) \
   union { \
     CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
-    uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
+    TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
   }
 
 // Declare an endpoint buffer with a type
 #define TUD_EPBUF_TYPE_DEF(_type, _name) \
   union { \
     CFG_TUD_MEM_ALIGN _type _name; \
-    uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+    TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
   }
 
 //------------- Host DCache declaration -------------//
-#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
+#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \
   (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
 
 // Declare an endpoint buffer with uint8_t[size]
 #define TUH_EPBUF_DEF(_name, _size) \
   union { \
     CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
-    uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
+    TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
   }
 
 // Declare an endpoint buffer with a type
 #define TUH_EPBUF_TYPE_DEF(_type, _name) \
   union { \
     CFG_TUH_MEM_ALIGN _type _name; \
-    uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+    TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
   }
 
 
diff --git a/src/tusb_option.h b/src/tusb_option.h
index cca6096c6..42c2e650f 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -465,6 +465,13 @@
   #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
 #endif
 
+#if CFG_TUD_MEM_DCACHE_ENABLE && \
+  (CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
+  #define TUD_EPBUF_DCACHE_ALIGNED 1
+#else
+  #define TUD_EPBUF_DCACHE_ALIGNED 0
+#endif
+
 #ifndef CFG_TUD_ENDPOINT0_SIZE
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
@@ -584,6 +591,13 @@
   #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
 #endif
 
+#if CFG_TUH_MEM_DCACHE_ENABLE && \
+  (CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
+  #define TUH_EPBUF_DCACHE_ALIGNED 1
+#else
+  #define TUH_EPBUF_DCACHE_ALIGNED 0
+#endif
+
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
-- 
cgit v1.3.1


From ea02e929b4daafb28be30b08609a6f68f64e2a0d Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Fri, 13 Jun 2025 18:44:05 +0200
Subject: audio: buffer macro update

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/class/audio/audio_device.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c
index 11a3d4a73..dc45a72bc 100644
--- a/src/class/audio/audio_device.c
+++ b/src/class/audio/audio_device.c
@@ -109,14 +109,14 @@
 
 // Put swap buffer in USB section only if necessary
 #if USE_LINEAR_BUFFER
-  #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
+  #define IN_SW_BUF_MEM_ATTR
 #else
-  #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
+  #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
 #endif
 #if USE_LINEAR_BUFFER
-  #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
+  #define OUT_SW_BUF_MEM_ATTR
 #else
-  #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
+  #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION
 #endif
 
 // EP IN software buffers and mutexes
-- 
cgit v1.3.1


From 3287cfaf76fb37644aa17c2e639d7d59b2764e59 Mon Sep 17 00:00:00 2001
From: HiFiPhile <admin@hifiphile.com>
Date: Sat, 5 Jul 2025 12:35:47 +0200
Subject: Use DMA enable for DCache condition

Signed-off-by: HiFiPhile <admin@hifiphile.com>
---
 src/common/tusb_mcu.h                   | 15 +++++++++------
 src/common/tusb_types.h                 | 12 ++++++------
 src/portable/synopsys/dwc2/dcd_dwc2.c   |  2 +-
 src/portable/synopsys/dwc2/dwc2_stm32.h |  2 +-
 src/portable/synopsys/dwc2/hcd_dwc2.c   |  2 +-
 src/tusb_option.h                       | 14 --------------
 6 files changed, 18 insertions(+), 29 deletions(-)

(limited to 'src')

diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 8b30c98cd..4205239f1 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -220,8 +220,9 @@
     #define TUP_RHPORT_HIGHSPEED  1 // Port0: FS, Port1: HS
   #endif
 
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
@@ -232,8 +233,9 @@
   #define TUP_DCD_ENDPOINT_MAX    9
 
   #if __CORTEX_M == 7
-    #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
-    #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  // Enable dcache if DMA is enabled
+    #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
+    #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
     #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
   #endif
 
@@ -333,8 +335,9 @@
   // MCU with on-chip HS Phy
   #define TUP_RHPORT_HIGHSPEED    1
 
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
+  // Enable dcache if DMA is enabled
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
 
 //--------------------------------------------------------------------+
diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h
index 4735c983a..ee97069bd 100644
--- a/src/common/tusb_types.h
+++ b/src/common/tusb_types.h
@@ -36,39 +36,39 @@
 #endif
 
 //------------- Device DCache declaration -------------//
-#define TUD_EPBUF_DCACHE_SIZE(_size) (TUD_EPBUF_DCACHE_ALIGNED ? \
+#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
   (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
 
 // Declare an endpoint buffer with uint8_t[size]
 #define TUD_EPBUF_DEF(_name, _size) \
   union { \
     CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
-    TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
+    TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
   }
 
 // Declare an endpoint buffer with a type
 #define TUD_EPBUF_TYPE_DEF(_type, _name) \
   union { \
     CFG_TUD_MEM_ALIGN _type _name; \
-    TU_ATTR_ALIGNED(TUD_EPBUF_DCACHE_ALIGNED ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+    TU_ATTR_ALIGNED(CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
   }
 
 //------------- Host DCache declaration -------------//
-#define TUH_EPBUF_DCACHE_SIZE(_size) (TUH_EPBUF_DCACHE_ALIGNED ? \
+#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
   (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
 
 // Declare an endpoint buffer with uint8_t[size]
 #define TUH_EPBUF_DEF(_name, _size) \
   union { \
     CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
-    TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
+    TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
   }
 
 // Declare an endpoint buffer with a type
 #define TUH_EPBUF_TYPE_DEF(_type, _name) \
   union { \
     CFG_TUH_MEM_ALIGN _type _name; \
-    TU_ATTR_ALIGNED(TUH_EPBUF_DCACHE_ALIGNED ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
+    TU_ATTR_ALIGNED(CFG_TUH_MEM_DCACHE_ENABLE ? CFG_TUH_MEM_DCACHE_LINE_SIZE : 1) uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
   }
 
 
diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c
index f7e9aacfe..5f86d6b76 100644
--- a/src/portable/synopsys/dwc2/dcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/dcd_dwc2.c
@@ -88,7 +88,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
-#if CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE
+#if CFG_TUD_MEM_DCACHE_ENABLE
 bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
   TU_VERIFY(addr && data_size);
   return dwc2_dcache_clean(addr, data_size);
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index f01d11fe8..f9aa5301b 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -280,7 +280,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 }
 
 //------------- DCache -------------//
-#if (CFG_TUD_MEM_DCACHE_ENABLE && CFG_TUD_DWC2_DMA_ENABLE) || (CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE)
+#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
 
 typedef struct
 {
diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c
index 6b48c2346..257fa2833 100644
--- a/src/portable/synopsys/dwc2/hcd_dwc2.c
+++ b/src/portable/synopsys/dwc2/hcd_dwc2.c
@@ -141,7 +141,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
   return CFG_TUH_DWC2_DMA_ENABLE && ghwcfg2.arch == GHWCFG2_ARCH_INTERNAL_DMA;
 }
 
-#if CFG_TUH_MEM_DCACHE_ENABLE && CFG_TUH_DWC2_DMA_ENABLE
+#if CFG_TUH_MEM_DCACHE_ENABLE
 bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
   TU_VERIFY(addr && data_size);
   return dwc2_dcache_clean(addr, data_size);
diff --git a/src/tusb_option.h b/src/tusb_option.h
index b8a4059a8..867babc33 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -465,13 +465,6 @@
   #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
 #endif
 
-#if CFG_TUD_MEM_DCACHE_ENABLE && \
-  (CFG_TUD_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
-  #define TUD_EPBUF_DCACHE_ALIGNED 1
-#else
-  #define TUD_EPBUF_DCACHE_ALIGNED 0
-#endif
-
 #ifndef CFG_TUD_ENDPOINT0_SIZE
   #define CFG_TUD_ENDPOINT0_SIZE  64
 #endif
@@ -591,13 +584,6 @@
   #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
 #endif
 
-#if CFG_TUH_MEM_DCACHE_ENABLE && \
-  (CFG_TUH_DWC2_DMA_ENABLE || defined(TUP_USBIP_CHIPIDEA_HS))
-  #define TUH_EPBUF_DCACHE_ALIGNED 1
-#else
-  #define TUH_EPBUF_DCACHE_ALIGNED 0
-#endif
-
 //------------- CLASS -------------//
 
 #ifndef CFG_TUH_HUB
-- 
cgit v1.3.1


From 3eb04518796e81e41ff119dc5acf33bf5241fdec Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 7 Jul 2025 12:33:14 +0700
Subject: change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1 use
 stock iar linker

---
 hw/bsp/stm32h7rs/family.cmake                 |  2 +-
 hw/bsp/stm32h7rs/family.mk                    |  2 +-
 hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf | 55 ---------------------------
 src/common/tusb_mcu.h                         | 30 +++++++--------
 src/portable/synopsys/dwc2/dwc2_stm32.h       | 10 ++---
 src/tusb_option.h                             |  4 +-
 6 files changed, 23 insertions(+), 80 deletions(-)
 delete mode 100644 hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf

(limited to 'src')

diff --git a/hw/bsp/stm32h7rs/family.cmake b/hw/bsp/stm32h7rs/family.cmake
index 6b7915c93..40230ef12 100644
--- a/hw/bsp/stm32h7rs/family.cmake
+++ b/hw/bsp/stm32h7rs/family.cmake
@@ -58,7 +58,7 @@ function(add_board_target BOARD_TARGET)
   endif()
   set(LD_FILE_Clang ${LD_FILE_GNU})
   if(NOT DEFINED LD_FILE_IAR)
-    set(LD_FILE_IAR ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/${MCU_VARIANT}_flash.icf)
+    set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf)
   endif()
 
   add_library(${BOARD_TARGET} STATIC
diff --git a/hw/bsp/stm32h7rs/family.mk b/hw/bsp/stm32h7rs/family.mk
index 45d4da0cf..fba38448d 100644
--- a/hw/bsp/stm32h7rs/family.mk
+++ b/hw/bsp/stm32h7rs/family.mk
@@ -92,4 +92,4 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s
 
 # Linker
 LD_FILE_GCC ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.ld
-LD_FILE_IAR ?= $(FAMILY_PATH)/linker/$(MCU_VARIANT)_flash.icf
+LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf
diff --git a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf b/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf
deleted file mode 100644
index 786be3560..000000000
--- a/hw/bsp/stm32h7rs/linker/stm32h7s3xx_flash.icf
+++ /dev/null
@@ -1,55 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-/*-Memory Regions-*/
-define symbol NONCACHEABLEBUFFER_size   = 0x400;
-define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0800FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x24000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2404FFFF - NONCACHEABLEBUFFER_size;
-define symbol NONCACHEABLEBUFFER_start     = __ICFEDIT_region_RAM_end__ + 1;
-define symbol NONCACHEABLEBUFFER_end       = __ICFEDIT_region_RAM_end__ + NONCACHEABLEBUFFER_size;
-
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-define symbol __region_ITCM_start__ = 0x00000000;
-define symbol __region_ITCM_end__   = 0x0000FFFF;
-define symbol __region_DTCM_start__ = 0x20000000;
-define symbol __region_DTCM_end__   = 0x2000FFFF;
-define symbol __region_SRAMAHB_start__ = 0x30000000;
-define symbol __region_SRAMAHB_end__   = 0x30007FFF;
-define symbol __region_BKPSRAM_start__ = 0x38800000;
-define symbol __region_BKPSRAM_end__   = 0x38800FFF;
-
-export symbol NONCACHEABLEBUFFER_start;
-export symbol NONCACHEABLEBUFFER_size;
-
-export symbol __ICFEDIT_region_ROM_start__;
-export symbol __ICFEDIT_region_ROM_end__;
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
-define region NONCACHEABLE_region   = mem:[from NONCACHEABLEBUFFER_start to NONCACHEABLEBUFFER_end];
-define region ITCM_region     = mem:[from __region_ITCM_start__ to __region_ITCM_end__];
-define region DTCM_region     = mem:[from __region_DTCM_start__ to __region_DTCM_end__];
-define region SRAMAHB_region  = mem:[from __region_SRAMAHB_start__ to __region_SRAMAHB_end__];
-define region BKPSRAM_region  = mem:[from __region_BKPSRAM_start__ to __region_BKPSRAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite };
-place in DTCM_region  { block CSTACK, block HEAP };
-place in NONCACHEABLE_region { section noncacheable_buffer };
diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h
index 4205239f1..94eeb1294 100644
--- a/src/common/tusb_mcu.h
+++ b/src/common/tusb_mcu.h
@@ -117,9 +117,9 @@
   #define TUP_RHPORT_HIGHSPEED    1
 
   #if __CORTEX_M == 7
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  1
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  1
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT        1
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT        1
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT   32
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K)
@@ -221,9 +221,9 @@
   #endif
 
   // Enable dcache if DMA is enabled
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT  32
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H7)
   #include "stm32h7xx.h"
@@ -233,10 +233,10 @@
   #define TUP_DCD_ENDPOINT_MAX    9
 
   #if __CORTEX_M == 7
-  // Enable dcache if DMA is enabled
-    #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
-    #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
-    #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+    // Enable dcache if DMA is enabled
+    #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUD_DWC2_DMA_ENABLE
+    #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUH_DWC2_DMA_ENABLE
+    #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT  32
   #endif
 
 #elif TU_CHECK_MCU(OPT_MCU_STM32H5)
@@ -336,9 +336,9 @@
   #define TUP_RHPORT_HIGHSPEED    1
 
   // Enable dcache if DMA is enabled
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE      32
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT     CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
 
 //--------------------------------------------------------------------+
 // Sony
@@ -410,8 +410,8 @@
   #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT  !CFG_TUH_DWC2_DMA_ENABLE
 
   // Enable dcache if DMA is enabled
-  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUD_DWC2_DMA_ENABLE
-  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT  CFG_TUH_DWC2_DMA_ENABLE
+  #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT      CFG_TUH_DWC2_DMA_ENABLE
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT  64
 
 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h
index f9aa5301b..5f2b8419c 100644
--- a/src/portable/synopsys/dwc2/dwc2_stm32.h
+++ b/src/portable/synopsys/dwc2/dwc2_stm32.h
@@ -282,8 +282,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
 //------------- DCache -------------//
 #if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE
 
-typedef struct
-{
+typedef struct {
   uintptr_t start;
   uintptr_t end;
 } mem_region_t;
@@ -310,16 +309,15 @@ static mem_region_t uncached_regions[] = {
 };
 
 TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
-  if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) {
-    size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE;
+  if (size & (CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) {
+    size = (size & ~(CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT-1)) + CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT;
   }
   return size;
 }
 
 TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uintptr_t addr) {
   for (unsigned int i = 0; i < TU_ARRAY_SIZE(uncached_regions); i++) {
-    if (addr >= uncached_regions[i].start && addr <= uncached_regions[i].end)
-      return false;
+    if (uncached_regions[i].start <= addr && addr <= uncached_regions[i].end) { return false; }
   }
   return true;
 }
diff --git a/src/tusb_option.h b/src/tusb_option.h
index 867babc33..e6f5004b6 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -420,7 +420,7 @@
 
 #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
   #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
-  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
+  #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 1
   #endif
 
   #define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
@@ -428,7 +428,7 @@
 
 // OS selection
 #ifndef CFG_TUSB_OS
-  #define CFG_TUSB_OS             OPT_OS_NONE
+  #define CFG_TUSB_OS           OPT_OS_NONE
 #endif
 
 #ifndef CFG_TUSB_OS_INC_PATH
-- 
cgit v1.3.1